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authorM V Pratap Reddy2019-10-03 03:37:36 -0500
committerM V Pratap Reddy2019-10-03 03:42:43 -0500
commita5748506cc68c27d17f19f983dc34c020c714b5d (patch)
treeb3218b994667d9fae8c2a74335080f21535f2301
parent059347363eed84dbdc9438c4f0fd52ff2bf8b5d4 (diff)
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PDK-4475: Updated J7 Board Ethernet config to remove magic numbers
Diffstat
-rwxr-xr-xsrc/j721e_evm/board_ethernet_config.c166
1 files changed, 117 insertions, 49 deletions
diff --git a/src/j721e_evm/board_ethernet_config.c b/src/j721e_evm/board_ethernet_config.c
index aaabfb9c..b835cf05 100755
--- a/src/j721e_evm/board_ethernet_config.c
+++ b/src/j721e_evm/board_ethernet_config.c
@@ -173,10 +173,16 @@ static void Board_ethPhyExtendedRegRead (uint32_t baseAddr,
173 uint32_t regNum, 173 uint32_t regNum,
174 uint16_t *pData) 174 uint16_t *pData)
175{ 175{
176 Board_ethPhyRegWrite(baseAddr, phyAddr, 0x0D, 0x001F); 176 Board_ethPhyRegWrite(baseAddr, phyAddr,
177 Board_ethPhyRegWrite(baseAddr, phyAddr, 0x0E, regNum); 177 BOARD_ETHPHY_REGCR_REG_ADDR,
178 Board_ethPhyRegWrite(baseAddr, phyAddr, 0x0D, 0x401F); 178 BOARD_ETHPHY_REGCR_ADDR_EN);
179 BoardDiag_ethPhyRegRead(baseAddr, phyAddr, 0x0E, pData); 179 Board_ethPhyRegWrite(baseAddr, phyAddr,
180 BOARD_ETHPHY_ADDAR_REG_ADDR, regNum);
181 Board_ethPhyRegWrite(baseAddr, phyAddr,
182 BOARD_ETHPHY_REGCR_REG_ADDR,
183 BOARD_ETHPHY_REGCR_DATA_EN);
184 BoardDiag_ethPhyRegRead(baseAddr, phyAddr,
185 BOARD_ETHPHY_ADDAR_REG_ADDR, pData);
180} 186}
181 187
182/** 188/**
@@ -194,10 +200,16 @@ static void Board_ethPhyExtendedRegWrite(uint32_t baseAddr,
194 uint32_t regNum, 200 uint32_t regNum,
195 uint16_t regVal) 201 uint16_t regVal)
196{ 202{
197 Board_ethPhyRegWrite(baseAddr, phyAddr, 0x0D, 0x001F); 203 Board_ethPhyRegWrite(baseAddr, phyAddr,
198 Board_ethPhyRegWrite(baseAddr, phyAddr, 0x0E, regNum); 204 BOARD_ETHPHY_REGCR_REG_ADDR,
199 Board_ethPhyRegWrite(baseAddr, phyAddr, 0x0D, 0x401F); 205 BOARD_ETHPHY_REGCR_ADDR_EN);
200 Board_ethPhyRegWrite(baseAddr, phyAddr, 0x0E, regVal); 206 Board_ethPhyRegWrite(baseAddr, phyAddr,
207 BOARD_ETHPHY_ADDAR_REG_ADDR, regNum);
208 Board_ethPhyRegWrite(baseAddr, phyAddr,
209 BOARD_ETHPHY_REGCR_REG_ADDR,
210 BOARD_ETHPHY_REGCR_DATA_EN);
211 Board_ethPhyRegWrite(baseAddr, phyAddr,
212 BOARD_ETHPHY_ADDAR_REG_ADDR, regVal);
201} 213}
202 214
203/** 215/**
@@ -295,21 +307,23 @@ Board_STATUS Board_cpsw9gEthPhyConfig(void)
295 307
296 Board_mdioInit(baseAddr); 308 Board_mdioInit(baseAddr);
297 309
298 /* Enable the PHY delay configurations */
299 Board_ethPhyExtendedRegWrite(baseAddr, phyAddr, 0x32, 0xd3);
300
301 /* Setting delay */
302 Board_ethPhyExtendedRegWrite(baseAddr, phyAddr, 0x86, 0x6B);
303
304 /* Enable PHY speed LED functionality */ 310 /* Enable PHY speed LED functionality */
305 Board_ethPhyExtendedRegRead(baseAddr, phyAddr, 0x172, &regData); 311 Board_ethPhyExtendedRegRead(baseAddr, phyAddr,
306 regData = (regData & ~0xF) | 0x6; 312 BOARD_ETHPHY_GPIO_MUX_CTRL2_REG_ADDR,
307 Board_ethPhyExtendedRegWrite(baseAddr, phyAddr, 0x172, regData); 313 &regData);
314 regData = (regData & ~(BOARD_ETHPHY_GPIO_MUX_CTRL2_REG_MASK)) |
315 BOARD_ETHPHY_GPIO_MUX_CTRL2_REG_CFG;
316 Board_ethPhyExtendedRegWrite(baseAddr, phyAddr,
317 BOARD_ETHPHY_GPIO_MUX_CTRL2_REG_ADDR,
318 regData);
308 319
309 regData = 0; 320 regData = 0;
310 BoardDiag_ethPhyRegRead(baseAddr, phyAddr, 0x18, &regData); 321 BoardDiag_ethPhyRegRead(baseAddr, phyAddr,
311 regData = (regData & ~0xF000) | 0x8000; 322 BOARD_ETHPHY_LEDCR1_REG_ADDR, &regData);
312 Board_ethPhyRegWrite(baseAddr, phyAddr, 0x18, regData); 323 regData = (regData & ~(BOARD_ETHPHY_LEDCR1_REG_MASK)) |
324 BOARD_ETHPHY_LEDCR1_REG_CFG;
325 Board_ethPhyRegWrite(baseAddr, phyAddr,
326 BOARD_ETHPHY_LEDCR1_REG_ADDR, regData);
313 327
314 /* When the Phy is strapped to enable Fast Link Drop (FLD) feature, 328 /* When the Phy is strapped to enable Fast Link Drop (FLD) feature,
315 * the detect threshold value becomes 0x2 in bit 2:0 instead of 0x1 329 * the detect threshold value becomes 0x2 in bit 2:0 instead of 0x1
@@ -319,21 +333,40 @@ Board_STATUS Board_cpsw9gEthPhyConfig(void)
319 * bit 10 of STRAP_STS2 (0x6f) register is set (enable FLD). 333 * bit 10 of STRAP_STS2 (0x6f) register is set (enable FLD).
320 */ 334 */
321 regData = 0; 335 regData = 0;
322 Board_ethPhyExtendedRegRead(baseAddr, phyAddr, 0x6f, &regData); 336 Board_ethPhyExtendedRegRead(baseAddr, phyAddr,
337 BOARD_ETHPHY_STRAP_STS2_REG_ADDR,
338 &regData);
323 if (regData & 0x0400) 339 if (regData & 0x0400)
324 { 340 {
325 regData = 0; 341 regData = 0;
326 Board_ethPhyExtendedRegRead(baseAddr, phyAddr, 0x2e, &regData); 342 Board_ethPhyExtendedRegRead(baseAddr, phyAddr,
343 BOARD_ETHPHY_FLD_THRESH_REG_ADDR,
344 &regData);
327 if (regData == 0x222) 345 if (regData == 0x222)
328 { 346 {
329 regData &= ~0x7; 347 regData &= ~0x7;
330 Board_ethPhyExtendedRegWrite(baseAddr, phyAddr, 0x2e, regData | 0x1); 348 Board_ethPhyExtendedRegWrite(baseAddr, phyAddr,
349 BOARD_ETHPHY_FLD_THRESH_REG_ADDR,
350 (regData | 0x1));
331 } 351 }
332 } 352 }
353
354 /*Setting IO impedance to 35ohms */
355 Board_ethPhyExtendedRegWrite(baseAddr, phyAddr,
356 BOARD_ETHPHY_GPIO_MUX_CFG_REG_ADDR,
357 BOARD_ETHPHY_IO_IMPEDANCE);
358
359 /* Enable the PHY delay configurations */
360 Board_ethPhyExtendedRegWrite(baseAddr, phyAddr, BOARD_ETHPHY_RGMIICTL_REG_ADDR,
361 BOARD_ETHPHY_DELAY_CTRL);
362
363 /* Setting delay */
364 Board_ethPhyExtendedRegWrite(baseAddr, phyAddr,
365 BOARD_ETHPHY_RGMIIDCTL_REG_ADDR,
366 BOARD_ETHPHY_CPSW9G_DELAY);
333 } 367 }
334 368
335 return BOARD_SOK; 369 return BOARD_SOK;
336
337} 370}
338 371
339/** 372/**
@@ -354,14 +387,22 @@ Board_STATUS Board_cpsw2gEthPhyConfig(void)
354 Board_mdioInit(baseAddr); 387 Board_mdioInit(baseAddr);
355 388
356 /* Enable PHY speed LED functionality */ 389 /* Enable PHY speed LED functionality */
357 Board_ethPhyExtendedRegRead(baseAddr, BOARD_MCU_EMAC_PHY_ADDR, 0x172, &regData); 390 Board_ethPhyExtendedRegRead(baseAddr, BOARD_MCU_EMAC_PHY_ADDR,
358 regData = (regData & ~0xF) | 0x6; 391 BOARD_ETHPHY_GPIO_MUX_CTRL2_REG_ADDR,
359 Board_ethPhyExtendedRegWrite(baseAddr, BOARD_MCU_EMAC_PHY_ADDR, 0x172, regData); 392 &regData);
393 regData = (regData & ~(BOARD_ETHPHY_GPIO_MUX_CTRL2_REG_MASK)) |
394 BOARD_ETHPHY_GPIO_MUX_CTRL2_REG_CFG;
395 Board_ethPhyExtendedRegWrite(baseAddr, BOARD_MCU_EMAC_PHY_ADDR,
396 BOARD_ETHPHY_GPIO_MUX_CTRL2_REG_ADDR,
397 regData);
360 398
361 regData = 0; 399 regData = 0;
362 BoardDiag_ethPhyRegRead(baseAddr, BOARD_MCU_EMAC_PHY_ADDR, 0x18, &regData); 400 BoardDiag_ethPhyRegRead(baseAddr, BOARD_MCU_EMAC_PHY_ADDR,
363 regData = (regData & ~0xF000) | 0x8000; 401 BOARD_ETHPHY_LEDCR1_REG_ADDR, &regData);
364 Board_ethPhyRegWrite(baseAddr, BOARD_MCU_EMAC_PHY_ADDR, 0x18, regData); 402 regData = (regData & ~(BOARD_ETHPHY_LEDCR1_REG_MASK)) |
403 BOARD_ETHPHY_LEDCR1_REG_CFG;
404 Board_ethPhyRegWrite(baseAddr, BOARD_MCU_EMAC_PHY_ADDR,
405 BOARD_ETHPHY_LEDCR1_REG_ADDR, regData);
365 406
366 /* When the Phy is strapped to enable Fast Link Drop (FLD) feature, 407 /* When the Phy is strapped to enable Fast Link Drop (FLD) feature,
367 * the detect threshold value becomes 0x2 in bit 2:0 instead of 0x1 408 * the detect threshold value becomes 0x2 in bit 2:0 instead of 0x1
@@ -371,26 +412,34 @@ Board_STATUS Board_cpsw2gEthPhyConfig(void)
371 * bit 10 of STRAP_STS2 (0x6f) register is set (enable FLD). 412 * bit 10 of STRAP_STS2 (0x6f) register is set (enable FLD).
372 */ 413 */
373 regData = 0; 414 regData = 0;
374 Board_ethPhyExtendedRegRead(baseAddr, BOARD_MCU_EMAC_PHY_ADDR, 0x6f, &regData); 415 Board_ethPhyExtendedRegRead(baseAddr, BOARD_MCU_EMAC_PHY_ADDR,
416 BOARD_ETHPHY_STRAP_STS2_REG_ADDR,
417 &regData);
375 if (regData & 0x0400) 418 if (regData & 0x0400)
376 { 419 {
377 regData = 0; 420 regData = 0;
378 Board_ethPhyExtendedRegRead(baseAddr, BOARD_MCU_EMAC_PHY_ADDR, 0x2e, &regData); 421 Board_ethPhyExtendedRegRead(baseAddr, BOARD_MCU_EMAC_PHY_ADDR,
422 BOARD_ETHPHY_FLD_THRESH_REG_ADDR,
423 &regData);
379 if (regData == 0x222) 424 if (regData == 0x222)
380 { 425 {
381 regData &= ~0x7; 426 regData &= ~0x7;
382 Board_ethPhyExtendedRegWrite(baseAddr, BOARD_MCU_EMAC_PHY_ADDR, 0x2e, regData | 0x1); 427 Board_ethPhyExtendedRegWrite(baseAddr, BOARD_MCU_EMAC_PHY_ADDR,
428 BOARD_ETHPHY_FLD_THRESH_REG_ADDR,
429 (regData | 0x1));
383 } 430 }
384 } 431 }
385 432
386 /* Enabling the TX and RX delay */ 433 /* Enabling the TX and RX delay */
387 Board_ethPhyExtendedRegRead(baseAddr, BOARD_MCU_EMAC_PHY_ADDR, 0x32, &regData); 434 Board_ethPhyExtendedRegRead(baseAddr, BOARD_MCU_EMAC_PHY_ADDR,
435 BOARD_ETHPHY_RGMIICTL_REG_ADDR, &regData);
388 regData = regData | 0x3; 436 regData = regData | 0x3;
389 Board_ethPhyExtendedRegWrite(baseAddr, BOARD_MCU_EMAC_PHY_ADDR, 0x32, regData); 437 Board_ethPhyExtendedRegWrite(baseAddr, BOARD_MCU_EMAC_PHY_ADDR,
438 BOARD_ETHPHY_RGMIICTL_REG_ADDR, regData);
390 439
391 /* Setting delay */ 440 /* Setting delay */
392 Board_ethPhyExtendedRegWrite(baseAddr, BOARD_MCU_EMAC_PHY_ADDR, 0x86, 0x77); 441 Board_ethPhyExtendedRegWrite(baseAddr, BOARD_MCU_EMAC_PHY_ADDR,
393 442 BOARD_ETHPHY_RGMIIDCTL_REG_ADDR, 0x77);
394 443
395 return BOARD_SOK; 444 return BOARD_SOK;
396 445
@@ -423,23 +472,36 @@ Board_STATUS Board_icssEthPhyConfig(void)
423 Board_mdioInit(baseAddr); 472 Board_mdioInit(baseAddr);
424 473
425 /* Enable the PHY delay configurations */ 474 /* Enable the PHY delay configurations */
426 Board_ethPhyExtendedRegWrite(baseAddr, phyAddr, 0x32, 0xd3); 475 Board_ethPhyExtendedRegWrite(baseAddr, phyAddr,
476 BOARD_ETHPHY_RGMIICTL_REG_ADDR,
477 BOARD_ETHPHY_DELAY_CTRL);
427 478
428 /* Setting delay */ 479 /* Setting delay */
429 Board_ethPhyExtendedRegWrite(baseAddr, phyAddr, 0x86, 0xA9); 480 Board_ethPhyExtendedRegWrite(baseAddr, phyAddr,
481 BOARD_ETHPHY_RGMIIDCTL_REG_ADDR,
482 BOARD_ETHPHY_ICSSG_DELAY);
430 483
431 /*Setting IO impedance to 35ohms */ 484 /*Setting IO impedance to 35ohms */
432 Board_ethPhyExtendedRegWrite(baseAddr, phyAddr, 0x170, 0x0C1F); 485 Board_ethPhyExtendedRegWrite(baseAddr, phyAddr,
486 BOARD_ETHPHY_GPIO_MUX_CFG_REG_ADDR,
487 BOARD_ETHPHY_IO_IMPEDANCE);
433 488
434 /* Enable PHY speed LED functionality */ 489 /* Enable PHY speed LED functionality */
435 Board_ethPhyExtendedRegRead(baseAddr, phyAddr, 0x172, &regData); 490 Board_ethPhyExtendedRegRead(baseAddr, phyAddr,
436 regData = (regData & ~0xF) | 0x6; 491 BOARD_ETHPHY_GPIO_MUX_CTRL2_REG_ADDR,
437 Board_ethPhyExtendedRegWrite(baseAddr, phyAddr, 0x172, regData); 492 &regData);
493 regData = (regData & ~(BOARD_ETHPHY_GPIO_MUX_CTRL2_REG_MASK)) | 0x6;
494 Board_ethPhyExtendedRegWrite(baseAddr, phyAddr,
495 BOARD_ETHPHY_GPIO_MUX_CTRL2_REG_ADDR,
496 regData);
438 497
439 regData = 0; 498 regData = 0;
440 BoardDiag_ethPhyRegRead(baseAddr, phyAddr, 0x18, &regData); 499 BoardDiag_ethPhyRegRead(baseAddr, phyAddr,
441 regData = (regData & ~0xF000) | 0x8000; 500 BOARD_ETHPHY_LEDCR1_REG_ADDR, &regData);
442 Board_ethPhyRegWrite(baseAddr, phyAddr, 0x18, regData); 501 regData = (regData & ~(BOARD_ETHPHY_LEDCR1_REG_MASK)) |
502 BOARD_ETHPHY_LEDCR1_REG_CFG;
503 Board_ethPhyRegWrite(baseAddr, phyAddr,
504 BOARD_ETHPHY_LEDCR1_REG_ADDR, regData);
443 505
444 /* When the Phy is strapped to enable Fast Link Drop (FLD) feature, 506 /* When the Phy is strapped to enable Fast Link Drop (FLD) feature,
445 * the detect threshold value becomes 0x2 in bit 2:0 instead of 0x1 507 * the detect threshold value becomes 0x2 in bit 2:0 instead of 0x1
@@ -449,15 +511,21 @@ Board_STATUS Board_icssEthPhyConfig(void)
449 * bit 10 of STRAP_STS2 (0x6f) register is set (enable FLD). 511 * bit 10 of STRAP_STS2 (0x6f) register is set (enable FLD).
450 */ 512 */
451 regData = 0; 513 regData = 0;
452 Board_ethPhyExtendedRegRead(baseAddr, phyAddr, 0x6f, &regData); 514 Board_ethPhyExtendedRegRead(baseAddr, phyAddr,
515 BOARD_ETHPHY_STRAP_STS2_REG_ADDR,
516 &regData);
453 if (regData & 0x0400) 517 if (regData & 0x0400)
454 { 518 {
455 regData = 0; 519 regData = 0;
456 Board_ethPhyExtendedRegRead(baseAddr, phyAddr, 0x2e, &regData); 520 Board_ethPhyExtendedRegRead(baseAddr, phyAddr,
521 BOARD_ETHPHY_FLD_THRESH_REG_ADDR,
522 &regData);
457 if (regData == 0x222) 523 if (regData == 0x222)
458 { 524 {
459 regData &= ~0x7; 525 regData &= ~0x7;
460 Board_ethPhyExtendedRegWrite(baseAddr, phyAddr, 0x2e, regData | 0x1); 526 Board_ethPhyExtendedRegWrite(baseAddr, phyAddr,
527 BOARD_ETHPHY_FLD_THRESH_REG_ADDR,
528 (regData | 0x1));
461 } 529 }
462 } 530 }
463 } 531 }
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