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author | Subhajit Paul | 2019-08-27 07:09:37 -0500 |
---|---|---|
committer | Subhajit Paul | 2019-09-03 02:43:30 -0500 |
commit | 5386ebfc382b8c31c0844d1b05830ab272744b2c (patch) | |
tree | a3b3c3e193a8b2ee03d224e36d1704e957cfac2b | |
parent | 101254e76e6cfc8c9fe8b0837b8bdd495033deca (diff) | |
download | dss-lld-5386ebfc382b8c31c0844d1b05830ab272744b2c.tar.gz dss-lld-5386ebfc382b8c31c0844d1b05830ab272744b2c.tar.xz dss-lld-5386ebfc382b8c31c0844d1b05830ab272744b2c.zip |
PDK-4396, PDK-4398, PDK-4405, PDK-4571 eDP fixes
DCTRL to DP interface modifications
Major changes in this patch:
- HPD for non-blocking initialisation of DP
- Enforced link trainig for each HPD for better usability / compatibility
- Code cleanup
Signed-off-by: Subhajit Paul <subhajit_paul@ti.com>
-rwxr-xr-x | soc/V1/dss_soc.h | 29 | ||||
-rwxr-xr-x | src/drv/common/dss_init.c | 4 | ||||
-rwxr-xr-x | src/drv/dctrl/dss_dctrlApi.c | 66 | ||||
-rwxr-xr-x | src/drv/dctrl/dss_dctrlDrv.h | 4 | ||||
-rwxr-xr-x | src/drv/dctrl/dss_dctrlExtended.c | 828 | ||||
-rwxr-xr-x | src/drv/dctrl/dss_dctrlPriv.h | 9 |
6 files changed, 682 insertions, 258 deletions
diff --git a/soc/V1/dss_soc.h b/soc/V1/dss_soc.h index 23cb02e..497453f 100755 --- a/soc/V1/dss_soc.h +++ b/soc/V1/dss_soc.h | |||
@@ -236,6 +236,15 @@ typedef struct | |||
236 | } Dss_RmInfo; | 236 | } Dss_RmInfo; |
237 | 237 | ||
238 | /** | 238 | /** |
239 | * \brief Structure containing Display Port init parameters | ||
240 | */ | ||
241 | typedef struct | ||
242 | { | ||
243 | uint32_t isAvailable; | ||
244 | /**< Flag to indicate whether eDP module is available */ | ||
245 | } Dss_DpInitParams; | ||
246 | |||
247 | /** | ||
239 | * \brief DSS SOC parameters. | 248 | * \brief DSS SOC parameters. |
240 | */ | 249 | */ |
241 | typedef struct | 250 | typedef struct |
@@ -244,6 +253,8 @@ typedef struct | |||
244 | /**< DSS interrupt information */ | 253 | /**< DSS interrupt information */ |
245 | Dss_RmInfo rmInfo; | 254 | Dss_RmInfo rmInfo; |
246 | /**< DSS resource information */ | 255 | /**< DSS resource information */ |
256 | Dss_DpInitParams dpInitParams; | ||
257 | /**< DSS DP init information */ | ||
247 | } Dss_SocParams; | 258 | } Dss_SocParams; |
248 | 259 | ||
249 | /* ========================================================================== */ | 260 | /* ========================================================================== */ |
@@ -287,6 +298,15 @@ static inline void Dss_irqParamsInit(Dss_IrqParams *irqParams); | |||
287 | static inline void Dss_rmInfoInit(Dss_RmInfo *rmInfo); | 298 | static inline void Dss_rmInfoInit(Dss_RmInfo *rmInfo); |
288 | 299 | ||
289 | /** | 300 | /** |
301 | * \brief Dss_DpInfo structure init function. | ||
302 | * | ||
303 | * \param dpInfo Pointer to #Dss_DpInfo structure. | ||
304 | * | ||
305 | * \return None | ||
306 | */ | ||
307 | static inline void Dss_dpInitParamsInit(Dss_DpInitParams *dpInitParams); | ||
308 | |||
309 | /** | ||
290 | * \brief Dss_SocParams structure init function. | 310 | * \brief Dss_SocParams structure init function. |
291 | * | 311 | * |
292 | * \param socParams Pointer to #Dss_SocParams structure. | 312 | * \param socParams Pointer to #Dss_SocParams structure. |
@@ -369,12 +389,21 @@ static inline void Dss_rmInfoInit(Dss_RmInfo *rmInfo) | |||
369 | } | 389 | } |
370 | } | 390 | } |
371 | 391 | ||
392 | static inline void Dss_dpInitParamsInit(Dss_DpInitParams *dpInitParams) | ||
393 | { | ||
394 | if(NULL != dpInitParams) | ||
395 | { | ||
396 | dpInitParams->isAvailable = TRUE; | ||
397 | } | ||
398 | } | ||
399 | |||
372 | static inline void Dss_socParamsInit(Dss_SocParams *socParams) | 400 | static inline void Dss_socParamsInit(Dss_SocParams *socParams) |
373 | { | 401 | { |
374 | if(NULL != socParams) | 402 | if(NULL != socParams) |
375 | { | 403 | { |
376 | Dss_irqParamsInit(&(socParams->irqParams)); | 404 | Dss_irqParamsInit(&(socParams->irqParams)); |
377 | Dss_rmInfoInit(&(socParams->rmInfo)); | 405 | Dss_rmInfoInit(&(socParams->rmInfo)); |
406 | Dss_dpInitParamsInit(&(socParams->dpInitParams)); | ||
378 | } | 407 | } |
379 | } | 408 | } |
380 | 409 | ||
diff --git a/src/drv/common/dss_init.c b/src/drv/common/dss_init.c index d64e521..b9f1ae2 100755 --- a/src/drv/common/dss_init.c +++ b/src/drv/common/dss_init.c | |||
@@ -133,6 +133,10 @@ int32_t Dss_init(const Dss_InitParams *initParams) | |||
133 | dctrlInitParams.numAvailablePorts++; | 133 | dctrlInitParams.numAvailablePorts++; |
134 | } | 134 | } |
135 | } | 135 | } |
136 | |||
137 | #if defined(SOC_J721E) | ||
138 | dctrlInitParams.dpInitParams.isAvailable = initParams->socParams.dpInitParams.isAvailable; | ||
139 | #endif | ||
136 | retVal = Dss_dctrlDrvInit(&dctrlInitParams); | 140 | retVal = Dss_dctrlDrvInit(&dctrlInitParams); |
137 | } | 141 | } |
138 | 142 | ||
diff --git a/src/drv/dctrl/dss_dctrlApi.c b/src/drv/dctrl/dss_dctrlApi.c index 44a84d8..6fce4a0 100755 --- a/src/drv/dctrl/dss_dctrlApi.c +++ b/src/drv/dctrl/dss_dctrlApi.c | |||
@@ -161,6 +161,10 @@ static int32_t Dss_dctrlDrvSetOldiParamsIoctl( | |||
161 | Dss_DctrlDrvInstObj *instObj, | 161 | Dss_DctrlDrvInstObj *instObj, |
162 | const Dss_DctrlOldiParams *oldiParams); | 162 | const Dss_DctrlOldiParams *oldiParams); |
163 | #endif | 163 | #endif |
164 | #if defined (SOC_J721E) | ||
165 | static uint32_t Dss_dctrlDrvIsOutputDP(uint32_t vpId); | ||
166 | #endif | ||
167 | |||
164 | static void Dss_dctrlVpSetGoBit(uint32_t vpId); | 168 | static void Dss_dctrlVpSetGoBit(uint32_t vpId); |
165 | static void Dss_dctrlVpReset(uint32_t vpId); | 169 | static void Dss_dctrlVpReset(uint32_t vpId); |
166 | static void Dss_dctrlVpEnable(uint32_t vpId, uint32_t enable); | 170 | static void Dss_dctrlVpEnable(uint32_t vpId, uint32_t enable); |
@@ -280,6 +284,14 @@ int32_t Dss_dctrlDrvInit(const Dss_DctrlDrvInitParams *drvInitParams) | |||
280 | } | 284 | } |
281 | } | 285 | } |
282 | 286 | ||
287 | #if defined (SOC_J721E) | ||
288 | if((FVID2_SOK == retVal) && | ||
289 | (TRUE == drvInitParams->dpInitParams.isAvailable)) | ||
290 | { | ||
291 | retVal = Dss_dctrlDrvInitDp(); | ||
292 | } | ||
293 | #endif | ||
294 | |||
283 | if(FVID2_SOK == retVal) | 295 | if(FVID2_SOK == retVal) |
284 | { | 296 | { |
285 | /* Initialize Driver operations */ | 297 | /* Initialize Driver operations */ |
@@ -1068,6 +1080,16 @@ static int32_t Dss_dctrlDrvSetVpParamsIoctl( | |||
1068 | Dss_dctrlVpEnable(vpId, TRUE); | 1080 | Dss_dctrlVpEnable(vpId, TRUE); |
1069 | } | 1081 | } |
1070 | 1082 | ||
1083 | #if defined (SOC_J721E) | ||
1084 | if((FVID2_SOK == retVal) && | ||
1085 | (TRUE == Dss_dctrlDrvIsOutputDP(vpId))) | ||
1086 | { | ||
1087 | retVal = Dss_dctrlDrvEnableVideoDP(&lcdOpTimingCfg->mInfo, | ||
1088 | lcdPolarityCfg->hsPolarity, | ||
1089 | lcdPolarityCfg->vsPolarity); | ||
1090 | } | ||
1091 | #endif | ||
1092 | |||
1071 | if(FVID2_SOK != retVal) | 1093 | if(FVID2_SOK != retVal) |
1072 | { | 1094 | { |
1073 | GT_0trace(DssTrace, GT_ERR, "Set VP parameters IOCTL failed\r\n"); | 1095 | GT_0trace(DssTrace, GT_ERR, "Set VP parameters IOCTL failed\r\n"); |
@@ -1079,6 +1101,34 @@ static int32_t Dss_dctrlDrvSetVpParamsIoctl( | |||
1079 | return retVal; | 1101 | return retVal; |
1080 | } | 1102 | } |
1081 | 1103 | ||
1104 | #if defined (SOC_J721E) | ||
1105 | static uint32_t Dss_dctrlDrvIsOutputDP(uint32_t vpId) | ||
1106 | { | ||
1107 | uint32_t retVal, i; | ||
1108 | uint32_t nodeId, vpFound = FALSE; | ||
1109 | Fvid2_GraphEdgeInfo *currEdge; | ||
1110 | |||
1111 | retVal = Dss_convModuletoNode(&nodeId, vpId, DSS_DCTRL_NODE_TYPE_VP); | ||
1112 | GT_assert(DssTrace, | ||
1113 | ((DSS_DCTRL_NODE_INVALID != nodeId) || | ||
1114 | (FVID2_SOK == retVal))); | ||
1115 | |||
1116 | for(i=0U; i<gDss_DctrlDrvGraphObj.dctrlEdgeList.numEdges; i++) | ||
1117 | { | ||
1118 | currEdge = &gDss_DctrlDrvGraphObj.dctrlEdgeList.list[i]; | ||
1119 | if((DSS_DCTRL_NODE_EDP_DPI0 == currEdge->endNode) && | ||
1120 | (nodeId == currEdge->startNode)) | ||
1121 | { | ||
1122 | vpFound = TRUE; | ||
1123 | break; | ||
1124 | } | ||
1125 | } | ||
1126 | |||
1127 | return vpFound; | ||
1128 | } | ||
1129 | #endif | ||
1130 | |||
1131 | |||
1082 | static int32_t Dss_dctrlDrvSetOverlayParamsIoctl( | 1132 | static int32_t Dss_dctrlDrvSetOverlayParamsIoctl( |
1083 | Dss_DctrlDrvInstObj *instObj, | 1133 | Dss_DctrlDrvInstObj *instObj, |
1084 | const Dss_DctrlOverlayParams *overlayParams) | 1134 | const Dss_DctrlOverlayParams *overlayParams) |
@@ -1660,6 +1710,14 @@ static int32_t Dss_dctrlDrvStopVpIoctl(Dss_DctrlDrvInstObj *instObj, | |||
1660 | 1710 | ||
1661 | if(FVID2_SOK == retVal) | 1711 | if(FVID2_SOK == retVal) |
1662 | { | 1712 | { |
1713 | |||
1714 | #if defined (SOC_J721E) | ||
1715 | if(TRUE == Dss_dctrlDrvIsOutputDP(vpId)) | ||
1716 | { | ||
1717 | Dss_dctrlDrvDisableVideoDP(); | ||
1718 | } | ||
1719 | #endif | ||
1720 | |||
1663 | cookie = HwiP_disable(); | 1721 | cookie = HwiP_disable(); |
1664 | Dss_dctrlVpEnable(vpId, FALSE); | 1722 | Dss_dctrlVpEnable(vpId, FALSE); |
1665 | HwiP_restore(cookie); | 1723 | HwiP_restore(cookie); |
@@ -1977,14 +2035,6 @@ static int32_t Dss_dctrlConnectNodes(uint32_t inputNode, uint32_t outNode) | |||
1977 | GT_assert(DssTrace, (FVID2_SOK == retVal)); | 2035 | GT_assert(DssTrace, (FVID2_SOK == retVal)); |
1978 | } | 2036 | } |
1979 | 2037 | ||
1980 | #if defined (SOC_J721E) | ||
1981 | if(DSS_DCTRL_NODE_EDP_DPI0 == outNode) | ||
1982 | { | ||
1983 | retVal = Dss_dctrlDrvProgDP(); | ||
1984 | GT_assert(DssTrace, (FVID2_SOK == retVal)); | ||
1985 | } | ||
1986 | #endif | ||
1987 | |||
1988 | return (retVal); | 2038 | return (retVal); |
1989 | } | 2039 | } |
1990 | 2040 | ||
diff --git a/src/drv/dctrl/dss_dctrlDrv.h b/src/drv/dctrl/dss_dctrlDrv.h index 0367fd5..6d68e01 100755 --- a/src/drv/dctrl/dss_dctrlDrv.h +++ b/src/drv/dctrl/dss_dctrlDrv.h | |||
@@ -71,6 +71,10 @@ typedef struct | |||
71 | /**< Number of video ports available to driver */ | 71 | /**< Number of video ports available to driver */ |
72 | uint32_t availablePortId[CSL_DSS_VP_ID_MAX]; | 72 | uint32_t availablePortId[CSL_DSS_VP_ID_MAX]; |
73 | /**< Id of available video ports */ | 73 | /**< Id of available video ports */ |
74 | #if defined(SOC_J721E) | ||
75 | Dss_DpInitParams dpInitParams; | ||
76 | /**< DP init parameters */ | ||
77 | #endif | ||
74 | } Dss_DctrlDrvInitParams; | 78 | } Dss_DctrlDrvInitParams; |
75 | 79 | ||
76 | /* ========================================================================== */ | 80 | /* ========================================================================== */ |
diff --git a/src/drv/dctrl/dss_dctrlExtended.c b/src/drv/dctrl/dss_dctrlExtended.c index 4450b6e..2b7c0a8 100755 --- a/src/drv/dctrl/dss_dctrlExtended.c +++ b/src/drv/dctrl/dss_dctrlExtended.c | |||
@@ -52,18 +52,60 @@ | |||
52 | #include <ti/drv/dss/src/drv/dctrl/dss_dctrlPriv.h> | 52 | #include <ti/drv/dss/src/drv/dctrl/dss_dctrlPriv.h> |
53 | #include <dss_soc_priv.h> | 53 | #include <dss_soc_priv.h> |
54 | 54 | ||
55 | #include <ti/osal/SwiP.h> | ||
56 | |||
55 | /* ========================================================================== */ | 57 | /* ========================================================================== */ |
56 | /* Macros & Typedefs */ | 58 | /* Macros & Typedefs */ |
57 | /* ========================================================================== */ | 59 | /* ========================================================================== */ |
58 | 60 | ||
59 | #define STATIC_PD_SIZE 131072 | 61 | typedef enum |
60 | #define STATIC_PHY_PD_SIZE 1024 | 62 | { |
63 | DP_VIDEO_STATE_IDLE = 0U, | ||
64 | DP_VIDEO_STATE_REQUESTED = 1U, | ||
65 | DP_VIDEO_STATE_RUNNING = 2U, | ||
66 | } Dss_DctrlDisplayPortVideoState; | ||
67 | |||
68 | #define DP_PRIVATE_DATA_SIZE (131072U) | ||
69 | #define DP_PHY_PRIVATE_DATA_SIZE (1024U) | ||
70 | #define DP_INTR (64U) | ||
71 | #define ADDR_AFE (0x05050000) | ||
61 | 72 | ||
62 | /* ========================================================================== */ | 73 | /* ========================================================================== */ |
63 | /* Structure Declarations */ | 74 | /* Structure Declarations */ |
64 | /* ========================================================================== */ | 75 | /* ========================================================================== */ |
65 | 76 | ||
66 | /* None */ | 77 | typedef struct |
78 | { | ||
79 | uint32_t width; | ||
80 | uint32_t height; | ||
81 | uint32_t hfp; | ||
82 | uint32_t hsw; | ||
83 | uint32_t hbp; | ||
84 | uint32_t vfp; | ||
85 | uint32_t vsw; | ||
86 | uint32_t vbp; | ||
87 | uint32_t pclk; | ||
88 | uint32_t scanMode; | ||
89 | uint32_t hsyncPol; | ||
90 | uint32_t vsyncPol; | ||
91 | } Dss_DctrlDisplayPortVideoMode; | ||
92 | |||
93 | typedef struct | ||
94 | { | ||
95 | DP_Config dpCfg; | ||
96 | DP_SD0801_Config dpPhyCfg; | ||
97 | DP_FirmwareImage dpFWImage; | ||
98 | DP_PrivateData *dpPrivData; | ||
99 | DP_SD0801_PrivateData *dpPhyPrivData; | ||
100 | DP_Callbacks dpCbInfo; | ||
101 | DP_UcpuClock dpClkInfo; | ||
102 | DP_SourceDeviceCapabilities srcCaps; | ||
103 | HwiP_Handle intrHandle; | ||
104 | SwiP_Handle swiHandle; | ||
105 | uint32_t isConnected; | ||
106 | Dss_DctrlDisplayPortVideoState videoState; | ||
107 | Dss_DctrlDisplayPortVideoMode videoMode; | ||
108 | } Dss_DctrlDisplayPortDrvObj; | ||
67 | 109 | ||
68 | /* ========================================================================== */ | 110 | /* ========================================================================== */ |
69 | /* Function Declarations */ | 111 | /* Function Declarations */ |
@@ -78,81 +120,195 @@ | |||
78 | extern uint8_t gDctrlDpDram[DCTRL_DP_DMEM_SIZE]; | 120 | extern uint8_t gDctrlDpDram[DCTRL_DP_DMEM_SIZE]; |
79 | extern uint8_t gDctrlDpIram[DCTRL_DP_IMEM_SIZE]; | 121 | extern uint8_t gDctrlDpIram[DCTRL_DP_IMEM_SIZE]; |
80 | 122 | ||
123 | static uint8_t gDssDctrlDisplayPortDpPrivateData[DP_PRIVATE_DATA_SIZE]; | ||
124 | static uint8_t gDssDctrlDisplayPortDpPhyPrivateData[DP_PHY_PRIVATE_DATA_SIZE]; | ||
125 | |||
126 | static Dss_DctrlDisplayPortDrvObj gDssDctrlDisplayPortDrvObj; | ||
127 | |||
128 | Fvid2_ModeInfo gDpStdModeInfo[] = { | ||
129 | {FVID2_STD_1080P_60, 1920, 1080, FVID2_SF_PROGRESSIVE, 148500, 60, | ||
130 | 88, 148, 44, 4, 36, 5} | ||
131 | }; | ||
132 | |||
81 | /* ========================================================================== */ | 133 | /* ========================================================================== */ |
82 | /* Internal/Private Function Declarations */ | 134 | /* Internal/Private Function Declarations */ |
83 | /* ========================================================================== */ | 135 | /* ========================================================================== */ |
84 | 136 | ||
85 | static int32_t Dss_dctrlSetDPConfig(int32_t *status); | 137 | static int32_t Dss_dctrlDrvInitDPTX(void); |
138 | static void Dss_dctrlDrvDpIntr(uintptr_t arg); | ||
139 | static void Dss_dctrlDrvDpHpdWork(uintptr_t arg0, uintptr_t arg1); | ||
140 | static int32_t Dss_dctrlDrvDpStartVideo(Dss_DctrlDisplayPortDrvObj *pObj); | ||
141 | static int32_t Dss_dctrlDrvDpStopVideo(Dss_DctrlDisplayPortDrvObj *pObj); | ||
86 | 142 | ||
87 | /* ========================================================================== */ | 143 | /* ========================================================================== */ |
88 | /* Function Definitions */ | 144 | /* Function Definitions */ |
89 | /* ========================================================================== */ | 145 | /* ========================================================================== */ |
90 | 146 | ||
147 | int32_t Dss_dctrlDrvDisableVideoDP(void) | ||
148 | { | ||
149 | int32_t retVal = FVID2_SOK; | ||
150 | uint32_t cookie; | ||
151 | Dss_DctrlDisplayPortDrvObj *pObj = &gDssDctrlDisplayPortDrvObj; | ||
152 | |||
153 | cookie = HwiP_disable(); | ||
154 | |||
155 | /* | ||
156 | * We cannot be IDLE when this function is called. | ||
157 | * Valid states are REQUESTED || RUNNING | ||
158 | * | ||
159 | * If state == REQUESTED, HPD never happened, and we | ||
160 | * never went to RUNNING. So just go back to IDLE | ||
161 | * | ||
162 | * If state == RUNNING, we stop video and go to IDLE | ||
163 | * | ||
164 | * There is nothing we can do if stopVideo fails, so | ||
165 | * dont bother | ||
166 | */ | ||
167 | if((DP_VIDEO_STATE_REQUESTED == pObj->videoState) || | ||
168 | (DP_VIDEO_STATE_RUNNING == pObj->videoState)) | ||
169 | { | ||
170 | if(DP_VIDEO_STATE_RUNNING == pObj->videoState) | ||
171 | { | ||
172 | Dss_dctrlDrvDpStopVideo(pObj); | ||
173 | } | ||
174 | pObj->videoState = DP_VIDEO_STATE_IDLE; | ||
175 | } | ||
176 | |||
177 | HwiP_restore(cookie); | ||
91 | 178 | ||
92 | static int gDctrlEdpInit = 0U; | 179 | return retVal; |
180 | } | ||
93 | 181 | ||
94 | int32_t Dss_dctrlDrvProgDP(void) | 182 | int32_t Dss_dctrlDrvEnableVideoDP(const Fvid2_ModeInfo *mInfo, |
183 | uint32_t hsyncPolarity, | ||
184 | uint32_t vsyncPolarity) | ||
95 | { | 185 | { |
96 | int32_t retVal = FVID2_SOK; | 186 | int32_t retVal = FVID2_SOK; |
97 | if(gDctrlEdpInit == 0U) | 187 | uint32_t cookie; |
188 | Dss_DctrlDisplayPortDrvObj *pObj = &gDssDctrlDisplayPortDrvObj; | ||
189 | uint32_t numStdModes, modeCnt; | ||
190 | |||
191 | cookie = HwiP_disable(); | ||
192 | |||
193 | /* | ||
194 | * Copy the video mode parameters to be | ||
195 | * used by subsequent videoStart calls | ||
196 | * | ||
197 | * XXX bring in EDID support so that we can validate | ||
198 | * params passed by app, and when all parameters not | ||
199 | * provided, make a good guess whether to continue or not | ||
200 | */ | ||
201 | if(FVID2_STD_CUSTOM != mInfo->standard) | ||
98 | { | 202 | { |
99 | gDctrlEdpInit = 1U; | 203 | numStdModes = sizeof (gDpStdModeInfo) / sizeof (Fvid2_ModeInfo); |
100 | 204 | for (modeCnt = 0U; modeCnt < numStdModes; modeCnt++) | |
101 | /* HPD Pin Mux */ | 205 | { |
102 | CSL_REG32_WR(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_PADCONFIG0 + 0x1c4, 0x00040005); | 206 | if (mInfo->standard == gDpStdModeInfo[modeCnt].standard) |
103 | 207 | { | |
104 | /* Select EDP PHY CLK source */ | 208 | pObj->videoMode.width = gDpStdModeInfo[modeCnt].width; |
105 | CSL_REG32_WR(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_EDP_PHY0_CLKSEL, 0x0); | 209 | pObj->videoMode.height = gDpStdModeInfo[modeCnt].height; |
106 | 210 | pObj->videoMode.hfp = gDpStdModeInfo[modeCnt].hFrontPorch; | |
107 | /* Set DPTX_SRC_CFG, 0:vif0_en, 1:vif_1_en, 2:vif_2_en, 3: vif_3_en, 4: vif_0_sel, TBD */ | 211 | pObj->videoMode.hsw = gDpStdModeInfo[modeCnt].hSyncLen; |
108 | CSL_REG32_WR(CSL_DSS_EDP0_INTG_CFG_VP_BASE + CSL_DPTX_DPTX_SRC_CFG, 0x1F); | 212 | pObj->videoMode.hbp = gDpStdModeInfo[modeCnt].hBackPorch; |
109 | 213 | pObj->videoMode.vfp = gDpStdModeInfo[modeCnt].vFrontPorch; | |
110 | /* WIZ PHY */ | 214 | pObj->videoMode.vsw = gDpStdModeInfo[modeCnt].vSyncLen; |
111 | #define ADDR_AFE (0x05050000) | 215 | pObj->videoMode.vbp = gDpStdModeInfo[modeCnt].vBackPorch; |
112 | CSL_REG32_WR(ADDR_AFE + 0x408, 0x30000000); | 216 | pObj->videoMode.pclk = gDpStdModeInfo[modeCnt].pixelClock; |
113 | CSL_REG32_WR(ADDR_AFE + 0x40c, 0x39000000); | 217 | pObj->videoMode.scanMode = gDpStdModeInfo[modeCnt].scanFormat; |
114 | CSL_REG32_WR(ADDR_AFE + 0x480, 0x70000000); | 218 | break; |
115 | CSL_REG32_WR(ADDR_AFE + 0x4c0, 0x80000000); | 219 | } |
116 | CSL_REG32_WR(ADDR_AFE + 0x500, 0x80000000); | 220 | } |
117 | CSL_REG32_WR(ADDR_AFE + 0x540, 0x80000000); | 221 | if (modeCnt == numStdModes) |
118 | CSL_REG32_WR(ADDR_AFE + 0x484, 0x10001 ); | ||
119 | CSL_REG32_WR(ADDR_AFE + 0x4c4, 0x10001 ); | ||
120 | CSL_REG32_WR(ADDR_AFE + 0x504, 0x10001 ); | ||
121 | CSL_REG32_WR(ADDR_AFE + 0x544, 0x10001 ); | ||
122 | |||
123 | uint32_t memReq, memReqPhy; | ||
124 | DP_Config dpConfig = {.regBase = (struct MHDP_ApbRegs_s *)CSL_DSS_EDP0_V2A_CORE_VP_REGS_APB_BASE, | ||
125 | .regBaseSapb = (struct MHDP_ApbRegs_s *)CSL_DSS_EDP0_V2A_S_CORE_VP_REGS_SAPB_BASE}; | ||
126 | |||
127 | DP_SD0801_Config phyCfg = {.regBase = (uint32_t*)CSL_SERDES_10G0_BASE, | ||
128 | .regBaseDp = (struct DP_Regs_s *)CSL_DSS_EDP0_V2A_CORE_VP_REGS_APB_BASE}; | ||
129 | DP_Probe(&dpConfig, &memReq); | ||
130 | DP_SD0801_Probe(&phyCfg, &memReqPhy); | ||
131 | |||
132 | DP_PrivateData* pD = NULL; | ||
133 | |||
134 | static uint8_t pdMem[STATIC_PD_SIZE] = { 0 }; | ||
135 | volatile uint8_t pdPhyMem[STATIC_PHY_PD_SIZE] = { 0 }; | ||
136 | if ((memReq > sizeof(pdMem)) || (memReqPhy > sizeof(pdPhyMem))) | ||
137 | { | 222 | { |
138 | retVal = FVID2_EFAIL; | 223 | retVal = FVID2_EFAIL; |
139 | } | 224 | } |
225 | } | ||
226 | else | ||
227 | { | ||
228 | pObj->videoMode.width = mInfo->width; | ||
229 | pObj->videoMode.height = mInfo->height; | ||
230 | pObj->videoMode.hfp = mInfo->hFrontPorch; | ||
231 | pObj->videoMode.hsw = mInfo->hSyncLen; | ||
232 | pObj->videoMode.hbp = mInfo->hBackPorch; | ||
233 | pObj->videoMode.vfp = mInfo->vFrontPorch; | ||
234 | pObj->videoMode.vsw = mInfo->vSyncLen; | ||
235 | pObj->videoMode.vbp = mInfo->vBackPorch; | ||
236 | pObj->videoMode.pclk = mInfo->pixelClock; | ||
237 | pObj->videoMode.scanMode = mInfo->scanFormat; | ||
238 | } | ||
140 | 239 | ||
141 | pD = (void*)&pdMem[0]; | 240 | pObj->videoMode.hsyncPol = hsyncPolarity; |
142 | DP_FirmwareImage image = {.iMem = gDctrlDpIram, | 241 | pObj->videoMode.vsyncPol = vsyncPolarity; |
143 | .iMemSize = DCTRL_DP_IMEM_SIZE, | 242 | |
144 | .dMem = gDctrlDpDram, | 243 | /* |
145 | .dMemSize = DCTRL_DP_DMEM_SIZE}; | 244 | * We are supposed to be IDLE when this function is called |
146 | 245 | * | |
147 | if (DP_Init(pD, &dpConfig, &(DP_Callbacks){.event = NULL})) | 246 | * If HPD didnt happen yet, we set to REQUESTED, HDP will |
247 | * start video later if this flag is set, and then set us | ||
248 | * to RUNNING | ||
249 | * | ||
250 | * If HPD happend, and LT was successful, we start video | ||
251 | * and set to RUNNING | ||
252 | * | ||
253 | * If startVideo fails, we stay at REQUESTED. reason: | ||
254 | * startVideo can fail because the connected monitor | ||
255 | * does not support the timings provided. So we hope | ||
256 | * that when another monitor is connected, we are at | ||
257 | * REQUESTED, and HPD takes us to RUNNING | ||
258 | * | ||
259 | * XXX check the timings, match with EDID and print a trace | ||
260 | * accordingly | ||
261 | */ | ||
262 | if((FVID2_SOK == retVal) && | ||
263 | (DP_VIDEO_STATE_IDLE == pObj->videoState)) | ||
264 | { | ||
265 | pObj->videoState = DP_VIDEO_STATE_REQUESTED; | ||
266 | if(TRUE == pObj->isConnected) | ||
148 | { | 267 | { |
149 | retVal = FVID2_EFAIL; | 268 | retVal = Dss_dctrlDrvDpStartVideo(pObj); |
269 | if(FVID2_SOK == retVal) | ||
270 | { | ||
271 | pObj->videoState = DP_VIDEO_STATE_RUNNING; | ||
272 | } | ||
150 | } | 273 | } |
274 | } | ||
151 | 275 | ||
152 | DP_LoadFirmware(pD, &image); | 276 | HwiP_restore(cookie); |
277 | |||
278 | return retVal; | ||
279 | } | ||
280 | |||
281 | int32_t Dss_dctrlDrvInitDp(void) | ||
282 | { | ||
283 | uint32_t retVal = FVID2_SOK; | ||
284 | |||
285 | /* | ||
286 | * XXX push this things to some CSL kind of functions | ||
287 | */ | ||
288 | |||
289 | /* HPD Pin Mux */ | ||
290 | CSL_REG32_WR(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_PADCONFIG0 + 0x1c4, 0x00040005); | ||
291 | |||
292 | /* Select EDP PHY CLK source */ | ||
293 | CSL_REG32_WR(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_EDP_PHY0_CLKSEL, 0x0); | ||
294 | |||
295 | /* Set DPTX_SRC_CFG, 0:vif0_en, 1:vif_1_en, 2:vif_2_en, 3: vif_3_en, 4: vif_0_sel, TBD */ | ||
296 | CSL_REG32_WR(CSL_DSS_EDP0_INTG_CFG_VP_BASE + CSL_DPTX_DPTX_SRC_CFG, 0x1F); | ||
297 | |||
298 | /* WIZ PHY */ | ||
299 | CSL_REG32_WR(ADDR_AFE + 0x408, 0x30000000); | ||
300 | CSL_REG32_WR(ADDR_AFE + 0x40c, 0x39000000); | ||
301 | CSL_REG32_WR(ADDR_AFE + 0x480, 0x70000000); | ||
302 | CSL_REG32_WR(ADDR_AFE + 0x4c0, 0x80000000); | ||
303 | CSL_REG32_WR(ADDR_AFE + 0x500, 0x80000000); | ||
304 | CSL_REG32_WR(ADDR_AFE + 0x540, 0x80000000); | ||
305 | CSL_REG32_WR(ADDR_AFE + 0x484, 0x10001 ); | ||
306 | CSL_REG32_WR(ADDR_AFE + 0x4c4, 0x10001 ); | ||
307 | CSL_REG32_WR(ADDR_AFE + 0x504, 0x10001 ); | ||
308 | CSL_REG32_WR(ADDR_AFE + 0x544, 0x10001 ); | ||
309 | |||
310 | retVal = Dss_dctrlDrvInitDPTX(); | ||
153 | 311 | ||
154 | Dss_dctrlSetDPConfig(&retVal); | ||
155 | } | ||
156 | return retVal; | 312 | return retVal; |
157 | } | 313 | } |
158 | 314 | ||
@@ -160,260 +316,436 @@ int32_t Dss_dctrlDrvProgDP(void) | |||
160 | /* Static Function Definitions */ | 316 | /* Static Function Definitions */ |
161 | /* ========================================================================== */ | 317 | /* ========================================================================== */ |
162 | 318 | ||
163 | static int32_t Dss_dctrlSetDPConfig(int32_t *status) | 319 | |
320 | static void Dss_dctrlDrvDpIntr(uintptr_t arg) | ||
164 | { | 321 | { |
165 | uint32_t ret; | 322 | Dss_DctrlDisplayPortDrvObj *pObj = (Dss_DctrlDisplayPortDrvObj *)arg; |
166 | unsigned char resp; | 323 | uint32_t evt; |
167 | uint8_t echo_msg[] = "echo test"; | 324 | uint32_t retVal; |
168 | uint8_t echo_resp[sizeof(echo_msg) + 1]; | ||
169 | |||
170 | // Set Host capabilities | ||
171 | // Max Link Rate: 06h (1.62Gbps), 0Ah (2.7Gbps), 14h (5.4Gbps), 1Eh // (8.1Gbps) | ||
172 | uint8_t max_link_rate; | ||
173 | |||
174 | // Number of lanes and SSC | ||
175 | uint8_t num_lanes; // number of lanes | ||
176 | |||
177 | // Bits per component (bpc) | ||
178 | uint8_t bits_per_component; | ||
179 | |||
180 | //VIC MODE | ||
181 | uint8_t vicMode; | ||
182 | |||
183 | // Pixel formats: 1 (RGB), 2 (YCbCr444), 3 (YCbCr420) | ||
184 | DP_PixelEncodingFormat pixel_format; | ||
185 | |||
186 | bool aux_hpd; | ||
187 | unsigned int evt; | ||
188 | unsigned char HPDevents; | ||
189 | |||
190 | uint32_t memReq, memReqPhy; | ||
191 | DP_Config dpConfig = {.regBase = (struct MHDP_ApbRegs_s *)CSL_DSS_EDP0_V2A_CORE_VP_REGS_APB_BASE, | ||
192 | .regBaseSapb = (struct MHDP_ApbRegs_s *)CSL_DSS_EDP0_V2A_S_CORE_VP_REGS_SAPB_BASE}; | ||
193 | |||
194 | DP_SD0801_Config phyCfg = {.regBase = (uint32_t*)CSL_SERDES_10G0_BASE, | ||
195 | .regBaseDp = (struct DP_Regs_s *)CSL_DSS_EDP0_V2A_CORE_VP_REGS_APB_BASE}; | ||
196 | |||
197 | DP_PrivateData* pD = NULL; | ||
198 | DP_SD0801_PrivateData* pDPhy = NULL; | ||
199 | static uint8_t pdMem[STATIC_PD_SIZE] = { 0 }; | ||
200 | static uint8_t pdPhyMem[STATIC_PHY_PD_SIZE] = { 0 }; | ||
201 | |||
202 | *status = 0; | ||
203 | |||
204 | num_lanes = 4; | ||
205 | max_link_rate = 3; | ||
206 | pixel_format = (DP_PixelEncodingFormat)1; | ||
207 | bits_per_component = 8; | ||
208 | vicMode = 130; | ||
209 | |||
210 | DP_AudioVideoClkCfg audioVideoClkCfg = { | ||
211 | .videoClockEnable = true, | ||
212 | .audioClockEnable = true, | ||
213 | .pktDataClockEnable = true | ||
214 | }; | ||
215 | |||
216 | DP_VideoParameters videoParams = { | ||
217 | .bitsPerSubpixel = bits_per_component, | ||
218 | .pxEncFormat = pixel_format, | ||
219 | .stereoVidAttr = DP_STEREO_VIDEO_LEFT, | ||
220 | .btType = DP_BT_601, | ||
221 | .forceMiscIgnoreBit = false, | ||
222 | .alignment = DP_ALIGN_MSB, /* TI changed LSB to MSB */ | ||
223 | .dscEnable = 0 | ||
224 | }; | ||
225 | DP_FillVideoFormat(&videoParams.vicParams, (DP_VicModes)vicMode); | ||
226 | |||
227 | DP_SourceDeviceCapabilities sourceCaps = { | ||
228 | .maxLinkRate = (DP_LinkRate)max_link_rate, | ||
229 | .laneCount = num_lanes, | ||
230 | .ssc = false, | ||
231 | .scramblerDisable = false, | ||
232 | .tps3 = true, | ||
233 | .tps4 = true, | ||
234 | .fastLinkTraining = false, | ||
235 | .maxVoltageSwing = 3, | ||
236 | .maxPreemphasis = 2, | ||
237 | .forceVoltageSwing = false, | ||
238 | .forcePreemphasis = false, | ||
239 | .laneMapping = DP_LANE_MAPPING_SINGLE_REGULAR, | ||
240 | .controllersPerPhy = DP_SINGLE_CONTROLLER | ||
241 | }; | ||
242 | |||
243 | DP_Probe(&dpConfig, &memReq); | ||
244 | DP_SD0801_Probe(&phyCfg, &memReqPhy); | ||
245 | if (memReq > sizeof(pdMem)) { | ||
246 | *status = FVID2_EFAIL; | ||
247 | } | ||
248 | if (memReqPhy > sizeof(pdPhyMem)) { | ||
249 | *status = FVID2_EFAIL; | ||
250 | } | ||
251 | pD = (void*)&pdMem[0]; | ||
252 | pDPhy = (void*)&pdPhyMem[0]; | ||
253 | 325 | ||
254 | if (DP_Init(pD, &dpConfig, &(DP_Callbacks){.event = NULL})) { | 326 | retVal = DP_GetEvent(pObj->dpPrivData, &evt); |
255 | *status = FVID2_EFAIL; | 327 | if((CDN_EOK == retVal) && |
256 | } | 328 | (0 != (evt & DP_TX_HPD_EVENT))) |
257 | if (DP_SD0801_Init(pDPhy, &phyCfg)) { | 329 | { |
258 | *status = FVID2_EFAIL; | 330 | SwiP_post(pObj->swiHandle); |
259 | } | ||
260 | if (DP_SetPhyPd(pD, pDPhy)) { | ||
261 | *status = FVID2_EFAIL; | ||
262 | } | 331 | } |
332 | } | ||
263 | 333 | ||
264 | DP_SetClock(pD, &(DP_UcpuClock){.mhz = 125}); | 334 | static void Dss_dctrlDrvDpHpdWork(uintptr_t arg0, uintptr_t arg1) |
335 | { | ||
336 | uint32_t retVal; | ||
337 | uint8_t hpdEvents; | ||
338 | uint32_t cookie; | ||
339 | uint32_t needLinkTraining = FALSE; | ||
340 | Dss_DctrlDisplayPortDrvObj *pObj = (Dss_DctrlDisplayPortDrvObj *)arg0; | ||
341 | DP_TrainingStatus trainingResult; | ||
265 | 342 | ||
266 | // Run CPU | 343 | cookie = HwiP_disable(); |
267 | DP_StartUcpu(pD); | ||
268 | 344 | ||
269 | ret = DP_WaitAlive(pD); | 345 | /* We do not support HPD PULSE yet */ |
270 | if (EOK != ret) | 346 | retVal = DP_ReadHpdEvent(pObj->dpPrivData, &hpdEvents); |
347 | if(CDN_EOK == retVal) | ||
271 | { | 348 | { |
272 | *status = FVID2_EFAIL; | 349 | if((0U != (hpdEvents & DP_HPD_STATE)) && |
350 | (0U != (hpdEvents & DP_HPD_TO_HIGH))) | ||
351 | { | ||
352 | /* we set connected = TRUE if LT passes */ | ||
353 | pObj->isConnected = FALSE; | ||
354 | needLinkTraining = TRUE; | ||
355 | } | ||
356 | else | ||
357 | { | ||
358 | pObj->isConnected = FALSE; | ||
359 | } | ||
273 | } | 360 | } |
274 | 361 | ||
275 | // Activate DisplayPort controller through mailbox | 362 | if((CDN_EOK == retVal) && |
276 | ret = DP_MainControl(pD, 1, &resp); | 363 | (TRUE == needLinkTraining)) |
277 | if (EOK != ret) | ||
278 | { | 364 | { |
279 | *status = FVID2_EFAIL; | 365 | retVal = DP_LinkTraining(pObj->dpPrivData, &trainingResult); |
366 | if ((CDN_EOK == retVal) && | ||
367 | (trainingResult == DP_LT_OK)) | ||
368 | { | ||
369 | pObj->isConnected = TRUE; | ||
370 | } | ||
280 | } | 371 | } |
281 | 372 | ||
282 | ret = DP_TestEchoExt(pD, echo_msg, echo_resp, sizeof(echo_msg), DP_BUS_TYPE_APB); | 373 | /* |
283 | if (EOK != ret) | 374 | * If we just connected, check if REQUESTED or RUNNING |
375 | * | ||
376 | * If RUNNING, then start video | ||
377 | * If startVideo fails, go back to REQUESTED, so that we | ||
378 | * do not do anything unexpected when stopVideo is called | ||
379 | * | ||
380 | * If REQUESTED, then start video, and if it passes, | ||
381 | * set to RUNNING | ||
382 | * | ||
383 | * If we just disconnected, and we were previously RUNNING, | ||
384 | * we set to REQUESTED and stop video | ||
385 | */ | ||
386 | if(TRUE == pObj->isConnected) | ||
387 | { | ||
388 | if((DP_VIDEO_STATE_REQUESTED == pObj->videoState) || | ||
389 | (DP_VIDEO_STATE_RUNNING == pObj->videoState)) | ||
390 | { | ||
391 | retVal = Dss_dctrlDrvDpStartVideo(pObj); | ||
392 | if(FVID2_SOK == retVal) | ||
393 | { | ||
394 | if(DP_VIDEO_STATE_REQUESTED == pObj->videoState) | ||
395 | { | ||
396 | pObj->videoState = DP_VIDEO_STATE_RUNNING; | ||
397 | } | ||
398 | } | ||
399 | else | ||
400 | { | ||
401 | if(DP_VIDEO_STATE_RUNNING == pObj->videoState) | ||
402 | { | ||
403 | pObj->videoState = DP_VIDEO_STATE_REQUESTED; | ||
404 | } | ||
405 | } | ||
406 | } | ||
407 | } | ||
408 | else | ||
284 | { | 409 | { |
285 | *status = FVID2_EFAIL; | 410 | if(DP_VIDEO_STATE_RUNNING == pObj->videoState) |
411 | { | ||
412 | Dss_dctrlDrvDpStopVideo(pObj); | ||
413 | pObj->videoState = DP_VIDEO_STATE_REQUESTED; | ||
414 | } | ||
286 | } | 415 | } |
287 | 416 | ||
417 | HwiP_restore(cookie); | ||
418 | } | ||
288 | 419 | ||
289 | DP_ConfigurePhyAuxCtrl(pD); | 420 | static int32_t Dss_dctrlDrvDpStopVideo(Dss_DctrlDisplayPortDrvObj *pObj) |
421 | { | ||
422 | /* XXX framer off */ | ||
423 | return FVID2_SOK; | ||
424 | } | ||
425 | |||
426 | static int32_t Dss_dctrlDrvDpStartVideo(Dss_DctrlDisplayPortDrvObj *pObj) | ||
427 | { | ||
428 | int32_t retVal = FVID2_SOK; | ||
429 | int32_t dpApiRet = CDN_EOK; | ||
430 | DP_AudioVideoClkCfg clkCfg; | ||
431 | DP_VideoParameters videoParams; | ||
432 | |||
433 | clkCfg.videoClockEnable = true; | ||
434 | clkCfg.audioClockEnable = true; | ||
435 | clkCfg.pktDataClockEnable = true; | ||
436 | |||
437 | videoParams.bitsPerSubpixel = 8; | ||
438 | videoParams.pxEncFormat = DP_PXENC_PXL_RGB; | ||
439 | videoParams.stereoVidAttr = DP_STEREO_VIDEO_LEFT; | ||
440 | videoParams.btType = DP_BT_601; | ||
441 | videoParams.forceMiscIgnoreBit = false; | ||
442 | videoParams.alignment = DP_ALIGN_MSB; | ||
443 | videoParams.dscEnable = 0; | ||
444 | |||
445 | /* fill the ones the driver does not care about */ | ||
446 | videoParams.vicParams.vic = 0U; | ||
447 | videoParams.vicParams.hFreq = 0.0; | ||
448 | videoParams.vicParams.vFreq = 0,0; | ||
449 | videoParams.vicParams.vicR = 0; | ||
450 | videoParams.vicParams.vicPR = 0; | ||
451 | |||
452 | /* and, now the actually important ones */ | ||
453 | videoParams.vicParams.hActive = pObj->videoMode.width; | ||
454 | videoParams.vicParams.hSync = pObj->videoMode.hsw; | ||
455 | videoParams.vicParams.hFrontPorch = pObj->videoMode.hfp; | ||
456 | videoParams.vicParams.hBackPorch = pObj->videoMode.hbp; | ||
457 | videoParams.vicParams.hBlank = pObj->videoMode.hbp + pObj->videoMode.hfp + pObj->videoMode.hsw; | ||
458 | videoParams.vicParams.hTotal = videoParams.vicParams.hBlank + videoParams.vicParams.hActive; | ||
459 | videoParams.vicParams.vActive = pObj->videoMode.height; | ||
460 | videoParams.vicParams.vSync = pObj->videoMode.vsw; | ||
461 | videoParams.vicParams.vFrontPorch = pObj->videoMode.vfp; | ||
462 | videoParams.vicParams.vBackPorch = pObj->videoMode.vbp; | ||
463 | videoParams.vicParams.vBlank = pObj->videoMode.vbp + pObj->videoMode.vfp + pObj->videoMode.vsw; | ||
464 | videoParams.vicParams.vTotal = videoParams.vicParams.vBlank + videoParams.vicParams.vActive; | ||
465 | videoParams.vicParams.pxlFreq = pObj->videoMode.pclk / (float64_t)1000; | ||
466 | videoParams.vicParams.scanMode = ((FVID2_SF_PROGRESSIVE == pObj->videoMode.scanMode) ? DP_SM_PROGRESSIVE : DP_SM_INTERLACED); | ||
467 | videoParams.vicParams.hSyncPolarity = ((FVID2_POL_HIGH == pObj->videoMode.hsyncPol) ? DP_SP_ACTIVE_HIGH : DP_SP_ACTIVE_LOW); | ||
468 | videoParams.vicParams.vSyncPolarity = ((FVID2_POL_HIGH == pObj->videoMode.vsyncPol) ? DP_SP_ACTIVE_HIGH : DP_SP_ACTIVE_LOW); | ||
469 | |||
470 | if(CDN_EOK == dpApiRet) | ||
471 | { | ||
472 | dpApiRet = DP_SetVic(pObj->dpPrivData, 0, &videoParams); | ||
473 | if(CDN_EOK != dpApiRet) | ||
474 | { | ||
475 | GT_0trace(DssTrace, GT_ERR, "error : DP_SetVic\r\n"); | ||
476 | retVal = FVID2_EFAIL; | ||
477 | } | ||
478 | } | ||
479 | |||
480 | if(CDN_EOK == dpApiRet) | ||
481 | { | ||
482 | dpApiRet = DP_SetAudioVideoClkCfg(pObj->dpPrivData, 0, &clkCfg); | ||
483 | if(CDN_EOK != dpApiRet) | ||
484 | { | ||
485 | GT_0trace(DssTrace, GT_ERR, "error : DP_SetAudioVideoClkCfg\r\n"); | ||
486 | retVal = FVID2_EFAIL; | ||
487 | } | ||
488 | } | ||
290 | 489 | ||
291 | do | 490 | if(CDN_EOK == dpApiRet) |
292 | { | 491 | { |
293 | ret = DP_GetEvent(pD, &evt); | 492 | dpApiRet = DP_SetFramerEnable(pObj->dpPrivData, true); |
493 | if(CDN_EOK != dpApiRet) | ||
494 | { | ||
495 | GT_0trace(DssTrace, GT_ERR, "error : DP_SetFramerEnable\r\n"); | ||
496 | retVal = FVID2_EFAIL; | ||
497 | } | ||
294 | } | 498 | } |
295 | while ((evt & 1) == 0); | ||
296 | ret = DP_ReadHpdEvent(pD, &HPDevents); | ||
297 | 499 | ||
298 | if ((ret = DP_GetHpdStatus(pD, &aux_hpd)) != EOK) | 500 | if(CDN_EOK == dpApiRet) |
299 | { | 501 | { |
300 | *status = FVID2_EFAIL; | 502 | dpApiRet = DP_SetVideoSst(pObj->dpPrivData, true); |
503 | if(CDN_EOK != dpApiRet) | ||
504 | { | ||
505 | GT_0trace(DssTrace, GT_ERR, "error : DP_SetVideoSst\r\n"); | ||
506 | retVal = FVID2_EFAIL; | ||
507 | } | ||
301 | } | 508 | } |
302 | 509 | ||
303 | DP_AuxStatus aux_sts; | 510 | return retVal; |
304 | DP_DpcdTransfer transfer = {0}; | 511 | } |
305 | 512 | ||
306 | uint8_t dpcd_resp_buff[16]; | 513 | static int32_t Dss_dctrlDrvInitDPTX(void) |
307 | transfer.buff = dpcd_resp_buff; | 514 | { |
308 | DP_ReadEdidResponse edidResp; | 515 | Dss_DctrlDisplayPortDrvObj *pObj; |
309 | uint8_t edidBuff[128]; | 516 | uint32_t memReqDp, memReqDpPhy; |
310 | edidResp.buff = edidBuff; | 517 | HwiP_Params hwiParams; |
311 | unsigned char cs = 0; | 518 | SwiP_Params swiParams; |
519 | uint32_t dpApiRet; | ||
520 | int32_t retVal = FVID2_SOK; | ||
312 | 521 | ||
313 | // Read 16 bytes of DPCD data from address 0x0000 through AUX interface | 522 | pObj = &gDssDctrlDisplayPortDrvObj; |
314 | // This fields represent the capability of sink device | ||
315 | 523 | ||
316 | transfer.size = 0x10; | 524 | pObj->dpCfg.regBase = (struct MHDP_ApbRegs_s *)CSL_DSS_EDP0_V2A_CORE_VP_REGS_APB_BASE; |
317 | transfer.addr = 0x00; | 525 | pObj->dpCfg.regBaseSapb = (struct MHDP_ApbRegs_s *)CSL_DSS_EDP0_V2A_S_CORE_VP_REGS_SAPB_BASE; |
318 | ret = DP_ReadDpcd(pD, &transfer); | ||
319 | 526 | ||
320 | if (ret != EOK) { | 527 | pObj->dpPhyCfg.regBase = (uint32_t*)CSL_SERDES_10G0_BASE; |
321 | *status = FVID2_EFAIL; | 528 | pObj->dpPhyCfg.regBaseDp = (struct DP_Regs_s *)CSL_DSS_EDP0_V2A_CORE_VP_REGS_APB_BASE; |
322 | } | ||
323 | 529 | ||
324 | // Example response: 12 0a c4 01 00 00 01 00 00 00 00 00 00 02 00 00 | 530 | pObj->dpFWImage.iMem = gDctrlDpIram; |
531 | pObj->dpFWImage.iMemSize = DCTRL_DP_IMEM_SIZE; | ||
532 | pObj->dpFWImage.dMem = gDctrlDpDram; | ||
533 | pObj->dpFWImage.dMemSize = DCTRL_DP_DMEM_SIZE; | ||
325 | 534 | ||
326 | ret = DP_GetAuxStatus(pD, &aux_sts); | 535 | pObj->dpCbInfo.event = NULL; |
327 | if (EOK != ret) | 536 | pObj->dpClkInfo.mhz = 125; |
537 | |||
538 | pObj->srcCaps.maxLinkRate = DP_LINK_RATE_8_10; | ||
539 | pObj->srcCaps.laneCount = 4; | ||
540 | pObj->srcCaps.ssc = false; | ||
541 | pObj->srcCaps.scramblerDisable = false; | ||
542 | pObj->srcCaps.tps3 = true; | ||
543 | pObj->srcCaps.tps4 = true; | ||
544 | pObj->srcCaps.fastLinkTraining = false; | ||
545 | pObj->srcCaps.maxVoltageSwing = 3; | ||
546 | pObj->srcCaps.maxPreemphasis = 3; | ||
547 | pObj->srcCaps.forceVoltageSwing = false; | ||
548 | pObj->srcCaps.forcePreemphasis = false; | ||
549 | pObj->srcCaps.laneMapping = DP_LANE_MAPPING_SINGLE_REGULAR; | ||
550 | pObj->srcCaps.controllersPerPhy = DP_SINGLE_CONTROLLER; | ||
551 | |||
552 | pObj->isConnected = FALSE; | ||
553 | pObj->videoState = DP_VIDEO_STATE_IDLE; | ||
554 | |||
555 | if(FVID2_SOK == retVal) | ||
328 | { | 556 | { |
329 | *status = FVID2_EFAIL; | 557 | dpApiRet = DP_Probe(&pObj->dpCfg, &memReqDp); |
558 | if((CDN_EOK != dpApiRet) || | ||
559 | (memReqDp > DP_PRIVATE_DATA_SIZE)) | ||
560 | { | ||
561 | GT_0trace(DssTrace, GT_ERR, "error : DP_Probe\r\n"); | ||
562 | retVal = FVID2_EFAIL; | ||
563 | } | ||
330 | } | 564 | } |
331 | 565 | ||
332 | // Sink response (0 ACK, 1 NACK, 2 DEFER,3 sink error (when there is no stop | 566 | if(FVID2_SOK == retVal) |
333 | // condition), 4 bus error incorrect bus selected: regular or secure | 567 | { |
334 | 568 | dpApiRet = DP_SD0801_Probe(&pObj->dpPhyCfg, &memReqDpPhy); | |
335 | // Read EDID parameters of sink device through AUX interface | 569 | if ((CDN_EOK != dpApiRet) || |
336 | if ((ret = DP_ReadEdid(pD, 0, 0, &edidResp)) != EOK) { | 570 | (memReqDpPhy > DP_PHY_PRIVATE_DATA_SIZE)) |
337 | *status = FVID2_EFAIL; | 571 | { |
572 | GT_0trace(DssTrace, GT_ERR, "error : DP_SD0801_Probe\r\n"); | ||
573 | retVal = FVID2_EFAIL; | ||
574 | } | ||
338 | } | 575 | } |
339 | 576 | ||
340 | if (edidResp.size < 128) { | 577 | if(FVID2_SOK == retVal) |
341 | *status = FVID2_EFAIL; | 578 | { |
579 | pObj->dpPrivData = (DP_PrivateData *)(&gDssDctrlDisplayPortDpPrivateData[0]); | ||
580 | pObj->dpPhyPrivData = (DP_SD0801_PrivateData *)(&gDssDctrlDisplayPortDpPhyPrivateData[0]); | ||
581 | |||
582 | dpApiRet = DP_Init(pObj->dpPrivData, &pObj->dpCfg, &pObj->dpCbInfo); | ||
583 | if (CDN_EOK != dpApiRet) | ||
584 | { | ||
585 | GT_0trace(DssTrace, GT_ERR, "error : DP_Init\r\n"); | ||
586 | retVal = FVID2_EFAIL; | ||
587 | } | ||
342 | } | 588 | } |
343 | uint32_t i; | 589 | |
344 | for (i = 0; i < edidResp.size; i++) { | 590 | if(FVID2_SOK == retVal) |
345 | cs += edidResp.buff[i]; | 591 | { |
592 | dpApiRet = DP_SD0801_Init(pObj->dpPhyPrivData, &pObj->dpPhyCfg); | ||
593 | if (CDN_EOK != dpApiRet) | ||
594 | { | ||
595 | GT_0trace(DssTrace, GT_ERR, "error : DP_SD0801_Init\r\n"); | ||
596 | retVal = FVID2_EFAIL; | ||
597 | } | ||
346 | } | 598 | } |
347 | 599 | ||
348 | if (cs != 0) { | 600 | if(FVID2_SOK == retVal) |
349 | *status = FVID2_EFAIL; | 601 | { |
602 | dpApiRet = DP_SetPhyPd(pObj->dpPrivData, pObj->dpPhyPrivData); | ||
603 | if (CDN_EOK != dpApiRet) | ||
604 | { | ||
605 | GT_0trace(DssTrace, GT_ERR, "error : DP_SetPhyPd\r\n"); | ||
606 | retVal = FVID2_EFAIL; | ||
607 | } | ||
350 | } | 608 | } |
351 | 609 | ||
352 | if (memcmp("\x00\xff\xff\xff\xff\xff\xff\x00", &edidResp.buff[0], 8) != 0) { | 610 | if(FVID2_SOK == retVal) |
353 | *status = FVID2_EFAIL; | 611 | { |
612 | dpApiRet = DP_LoadFirmware(pObj->dpPrivData, &pObj->dpFWImage); | ||
613 | if (CDN_EOK != dpApiRet) | ||
614 | { | ||
615 | GT_0trace(DssTrace, GT_ERR, "error : DP_LoadFirmware\r\n"); | ||
616 | retVal = FVID2_EFAIL; | ||
617 | } | ||
354 | } | 618 | } |
355 | |||
356 | DP_ConfigurePhyStartUp(pD, num_lanes,(DP_LinkRate)max_link_rate); | ||
357 | 619 | ||
358 | // Settings DisplayPort controller capability | 620 | if(FVID2_SOK == retVal) |
359 | ret = DP_SetSourceCapabilities(pD, &sourceCaps); | ||
360 | if (EOK != ret) | ||
361 | { | 621 | { |
362 | *status = FVID2_EFAIL; | 622 | dpApiRet = DP_SetClock(pObj->dpPrivData, &pObj->dpClkInfo); |
623 | if (CDN_EOK != dpApiRet) | ||
624 | { | ||
625 | GT_0trace(DssTrace, GT_ERR, "error : DP_SetClock\r\n"); | ||
626 | retVal = FVID2_EFAIL; | ||
627 | } | ||
363 | } | 628 | } |
364 | 629 | ||
365 | DP_TrainingStatus trainingResult; | 630 | if(FVID2_SOK == retVal) |
631 | { | ||
632 | dpApiRet = DP_StartUcpu(pObj->dpPrivData); | ||
633 | if(CDN_EOK != dpApiRet) | ||
634 | { | ||
635 | GT_0trace(DssTrace, GT_ERR, "error : DP_StartUcpu\r\n"); | ||
636 | retVal = FVID2_EFAIL; | ||
637 | } | ||
638 | } | ||
366 | 639 | ||
367 | DP_SetPowerMode(pD, DP_POWER_NORMAL_OPERATION); | 640 | if(FVID2_SOK == retVal) |
368 | ret = DP_LinkTraining(pD, &trainingResult); | ||
369 | if (EOK != ret) | ||
370 | { | 641 | { |
371 | *status = FVID2_EFAIL; | 642 | dpApiRet = DP_WaitAlive(pObj->dpPrivData); |
643 | if (CDN_EOK != dpApiRet) | ||
644 | { | ||
645 | GT_0trace(DssTrace, GT_ERR, "error : DP_WaitAlive\r\n"); | ||
646 | retVal = FVID2_EFAIL; | ||
647 | } | ||
372 | } | 648 | } |
373 | switch (trainingResult) { | 649 | |
374 | case DP_LT_OK: | 650 | if(FVID2_SOK == retVal) |
375 | break; | 651 | { |
376 | case DP_LT_CR_FAIL: | 652 | uint8_t mainCtrlResp; |
377 | *status = -1; | 653 | |
378 | break; | 654 | dpApiRet = DP_MainControl(pObj->dpPrivData, true, &mainCtrlResp); |
379 | case DP_LT_EQ_FAIL: | 655 | if (CDN_EOK != dpApiRet) |
380 | *status = -1; | 656 | { |
381 | break; | 657 | GT_0trace(DssTrace, GT_ERR, "error : DP_MainControl\r\n"); |
382 | default: | 658 | retVal = FVID2_EFAIL; |
383 | *status = -1; | 659 | } |
384 | } | 660 | } |
385 | if (0 != *status) | 661 | |
662 | if(FVID2_SOK == retVal) | ||
386 | { | 663 | { |
387 | return -1; | 664 | dpApiRet = DP_ConfigurePhyAuxCtrl(pObj->dpPrivData); |
665 | if (CDN_EOK != dpApiRet) | ||
666 | { | ||
667 | GT_0trace(DssTrace, GT_ERR, "error : DP_ConfigurePhyAuxCtrl\r\n"); | ||
668 | retVal = FVID2_EFAIL; | ||
669 | } | ||
388 | } | 670 | } |
389 | 671 | ||
390 | Osal_delay(1000); | 672 | if(FVID2_SOK == retVal) |
673 | { | ||
674 | dpApiRet = DP_ConfigurePhyStartUp(pObj->dpPrivData, | ||
675 | pObj->srcCaps.laneCount, | ||
676 | pObj->srcCaps.maxLinkRate); | ||
677 | if(CDN_EOK != dpApiRet) | ||
678 | { | ||
679 | GT_0trace(DssTrace, GT_ERR, "error : DP_ConfigurePhyStartUp\r\n"); | ||
680 | retVal = FVID2_EFAIL; | ||
681 | } | ||
682 | } | ||
391 | 683 | ||
392 | ret = DP_SetVic(pD, 0, &videoParams); | 684 | if(FVID2_SOK == retVal) |
393 | if (EOK != ret) | ||
394 | { | 685 | { |
395 | *status = FVID2_EFAIL; | 686 | dpApiRet = DP_SetSourceCapabilities(pObj->dpPrivData, &pObj->srcCaps); |
687 | if (CDN_EOK != dpApiRet) | ||
688 | { | ||
689 | GT_0trace(DssTrace, GT_ERR, "error : DP_SetSourceCapabilities\r\n"); | ||
690 | retVal = FVID2_EFAIL; | ||
691 | } | ||
396 | } | 692 | } |
397 | 693 | ||
398 | ret = DP_SetAudioVideoClkCfg(pD, 0, &audioVideoClkCfg); | 694 | if(FVID2_SOK == retVal) |
399 | if (EOK != ret) { | 695 | { |
400 | *status = FVID2_EFAIL; | 696 | dpApiRet = DP_SetPowerMode(pObj->dpPrivData, DP_POWER_NORMAL_OPERATION); |
697 | if (CDN_EOK != dpApiRet) | ||
698 | { | ||
699 | GT_0trace(DssTrace, GT_ERR, "error : DP_SetPowerMode\r\n"); | ||
700 | retVal = FVID2_EFAIL; | ||
701 | } | ||
401 | } | 702 | } |
402 | 703 | ||
403 | // Enable framer | 704 | if(FVID2_SOK == retVal) |
404 | ret = DP_SetFramerEnable(pD, true); | ||
405 | if (EOK != ret) | ||
406 | { | 705 | { |
407 | *status = FVID2_EFAIL; | 706 | dpApiRet = DP_Start(pObj->dpPrivData); |
707 | if(CDN_EOK != dpApiRet) | ||
708 | { | ||
709 | GT_0trace(DssTrace, GT_ERR, "error : DP_Start\r\n"); | ||
710 | retVal = FVID2_EFAIL; | ||
711 | } | ||
408 | } | 712 | } |
409 | 713 | ||
410 | // Set video on | 714 | if(FVID2_SOK == retVal) |
411 | ret = DP_SetVideoSst(pD, true); | ||
412 | if (EOK != ret) | ||
413 | { | 715 | { |
414 | *status = FVID2_EFAIL; | 716 | SwiP_Params_init(&swiParams); |
717 | swiParams.arg0 = (uintptr_t)pObj; | ||
718 | |||
719 | pObj->swiHandle = SwiP_create(Dss_dctrlDrvDpHpdWork, &swiParams); | ||
720 | |||
721 | if(NULL == pObj->swiHandle) | ||
722 | { | ||
723 | GT_0trace(DssTrace, | ||
724 | GT_ERR, | ||
725 | "Cannot create HPD SWI"); | ||
726 | retVal = FVID2_EALLOC; | ||
727 | } | ||
415 | } | 728 | } |
416 | 729 | ||
417 | return 0; | 730 | if(FVID2_SOK == retVal) |
731 | { | ||
732 | HwiP_clearInterrupt(DP_INTR); | ||
733 | |||
734 | HwiP_Params_init(&hwiParams); | ||
735 | hwiParams.arg = (uintptr_t) pObj; | ||
736 | |||
737 | pObj->intrHandle = HwiP_create(DP_INTR, | ||
738 | &Dss_dctrlDrvDpIntr, | ||
739 | &hwiParams); | ||
418 | 740 | ||
741 | if(NULL == pObj->intrHandle) | ||
742 | { | ||
743 | GT_0trace(DssTrace, | ||
744 | GT_ERR, | ||
745 | "Cannot Register IRQ"); | ||
746 | retVal = FVID2_EALLOC; | ||
747 | } | ||
748 | } | ||
749 | |||
750 | return retVal; | ||
419 | } | 751 | } |
diff --git a/src/drv/dctrl/dss_dctrlPriv.h b/src/drv/dctrl/dss_dctrlPriv.h index 7ab681b..f1692e9 100755 --- a/src/drv/dctrl/dss_dctrlPriv.h +++ b/src/drv/dctrl/dss_dctrlPriv.h | |||
@@ -208,9 +208,14 @@ int32_t Dss_dctrlDrvCreateEdgeList(Dss_DctrlDrvGraphObj *graphObj, | |||
208 | 208 | ||
209 | void Dss_dctrlDrvFreeEdgeList(Dss_DctrlDrvGraphObj *graphObj); | 209 | void Dss_dctrlDrvFreeEdgeList(Dss_DctrlDrvGraphObj *graphObj); |
210 | 210 | ||
211 | int32_t Dss_dctrlDrvProgDP(void); | 211 | #if defined(SOC_J721E) |
212 | int32_t Dss_dctrlDrvDisableVideoDP(void); | ||
213 | int32_t Dss_dctrlDrvEnableVideoDP(const Fvid2_ModeInfo *mInfo, | ||
214 | uint32_t hsyncPolarity, | ||
215 | uint32_t vsyncPolarity); | ||
212 | 216 | ||
213 | uint32_t Dss_dctrlDrvProgDSI(void); | 217 | int32_t Dss_dctrlDrvInitDp(void); |
218 | #endif | ||
214 | 219 | ||
215 | /* ========================================================================== */ | 220 | /* ========================================================================== */ |
216 | /* Static Function Definitions */ | 221 | /* Static Function Definitions */ |