diff options
author | Mahesh Radhakrishnan | 2018-02-26 15:51:20 -0600 |
---|---|---|
committer | Mahesh Radhakrishnan | 2018-02-26 15:51:20 -0600 |
commit | f68baa0cb7818f8783f857f39095a37d93507e66 (patch) | |
tree | 87ec652f39536497859545727f00903d5d58f947 | |
parent | 2ac8da9c1e08394a4b69c288cd221b9d173b0ced (diff) | |
parent | 24cc4bc8763902321b368dbd14207ce8af1ee056 (diff) | |
download | edma3_lld-f68baa0cb7818f8783f857f39095a37d93507e66.tar.gz edma3_lld-f68baa0cb7818f8783f857f39095a37d93507e66.tar.xz edma3_lld-f68baa0cb7818f8783f857f39095a37d93507e66.zip |
Merge pull request #27 in PROCESSOR-SDK/edma3_lld from PRSDK-415 to master
* commit '24cc4bc8763902321b368dbd14207ce8af1ee056':
Removing Extra lines
PRSDK-415 Reverting makefile changes
PRSDK-415 Address review comments
PRSDK-415 Address review comments.
PRSDK-415 Add support to verify allocated PaRAM Id
PRSDK-415: Address review comments
PRSDK-415: Updated config file to be generic
PRSDK-415 Update global cfgparams for AM335x
PRSDK-415 Disabled reserved parameters for AM335x
-rw-r--r-- | examples/edma3_driver/evmAM335x_A8/makefile | 2 | ||||
-rw-r--r-- | examples/edma3_driver/evmAM335x_A8/rtsc_config/edma3_drv_bios6_am335x_a8_st_sample.cfg | 11 | ||||
-rw-r--r-- | examples/edma3_driver/src/dma_poll_test.c | 280 | ||||
-rw-r--r-- | examples/edma3_driver/src/main.c | 77 | ||||
-rwxr-xr-x | packages/ti/sdo/edma3/drv/edma3_drv.h | 29 | ||||
-rwxr-xr-x | packages/ti/sdo/edma3/drv/src/edma3_drv_basic.c | 33 |
6 files changed, 425 insertions, 7 deletions
diff --git a/examples/edma3_driver/evmAM335x_A8/makefile b/examples/edma3_driver/evmAM335x_A8/makefile index 81f63e1..5844f8e 100644 --- a/examples/edma3_driver/evmAM335x_A8/makefile +++ b/examples/edma3_driver/evmAM335x_A8/makefile | |||
@@ -19,7 +19,7 @@ XDC_CFG_FILE_a8host = rtsc_config/edma3_drv_bios6_am335x_a8_st_sample.cfg | |||
19 | SRCS_COMMON = common.c dma_misc_test.c dma_test.c qdma_test.c dma_chain_test.c \ | 19 | SRCS_COMMON = common.c dma_misc_test.c dma_test.c qdma_test.c dma_chain_test.c \ |
20 | dma_ping_pong_test.c main.c dma_link_test.c dma_poll_test.c \ | 20 | dma_ping_pong_test.c main.c dma_link_test.c dma_poll_test.c \ |
21 | qdma_link_test.c | 21 | qdma_link_test.c |
22 | CFLAGS_LOCAL_COMMON = | 22 | CFLAGS_LOCAL_COMMON += -DSOC_AM335x |
23 | 23 | ||
24 | # Core/SoC/platform specific source files and CFLAGS | 24 | # Core/SoC/platform specific source files and CFLAGS |
25 | # Example: | 25 | # Example: |
diff --git a/examples/edma3_driver/evmAM335x_A8/rtsc_config/edma3_drv_bios6_am335x_a8_st_sample.cfg b/examples/edma3_driver/evmAM335x_A8/rtsc_config/edma3_drv_bios6_am335x_a8_st_sample.cfg index a47a178..0825892 100644 --- a/examples/edma3_driver/evmAM335x_A8/rtsc_config/edma3_drv_bios6_am335x_a8_st_sample.cfg +++ b/examples/edma3_driver/evmAM335x_A8/rtsc_config/edma3_drv_bios6_am335x_a8_st_sample.cfg | |||
@@ -12,7 +12,7 @@ var SemihostSupport = xdc.useModule('ti.sysbios.rts.gnu.SemiHostSupport'); | |||
12 | var Program = xdc.useModule("xdc.cfg.Program"); | 12 | var Program = xdc.useModule("xdc.cfg.Program"); |
13 | 13 | ||
14 | /* Heap used when creating semaphore's, TSK's or malloc() ... */ | 14 | /* Heap used when creating semaphore's, TSK's or malloc() ... */ |
15 | Program.heap = 0x1000; | 15 | Program.heap = 0x10000; |
16 | 16 | ||
17 | /* ISR/SWI stack */ | 17 | /* ISR/SWI stack */ |
18 | Program.stack = 0x4000; | 18 | Program.stack = 0x4000; |
@@ -93,3 +93,12 @@ for (var i= 0x49000000; i < 0x490FFFFF; i = i + 0x100000) | |||
93 | Mmu.setFirstLevelDescMeta(i, i, attrs); | 93 | Mmu.setFirstLevelDescMeta(i, i, attrs); |
94 | } | 94 | } |
95 | 95 | ||
96 | /* configure the Peripheral Clock Module memory range */ | ||
97 | var peripheralBaseAddr = 0x44e00400; | ||
98 | |||
99 | attrs.bufferable = false; | ||
100 | attrs.cacheable = false; | ||
101 | /* Configure the corresponding MMU page descriptor for Clock Module */ | ||
102 | Mmu.setFirstLevelDescMeta(peripheralBaseAddr, | ||
103 | peripheralBaseAddr, | ||
104 | attrs); | ||
diff --git a/examples/edma3_driver/src/dma_poll_test.c b/examples/edma3_driver/src/dma_poll_test.c index 948dc1a..fc0f037 100644 --- a/examples/edma3_driver/src/dma_poll_test.c +++ b/examples/edma3_driver/src/dma_poll_test.c | |||
@@ -7,7 +7,7 @@ | |||
7 | * to check the status of ongoing transfer. Interrupt will NOT occur in this | 7 | * to check the status of ongoing transfer. Interrupt will NOT occur in this |
8 | * case. | 8 | * case. |
9 | * | 9 | * |
10 | * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ | 10 | * Copyright (C) 2009-2018 Texas Instruments Incorporated - http://www.ti.com/ |
11 | * | 11 | * |
12 | * | 12 | * |
13 | * Redistribution and use in source and binary forms, with or without | 13 | * Redistribution and use in source and binary forms, with or without |
@@ -48,6 +48,7 @@ extern signed char _dstBuff1[MAX_BUFFER_SIZE]; | |||
48 | extern signed char *srcBuff1; | 48 | extern signed char *srcBuff1; |
49 | extern signed char *dstBuff1; | 49 | extern signed char *dstBuff1; |
50 | 50 | ||
51 | #define EDMA3_DRV_DMA_CHANNEL_USR_REQ (10) | ||
51 | /** | 52 | /** |
52 | * \brief EDMA3 mem-to-mem data copy test case, using a DMA channel. | 53 | * \brief EDMA3 mem-to-mem data copy test case, using a DMA channel. |
53 | * This test case doesnot rely on the callback mechanism. | 54 | * This test case doesnot rely on the callback mechanism. |
@@ -78,6 +79,9 @@ EDMA3_DRV_Result edma3_test_poll_mode( | |||
78 | uint32_t BRCnt = 0; | 79 | uint32_t BRCnt = 0; |
79 | int srcbidx = 0, desbidx = 0; | 80 | int srcbidx = 0, desbidx = 0; |
80 | int srccidx = 0, descidx = 0; | 81 | int srccidx = 0, descidx = 0; |
82 | #ifdef EDMA3_RES_USER_REQ | ||
83 | uint32_t paRAMId = 0; | ||
84 | #endif | ||
81 | 85 | ||
82 | 86 | ||
83 | srcBuff1 = (signed char*) GLOBAL_ADDR(_srcBuff1); | 87 | srcBuff1 = (signed char*) GLOBAL_ADDR(_srcBuff1); |
@@ -139,7 +143,6 @@ EDMA3_DRV_Result edma3_test_poll_mode( | |||
139 | tcc = EDMA3_DRV_TCC_ANY; | 143 | tcc = EDMA3_DRV_TCC_ANY; |
140 | chId = EDMA3_DRV_DMA_CHANNEL_ANY; | 144 | chId = EDMA3_DRV_DMA_CHANNEL_ANY; |
141 | 145 | ||
142 | |||
143 | /* Request any DMA channel and any TCC */ | 146 | /* Request any DMA channel and any TCC */ |
144 | if (result == EDMA3_DRV_SOK) | 147 | if (result == EDMA3_DRV_SOK) |
145 | { | 148 | { |
@@ -298,3 +301,276 @@ EDMA3_DRV_Result edma3_test_poll_mode( | |||
298 | } | 301 | } |
299 | return result; | 302 | return result; |
300 | } | 303 | } |
304 | |||
305 | |||
306 | /** | ||
307 | * \brief EDMA3 mem-to-mem data copy test case with user requested paRAMId | ||
308 | * using a DMA channel. | ||
309 | * This test case doesnot rely on the callback mechanism. | ||
310 | * Instead, it Polls the IPR register to check the transfer | ||
311 | * completion status. | ||
312 | * | ||
313 | * \param edma3Instance [IN] EDMA3 Instance number | ||
314 | * \param acnt [IN] Number of bytes in an array | ||
315 | * \param bcnt [IN] Number of arrays in a frame | ||
316 | * \param ccnt [IN] Number of frames in a block | ||
317 | * \param syncType [IN] Synchronization type (A/AB Sync) | ||
318 | * | ||
319 | * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code | ||
320 | */ | ||
321 | EDMA3_DRV_Result edma3_test_user_req_paRAMId( | ||
322 | EDMA3_DRV_Handle hEdma, | ||
323 | uint32_t edmaInstance, | ||
324 | uint32_t acnt, | ||
325 | uint32_t bcnt, | ||
326 | uint32_t ccnt, | ||
327 | EDMA3_DRV_SyncType syncType) | ||
328 | { | ||
329 | EDMA3_DRV_Result result = EDMA3_DRV_SOK; | ||
330 | uint32_t chId = 0; | ||
331 | uint32_t tcc = 0; | ||
332 | int i; | ||
333 | uint32_t count; | ||
334 | uint32_t Istestpassed = 0u; | ||
335 | uint32_t numenabled = 0; | ||
336 | uint32_t BRCnt = 0; | ||
337 | int srcbidx = 0, desbidx = 0; | ||
338 | int srccidx = 0, descidx = 0; | ||
339 | uint32_t paRAMId = 0; | ||
340 | |||
341 | |||
342 | srcBuff1 = (signed char*) GLOBAL_ADDR(_srcBuff1); | ||
343 | dstBuff1 = (signed char*) GLOBAL_ADDR(_dstBuff1); | ||
344 | |||
345 | /* Initalize source and destination buffers */ | ||
346 | for (count = 0u; count < (acnt*bcnt*ccnt); count++) | ||
347 | { | ||
348 | srcBuff1[count] = (int)count+5; | ||
349 | /** | ||
350 | * No need to initialize the destination buffer as it is being invalidated. | ||
351 | dstBuff1[count] = initval; | ||
352 | */ | ||
353 | } | ||
354 | |||
355 | #ifdef EDMA3_ENABLE_DCACHE | ||
356 | /* | ||
357 | * Note: These functions are required if the buffer is in DDR. | ||
358 | * For other cases, where buffer is NOT in DDR, user | ||
359 | * may or may not require the below functions. | ||
360 | */ | ||
361 | /* Flush the Source Buffer */ | ||
362 | if (result == EDMA3_DRV_SOK) | ||
363 | { | ||
364 | result = Edma3_CacheFlush((uint32_t)srcBuff1, (acnt*bcnt*ccnt)); | ||
365 | } | ||
366 | |||
367 | /* Invalidate the Destination Buffer */ | ||
368 | if (result == EDMA3_DRV_SOK) | ||
369 | { | ||
370 | result = Edma3_CacheInvalidate((uint32_t)dstBuff1, (acnt*bcnt*ccnt)); | ||
371 | } | ||
372 | #endif /* EDMA3_ENABLE_DCACHE */ | ||
373 | |||
374 | |||
375 | /* Set B count reload as B count. */ | ||
376 | BRCnt = bcnt; | ||
377 | |||
378 | /* Setting up the SRC/DES Index */ | ||
379 | srcbidx = (int)acnt; | ||
380 | desbidx = (int)acnt; | ||
381 | |||
382 | if (syncType == EDMA3_DRV_SYNC_A) | ||
383 | { | ||
384 | /* A Sync Transfer Mode */ | ||
385 | srccidx = (int)acnt; | ||
386 | descidx = (int)acnt; | ||
387 | } | ||
388 | else | ||
389 | { | ||
390 | /* AB Sync Transfer Mode */ | ||
391 | srccidx = ((int)acnt * (int)bcnt); | ||
392 | descidx = ((int)acnt * (int)bcnt); | ||
393 | } | ||
394 | |||
395 | |||
396 | /* Setup for Channel 1*/ | ||
397 | tcc = EDMA3_DRV_TCC_ANY; | ||
398 | |||
399 | chId = EDMA3_DRV_DMA_CHANNEL_USR_REQ; | ||
400 | |||
401 | /* Request any DMA channel and any TCC */ | ||
402 | if (result == EDMA3_DRV_SOK) | ||
403 | { | ||
404 | result = EDMA3_DRV_requestChannel (hEdma, &chId, &tcc, | ||
405 | (EDMA3_RM_EventQueue)0, | ||
406 | NULL, NULL); | ||
407 | |||
408 | result = EDMA3_DRV_getAllocatedPARAMId(hEdma, chId, &paRAMId); | ||
409 | if(result == EDMA3_DRV_SOK) | ||
410 | { | ||
411 | printf("\nReserved Channel ID Test\n"); | ||
412 | printf ("The Requested Channel ID: %d \nThe allocated PARAM Id:%d\n",chId,paRAMId); | ||
413 | |||
414 | if (chId == paRAMId) | ||
415 | { | ||
416 | printf("The Requested Param ID is allocated for the given Channel\n"); | ||
417 | } | ||
418 | else | ||
419 | { | ||
420 | printf("The Requested Param ID is not allocated as same as the DMA channel\n"); | ||
421 | result = EDMA3_DATA_MISMATCH_ERROR; | ||
422 | } | ||
423 | printf("\n"); | ||
424 | } | ||
425 | } | ||
426 | |||
427 | if (result == EDMA3_DRV_SOK) | ||
428 | { | ||
429 | result = EDMA3_DRV_setSrcParams (hEdma, chId, (uint32_t)(srcBuff1), | ||
430 | EDMA3_DRV_ADDR_MODE_INCR, | ||
431 | EDMA3_DRV_W8BIT); | ||
432 | } | ||
433 | |||
434 | if (result == EDMA3_DRV_SOK) | ||
435 | { | ||
436 | result = EDMA3_DRV_setDestParams (hEdma, chId, (uint32_t)(dstBuff1), | ||
437 | EDMA3_DRV_ADDR_MODE_INCR, | ||
438 | EDMA3_DRV_W8BIT); | ||
439 | } | ||
440 | |||
441 | if (result == EDMA3_DRV_SOK) | ||
442 | { | ||
443 | result = EDMA3_DRV_setSrcIndex (hEdma, chId, srcbidx, srccidx); | ||
444 | } | ||
445 | |||
446 | if (result == EDMA3_DRV_SOK) | ||
447 | { | ||
448 | result = EDMA3_DRV_setDestIndex (hEdma, chId, desbidx, descidx); | ||
449 | } | ||
450 | |||
451 | if (result == EDMA3_DRV_SOK) | ||
452 | { | ||
453 | if (syncType == EDMA3_DRV_SYNC_A) | ||
454 | { | ||
455 | result = EDMA3_DRV_setTransferParams (hEdma, chId, acnt, bcnt, ccnt, | ||
456 | BRCnt, EDMA3_DRV_SYNC_A); | ||
457 | } | ||
458 | else | ||
459 | { | ||
460 | result = EDMA3_DRV_setTransferParams (hEdma, chId, acnt, bcnt, ccnt, | ||
461 | BRCnt, EDMA3_DRV_SYNC_AB); | ||
462 | } | ||
463 | } | ||
464 | |||
465 | if (result == EDMA3_DRV_SOK) | ||
466 | { | ||
467 | result = EDMA3_DRV_setOptField (hEdma, chId, | ||
468 | EDMA3_DRV_OPT_FIELD_TCINTEN, 1u); | ||
469 | } | ||
470 | |||
471 | if (result == EDMA3_DRV_SOK) | ||
472 | { | ||
473 | result = EDMA3_DRV_setOptField (hEdma, chId, | ||
474 | EDMA3_DRV_OPT_FIELD_ITCINTEN, 1u); | ||
475 | } | ||
476 | |||
477 | /* | ||
478 | * Since the transfer is going to happen in Manual mode of EDMA3 | ||
479 | * operation, we have to 'Enable the Transfer' multiple times. | ||
480 | * Number of times depends upon the Mode (A/AB Sync) | ||
481 | * and the different counts. | ||
482 | */ | ||
483 | if (result == EDMA3_DRV_SOK) | ||
484 | { | ||
485 | /*Need to activate next param*/ | ||
486 | if (syncType == EDMA3_DRV_SYNC_A) | ||
487 | { | ||
488 | numenabled = bcnt * ccnt; | ||
489 | } | ||
490 | else | ||
491 | { | ||
492 | /* AB Sync Transfer Mode */ | ||
493 | numenabled = ccnt; | ||
494 | } | ||
495 | |||
496 | |||
497 | for (i = 0; i < numenabled; i++) | ||
498 | { | ||
499 | /* | ||
500 | * Now enable the transfer as many times as calculated above. | ||
501 | */ | ||
502 | result = EDMA3_DRV_enableTransfer (hEdma, chId, | ||
503 | EDMA3_DRV_TRIG_MODE_MANUAL); | ||
504 | if (result != EDMA3_DRV_SOK) | ||
505 | { | ||
506 | #ifdef EDMA3_DRV_DEBUG | ||
507 | EDMA3_DRV_PRINTF ("edma3_test_user_req_paRAMId: EDMA3_DRV_enableTransfer " \ | ||
508 | "Failed, error code: %d\r\n", result); | ||
509 | #endif /* EDMA3_DRV_DEBUG */ | ||
510 | break; | ||
511 | } | ||
512 | |||
513 | |||
514 | /* Wait for the Completion Bit to be SET in the IPR/IPRH register. */ | ||
515 | result = EDMA3_DRV_waitAndClearTcc (hEdma, tcc); | ||
516 | if (result != EDMA3_DRV_SOK) | ||
517 | { | ||
518 | #ifdef EDMA3_DRV_DEBUG | ||
519 | EDMA3_DRV_PRINTF ("edma3_test_user_req_paRAMId: EDMA3_DRV_waitAndClearTcc " \ | ||
520 | "Failed, error code: %d\r\n", result); | ||
521 | #endif /* EDMA3_DRV_DEBUG */ | ||
522 | break; | ||
523 | } | ||
524 | } | ||
525 | } | ||
526 | |||
527 | |||
528 | /* Match the Source and Destination Buffers. */ | ||
529 | if (EDMA3_DRV_SOK == result) | ||
530 | { | ||
531 | for (i = 0; i < (acnt*bcnt*ccnt); i++) | ||
532 | { | ||
533 | if (srcBuff1[i] != dstBuff1[i]) | ||
534 | { | ||
535 | Istestpassed = 0u; | ||
536 | #ifdef EDMA3_DRV_DEBUG | ||
537 | EDMA3_DRV_PRINTF("edma3_test_user_req_paRAMId: Data write-read matching" \ | ||
538 | "FAILED at i = %d\r\n", i); | ||
539 | #endif /* EDMA3_DRV_DEBUG */ | ||
540 | break; | ||
541 | } | ||
542 | } | ||
543 | if (i == (acnt*bcnt*ccnt)) | ||
544 | { | ||
545 | Istestpassed = 1u; | ||
546 | } | ||
547 | |||
548 | |||
549 | /* Free the previously allocated channel. */ | ||
550 | result = EDMA3_DRV_freeChannel (hEdma, chId); | ||
551 | if (result != EDMA3_DRV_SOK) | ||
552 | { | ||
553 | #ifdef EDMA3_DRV_DEBUG | ||
554 | EDMA3_DRV_PRINTF("edma3_test_user_req_paRAMId: EDMA3_DRV_freeChannel() FAILED, " \ | ||
555 | "error code: %d\r\n", result); | ||
556 | #endif /* EDMA3_DRV_DEBUG */ | ||
557 | } | ||
558 | } | ||
559 | |||
560 | |||
561 | if(Istestpassed == 1u) | ||
562 | { | ||
563 | #ifdef EDMA3_DRV_DEBUG | ||
564 | EDMA3_DRV_PRINTF("edma3_test_user_req_paRAMId PASSED\r\n"); | ||
565 | #endif /* EDMA3_DRV_DEBUG */ | ||
566 | } | ||
567 | else | ||
568 | { | ||
569 | #ifdef EDMA3_DRV_DEBUG | ||
570 | EDMA3_DRV_PRINTF("edma3_test_user_req_paRAMId FAILED\r\n"); | ||
571 | #endif /* EDMA3_DRV_DEBUG */ | ||
572 | result = ((EDMA3_DRV_SOK == result) ? | ||
573 | EDMA3_DATA_MISMATCH_ERROR : result); | ||
574 | } | ||
575 | return result; | ||
576 | } | ||
diff --git a/examples/edma3_driver/src/main.c b/examples/edma3_driver/src/main.c index a6d37c6..37796a6 100644 --- a/examples/edma3_driver/src/main.c +++ b/examples/edma3_driver/src/main.c | |||
@@ -4,7 +4,7 @@ | |||
4 | * This file contains the test / demo code to demonstrate the EDMA3 driver | 4 | * This file contains the test / demo code to demonstrate the EDMA3 driver |
5 | * functionality on DSP/BIOS 6. | 5 | * functionality on DSP/BIOS 6. |
6 | * | 6 | * |
7 | * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ | 7 | * Copyright (C) 2009-2018 Texas Instruments Incorporated - http://www.ti.com/ |
8 | * | 8 | * |
9 | * | 9 | * |
10 | * Redistribution and use in source and binary forms, with or without | 10 | * Redistribution and use in source and binary forms, with or without |
@@ -50,6 +50,19 @@ extern far const uint32_t numEdma3Instances; | |||
50 | extern const uint32_t numEdma3Instances; | 50 | extern const uint32_t numEdma3Instances; |
51 | #endif | 51 | #endif |
52 | 52 | ||
53 | #ifdef SOC_AM335x | ||
54 | #define WR_MEM_32(addr, data) *(unsigned int*)(addr) = (unsigned int)(data) | ||
55 | |||
56 | #define PRCM_BASE_ADDR (0x44E00000) | ||
57 | #define CM_PER_TPTC0_CLKCTRL (PRCM_BASE_ADDR +0x0024) | ||
58 | #define CM_PER_TPCC_CLKCTRL (PRCM_BASE_ADDR +0x00BC) | ||
59 | #define CM_PER_TPTC1_CLKCTRL (PRCM_BASE_ADDR +0x00FC) | ||
60 | #define CM_PER_TPTC2_CLKCTRL (PRCM_BASE_ADDR +0x0100) | ||
61 | |||
62 | /*To enable EDMA3 Clock Module */ | ||
63 | static void edma3PRCMEnable(); | ||
64 | #endif | ||
65 | |||
53 | /** | 66 | /** |
54 | * DSP instance number on which the executable is running. Its value is | 67 | * DSP instance number on which the executable is running. Its value is |
55 | * determined by reading the processor specific register DNUM. | 68 | * determined by reading the processor specific register DNUM. |
@@ -156,11 +169,17 @@ void echo() | |||
156 | EDMA3_DRV_Result edmaResult = EDMA3_DRV_SOK; | 169 | EDMA3_DRV_Result edmaResult = EDMA3_DRV_SOK; |
157 | uint32_t i, bypass; | 170 | uint32_t i, bypass; |
158 | uint32_t count=0; | 171 | uint32_t count=0; |
172 | uint32_t edmaInstance = 0; | ||
159 | EDMA3_DRV_Handle hEdma[MAX_NUM_EDMA_INSTANCES]; | 173 | EDMA3_DRV_Handle hEdma[MAX_NUM_EDMA_INSTANCES]; |
174 | EDMA3_DRV_Handle hndEdma = NULL; | ||
160 | Semaphore_Params semParams; | 175 | Semaphore_Params semParams; |
161 | 176 | ||
162 | memset(hEdma,0,sizeof(hEdma)); | 177 | memset(hEdma,0,sizeof(hEdma)); |
163 | 178 | ||
179 | #ifdef SOC_AM335x | ||
180 | edma3PRCMEnable(); | ||
181 | #endif | ||
182 | |||
164 | /* Print the Welcome Message */ | 183 | /* Print the Welcome Message */ |
165 | printWelcomeBanner(); | 184 | printWelcomeBanner(); |
166 | 185 | ||
@@ -301,6 +320,51 @@ void echo() | |||
301 | } | 320 | } |
302 | } | 321 | } |
303 | 322 | ||
323 | /* Mapping DMA channels to corresponding paRAM Id. The user can request for | ||
324 | * any DAM channel to map with the paRAM Id as same as the channel number | ||
325 | */ | ||
326 | for (count = 0u; count < EDMA3_MAX_DMA_CH; count++) | ||
327 | { | ||
328 | sampleEdma3GblCfgParams[edmaInstance].dmaChannelPaRAMMap[count] = count; | ||
329 | } | ||
330 | |||
331 | /*EDMA3 Initialization*/ | ||
332 | hndEdma = edma3init(edmaInstance, &edmaResult); | ||
333 | if (hndEdma) | ||
334 | { | ||
335 | printf("edma3init() Passed\n"); | ||
336 | } | ||
337 | else | ||
338 | { | ||
339 | printf("edma3init() Failed, error code: %d\n", (int)edmaResult); | ||
340 | } | ||
341 | |||
342 | /* User request PaRAMId test */ | ||
343 | if (edmaResult == EDMA3_DRV_SOK) | ||
344 | { | ||
345 | edmaResult = edma3_test_user_req_paRAMId(hndEdma, edmaInstance, | ||
346 | MAX_ACOUNT, MAX_BCOUNT, MAX_CCOUNT, EDMA3_DRV_SYNC_A); | ||
347 | } | ||
348 | |||
349 | if (edmaResult == EDMA3_DRV_SOK) | ||
350 | { | ||
351 | printf ("edma3_test_user_req_paRAMId Passed\r\n"); | ||
352 | } | ||
353 | else | ||
354 | { | ||
355 | printf ("edma3_test_user_req_paRAMId Failed\r\n"); | ||
356 | } | ||
357 | |||
358 | /*EDMA3 deinitialization */ | ||
359 | edmaResult = edma3deinit(edmaInstance, hndEdma); | ||
360 | if (edmaResult != EDMA3_DRV_SOK) | ||
361 | { | ||
362 | printf("edma3deinit() Failed, error code: %d\n", (int)edmaResult); | ||
363 | } | ||
364 | else | ||
365 | { | ||
366 | printf("edma3deinit() Passed\n"); | ||
367 | } | ||
304 | /* Start the Heart Beat Print */ | 368 | /* Start the Heart Beat Print */ |
305 | tskHeartBit(); | 369 | tskHeartBit(); |
306 | 370 | ||
@@ -459,3 +523,14 @@ void tskHeartBit() | |||
459 | counter++; | 523 | counter++; |
460 | } | 524 | } |
461 | } | 525 | } |
526 | |||
527 | #ifdef SOC_AM335x | ||
528 | /*To enable EDMA3 Clock Module of AM335x*/ | ||
529 | static void edma3PRCMEnable() | ||
530 | { | ||
531 | WR_MEM_32(CM_PER_TPCC_CLKCTRL, 2); | ||
532 | WR_MEM_32(CM_PER_TPTC0_CLKCTRL , 2); | ||
533 | WR_MEM_32(CM_PER_TPTC1_CLKCTRL , 2); | ||
534 | WR_MEM_32(CM_PER_TPTC2_CLKCTRL , 2); | ||
535 | } | ||
536 | #endif | ||
diff --git a/packages/ti/sdo/edma3/drv/edma3_drv.h b/packages/ti/sdo/edma3/drv/edma3_drv.h index 2c77bf8..a6040c5 100755 --- a/packages/ti/sdo/edma3/drv/edma3_drv.h +++ b/packages/ti/sdo/edma3/drv/edma3_drv.h | |||
@@ -5,7 +5,7 @@ | |||
5 | * uses the EDMA3 Resource Manager internally for resource allocation, interrupt | 5 | * uses the EDMA3 Resource Manager internally for resource allocation, interrupt |
6 | * handling and EDMA3 registers programming. | 6 | * handling and EDMA3 registers programming. |
7 | * | 7 | * |
8 | * Copyright (C) 2009-2013 Texas Instruments Incorporated - http://www.ti.com/ | 8 | * Copyright (C) 2009-2018 Texas Instruments Incorporated - http://www.ti.com/ |
9 | * | 9 | * |
10 | * | 10 | * |
11 | * Redistribution and use in source and binary forms, with or without | 11 | * Redistribution and use in source and binary forms, with or without |
@@ -3152,6 +3152,33 @@ EDMA3_DRV_Result EDMA3_DRV_initXbarEventMap (EDMA3_DRV_Handle hEdma, | |||
3152 | EDMA3_DRV_mapXbarEvtToChan mapXbarEvtFunc, | 3152 | EDMA3_DRV_mapXbarEvtToChan mapXbarEvtFunc, |
3153 | EDMA3_DRV_xbarConfigScr configXbarScr); | 3153 | EDMA3_DRV_xbarConfigScr configXbarScr); |
3154 | 3154 | ||
3155 | /** | ||
3156 | * \brief Returns the PARAM ID recently allocated for an EDMA channel | ||
3157 | * | ||
3158 | * This API will return the PARAM Id recently allocated by the EDMA3 | ||
3159 | * resource manager for a requested DMA channel | ||
3160 | * | ||
3161 | * This function can be called by the application after | ||
3162 | * the EDMA3_DRV_requestChannel() function is invoked to check the | ||
3163 | * allocated PaRAM Id for a requested channel if needed. | ||
3164 | * | ||
3165 | * \param hEdma [IN] Handle to the EDMA Driver Instance. | ||
3166 | * \param channelId [IN] DMA channel for which the PaRAMId | ||
3167 | * needs to be returned. | ||
3168 | * \param paRAMId [OUT] Return the paRAMId of which the | ||
3169 | * channel Id is mapped. | ||
3170 | * | ||
3171 | * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code | ||
3172 | * | ||
3173 | * \note This function is used to verify the requested DMA channel | ||
3174 | * is allocated/mapped with the PaRAM Id same as DMA channel number. | ||
3175 | * This function is not necessarily be used(invoked) for | ||
3176 | * any other general functionality. | ||
3177 | * | ||
3178 | */ | ||
3179 | EDMA3_DRV_Result EDMA3_DRV_getAllocatedPARAMId(EDMA3_DRV_Handle hEdma, | ||
3180 | uint32_t channelId, uint32_t *paRAMId); | ||
3181 | |||
3155 | 3182 | ||
3156 | 3183 | ||
3157 | /** | 3184 | /** |
diff --git a/packages/ti/sdo/edma3/drv/src/edma3_drv_basic.c b/packages/ti/sdo/edma3/drv/src/edma3_drv_basic.c index 1070973..fe00bb5 100755 --- a/packages/ti/sdo/edma3/drv/src/edma3_drv_basic.c +++ b/packages/ti/sdo/edma3/drv/src/edma3_drv_basic.c | |||
@@ -12,7 +12,7 @@ | |||
12 | * beyond this and have complete control on the EDMA3 hardware are advised | 12 | * beyond this and have complete control on the EDMA3 hardware are advised |
13 | * to refer edma3_drv_adv.c source file. | 13 | * to refer edma3_drv_adv.c source file. |
14 | * | 14 | * |
15 | * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ | 15 | * Copyright (C) 2009-2018 Texas Instruments Incorporated - http://www.ti.com/ |
16 | * | 16 | * |
17 | * | 17 | * |
18 | * Redistribution and use in source and binary forms, with or without | 18 | * Redistribution and use in source and binary forms, with or without |
@@ -2273,6 +2273,37 @@ EDMA3_DRV_Result EDMA3_DRV_disableLogicalChannel (EDMA3_DRV_Handle hEdma, | |||
2273 | return result; | 2273 | return result; |
2274 | } | 2274 | } |
2275 | 2275 | ||
2276 | /** Return the Param ID recently allocated for an EDMA request*/ | ||
2277 | EDMA3_DRV_Result EDMA3_DRV_getAllocatedPARAMId(EDMA3_DRV_Handle hEdma, | ||
2278 | uint32_t channelId, uint32_t *paRAMId) | ||
2279 | { | ||
2280 | uint32_t edma3Id = 0; | ||
2281 | EDMA3_DRV_Instance *drvInst = NULL; | ||
2282 | EDMA3_DRV_Object *drvObject = NULL; | ||
2283 | EDMA3_DRV_Result result = EDMA3_DRV_SOK; | ||
2284 | |||
2285 | drvInst = (EDMA3_DRV_Instance *)hEdma; | ||
2286 | drvObject = drvInst->pDrvObjectHandle; | ||
2287 | |||
2288 | if (drvObject == NULL) | ||
2289 | { | ||
2290 | result = EDMA3_DRV_E_INVALID_PARAM; | ||
2291 | } | ||
2292 | |||
2293 | if (EDMA3_DRV_SOK == result) | ||
2294 | { | ||
2295 | edma3Id = drvObject->phyCtrllerInstId; | ||
2296 | } | ||
2297 | else | ||
2298 | { | ||
2299 | result = EDMA3_DRV_E_INVALID_PARAM; | ||
2300 | } | ||
2301 | |||
2302 | *paRAMId = edma3DrvChBoundRes[edma3Id][channelId].paRAMId; | ||
2303 | |||
2304 | return result; | ||
2305 | } | ||
2306 | |||
2276 | /* Definitions of Local functions - Start */ | 2307 | /* Definitions of Local functions - Start */ |
2277 | /** Remove various mappings and do cleanup for DMA/QDMA channels */ | 2308 | /** Remove various mappings and do cleanup for DMA/QDMA channels */ |
2278 | static EDMA3_DRV_Result edma3RemoveMapping (EDMA3_DRV_Handle hEdma, | 2309 | static EDMA3_DRV_Result edma3RemoveMapping (EDMA3_DRV_Handle hEdma, |