Merge pull request #27 in PROCESSOR-SDK/edma3_lld from PRSDK-415 to master

* commit '24cc4bc8763902321b368dbd14207ce8af1ee056':
  Removing Extra lines
  PRSDK-415 Reverting makefile changes
  PRSDK-415 Address review comments
  PRSDK-415 Address review comments.
  PRSDK-415 Add support to verify allocated PaRAM Id
  PRSDK-415: Address review comments
  PRSDK-415: Updated config file to be generic
  PRSDK-415 Update global cfgparams for AM335x
  PRSDK-415 Disabled reserved parameters for AM335x

6 files changed, 425 insertions, 7 deletions

diff --git a/examples/edma3_driver/evmAM335x_A8/makefile b/examples/edma3_driver/evmAM335x_A8/makefile
index 81f63e1..5844f8e 100644
--- a/examples/edma3_driver/evmAM335x_A8/makefile
+++ b/examples/edma3_driver/evmAM335x_A8/makefile
@@ -19,7 +19,7 @@ XDC_CFG_FILE_a8host = rtsc_config/edma3_drv_bios6_am335x_a8_st_sample.cfg
 SRCS_COMMON = common.c dma_misc_test.c dma_test.c qdma_test.c dma_chain_test.c \
               dma_ping_pong_test.c main.c dma_link_test.c dma_poll_test.c      \
               qdma_link_test.c
-CFLAGS_LOCAL_COMMON =
+CFLAGS_LOCAL_COMMON += -DSOC_AM335x
 
 # Core/SoC/platform specific source files and CFLAGS
 # Example:
diff --git a/examples/edma3_driver/evmAM335x_A8/rtsc_config/edma3_drv_bios6_am335x_a8_st_sample.cfg b/examples/edma3_driver/evmAM335x_A8/rtsc_config/edma3_drv_bios6_am335x_a8_st_sample.cfg
index a47a178..0825892 100644
--- a/examples/edma3_driver/evmAM335x_A8/rtsc_config/edma3_drv_bios6_am335x_a8_st_sample.cfg
+++ b/examples/edma3_driver/evmAM335x_A8/rtsc_config/edma3_drv_bios6_am335x_a8_st_sample.cfg
@@ -12,7 +12,7 @@ var SemihostSupport = xdc.useModule('ti.sysbios.rts.gnu.SemiHostSupport');
 var Program     = xdc.useModule("xdc.cfg.Program");

 

 /* Heap used when creating semaphore's, TSK's or malloc() ... */

-Program.heap            = 0x1000;

+Program.heap            = 0x10000;

 

 /* ISR/SWI stack        */

 Program.stack           = 0x4000;

@@ -93,3 +93,12 @@ for (var i= 0x49000000; i < 0x490FFFFF; i = i + 0x100000)
     Mmu.setFirstLevelDescMeta(i, i, attrs);

 }

 

+/* configure the Peripheral Clock Module memory range                         */

+var peripheralBaseAddr = 0x44e00400;

+

+attrs.bufferable = false;

+attrs.cacheable = false;

+/* Configure the corresponding MMU page descriptor for Clock Module */

+Mmu.setFirstLevelDescMeta(peripheralBaseAddr,

+                          peripheralBaseAddr,

+                          attrs);

diff --git a/examples/edma3_driver/src/dma_poll_test.c b/examples/edma3_driver/src/dma_poll_test.c
index 948dc1a..fc0f037 100644
--- a/examples/edma3_driver/src/dma_poll_test.c
+++ b/examples/edma3_driver/src/dma_poll_test.c
@@ -7,7 +7,7 @@
 * to check the status of ongoing transfer. Interrupt will NOT occur in this 
 * case.
 *
-* Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - http://www.ti.com/
 * 
 * 
 *  Redistribution and use in source and binary forms, with or without 
@@ -48,6 +48,7 @@ extern signed char   _dstBuff1[MAX_BUFFER_SIZE];
 extern signed char *srcBuff1;
 extern signed char *dstBuff1;
 
+#define EDMA3_DRV_DMA_CHANNEL_USR_REQ     (10)
 /**
 *  \brief   EDMA3 mem-to-mem data copy test case, using a DMA channel.
 *              This test case doesnot rely on the callback mechanism.
@@ -78,6 +79,9 @@ EDMA3_DRV_Result edma3_test_poll_mode(
     uint32_t BRCnt = 0;
     int srcbidx = 0, desbidx = 0;
     int srccidx = 0, descidx = 0;
+#ifdef EDMA3_RES_USER_REQ
+    uint32_t paRAMId = 0;
+#endif
 
 
     srcBuff1 = (signed char*) GLOBAL_ADDR(_srcBuff1);
@@ -139,7 +143,6 @@ EDMA3_DRV_Result edma3_test_poll_mode(
     tcc = EDMA3_DRV_TCC_ANY;
     chId = EDMA3_DRV_DMA_CHANNEL_ANY;
 
-
     /* Request any DMA channel and any TCC */
     if (result == EDMA3_DRV_SOK)
     {
@@ -298,3 +301,276 @@ EDMA3_DRV_Result edma3_test_poll_mode(
     }
     return result;
 }
+
+
+/**
+*  \brief   EDMA3 mem-to-mem data copy test case with user requested paRAMId
+*           using a DMA channel.
+*           This test case doesnot rely on the callback mechanism.
+*           Instead, it Polls the IPR register to check the transfer
+*           completion status.
+*
+*  \param  edma3Instance [IN]    EDMA3 Instance number
+*  \param  acnt        [IN]      Number of bytes in an array
+*  \param  bcnt        [IN]      Number of arrays in a frame
+*  \param  ccnt        [IN]      Number of frames in a block
+*  \param  syncType    [IN]      Synchronization type (A/AB Sync)
+*
+*  \return  EDMA3_DRV_SOK or EDMA3_DRV Error Code
+*/
+EDMA3_DRV_Result edma3_test_user_req_paRAMId(
+                                      EDMA3_DRV_Handle hEdma,
+                                      uint32_t edmaInstance,
+                                      uint32_t acnt,
+                                      uint32_t bcnt,
+                                      uint32_t ccnt,
+                                      EDMA3_DRV_SyncType syncType)
+{
+    EDMA3_DRV_Result result = EDMA3_DRV_SOK;
+    uint32_t chId = 0;
+    uint32_t tcc = 0;
+    int i;
+    uint32_t count;
+    uint32_t Istestpassed = 0u;
+    uint32_t numenabled = 0;
+    uint32_t BRCnt = 0;
+    int srcbidx = 0, desbidx = 0;
+    int srccidx = 0, descidx = 0;
+    uint32_t paRAMId = 0;
+
+
+    srcBuff1 = (signed char*) GLOBAL_ADDR(_srcBuff1);
+    dstBuff1 = (signed char*) GLOBAL_ADDR(_dstBuff1);
+
+    /* Initalize source and destination buffers */
+    for (count = 0u; count < (acnt*bcnt*ccnt); count++)
+    {
+        srcBuff1[count] = (int)count+5;
+        /**
+        * No need to initialize the destination buffer as it is being invalidated.
+        dstBuff1[count] = initval;
+        */
+    }
+
+#ifdef EDMA3_ENABLE_DCACHE
+    /*
+    * Note: These functions are required if the buffer is in DDR.
+    * For other cases, where buffer is NOT in DDR, user
+    * may or may not require the below functions.
+    */
+    /* Flush the Source Buffer */
+    if (result == EDMA3_DRV_SOK)
+    {
+        result = Edma3_CacheFlush((uint32_t)srcBuff1, (acnt*bcnt*ccnt));
+    }
+
+    /* Invalidate the Destination Buffer */
+    if (result == EDMA3_DRV_SOK)
+    {
+        result = Edma3_CacheInvalidate((uint32_t)dstBuff1, (acnt*bcnt*ccnt));
+    }
+#endif  /* EDMA3_ENABLE_DCACHE */
+
+
+    /* Set B count reload as B count. */
+    BRCnt = bcnt;
+
+    /* Setting up the SRC/DES Index */
+    srcbidx = (int)acnt;
+    desbidx = (int)acnt;
+
+    if (syncType == EDMA3_DRV_SYNC_A)
+    {
+        /* A Sync Transfer Mode */
+        srccidx = (int)acnt;
+        descidx = (int)acnt;
+    }
+    else
+    {
+        /* AB Sync Transfer Mode */
+        srccidx = ((int)acnt * (int)bcnt);
+        descidx = ((int)acnt * (int)bcnt);
+    }
+
+
+    /* Setup for Channel 1*/
+    tcc = EDMA3_DRV_TCC_ANY;
+
+    chId = EDMA3_DRV_DMA_CHANNEL_USR_REQ;
+
+    /* Request any DMA channel and any TCC */
+    if (result == EDMA3_DRV_SOK)
+    {
+        result = EDMA3_DRV_requestChannel (hEdma, &chId, &tcc,
+            (EDMA3_RM_EventQueue)0,
+            NULL, NULL);
+
+        result = EDMA3_DRV_getAllocatedPARAMId(hEdma, chId, &paRAMId);
+        if(result == EDMA3_DRV_SOK)
+        {
+            printf("\nReserved Channel ID Test\n");
+            printf ("The Requested Channel ID: %d \nThe allocated PARAM Id:%d\n",chId,paRAMId);
+
+            if (chId == paRAMId)
+            {
+                printf("The Requested Param ID is allocated for the given Channel\n");
+            }
+            else
+            {
+                printf("The Requested Param ID is not allocated as same as the DMA channel\n");
+                result = EDMA3_DATA_MISMATCH_ERROR;
+            }
+            printf("\n");
+        }
+    }
+
+    if (result == EDMA3_DRV_SOK)
+    {
+        result = EDMA3_DRV_setSrcParams (hEdma, chId, (uint32_t)(srcBuff1),
+            EDMA3_DRV_ADDR_MODE_INCR,
+            EDMA3_DRV_W8BIT);
+    }
+
+    if (result == EDMA3_DRV_SOK)
+    {
+        result = EDMA3_DRV_setDestParams (hEdma, chId, (uint32_t)(dstBuff1),
+            EDMA3_DRV_ADDR_MODE_INCR,
+            EDMA3_DRV_W8BIT);
+    }
+
+    if (result == EDMA3_DRV_SOK)
+    {
+        result = EDMA3_DRV_setSrcIndex (hEdma, chId, srcbidx, srccidx);
+    }
+
+    if (result == EDMA3_DRV_SOK)
+    {
+        result =  EDMA3_DRV_setDestIndex (hEdma, chId, desbidx, descidx);
+    }
+
+    if (result == EDMA3_DRV_SOK)
+    {
+        if (syncType == EDMA3_DRV_SYNC_A)
+        {
+            result = EDMA3_DRV_setTransferParams (hEdma, chId, acnt, bcnt, ccnt,
+                BRCnt, EDMA3_DRV_SYNC_A);
+        }
+        else
+        {
+            result = EDMA3_DRV_setTransferParams (hEdma, chId, acnt, bcnt, ccnt,
+                BRCnt, EDMA3_DRV_SYNC_AB);
+        }
+    }
+
+    if (result == EDMA3_DRV_SOK)
+    {
+        result = EDMA3_DRV_setOptField (hEdma, chId,
+            EDMA3_DRV_OPT_FIELD_TCINTEN, 1u);
+    }
+
+    if (result == EDMA3_DRV_SOK)
+    {
+        result = EDMA3_DRV_setOptField (hEdma, chId,
+            EDMA3_DRV_OPT_FIELD_ITCINTEN, 1u);
+    }
+
+    /*
+    * Since the transfer is going to happen in Manual mode of EDMA3
+    * operation, we have to 'Enable the Transfer' multiple times.
+    * Number of times depends upon the Mode (A/AB Sync)
+    * and the different counts.
+    */
+    if (result == EDMA3_DRV_SOK)
+    {
+        /*Need to activate next param*/
+        if (syncType == EDMA3_DRV_SYNC_A)
+        {
+            numenabled = bcnt * ccnt;
+        }
+        else
+        {
+            /* AB Sync Transfer Mode */
+            numenabled = ccnt;
+        }
+
+
+        for (i = 0; i < numenabled; i++)
+        {
+            /*
+            * Now enable the transfer as many times as calculated above.
+            */
+            result = EDMA3_DRV_enableTransfer (hEdma, chId,
+                EDMA3_DRV_TRIG_MODE_MANUAL);
+            if (result != EDMA3_DRV_SOK)
+            {
+#ifdef EDMA3_DRV_DEBUG
+                EDMA3_DRV_PRINTF ("edma3_test_user_req_paRAMId: EDMA3_DRV_enableTransfer " \
+                    "Failed, error code: %d\r\n", result);
+#endif  /* EDMA3_DRV_DEBUG */
+                break;
+            }
+
+
+            /* Wait for the Completion Bit to be SET in the IPR/IPRH register. */
+            result = EDMA3_DRV_waitAndClearTcc (hEdma, tcc);
+            if (result != EDMA3_DRV_SOK)
+            {
+#ifdef EDMA3_DRV_DEBUG
+                EDMA3_DRV_PRINTF ("edma3_test_user_req_paRAMId: EDMA3_DRV_waitAndClearTcc " \
+                    "Failed, error code: %d\r\n", result);
+#endif  /* EDMA3_DRV_DEBUG */
+                break;
+            }
+        }
+    }
+
+
+    /* Match the Source and Destination Buffers. */
+    if (EDMA3_DRV_SOK == result)
+    {
+        for (i = 0; i < (acnt*bcnt*ccnt); i++)
+        {
+            if (srcBuff1[i] != dstBuff1[i])
+            {
+                Istestpassed = 0u;
+#ifdef EDMA3_DRV_DEBUG
+                EDMA3_DRV_PRINTF("edma3_test_user_req_paRAMId: Data write-read matching" \
+                    "FAILED at i = %d\r\n", i);
+#endif  /* EDMA3_DRV_DEBUG */
+                break;
+            }
+        }
+        if (i == (acnt*bcnt*ccnt))
+        {
+            Istestpassed = 1u;
+        }
+
+
+        /* Free the previously allocated channel. */
+        result = EDMA3_DRV_freeChannel (hEdma, chId);
+        if (result != EDMA3_DRV_SOK)
+        {
+#ifdef EDMA3_DRV_DEBUG
+            EDMA3_DRV_PRINTF("edma3_test_user_req_paRAMId: EDMA3_DRV_freeChannel() FAILED, " \
+                "error code: %d\r\n", result);
+#endif  /* EDMA3_DRV_DEBUG */
+        }
+    }
+
+
+    if(Istestpassed == 1u)
+    {
+#ifdef EDMA3_DRV_DEBUG
+        EDMA3_DRV_PRINTF("edma3_test_user_req_paRAMId PASSED\r\n");
+#endif  /* EDMA3_DRV_DEBUG */
+    }
+    else
+    {
+#ifdef EDMA3_DRV_DEBUG
+        EDMA3_DRV_PRINTF("edma3_test_user_req_paRAMId FAILED\r\n");
+#endif  /* EDMA3_DRV_DEBUG */
+        result = ((EDMA3_DRV_SOK == result) ?
+                    EDMA3_DATA_MISMATCH_ERROR : result);
+    }
+    return result;
+}
diff --git a/examples/edma3_driver/src/main.c b/examples/edma3_driver/src/main.c
index a6d37c6..37796a6 100644
--- a/examples/edma3_driver/src/main.c
+++ b/examples/edma3_driver/src/main.c
@@ -4,7 +4,7 @@
 * This file contains the test / demo code to demonstrate the EDMA3 driver
 * functionality on DSP/BIOS 6.
 *
-* Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - http://www.ti.com/
 *
 *
 *  Redistribution and use in source and binary forms, with or without
@@ -50,6 +50,19 @@ extern far const uint32_t numEdma3Instances;
 extern const uint32_t numEdma3Instances;
 #endif
 
+#ifdef SOC_AM335x
+#define WR_MEM_32(addr, data) *(unsigned int*)(addr) = (unsigned int)(data)
+
+#define PRCM_BASE_ADDR       (0x44E00000)
+#define CM_PER_TPTC0_CLKCTRL (PRCM_BASE_ADDR +0x0024)
+#define CM_PER_TPCC_CLKCTRL  (PRCM_BASE_ADDR +0x00BC)
+#define CM_PER_TPTC1_CLKCTRL (PRCM_BASE_ADDR +0x00FC)
+#define CM_PER_TPTC2_CLKCTRL (PRCM_BASE_ADDR +0x0100)
+
+/*To enable EDMA3 Clock Module */
+static void edma3PRCMEnable();
+#endif
+
 /**
 * DSP instance number on which the executable is running. Its value is
 * determined by reading the processor specific register DNUM.
@@ -156,11 +169,17 @@ void echo()
     EDMA3_DRV_Result edmaResult = EDMA3_DRV_SOK;
     uint32_t i, bypass;
     uint32_t count=0;
+    uint32_t edmaInstance = 0;
     EDMA3_DRV_Handle hEdma[MAX_NUM_EDMA_INSTANCES];
+    EDMA3_DRV_Handle hndEdma = NULL;
     Semaphore_Params semParams;
 
     memset(hEdma,0,sizeof(hEdma));
 
+#ifdef SOC_AM335x
+    edma3PRCMEnable();
+#endif
+
     /* Print the Welcome Message */
     printWelcomeBanner();
 
@@ -301,6 +320,51 @@ void echo()
         }
     }
 
+    /* Mapping DMA channels to corresponding paRAM Id. The user can request for 
+     * any DAM channel to map with the paRAM Id as same as the channel number
+     */
+    for (count = 0u; count < EDMA3_MAX_DMA_CH; count++)
+    {
+        sampleEdma3GblCfgParams[edmaInstance].dmaChannelPaRAMMap[count] = count;
+    }
+
+    /*EDMA3 Initialization*/
+    hndEdma = edma3init(edmaInstance, &edmaResult);
+    if (hndEdma)
+    {
+        printf("edma3init() Passed\n");
+    }
+    else
+    {
+        printf("edma3init() Failed, error code: %d\n", (int)edmaResult);
+    }
+
+    /* User request PaRAMId test */
+    if (edmaResult == EDMA3_DRV_SOK)
+    {
+        edmaResult = edma3_test_user_req_paRAMId(hndEdma, edmaInstance,
+                      MAX_ACOUNT, MAX_BCOUNT, MAX_CCOUNT, EDMA3_DRV_SYNC_A);
+    }
+
+    if (edmaResult == EDMA3_DRV_SOK)
+    {
+        printf ("edma3_test_user_req_paRAMId Passed\r\n");
+    }
+    else
+    {
+        printf ("edma3_test_user_req_paRAMId Failed\r\n");
+    }
+
+    /*EDMA3 deinitialization */
+    edmaResult = edma3deinit(edmaInstance, hndEdma);
+    if (edmaResult != EDMA3_DRV_SOK)
+    {
+        printf("edma3deinit() Failed, error code: %d\n", (int)edmaResult);
+    }
+    else
+    {
+        printf("edma3deinit() Passed\n");
+    }
     /* Start the Heart Beat Print */
     tskHeartBit();
 
@@ -459,3 +523,14 @@ void tskHeartBit()
         counter++;
     }
 }
+
+#ifdef SOC_AM335x
+/*To enable EDMA3 Clock Module of AM335x*/
+static void edma3PRCMEnable()
+{
+    WR_MEM_32(CM_PER_TPCC_CLKCTRL, 2);
+    WR_MEM_32(CM_PER_TPTC0_CLKCTRL ,   2);
+    WR_MEM_32(CM_PER_TPTC1_CLKCTRL ,   2);
+    WR_MEM_32(CM_PER_TPTC2_CLKCTRL ,   2);
+}
+#endif
diff --git a/packages/ti/sdo/edma3/drv/edma3_drv.h b/packages/ti/sdo/edma3/drv/edma3_drv.h
index 2c77bf8..a6040c5 100755
--- a/packages/ti/sdo/edma3/drv/edma3_drv.h
+++ b/packages/ti/sdo/edma3/drv/edma3_drv.h
@@ -5,7 +5,7 @@
  * uses the EDMA3 Resource Manager internally for resource allocation, interrupt
  * handling and EDMA3 registers programming.
  *
- * Copyright (C) 2009-2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2009-2018 Texas Instruments Incorporated - http://www.ti.com/
  *
  *
  *  Redistribution and use in source and binary forms, with or without
@@ -3152,6 +3152,33 @@ EDMA3_DRV_Result EDMA3_DRV_initXbarEventMap (EDMA3_DRV_Handle hEdma,
                  EDMA3_DRV_mapXbarEvtToChan mapXbarEvtFunc,
                  EDMA3_DRV_xbarConfigScr configXbarScr);
 
+/**
+ * \brief   Returns the PARAM ID recently allocated for an EDMA channel
+ *
+ * This API will return the PARAM Id recently allocated by the EDMA3
+ * resource manager for a requested DMA channel
+ *
+ * This function can be called by the application after
+ * the EDMA3_DRV_requestChannel() function is invoked to check the
+ * allocated PaRAM Id for a requested channel if needed.
+ *
+ * \param   hEdma              [IN]    Handle to the EDMA Driver Instance.
+ * \param   channelId          [IN]    DMA channel for which the PaRAMId
+ *                                     needs to be returned.
+ * \param   paRAMId            [OUT]   Return the paRAMId of which the
+ *                                     channel Id is mapped.
+ *
+ * \return  EDMA3_DRV_SOK or EDMA3_DRV Error Code
+ *
+ * \note    This function is used to verify the requested DMA channel
+ *          is allocated/mapped with the PaRAM Id same as DMA channel number.
+ *          This function is not necessarily be used(invoked) for
+ *          any other general functionality.
+ *
+ */
+EDMA3_DRV_Result EDMA3_DRV_getAllocatedPARAMId(EDMA3_DRV_Handle hEdma,
+                 uint32_t channelId, uint32_t *paRAMId);
+
 
                                                 
 /**
diff --git a/packages/ti/sdo/edma3/drv/src/edma3_drv_basic.c b/packages/ti/sdo/edma3/drv/src/edma3_drv_basic.c
index 1070973..fe00bb5 100755
--- a/packages/ti/sdo/edma3/drv/src/edma3_drv_basic.c
+++ b/packages/ti/sdo/edma3/drv/src/edma3_drv_basic.c
@@ -12,7 +12,7 @@
  * beyond this and have complete control on the EDMA3 hardware are advised
  * to refer edma3_drv_adv.c source file.
  *
- * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2009-2018 Texas Instruments Incorporated - http://www.ti.com/
  *
  *
  *  Redistribution and use in source and binary forms, with or without
@@ -2273,6 +2273,37 @@ EDMA3_DRV_Result EDMA3_DRV_disableLogicalChannel (EDMA3_DRV_Handle hEdma,
     return result;
     }
 
+/** Return the Param ID recently allocated for an EDMA request*/
+EDMA3_DRV_Result EDMA3_DRV_getAllocatedPARAMId(EDMA3_DRV_Handle hEdma,
+                                uint32_t channelId, uint32_t *paRAMId)
+{
+    uint32_t edma3Id = 0;
+    EDMA3_DRV_Instance *drvInst = NULL;
+    EDMA3_DRV_Object *drvObject = NULL;
+        EDMA3_DRV_Result result = EDMA3_DRV_SOK;
+
+    drvInst = (EDMA3_DRV_Instance *)hEdma;
+    drvObject = drvInst->pDrvObjectHandle;
+
+    if (drvObject == NULL)
+    {
+        result = EDMA3_DRV_E_INVALID_PARAM;
+    }
+
+    if (EDMA3_DRV_SOK == result)
+    {
+        edma3Id = drvObject->phyCtrllerInstId;
+    }
+    else
+    {
+            result = EDMA3_DRV_E_INVALID_PARAM;
+    }
+
+    *paRAMId = edma3DrvChBoundRes[edma3Id][channelId].paRAMId;
+
+        return result;
+}
+
 /* Definitions of Local functions - Start */
 /** Remove various mappings and do cleanup for DMA/QDMA channels */
 static EDMA3_DRV_Result edma3RemoveMapping (EDMA3_DRV_Handle hEdma,