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authorTinku Mannan2019-09-18 10:53:44 -0500
committerTinku Mannan2019-09-18 10:53:44 -0500
commit7bf90afaf25f55847cdd1908b63b6d94e83cb4f5 (patch)
treeab752ebac2f7e59f99fafe56b6e7355f34bdf249
parentaf5eb5d8f3b86c69f992e0a09144582d437aa0bb (diff)
downloademac-lld-7bf90afaf25f55847cdd1908b63b6d94e83cb4f5.tar.gz
emac-lld-7bf90afaf25f55847cdd1908b63b6d94e83cb4f5.tar.xz
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Updates from industrial development branch
syncing driver updates from commit id 09a409927a4bb0368309b5251bd
Diffstat
-rw-r--r--emac_drv.h5
-rw-r--r--emac_ioctl.h11
-rw-r--r--firmware/icss_switch/bin/switch_mem_map.h1424
-rw-r--r--firmware/icss_switch/config/emac_fw_config_switch.c9
-rw-r--r--soc/am65xx/emac_soc.c7
-rw-r--r--soc/j721e/emac_soc.c7
-rw-r--r--src/v5/emac_drv_v5.c25
-rw-r--r--src/v5/emac_drv_v5.h12
-rw-r--r--src/v5/emac_ioctl.c302
9 files changed, 1043 insertions, 759 deletions
diff --git a/emac_drv.h b/emac_drv.h
index b814cec..33e78cc 100644
--- a/emac_drv.h
+++ b/emac_drv.h
@@ -203,7 +203,6 @@ typedef void UTIL_TRACE_CB_T(uint8_t traceLevel, const char* traceString, ...);
203#else 203#else
204#define UTILS_trace(dbg_level, trace_fxn, fmt, ...) 204#define UTILS_trace(dbg_level, trace_fxn, fmt, ...)
205#endif 205#endif
206
207#endif 206#endif
208 207
209/** 208/**
@@ -901,7 +900,9 @@ typedef enum EMAC_IOCTL_CMD_E{
901 EMAC_IOCTL_INTERFACE_MAC_CONFIG, /**< interface mac config ioctl */ 900 EMAC_IOCTL_INTERFACE_MAC_CONFIG, /**< interface mac config ioctl */
902 EMAC_IOCTL_CUT_THROUGH_PREEMPT_SELECT, /**< cut through or prempt select config ioctl */ 901 EMAC_IOCTL_CUT_THROUGH_PREEMPT_SELECT, /**< cut through or prempt select config ioctl */
903 EMAC_IOCTL_SPECIAL_FRAME_PRIO_CONFIG, /**< special packets default prio config ioctl */ 902 EMAC_IOCTL_SPECIAL_FRAME_PRIO_CONFIG, /**< special packets default prio config ioctl */
904 EMAC_IOCTL_FRAME_PREEMPTION_CTRL /**< premption control config ioctl */ 903 EMAC_IOCTL_FRAME_PREEMPTION_CTRL, /**< premption control config ioctl */
904 EMAC_IOCTL_FDB_AGEING_TIMEOUT_CTRL /**< configure FDB ageing timeout */
905
905} EMAC_IOCTL_CMD; 906} EMAC_IOCTL_CMD;
906 907
907/** 908/**
diff --git a/emac_ioctl.h b/emac_ioctl.h
index ba6a172..bf6ec2c 100644
--- a/emac_ioctl.h
+++ b/emac_ioctl.h
@@ -244,6 +244,15 @@ typedef struct EMAC_IOCTL_SPECIAL_FRAME_DEFAULT_PRIO_S {
244 priority values possible(0-7)*/ 244 priority values possible(0-7)*/
245}EMAC_IOCTL_SPECIAL_FRAME_DEFAULT_PRIO; 245}EMAC_IOCTL_SPECIAL_FRAME_DEFAULT_PRIO;
246 246
247/**
248 * @brief FDB Ageing interval
249 * @details Value is in nanoseconds
250 */
251typedef struct EMAC_IOCTL_FDB_AGEING_INTERVAL_S {
252 uint64_t fdbAgeingInterval;
253 /**< Specifies FDB ageing interval in nanoseconds*/
254}EMAC_IOCTL_FDB_AGEING_INTERVAL;
255
247typedef enum Preempt_Verify_States_E{ 256typedef enum Preempt_Verify_States_E{
248 STATE_UNKNOWN = 0, 257 STATE_UNKNOWN = 0,
249 STATE_INITIAL, 258 STATE_INITIAL,
@@ -565,6 +574,8 @@ extern EMAC_DRV_ERR_E emac_ioctl_configure_interface_mac_ctrl(uint32_t port_num,
565extern EMAC_DRV_ERR_E emac_ioctl_configure_cut_through_or_prempt_select_ctrl(uint32_t port_num, uint32_t switch_port, void* p_params); 574extern EMAC_DRV_ERR_E emac_ioctl_configure_cut_through_or_prempt_select_ctrl(uint32_t port_num, uint32_t switch_port, void* p_params);
566extern EMAC_DRV_ERR_E emac_ioctl_configure_special_frame_prio_ctrl(uint32_t port_num, uint32_t switch_port, void* p_params); 575extern EMAC_DRV_ERR_E emac_ioctl_configure_special_frame_prio_ctrl(uint32_t port_num, uint32_t switch_port, void* p_params);
567extern EMAC_DRV_ERR_E emac_ioctl_frame_premption_ctrl(uint32_t port_num, uint32_t switch_port, void* p_params); 576extern EMAC_DRV_ERR_E emac_ioctl_frame_premption_ctrl(uint32_t port_num, uint32_t switch_port, void* p_params);
577extern EMAC_DRV_ERR_E emac_ioctl_configure_fdb_ageing_interval(uint32_t port_num, uint32_t switch_port, void* p_params);
578
568/*! @endcond */ 579/*! @endcond */
569 580
570/*! 581/*!
diff --git a/firmware/icss_switch/bin/switch_mem_map.h b/firmware/icss_switch/bin/switch_mem_map.h
index 3ae0411..d8ab710 100644
--- a/firmware/icss_switch/bin/switch_mem_map.h
+++ b/firmware/icss_switch/bin/switch_mem_map.h
@@ -1,708 +1,716 @@
1//*********************************************************************************** 1//***********************************************************************************
2//**+-----------------------------------------------------------------------------+** 2//**+-----------------------------------------------------------------------------+**
3//**| ****** |** 3//**| ****** |**
4//**| ****** o |** 4//**| ****** o |**
5//**| *******__////__**** |** 5//**| *******__////__**** |**
6//**| ***** /_ //___/ *** |** 6//**| ***** /_ //___/ *** |**
7//**| ********* ////__ ****** |** 7//**| ********* ////__ ****** |**
8//**| *******(_____/ ****** |** 8//**| *******(_____/ ****** |**
9//**| ********** |** 9//**| ********** |**
10//**| ****** |** 10//**| ****** |**
11//**| *** |** 11//**| *** |**
12//**| |** 12//**| |**
13//**| Copyright (c) 2019 Texas Instruments Incorporated |** 13//**| Copyright (c) 2019 Texas Instruments Incorporated |**
14//**| ALL RIGHTS RESERVED |** 14//**| ALL RIGHTS RESERVED |**
15//**| |** 15//**| |**
16//**| Permission is hereby granted to licensees of Texas Instruments |** 16//**| Permission is hereby granted to licensees of Texas Instruments |**
17//**| Incorporated (TI) products to use this computer program for the sole |** 17//**| Incorporated (TI) products to use this computer program for the sole |**
18//**| purpose of implementing a licensee product based on TI products. |** 18//**| purpose of implementing a licensee product based on TI products. |**
19//**| No other rights to reproduce, use, or disseminate this computer |** 19//**| No other rights to reproduce, use, or disseminate this computer |**
20//**| program, whether in part or in whole, are granted. |** 20//**| program, whether in part or in whole, are granted. |**
21//**| |** 21//**| |**
22//**| TI makes no representation or warranties with respect to the |** 22//**| TI makes no representation or warranties with respect to the |**
23//**| performance of this computer program, and specifically disclaims |** 23//**| performance of this computer program, and specifically disclaims |**
24//**| any responsibility for any damages, special or consequential, |** 24//**| any responsibility for any damages, special or consequential, |**
25//**| connected with the use of this program. |** 25//**| connected with the use of this program. |**
26//**| |** 26//**| |**
27//**+-----------------------------------------------------------------------------+** 27//**+-----------------------------------------------------------------------------+**
28//*********************************************************************************** 28//***********************************************************************************
29// file: switch_mem_map.h 29// file: switch_mem_map.h
30// 30//
31// brief: Contains memory map for Ethernet Switch. 31// brief: Contains memory map for Ethernet Switch.
32// This file is shared by firmware and driver. 32// This file is shared by firmware and driver.
33 33
34#ifndef ____switch_mem_map_h 34#ifndef ____switch_mem_map_h
35#define ____switch_mem_map_h 1 35#define ____switch_mem_map_h 1
36 36
37#include "switch_mmap_defines.h" 37#include "switch_mmap_defines.h"
38 38
39//************************************************************************************ 39//************************************************************************************
40// 40//
41// Memory Usage of : SHARED_MEMORY 41// Memory Usage of : SHARED_MEMORY
42// 42//
43//************************************************************************************ 43//************************************************************************************
44 44
45#define SHARED_MEMORY_START_OFFSET 0x0000 45#define SHARED_MEMORY_START_OFFSET 0x0000
46#define PRE_EMPTION_CONTEXT_OFFSET 0x0000 //Backup of active Tx and Q context. The offset is not used 46#define PRE_EMPTION_CONTEXT_OFFSET 0x0000 //Backup of active Tx and Q context. The offset is not used
47#define PRE_EMPTION_CONTEXT_OFFSET_SIZE 0x8 47#define PRE_EMPTION_CONTEXT_OFFSET_SIZE 0x8
48#define FW_HOST_HANDSHAKE_MAGIC_VAL_OFFSET 0x0008 //Firmware host handshake 48#define FW_HOST_HANDSHAKE_MAGIC_VAL_OFFSET 0x0008 //Firmware host handshake
49#define FW_HOST_HANDSHAKE_MAGIC_VAL_OFFSET_SIZE 0x4 49#define FW_HOST_HANDSHAKE_MAGIC_VAL_OFFSET_SIZE 0x4
50#define PSI_L_REGULAR_FLOW_ID_BASE_OFFSET 0x000C //Base Flow ID for sending packets to Host 50#define PSI_L_REGULAR_FLOW_ID_BASE_OFFSET 0x000C //Base Flow ID for sending packets to Host
51#define PSI_L_REGULAR_FLOW_ID_BASE_OFFSET_SIZE 0x2 51#define PSI_L_REGULAR_FLOW_ID_BASE_OFFSET_SIZE 0x2
52#define EMAC_ICSSG_SWITCH_PSI_L_REGULAR_FLOW_ID_BASE_OFFSET PSI_L_REGULAR_FLOW_ID_BASE_OFFSET //Same as PSI_L_REGULAR_FLOW_ID_BASE_OFFSET 52#define EMAC_ICSSG_SWITCH_PSI_L_REGULAR_FLOW_ID_BASE_OFFSET PSI_L_REGULAR_FLOW_ID_BASE_OFFSET //Same as PSI_L_REGULAR_FLOW_ID_BASE_OFFSET
53#define PSI_L_MGMT_FLOW_ID_OFFSET 0x000E //Base Flow ID for sending mgmt and Tx TS to Host 53#define PSI_L_MGMT_FLOW_ID_OFFSET 0x000E //Base Flow ID for sending mgmt and Tx TS to Host
54#define PSI_L_MGMT_FLOW_ID_OFFSET_SIZE 0x2 54#define PSI_L_MGMT_FLOW_ID_OFFSET_SIZE 0x2
55#define EMAC_ICSSG_SWITCH_PSI_L_MGMT_FLOW_ID_BASE_OFFSET PSI_L_MGMT_FLOW_ID_OFFSET //Same as PSI_L_MGMT_FLOW_ID_OFFSET 55#define EMAC_ICSSG_SWITCH_PSI_L_MGMT_FLOW_ID_BASE_OFFSET PSI_L_MGMT_FLOW_ID_OFFSET //Same as PSI_L_MGMT_FLOW_ID_OFFSET
56#define SPL_PKT_DEFAULT_PRIORITY 0x0010 //Queue number for Special packets written here. Only 1B is used 56#define SPL_PKT_DEFAULT_PRIORITY 0x0010 //Queue number for Special packets written here. Only 1B is used
57#define SPL_PKT_DEFAULT_PRIORITY_SIZE 0x4 57#define SPL_PKT_DEFAULT_PRIORITY_SIZE 0x4
58#define FDB_SA_MAC_ADDRESS 0x0014 //Used internally by FW for learning 58#define FDB_SA_MAC_ADDRESS 0x0014 //Used internally by FW for learning
59#define FDB_SA_MAC_ADDRESS_SIZE 0x8 59#define FDB_SA_MAC_ADDRESS_SIZE 0x8
60#define FDB_FID_FIDC2_OFFSET 0x001C //Used internally by FW for learning 60#define FDB_FID_FIDC2_OFFSET 0x001C //Used internally by FW for learning
61#define FDB_FID_FIDC2_OFFSET_SIZE 0x4 61#define FDB_FID_FIDC2_OFFSET_SIZE 0x4
62#define FDB_BUCKET_OFFSET 0x0020 //Used internally by FW for learning 62#define FDB_BUCKET_OFFSET 0x0020 //Used internally by FW for learning
63#define FDB_BUCKET_OFFSET_SIZE 0x4 63#define FDB_BUCKET_OFFSET_SIZE 0x4
64#define FDB_AGEING_LAST_USED_OFFSET 0x0024 //Used internally by FW for learning 64#define FDB_AGEING_LAST_USED_OFFSET 0x0024 //Used internally by FW for learning
65#define FDB_AGEING_LAST_USED_OFFSET_SIZE 0x4 65#define FDB_AGEING_LAST_USED_OFFSET_SIZE 0x4
66#define TX_SOF_TS_OFFSET 0x0028 //Used internally by FW to store Tx timestamp 66#define TX_SOF_TS_OFFSET 0x0028 //Used internally by FW to store Tx timestamp
67#define TX_SOF_TS_OFFSET_SIZE 0x8 67#define TX_SOF_TS_OFFSET_SIZE 0x8
68#define TX_TS_COOKIE_OFFSET 0x0030 //Used internally by FW to stash cookie 68#define TX_TS_COOKIE_OFFSET 0x0030 //Used internally by FW to stash cookie
69#define TX_TS_COOKIE_OFFSET_SIZE 0x4 69#define TX_TS_COOKIE_OFFSET_SIZE 0x4
70#define HOST_PORT_DF_VLAN_OFFSET 0x0034 //default VLAN tag for Host Port 70#define HOST_PORT_DF_VLAN_OFFSET 0x0034 //default VLAN tag for Host Port
71#define HOST_PORT_DF_VLAN_OFFSET_SIZE 0x4 71#define HOST_PORT_DF_VLAN_OFFSET_SIZE 0x4
72#define EMAC_ICSSG_SWITCH_PORT0_DEFAULT_VLAN_OFFSET HOST_PORT_DF_VLAN_OFFSET //Same as HOST_PORT_DF_VLAN_OFFSET 72#define EMAC_ICSSG_SWITCH_PORT0_DEFAULT_VLAN_OFFSET HOST_PORT_DF_VLAN_OFFSET //Same as HOST_PORT_DF_VLAN_OFFSET
73#define P1_PORT_DF_VLAN_OFFSET 0x0038 //default VLAN tag for P1 Port 73#define P1_PORT_DF_VLAN_OFFSET 0x0038 //default VLAN tag for P1 Port
74#define P1_PORT_DF_VLAN_OFFSET_SIZE 0x4 74#define P1_PORT_DF_VLAN_OFFSET_SIZE 0x4
75#define EMAC_ICSSG_SWITCH_PORT1_DEFAULT_VLAN_OFFSET P1_PORT_DF_VLAN_OFFSET //Same as P1_PORT_DF_VLAN_OFFSET 75#define EMAC_ICSSG_SWITCH_PORT1_DEFAULT_VLAN_OFFSET P1_PORT_DF_VLAN_OFFSET //Same as P1_PORT_DF_VLAN_OFFSET
76#define P2_PORT_DF_VLAN_OFFSET 0x003C //default VLAN tag for P2 Port 76#define P2_PORT_DF_VLAN_OFFSET 0x003C //default VLAN tag for P2 Port
77#define P2_PORT_DF_VLAN_OFFSET_SIZE 0x4 77#define P2_PORT_DF_VLAN_OFFSET_SIZE 0x4
78#define EMAC_ICSSG_SWITCH_PORT2_DEFAULT_VLAN_OFFSET P2_PORT_DF_VLAN_OFFSET //Same as P2_PORT_DF_VLAN_OFFSET 78#define EMAC_ICSSG_SWITCH_PORT2_DEFAULT_VLAN_OFFSET P2_PORT_DF_VLAN_OFFSET //Same as P2_PORT_DF_VLAN_OFFSET
79#define RX_TS_STASHED 0x0040 //Used internally by FW for stashed Rx timestamp 79#define RX_TS_STASHED 0x0040 //Used internally by FW for stashed Rx timestamp
80#define RX_TS_STASHED_SIZE 0x8 80#define RX_TS_STASHED_SIZE 0x8
81#define MGR_CMD_OFFSET 0x0048 //Management command from Host to RTU0 81#define MGR_CMD_OFFSET 0x0048 //Management command from Host to RTU0
82#define MGR_CMD_OFFSET_SIZE 0x20 82#define MGR_CMD_OFFSET_SIZE 0x20
83#define MGR_CMD_RET 0x0068 //Management reply to Host from RTU0 83#define MGR_CMD_RET 0x0068 //Management reply to Host from RTU0
84#define MGR_CMD_RET_SIZE 0xc 84#define MGR_CMD_RET_SIZE 0xc
85#define MGR_CMD_STATE 0x0074 //0 - idle; 1 - todo; 2 - executing 85#define MGR_CMD_STATE 0x0074 //0 - idle; 1 - todo; 2 - executing
86#define MGR_CMD_STATE_SIZE 0x1 86#define MGR_CMD_STATE_SIZE 0x1
87//Padding of 3 bytes 87//Padding of 3 bytes
88#define MGR_CMD_PRU0_STATUS 0x0078 //Used internally by FW to communicate from RTU0 to PRU0 88#define MGR_CMD_PRU0_STATUS 0x0078 //Used internally by FW to communicate from RTU0 to PRU0
89#define MGR_CMD_PRU0_STATUS_SIZE 0x2 89#define MGR_CMD_PRU0_STATUS_SIZE 0x2
90#define MGR_CMD_PRU1_STATUS 0x007A //Used internally by FW to communicate from RTU0 to PRU1 90#define MGR_CMD_PRU1_STATUS 0x007A //Used internally by FW to communicate from RTU0 to PRU1
91#define MGR_CMD_PRU1_STATUS_SIZE 0x2 91#define MGR_CMD_PRU1_STATUS_SIZE 0x2
92#define MGR_CMD_RTU0_STATUS 0x007C //Used internally by FW to communicate from RTU0 to RTU0 92#define MGR_CMD_RTU0_STATUS 0x007C //Used internally by FW to communicate from RTU0 to RTU0
93#define MGR_CMD_RTU0_STATUS_SIZE 0x2 93#define MGR_CMD_RTU0_STATUS_SIZE 0x2
94#define MGR_CMD_RTU1_STATUS 0x007E //Used internally by FW to for management state machine 94#define MGR_CMD_RTU1_STATUS 0x007E //Used internally by FW to for management state machine
95#define MGR_CMD_RTU1_STATUS_SIZE 0x42 95#define MGR_CMD_RTU1_STATUS_SIZE 0x42
96#define MGR_CMD_END_OFFSET 0x00C0 //End of Management command region 96#define MGR_CMD_END_OFFSET 0x00C0 //End of Management command region
97#define PORT_Q0_RD_PTR_OFFSET 0x0100 //Port Tx Q0 MSMC Read pointer stored here 97#define P1_QUEUE_NUM_UNTAGGED 0x00C0 //Port1 Default Queue number for untagged packets
98#define PORT_Q0_RD_PTR_OFFSET_SIZE 0x4 98#define P1_QUEUE_NUM_UNTAGGED_SIZE 0x1
99#define EMAC_ICSSG_SWITCH_PORT_QUEUE_READ_PTR_OFFSET PORT_Q0_RD_PTR_OFFSET //Same as PORT_Q0_RD_PTR_OFFSET 99#define P2_QUEUE_NUM_UNTAGGED 0x00C1 //Port2 Default Queue number for untagged packets
100#define PORT_Q1_RD_PTR_OFFSET 0x0104 //Port Tx Q1 MSMC Read pointer stored here 100#define P2_QUEUE_NUM_UNTAGGED_SIZE 0x1
101#define PORT_Q1_RD_PTR_OFFSET_SIZE 0x4 101#define PORT_Q0_RD_PTR_OFFSET 0x0100 //Port Tx Q0 MSMC Read pointer stored here
102#define PORT_Q2_RD_PTR_OFFSET 0x0108 //Port Tx Q2 MSMC Read pointer stored here 102#define PORT_Q0_RD_PTR_OFFSET_SIZE 0x4
103#define PORT_Q2_RD_PTR_OFFSET_SIZE 0x4 103#define EMAC_ICSSG_SWITCH_PORT_QUEUE_READ_PTR_OFFSET PORT_Q0_RD_PTR_OFFSET //Same as PORT_Q0_RD_PTR_OFFSET
104#define PORT_Q3_RD_PTR_OFFSET 0x010C //Port Tx Q3 MSMC Read pointer stored here 104#define PORT_Q1_RD_PTR_OFFSET 0x0104 //Port Tx Q1 MSMC Read pointer stored here
105#define PORT_Q3_RD_PTR_OFFSET_SIZE 0x4 105#define PORT_Q1_RD_PTR_OFFSET_SIZE 0x4
106#define PORT_Q4_RD_PTR_OFFSET 0x0110 //Port Tx Q4 MSMC Read pointer stored here 106#define PORT_Q2_RD_PTR_OFFSET 0x0108 //Port Tx Q2 MSMC Read pointer stored here
107#define PORT_Q4_RD_PTR_OFFSET_SIZE 0x4 107#define PORT_Q2_RD_PTR_OFFSET_SIZE 0x4
108#define PORT_Q5_RD_PTR_OFFSET 0x0114 //Port Tx Q5 MSMC Read pointer stored here 108#define PORT_Q3_RD_PTR_OFFSET 0x010C //Port Tx Q3 MSMC Read pointer stored here
109#define PORT_Q5_RD_PTR_OFFSET_SIZE 0x4 109#define PORT_Q3_RD_PTR_OFFSET_SIZE 0x4
110#define PORT_Q6_RD_PTR_OFFSET 0x0118 //Port Tx Q6 MSMC Read pointer stored here 110#define PORT_Q4_RD_PTR_OFFSET 0x0110 //Port Tx Q4 MSMC Read pointer stored here
111#define PORT_Q6_RD_PTR_OFFSET_SIZE 0x4 111#define PORT_Q4_RD_PTR_OFFSET_SIZE 0x4
112#define PORT_Q7_RD_PTR_OFFSET 0x011C //Port Tx Q1 MSMC Read pointer stored here 112#define PORT_Q5_RD_PTR_OFFSET 0x0114 //Port Tx Q5 MSMC Read pointer stored here
113#define PORT_Q7_RD_PTR_OFFSET_SIZE 0x4 113#define PORT_Q5_RD_PTR_OFFSET_SIZE 0x4
114#define HOST_Q0_RD_PTR_OFFSET 0x0120 //Host Tx Q0 MSMC Read pointer stored here 114#define PORT_Q6_RD_PTR_OFFSET 0x0118 //Port Tx Q6 MSMC Read pointer stored here
115#define HOST_Q0_RD_PTR_OFFSET_SIZE 0x4 115#define PORT_Q6_RD_PTR_OFFSET_SIZE 0x4
116#define HOST_Q1_RD_PTR_OFFSET 0x0124 //Host Tx Q1 MSMC Read pointer stored here 116#define PORT_Q7_RD_PTR_OFFSET 0x011C //Port Tx Q1 MSMC Read pointer stored here
117#define HOST_Q1_RD_PTR_OFFSET_SIZE 0x4 117#define PORT_Q7_RD_PTR_OFFSET_SIZE 0x4
118#define HOST_Q2_RD_PTR_OFFSET 0x0128 //Host Tx Q2 MSMC Read pointer stored here 118#define HOST_Q0_RD_PTR_OFFSET 0x0120 //Host Tx Q0 MSMC Read pointer stored here
119#define HOST_Q2_RD_PTR_OFFSET_SIZE 0x4 119#define HOST_Q0_RD_PTR_OFFSET_SIZE 0x4
120#define HOST_Q3_RD_PTR_OFFSET 0x012C //Host Tx Q3 MSMC Read pointer stored here 120#define HOST_Q1_RD_PTR_OFFSET 0x0124 //Host Tx Q1 MSMC Read pointer stored here
121#define HOST_Q3_RD_PTR_OFFSET_SIZE 0x4 121#define HOST_Q1_RD_PTR_OFFSET_SIZE 0x4
122#define HOST_Q4_RD_PTR_OFFSET 0x0130 //Host Tx Q4 MSMC Read pointer stored here 122#define HOST_Q2_RD_PTR_OFFSET 0x0128 //Host Tx Q2 MSMC Read pointer stored here
123#define HOST_Q4_RD_PTR_OFFSET_SIZE 0x4 123#define HOST_Q2_RD_PTR_OFFSET_SIZE 0x4
124#define HOST_Q5_RD_PTR_OFFSET 0x0134 //Host Tx Q5 MSMC Read pointer stored here 124#define HOST_Q3_RD_PTR_OFFSET 0x012C //Host Tx Q3 MSMC Read pointer stored here
125#define HOST_Q5_RD_PTR_OFFSET_SIZE 0x4 125#define HOST_Q3_RD_PTR_OFFSET_SIZE 0x4
126#define HOST_Q6_RD_PTR_OFFSET 0x0138 //Host Tx Q6 MSMC Read pointer stored here 126#define HOST_Q4_RD_PTR_OFFSET 0x0130 //Host Tx Q4 MSMC Read pointer stored here
127#define HOST_Q6_RD_PTR_OFFSET_SIZE 0x4 127#define HOST_Q4_RD_PTR_OFFSET_SIZE 0x4
128#define HOST_Q7_RD_PTR_OFFSET 0x013C //Host Tx Q7 MSMC Read pointer stored here 128#define HOST_Q5_RD_PTR_OFFSET 0x0134 //Host Tx Q5 MSMC Read pointer stored here
129#define HOST_Q7_RD_PTR_OFFSET_SIZE 0x4 129#define HOST_Q5_RD_PTR_OFFSET_SIZE 0x4
130#define HOST_RX_PRE_RD_PTR_OFFSET 0x0140 //Host Egress Q MSMC Read pointer (for Pre-emptive queue) stored here 130#define HOST_Q6_RD_PTR_OFFSET 0x0138 //Host Tx Q6 MSMC Read pointer stored here
131#define HOST_RX_PRE_RD_PTR_OFFSET_SIZE 0x4 131#define HOST_Q6_RD_PTR_OFFSET_SIZE 0x4
132#define EMAC_ICSSG_SWITCH_HOST_QUEUE_READ_PTR_OFFSET HOST_RX_PRE_RD_PTR_OFFSET //Same as HOST_RX_PRE_RD_PTR_OFFSET 132#define HOST_Q7_RD_PTR_OFFSET 0x013C //Host Tx Q7 MSMC Read pointer stored here
133#define HOST_RX_PRE_WR_PTR_OFFSET 0x0144 //Host Egress Q MSMC Write pointer (for Pre-emptive queue) stored here 133#define HOST_Q7_RD_PTR_OFFSET_SIZE 0x4
134#define HOST_RX_PRE_WR_PTR_OFFSET_SIZE 0x4 134#define HOST_RX_PRE_RD_PTR_OFFSET 0x0140 //Host Egress Q MSMC Read pointer (for Pre-emptive queue) stored here
135#define HOST_RX_EXP_RD_PTR_OFFSET 0x0148 //Reserved for Future Use 135#define HOST_RX_PRE_RD_PTR_OFFSET_SIZE 0x4
136#define HOST_RX_EXP_RD_PTR_OFFSET_SIZE 0x4 136#define EMAC_ICSSG_SWITCH_HOST_QUEUE_READ_PTR_OFFSET HOST_RX_PRE_RD_PTR_OFFSET //Same as HOST_RX_PRE_RD_PTR_OFFSET
137#define HOST_RX_EXP_WR_PTR_OFFSET 0x014C //Reserved for Future Use 137#define HOST_RX_PRE_WR_PTR_OFFSET 0x0144 //Host Egress Q MSMC Write pointer (for Pre-emptive queue) stored here
138#define HOST_RX_EXP_WR_PTR_OFFSET_SIZE 0x4 138#define HOST_RX_PRE_WR_PTR_OFFSET_SIZE 0x4
139#define PORT_Q0_DESC_RD_PTR_OFFSET 0x0150 //Port Tx Q0 Desc Read pointer stored here 139#define HOST_RX_EXP_RD_PTR_OFFSET 0x0148 //Reserved for Future Use
140#define PORT_Q0_DESC_RD_PTR_OFFSET_SIZE 0x2 140#define HOST_RX_EXP_RD_PTR_OFFSET_SIZE 0x4
141#define PORT_Q0_DESC_WR_PTR_OFFSET 0x0152 //Port Tx Q0 Desc Write pointer stored here 141#define HOST_RX_EXP_WR_PTR_OFFSET 0x014C //Reserved for Future Use
142#define PORT_Q0_DESC_WR_PTR_OFFSET_SIZE 0x2 142#define HOST_RX_EXP_WR_PTR_OFFSET_SIZE 0x4
143#define PORT_Q1_DESC_RD_PTR_OFFSET 0x0154 //Port Tx Q1 Desc Read pointer stored here 143#define PORT_Q0_DESC_RD_PTR_OFFSET 0x0150 //Port Tx Q0 Desc Read pointer stored here
144#define PORT_Q1_DESC_RD_PTR_OFFSET_SIZE 0x2 144#define PORT_Q0_DESC_RD_PTR_OFFSET_SIZE 0x2
145#define PORT_Q1_DESC_WR_PTR_OFFSET 0x0156 //Port Tx Q1 Desc Write pointer stored here 145#define PORT_Q0_DESC_WR_PTR_OFFSET 0x0152 //Port Tx Q0 Desc Write pointer stored here
146#define PORT_Q1_DESC_WR_PTR_OFFSET_SIZE 0x2 146#define PORT_Q0_DESC_WR_PTR_OFFSET_SIZE 0x2
147#define PORT_Q2_DESC_RD_PTR_OFFSET 0x0158 //Port Tx Q2 Desc Read pointer stored here 147#define PORT_Q1_DESC_RD_PTR_OFFSET 0x0154 //Port Tx Q1 Desc Read pointer stored here
148#define PORT_Q2_DESC_RD_PTR_OFFSET_SIZE 0x2 148#define PORT_Q1_DESC_RD_PTR_OFFSET_SIZE 0x2
149#define PORT_Q2_DESC_WR_PTR_OFFSET 0x015A //Port Tx Q2 Desc Write pointer stored here 149#define PORT_Q1_DESC_WR_PTR_OFFSET 0x0156 //Port Tx Q1 Desc Write pointer stored here
150#define PORT_Q2_DESC_WR_PTR_OFFSET_SIZE 0x2 150#define PORT_Q1_DESC_WR_PTR_OFFSET_SIZE 0x2
151#define PORT_Q3_DESC_RD_PTR_OFFSET 0x015C //Port Tx Q3 Desc Read pointer stored here 151#define PORT_Q2_DESC_RD_PTR_OFFSET 0x0158 //Port Tx Q2 Desc Read pointer stored here
152#define PORT_Q3_DESC_RD_PTR_OFFSET_SIZE 0x2 152#define PORT_Q2_DESC_RD_PTR_OFFSET_SIZE 0x2
153#define PORT_Q3_DESC_WR_PTR_OFFSET 0x015E //Port Tx Q3 Desc Write pointer stored here 153#define PORT_Q2_DESC_WR_PTR_OFFSET 0x015A //Port Tx Q2 Desc Write pointer stored here
154#define PORT_Q3_DESC_WR_PTR_OFFSET_SIZE 0x2 154#define PORT_Q2_DESC_WR_PTR_OFFSET_SIZE 0x2
155#define PORT_Q4_DESC_RD_PTR_OFFSET 0x0160 //Port Tx Q4 Desc Read pointer stored here 155#define PORT_Q3_DESC_RD_PTR_OFFSET 0x015C //Port Tx Q3 Desc Read pointer stored here
156#define PORT_Q4_DESC_RD_PTR_OFFSET_SIZE 0x2 156#define PORT_Q3_DESC_RD_PTR_OFFSET_SIZE 0x2
157#define PORT_Q4_DESC_WR_PTR_OFFSET 0x0162 //Port Tx Q4 Desc Write pointer stored here 157#define PORT_Q3_DESC_WR_PTR_OFFSET 0x015E //Port Tx Q3 Desc Write pointer stored here
158#define PORT_Q4_DESC_WR_PTR_OFFSET_SIZE 0x2 158#define PORT_Q3_DESC_WR_PTR_OFFSET_SIZE 0x2
159#define PORT_Q5_DESC_RD_PTR_OFFSET 0x0164 //Port Tx Q5 Desc Read pointer stored here 159#define PORT_Q4_DESC_RD_PTR_OFFSET 0x0160 //Port Tx Q4 Desc Read pointer stored here
160#define PORT_Q5_DESC_RD_PTR_OFFSET_SIZE 0x2 160#define PORT_Q4_DESC_RD_PTR_OFFSET_SIZE 0x2
161#define PORT_Q5_DESC_WR_PTR_OFFSET 0x0166 //Port Tx Q5 Desc Write pointer stored here 161#define PORT_Q4_DESC_WR_PTR_OFFSET 0x0162 //Port Tx Q4 Desc Write pointer stored here
162#define PORT_Q5_DESC_WR_PTR_OFFSET_SIZE 0x2 162#define PORT_Q4_DESC_WR_PTR_OFFSET_SIZE 0x2
163#define PORT_Q6_DESC_RD_PTR_OFFSET 0x0168 //Port Tx Q3 Desc Read pointer stored here 163#define PORT_Q5_DESC_RD_PTR_OFFSET 0x0164 //Port Tx Q5 Desc Read pointer stored here
164#define PORT_Q6_DESC_RD_PTR_OFFSET_SIZE 0x2 164#define PORT_Q5_DESC_RD_PTR_OFFSET_SIZE 0x2
165#define PORT_Q6_DESC_WR_PTR_OFFSET 0x016A //Port Tx Q6 Desc Write pointer stored here 165#define PORT_Q5_DESC_WR_PTR_OFFSET 0x0166 //Port Tx Q5 Desc Write pointer stored here
166#define PORT_Q6_DESC_WR_PTR_OFFSET_SIZE 0x2 166#define PORT_Q5_DESC_WR_PTR_OFFSET_SIZE 0x2
167#define PORT_Q7_DESC_RD_PTR_OFFSET 0x016C //Port Tx Q7 Desc Read pointer stored here 167#define PORT_Q6_DESC_RD_PTR_OFFSET 0x0168 //Port Tx Q3 Desc Read pointer stored here
168#define PORT_Q7_DESC_RD_PTR_OFFSET_SIZE 0x2 168#define PORT_Q6_DESC_RD_PTR_OFFSET_SIZE 0x2
169#define PORT_Q7_DESC_WR_PTR_OFFSET 0x016E //Port Tx Q7 Desc Write pointer stored here 169#define PORT_Q6_DESC_WR_PTR_OFFSET 0x016A //Port Tx Q6 Desc Write pointer stored here
170#define PORT_Q7_DESC_WR_PTR_OFFSET_SIZE 0x2 170#define PORT_Q6_DESC_WR_PTR_OFFSET_SIZE 0x2
171#define HOST_Q0_DESC_RD_PTR_OFFSET 0x0170 //Host Tx Q0 Desc Read pointer stored here 171#define PORT_Q7_DESC_RD_PTR_OFFSET 0x016C //Port Tx Q7 Desc Read pointer stored here
172#define HOST_Q0_DESC_RD_PTR_OFFSET_SIZE 0x2 172#define PORT_Q7_DESC_RD_PTR_OFFSET_SIZE 0x2
173#define HOST_Q0_DESC_WR_PTR_OFFSET 0x0172 //Host Tx Q0 Desc Write pointer stored here 173#define PORT_Q7_DESC_WR_PTR_OFFSET 0x016E //Port Tx Q7 Desc Write pointer stored here
174#define HOST_Q0_DESC_WR_PTR_OFFSET_SIZE 0x2 174#define PORT_Q7_DESC_WR_PTR_OFFSET_SIZE 0x2
175#define HOST_Q1_DESC_RD_PTR_OFFSET 0x0174 //Host Tx Q1 Desc Read pointer stored here 175#define HOST_Q0_DESC_RD_PTR_OFFSET 0x0170 //Host Tx Q0 Desc Read pointer stored here
176#define HOST_Q1_DESC_RD_PTR_OFFSET_SIZE 0x2 176#define HOST_Q0_DESC_RD_PTR_OFFSET_SIZE 0x2
177#define HOST_Q1_DESC_WR_PTR_OFFSET 0x0176 //Host Tx Q1 Desc Write pointer stored here 177#define HOST_Q0_DESC_WR_PTR_OFFSET 0x0172 //Host Tx Q0 Desc Write pointer stored here
178#define HOST_Q1_DESC_WR_PTR_OFFSET_SIZE 0x2 178#define HOST_Q0_DESC_WR_PTR_OFFSET_SIZE 0x2
179#define HOST_Q2_DESC_RD_PTR_OFFSET 0x0178 //Host Tx Q2 Desc Read pointer stored here 179#define HOST_Q1_DESC_RD_PTR_OFFSET 0x0174 //Host Tx Q1 Desc Read pointer stored here
180#define HOST_Q2_DESC_RD_PTR_OFFSET_SIZE 0x2 180#define HOST_Q1_DESC_RD_PTR_OFFSET_SIZE 0x2
181#define HOST_Q2_DESC_WR_PTR_OFFSET 0x017A //Host Tx Q2 Desc Write pointer stored here 181#define HOST_Q1_DESC_WR_PTR_OFFSET 0x0176 //Host Tx Q1 Desc Write pointer stored here
182#define HOST_Q2_DESC_WR_PTR_OFFSET_SIZE 0x2 182#define HOST_Q1_DESC_WR_PTR_OFFSET_SIZE 0x2
183#define HOST_Q3_DESC_RD_PTR_OFFSET 0x017C //Host Tx Q3 Desc Read pointer stored here 183#define HOST_Q2_DESC_RD_PTR_OFFSET 0x0178 //Host Tx Q2 Desc Read pointer stored here
184#define HOST_Q3_DESC_RD_PTR_OFFSET_SIZE 0x2 184#define HOST_Q2_DESC_RD_PTR_OFFSET_SIZE 0x2
185#define HOST_Q3_DESC_WR_PTR_OFFSET 0x017E //Host Tx Q3 Desc Write pointer stored here 185#define HOST_Q2_DESC_WR_PTR_OFFSET 0x017A //Host Tx Q2 Desc Write pointer stored here
186#define HOST_Q3_DESC_WR_PTR_OFFSET_SIZE 0x2 186#define HOST_Q2_DESC_WR_PTR_OFFSET_SIZE 0x2
187#define HOST_Q4_DESC_RD_PTR_OFFSET 0x0180 //Host Tx Q4 Desc Read pointer stored here 187#define HOST_Q3_DESC_RD_PTR_OFFSET 0x017C //Host Tx Q3 Desc Read pointer stored here
188#define HOST_Q4_DESC_RD_PTR_OFFSET_SIZE 0x2 188#define HOST_Q3_DESC_RD_PTR_OFFSET_SIZE 0x2
189#define HOST_Q4_DESC_WR_PTR_OFFSET 0x0182 //Host Tx Q4 Desc Write pointer stored here 189#define HOST_Q3_DESC_WR_PTR_OFFSET 0x017E //Host Tx Q3 Desc Write pointer stored here
190#define HOST_Q4_DESC_WR_PTR_OFFSET_SIZE 0x2 190#define HOST_Q3_DESC_WR_PTR_OFFSET_SIZE 0x2
191#define HOST_Q5_DESC_RD_PTR_OFFSET 0x0184 //Host Tx Q5 Desc Read pointer stored here 191#define HOST_Q4_DESC_RD_PTR_OFFSET 0x0180 //Host Tx Q4 Desc Read pointer stored here
192#define HOST_Q5_DESC_RD_PTR_OFFSET_SIZE 0x2 192#define HOST_Q4_DESC_RD_PTR_OFFSET_SIZE 0x2
193#define HOST_Q5_DESC_WR_PTR_OFFSET 0x0186 //Host Tx Q5 Desc Write pointer stored here 193#define HOST_Q4_DESC_WR_PTR_OFFSET 0x0182 //Host Tx Q4 Desc Write pointer stored here
194#define HOST_Q5_DESC_WR_PTR_OFFSET_SIZE 0x2 194#define HOST_Q4_DESC_WR_PTR_OFFSET_SIZE 0x2
195#define HOST_Q6_DESC_RD_PTR_OFFSET 0x0188 //Host Tx Q6 Desc Read pointer stored here 195#define HOST_Q5_DESC_RD_PTR_OFFSET 0x0184 //Host Tx Q5 Desc Read pointer stored here
196#define HOST_Q6_DESC_RD_PTR_OFFSET_SIZE 0x2 196#define HOST_Q5_DESC_RD_PTR_OFFSET_SIZE 0x2
197#define HOST_Q6_DESC_WR_PTR_OFFSET 0x018A //Host Tx Q6 Desc Write pointer stored here 197#define HOST_Q5_DESC_WR_PTR_OFFSET 0x0186 //Host Tx Q5 Desc Write pointer stored here
198#define HOST_Q6_DESC_WR_PTR_OFFSET_SIZE 0x2 198#define HOST_Q5_DESC_WR_PTR_OFFSET_SIZE 0x2
199#define HOST_Q7_DESC_RD_PTR_OFFSET 0x018C //Host Tx Q7 Desc Read pointer stored here 199#define HOST_Q6_DESC_RD_PTR_OFFSET 0x0188 //Host Tx Q6 Desc Read pointer stored here
200#define HOST_Q7_DESC_RD_PTR_OFFSET_SIZE 0x2 200#define HOST_Q6_DESC_RD_PTR_OFFSET_SIZE 0x2
201#define HOST_Q7_DESC_WR_PTR_OFFSET 0x018E //Host Tx Q7 Desc Write pointer stored here 201#define HOST_Q6_DESC_WR_PTR_OFFSET 0x018A //Host Tx Q6 Desc Write pointer stored here
202#define HOST_Q7_DESC_WR_PTR_OFFSET_SIZE 0x2 202#define HOST_Q6_DESC_WR_PTR_OFFSET_SIZE 0x2
203#define VLAN_STATIC_REG_TABLE_OFFSET 0x0190 //VLAN-FID Table offset. 4096 VIDs. 2B per VID = 8KB = 0x2000 203#define HOST_Q7_DESC_RD_PTR_OFFSET 0x018C //Host Tx Q7 Desc Read pointer stored here
204#define VLAN_STATIC_REG_TABLE_OFFSET_SIZE 0x2000 204#define HOST_Q7_DESC_RD_PTR_OFFSET_SIZE 0x2
205#define EMAC_ICSSG_SWITCH_DEFAULT_VLAN_TABLE_OFFSET VLAN_STATIC_REG_TABLE_OFFSET //VLAN-FID Table offset for EMAC 205#define HOST_Q7_DESC_WR_PTR_OFFSET 0x018E //Host Tx Q7 Desc Write pointer stored here
206#define SMEM_VLAN_END_OF_MEM 0x2190 //End of VLAN-FID table marker 206#define HOST_Q7_DESC_WR_PTR_OFFSET_SIZE 0x2
207#define SMEM_VLAN_END_OF_MEM_SIZE 0x4 207#define VLAN_STATIC_REG_TABLE_OFFSET 0x0190 //VLAN-FID Table offset. 4096 VIDs. 2B per VID = 8KB = 0x2000
208#define PORT_Q0_CONTEXT_OFFSET 0x2194 //16B for Port Tx MSMC Q context 208#define VLAN_STATIC_REG_TABLE_OFFSET_SIZE 0x2000
209#define PORT_Q0_CONTEXT_OFFSET_SIZE (NRT_QUEUE_CONTEXT_SIZE) //0x10 209#define EMAC_ICSSG_SWITCH_DEFAULT_VLAN_TABLE_OFFSET VLAN_STATIC_REG_TABLE_OFFSET //VLAN-FID Table offset for EMAC
210#define EMAC_ICSSG_SWITCH_PORT_QUEUE_CONTEXT_OFFSET PORT_Q0_CONTEXT_OFFSET //Same as PORT_Q0_CONTEXT_OFFSET 210#define SMEM_VLAN_END_OF_MEM 0x2190 //End of VLAN-FID table marker
211#define PORT_Q1_CONTEXT_OFFSET 0x21A4 //16B for Port Tx MSMC Q context 211#define SMEM_VLAN_END_OF_MEM_SIZE 0x4
212#define PORT_Q1_CONTEXT_OFFSET_SIZE (NRT_QUEUE_CONTEXT_SIZE) //0x10 212#define PORT_Q0_CONTEXT_OFFSET 0x2194 //16B for Port Tx MSMC Q context
213#define PORT_Q2_CONTEXT_OFFSET 0x21B4 //16B for Port Tx MSMC Q context 213#define PORT_Q0_CONTEXT_OFFSET_SIZE (NRT_QUEUE_CONTEXT_SIZE) //0x10
214#define PORT_Q2_CONTEXT_OFFSET_SIZE (NRT_QUEUE_CONTEXT_SIZE) //0x10 214#define EMAC_ICSSG_SWITCH_PORT_QUEUE_CONTEXT_OFFSET PORT_Q0_CONTEXT_OFFSET //Same as PORT_Q0_CONTEXT_OFFSET
215#define PORT_Q3_CONTEXT_OFFSET 0x21C4 //16B for Port Tx MSMC Q context 215#define PORT_Q1_CONTEXT_OFFSET 0x21A4 //16B for Port Tx MSMC Q context
216#define PORT_Q3_CONTEXT_OFFSET_SIZE (NRT_QUEUE_CONTEXT_SIZE) //0x10 216#define PORT_Q1_CONTEXT_OFFSET_SIZE (NRT_QUEUE_CONTEXT_SIZE) //0x10
217#define PORT_Q4_CONTEXT_OFFSET 0x21D4 //16B for Port Tx MSMC Q context 217#define PORT_Q2_CONTEXT_OFFSET 0x21B4 //16B for Port Tx MSMC Q context
218#define PORT_Q4_CONTEXT_OFFSET_SIZE (NRT_QUEUE_CONTEXT_SIZE) //0x10 218#define PORT_Q2_CONTEXT_OFFSET_SIZE (NRT_QUEUE_CONTEXT_SIZE) //0x10
219#define PORT_Q5_CONTEXT_OFFSET 0x21E4 //16B for Port Tx MSMC Q context 219#define PORT_Q3_CONTEXT_OFFSET 0x21C4 //16B for Port Tx MSMC Q context
220#define PORT_Q5_CONTEXT_OFFSET_SIZE (NRT_QUEUE_CONTEXT_SIZE) //0x10 220#define PORT_Q3_CONTEXT_OFFSET_SIZE (NRT_QUEUE_CONTEXT_SIZE) //0x10
221#define PORT_Q6_CONTEXT_OFFSET 0x21F4 //16B for Port Tx MSMC Q context 221#define PORT_Q4_CONTEXT_OFFSET 0x21D4 //16B for Port Tx MSMC Q context
222#define PORT_Q6_CONTEXT_OFFSET_SIZE (NRT_QUEUE_CONTEXT_SIZE) //0x10 222#define PORT_Q4_CONTEXT_OFFSET_SIZE (NRT_QUEUE_CONTEXT_SIZE) //0x10
223#define PORT_Q7_CONTEXT_OFFSET 0x2204 //16B for Port Tx MSMC Q context 223#define PORT_Q5_CONTEXT_OFFSET 0x21E4 //16B for Port Tx MSMC Q context
224#define PORT_Q7_CONTEXT_OFFSET_SIZE (NRT_QUEUE_CONTEXT_SIZE) //0x10 224#define PORT_Q5_CONTEXT_OFFSET_SIZE (NRT_QUEUE_CONTEXT_SIZE) //0x10
225#define HOST_Q0_CONTEXT_OFFSET 0x2214 //16B for Host Tx MSMC Q context 225#define PORT_Q6_CONTEXT_OFFSET 0x21F4 //16B for Port Tx MSMC Q context
226#define HOST_Q0_CONTEXT_OFFSET_SIZE (NRT_QUEUE_CONTEXT_SIZE) //0x10 226#define PORT_Q6_CONTEXT_OFFSET_SIZE (NRT_QUEUE_CONTEXT_SIZE) //0x10
227#define HOST_Q1_CONTEXT_OFFSET 0x2224 //16B for Host Tx MSMC Q context 227#define PORT_Q7_CONTEXT_OFFSET 0x2204 //16B for Port Tx MSMC Q context
228#define HOST_Q1_CONTEXT_OFFSET_SIZE (NRT_QUEUE_CONTEXT_SIZE) //0x10 228#define PORT_Q7_CONTEXT_OFFSET_SIZE (NRT_QUEUE_CONTEXT_SIZE) //0x10
229#define HOST_Q2_CONTEXT_OFFSET 0x2234 //16B for Host Tx MSMC Q context 229#define HOST_Q0_CONTEXT_OFFSET 0x2214 //16B for Host Tx MSMC Q context
230#define HOST_Q2_CONTEXT_OFFSET_SIZE (NRT_QUEUE_CONTEXT_SIZE) //0x10 230#define HOST_Q0_CONTEXT_OFFSET_SIZE (NRT_QUEUE_CONTEXT_SIZE) //0x10
231#define HOST_Q3_CONTEXT_OFFSET 0x2244 //16B for Host Tx MSMC Q context 231#define HOST_Q1_CONTEXT_OFFSET 0x2224 //16B for Host Tx MSMC Q context
232#define HOST_Q3_CONTEXT_OFFSET_SIZE (NRT_QUEUE_CONTEXT_SIZE) //0x10 232#define HOST_Q1_CONTEXT_OFFSET_SIZE (NRT_QUEUE_CONTEXT_SIZE) //0x10
233#define HOST_Q4_CONTEXT_OFFSET 0x2254 //16B for Host Tx MSMC Q context 233#define HOST_Q2_CONTEXT_OFFSET 0x2234 //16B for Host Tx MSMC Q context
234#define HOST_Q4_CONTEXT_OFFSET_SIZE (NRT_QUEUE_CONTEXT_SIZE) //0x10 234#define HOST_Q2_CONTEXT_OFFSET_SIZE (NRT_QUEUE_CONTEXT_SIZE) //0x10
235#define HOST_Q5_CONTEXT_OFFSET 0x2264 //16B for Host Tx MSMC Q context 235#define HOST_Q3_CONTEXT_OFFSET 0x2244 //16B for Host Tx MSMC Q context
236#define HOST_Q5_CONTEXT_OFFSET_SIZE (NRT_QUEUE_CONTEXT_SIZE) //0x10 236#define HOST_Q3_CONTEXT_OFFSET_SIZE (NRT_QUEUE_CONTEXT_SIZE) //0x10
237#define HOST_Q6_CONTEXT_OFFSET 0x2274 //16B for Host Tx MSMC Q context 237#define HOST_Q4_CONTEXT_OFFSET 0x2254 //16B for Host Tx MSMC Q context
238#define HOST_Q6_CONTEXT_OFFSET_SIZE (NRT_QUEUE_CONTEXT_SIZE) //0x10 238#define HOST_Q4_CONTEXT_OFFSET_SIZE (NRT_QUEUE_CONTEXT_SIZE) //0x10
239#define HOST_Q7_CONTEXT_OFFSET 0x2284 //16B for Host Tx MSMC Q context 239#define HOST_Q5_CONTEXT_OFFSET 0x2264 //16B for Host Tx MSMC Q context
240#define HOST_Q7_CONTEXT_OFFSET_SIZE (NRT_QUEUE_CONTEXT_SIZE) //0x10 240#define HOST_Q5_CONTEXT_OFFSET_SIZE (NRT_QUEUE_CONTEXT_SIZE) //0x10
241#define HOST_RX_Q_PRE_CONTEXT_OFFSET 0x2294 //16B for Host Egress MSMC Q (Pre-emptible) context 241#define HOST_Q6_CONTEXT_OFFSET 0x2274 //16B for Host Tx MSMC Q context
242#define HOST_RX_Q_PRE_CONTEXT_OFFSET_SIZE (NRT_QUEUE_CONTEXT_SIZE) //0x10 242#define HOST_Q6_CONTEXT_OFFSET_SIZE (NRT_QUEUE_CONTEXT_SIZE) //0x10
243#define HOST_RX_Q_EXP_CONTEXT_OFFSET 0x22A4 //16B for Host Egress MSMC Q (Express) context 243#define HOST_Q7_CONTEXT_OFFSET 0x2284 //16B for Host Tx MSMC Q context
244#define HOST_RX_Q_EXP_CONTEXT_OFFSET_SIZE (NRT_QUEUE_CONTEXT_SIZE) //0x10 244#define HOST_Q7_CONTEXT_OFFSET_SIZE (NRT_QUEUE_CONTEXT_SIZE) //0x10
245#define DEFAULT_MSMC_Q_OFFSET (HOST_RX_Q_EXP_CONTEXT_OFFSET + 12) //End of NRT MSMC region. 245#define HOST_RX_Q_PRE_CONTEXT_OFFSET 0x2294 //16B for Host Egress MSMC Q (Pre-emptible) context
246#define PORT_Q0_DESC_CONTEXT_OFFSET 0x22B4 //16B for Port Tx Q Desc context 246#define HOST_RX_Q_PRE_CONTEXT_OFFSET_SIZE (NRT_QUEUE_CONTEXT_SIZE) //0x10
247#define PORT_Q0_DESC_CONTEXT_OFFSET_SIZE (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10 247#define HOST_RX_Q_EXP_CONTEXT_OFFSET 0x22A4 //16B for Host Egress MSMC Q (Express) context
248#define EMAC_ICSSG_SWITCH_PORT_DESC_QUEUE_CONTEXT_OFFSET PORT_Q0_DESC_CONTEXT_OFFSET //Start of Queue Descriptors for EMAC 248#define HOST_RX_Q_EXP_CONTEXT_OFFSET_SIZE (NRT_QUEUE_CONTEXT_SIZE) //0x10
249#define PORT_Q1_DESC_CONTEXT_OFFSET 0x22C4 //16B for Port Tx Q Desc context 249#define DEFAULT_MSMC_Q_OFFSET (HOST_RX_Q_EXP_CONTEXT_OFFSET + 12) //End of NRT MSMC region.
250#define PORT_Q1_DESC_CONTEXT_OFFSET_SIZE (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10 250#define PORT_Q0_DESC_CONTEXT_OFFSET 0x22B4 //16B for Port Tx Q Desc context
251#define PORT_Q2_DESC_CONTEXT_OFFSET 0x22D4 //16B for Port Tx Q Desc context 251#define PORT_Q0_DESC_CONTEXT_OFFSET_SIZE (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10
252#define PORT_Q2_DESC_CONTEXT_OFFSET_SIZE (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10 252#define EMAC_ICSSG_SWITCH_PORT_DESC_QUEUE_CONTEXT_OFFSET PORT_Q0_DESC_CONTEXT_OFFSET //Start of Queue Descriptors for EMAC
253#define PORT_Q3_DESC_CONTEXT_OFFSET 0x22E4 //16B for Port Tx Q Desc context 253#define PORT_Q1_DESC_CONTEXT_OFFSET 0x22C4 //16B for Port Tx Q Desc context
254#define PORT_Q3_DESC_CONTEXT_OFFSET_SIZE (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10 254#define PORT_Q1_DESC_CONTEXT_OFFSET_SIZE (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10
255#define PORT_Q4_DESC_CONTEXT_OFFSET 0x22F4 //16B for Port Tx Q Desc context 255#define PORT_Q2_DESC_CONTEXT_OFFSET 0x22D4 //16B for Port Tx Q Desc context
256#define PORT_Q4_DESC_CONTEXT_OFFSET_SIZE (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10 256#define PORT_Q2_DESC_CONTEXT_OFFSET_SIZE (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10
257#define PORT_Q5_DESC_CONTEXT_OFFSET 0x2304 //16B for Port Tx Q Desc context 257#define PORT_Q3_DESC_CONTEXT_OFFSET 0x22E4 //16B for Port Tx Q Desc context
258#define PORT_Q5_DESC_CONTEXT_OFFSET_SIZE (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10 258#define PORT_Q3_DESC_CONTEXT_OFFSET_SIZE (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10
259#define PORT_Q6_DESC_CONTEXT_OFFSET 0x2314 //16B for Port Tx Q Desc context 259#define PORT_Q4_DESC_CONTEXT_OFFSET 0x22F4 //16B for Port Tx Q Desc context
260#define PORT_Q6_DESC_CONTEXT_OFFSET_SIZE (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10 260#define PORT_Q4_DESC_CONTEXT_OFFSET_SIZE (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10
261#define PORT_Q7_DESC_CONTEXT_OFFSET 0x2324 //16B for Port Tx Q Desc context 261#define PORT_Q5_DESC_CONTEXT_OFFSET 0x2304 //16B for Port Tx Q Desc context
262#define PORT_Q7_DESC_CONTEXT_OFFSET_SIZE (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10 262#define PORT_Q5_DESC_CONTEXT_OFFSET_SIZE (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10
263#define HOST_Q0_DESC_CONTEXT_OFFSET 0x2334 //16B for Port Tx Q Desc context 263#define PORT_Q6_DESC_CONTEXT_OFFSET 0x2314 //16B for Port Tx Q Desc context
264#define HOST_Q0_DESC_CONTEXT_OFFSET_SIZE (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10 264#define PORT_Q6_DESC_CONTEXT_OFFSET_SIZE (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10
265#define HOST_Q1_DESC_CONTEXT_OFFSET 0x2344 //16B for Host Tx Q Desc context 265#define PORT_Q7_DESC_CONTEXT_OFFSET 0x2324 //16B for Port Tx Q Desc context
266#define HOST_Q1_DESC_CONTEXT_OFFSET_SIZE (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10 266#define PORT_Q7_DESC_CONTEXT_OFFSET_SIZE (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10
267#define HOST_Q2_DESC_CONTEXT_OFFSET 0x2354 //16B for Host Tx Q Desc context 267#define HOST_Q0_DESC_CONTEXT_OFFSET 0x2334 //16B for Port Tx Q Desc context
268#define HOST_Q2_DESC_CONTEXT_OFFSET_SIZE (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10 268#define HOST_Q0_DESC_CONTEXT_OFFSET_SIZE (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10
269#define HOST_Q3_DESC_CONTEXT_OFFSET 0x2364 //16B for Host Tx Q Desc context 269#define HOST_Q1_DESC_CONTEXT_OFFSET 0x2344 //16B for Host Tx Q Desc context
270#define HOST_Q3_DESC_CONTEXT_OFFSET_SIZE (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10 270#define HOST_Q1_DESC_CONTEXT_OFFSET_SIZE (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10
271#define HOST_Q4_DESC_CONTEXT_OFFSET 0x2374 //16B for Host Tx Q Desc context 271#define HOST_Q2_DESC_CONTEXT_OFFSET 0x2354 //16B for Host Tx Q Desc context
272#define HOST_Q4_DESC_CONTEXT_OFFSET_SIZE (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10 272#define HOST_Q2_DESC_CONTEXT_OFFSET_SIZE (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10
273#define HOST_Q5_DESC_CONTEXT_OFFSET 0x2384 //16B for Host Tx Q Desc context 273#define HOST_Q3_DESC_CONTEXT_OFFSET 0x2364 //16B for Host Tx Q Desc context
274#define HOST_Q5_DESC_CONTEXT_OFFSET_SIZE (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10 274#define HOST_Q3_DESC_CONTEXT_OFFSET_SIZE (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10
275#define HOST_Q6_DESC_CONTEXT_OFFSET 0x2394 //16B for Host Tx Q Desc context 275#define HOST_Q4_DESC_CONTEXT_OFFSET 0x2374 //16B for Host Tx Q Desc context
276#define HOST_Q6_DESC_CONTEXT_OFFSET_SIZE (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10 276#define HOST_Q4_DESC_CONTEXT_OFFSET_SIZE (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10
277#define HOST_Q7_DESC_CONTEXT_OFFSET 0x23A4 //16B for Host Tx Q Desc context 277#define HOST_Q5_DESC_CONTEXT_OFFSET 0x2384 //16B for Host Tx Q Desc context
278#define HOST_Q7_DESC_CONTEXT_OFFSET_SIZE (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10 278#define HOST_Q5_DESC_CONTEXT_OFFSET_SIZE (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10
279#define HOST_RX_Q_PRE_DESC_CONTEXT_OFFSET 0x23B4 //16B for Host Egress Q (pre-emptible) Desc context 279#define HOST_Q6_DESC_CONTEXT_OFFSET 0x2394 //16B for Host Tx Q Desc context
280#define HOST_RX_Q_PRE_DESC_CONTEXT_OFFSET_SIZE (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10 280#define HOST_Q6_DESC_CONTEXT_OFFSET_SIZE (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10
281#define HOST_RX_Q_EXP_DESC_CONTEXT_OFFSET 0x23C4 //16B for Host Egress Q (Express) Desc context. redundant 281#define HOST_Q7_DESC_CONTEXT_OFFSET 0x23A4 //16B for Host Tx Q Desc context
282#define HOST_RX_Q_EXP_DESC_CONTEXT_OFFSET_SIZE (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10 282#define HOST_Q7_DESC_CONTEXT_OFFSET_SIZE (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10
283#define PORT_DESC_Q0_OFFSET 0x23D4 //packet descriptor Q reserved memory 283#define HOST_RX_Q_PRE_DESC_CONTEXT_OFFSET 0x23B4 //16B for Host Egress Q (pre-emptible) Desc context
284#define PORT_DESC_Q0_OFFSET_SIZE (NRT_PORT_DESC_QUEUE_SIZE) //0x734 284#define HOST_RX_Q_PRE_DESC_CONTEXT_OFFSET_SIZE (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10
285#define PORT_DESC_Q1_OFFSET 0x2B08 //packet descriptor Q reserved memory for Port Tx queues 285#define HOST_RX_Q_EXP_DESC_CONTEXT_OFFSET 0x23C4 //16B for Host Egress Q (Express) Desc context. redundant
286#define PORT_DESC_Q1_OFFSET_SIZE (NRT_PORT_DESC_QUEUE_SIZE) //0x734 286#define HOST_RX_Q_EXP_DESC_CONTEXT_OFFSET_SIZE (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10
287#define PORT_DESC_Q2_OFFSET 0x323C //packet descriptor Q reserved memory for Port Tx queues 287#define PORT_DESC_Q0_OFFSET 0x23D4 //packet descriptor Q reserved memory
288#define PORT_DESC_Q2_OFFSET_SIZE (NRT_PORT_DESC_QUEUE_SIZE) //0x734 288#define PORT_DESC_Q0_OFFSET_SIZE (NRT_PORT_DESC_QUEUE_SIZE) //0x734
289#define PORT_DESC_Q3_OFFSET 0x3970 //packet descriptor Q reserved memory for Port Tx queues 289#define PORT_DESC_Q1_OFFSET 0x2B08 //packet descriptor Q reserved memory for Port Tx queues
290#define PORT_DESC_Q3_OFFSET_SIZE (NRT_PORT_DESC_QUEUE_SIZE) //0x734 290#define PORT_DESC_Q1_OFFSET_SIZE (NRT_PORT_DESC_QUEUE_SIZE) //0x734
291#define PORT_DESC_Q4_OFFSET 0x40A4 //packet descriptor Q reserved memory for Port Tx queues 291#define PORT_DESC_Q2_OFFSET 0x323C //packet descriptor Q reserved memory for Port Tx queues
292#define PORT_DESC_Q4_OFFSET_SIZE (NRT_PORT_DESC_QUEUE_SIZE) //0x734 292#define PORT_DESC_Q2_OFFSET_SIZE (NRT_PORT_DESC_QUEUE_SIZE) //0x734
293#define PORT_DESC_Q5_OFFSET 0x47D8 //packet descriptor Q reserved memory for Port Tx queues 293#define PORT_DESC_Q3_OFFSET 0x3970 //packet descriptor Q reserved memory for Port Tx queues
294#define PORT_DESC_Q5_OFFSET_SIZE (NRT_PORT_DESC_QUEUE_SIZE) //0x734 294#define PORT_DESC_Q3_OFFSET_SIZE (NRT_PORT_DESC_QUEUE_SIZE) //0x734
295#define PORT_DESC_Q6_OFFSET 0x4F0C //packet descriptor Q reserved memory for Port Tx queues 295#define PORT_DESC_Q4_OFFSET 0x40A4 //packet descriptor Q reserved memory for Port Tx queues
296#define PORT_DESC_Q6_OFFSET_SIZE (NRT_PORT_DESC_QUEUE_SIZE) //0x734 296#define PORT_DESC_Q4_OFFSET_SIZE (NRT_PORT_DESC_QUEUE_SIZE) //0x734
297#define PORT_DESC_Q7_OFFSET 0x5640 //packet descriptor Q reserved memory for Port Tx queues 297#define PORT_DESC_Q5_OFFSET 0x47D8 //packet descriptor Q reserved memory for Port Tx queues
298#define PORT_DESC_Q7_OFFSET_SIZE (NRT_PORT_DESC_QUEUE_SIZE) //0x734 298#define PORT_DESC_Q5_OFFSET_SIZE (NRT_PORT_DESC_QUEUE_SIZE) //0x734
299#define HOST_DESC_Q0_OFFSET 0x5D74 //packet descriptor Q reserved memory for Host Tx queues 299#define PORT_DESC_Q6_OFFSET 0x4F0C //packet descriptor Q reserved memory for Port Tx queues
300#define HOST_DESC_Q0_OFFSET_SIZE (NRT_HOST_DESC_QUEUE_SIZE) //0x234 300#define PORT_DESC_Q6_OFFSET_SIZE (NRT_PORT_DESC_QUEUE_SIZE) //0x734
301#define HOST_DESC_Q1_OFFSET 0x5FA8 //packet descriptor Q reserved memory for Host Tx queues 301#define PORT_DESC_Q7_OFFSET 0x5640 //packet descriptor Q reserved memory for Port Tx queues
302#define HOST_DESC_Q1_OFFSET_SIZE (NRT_HOST_DESC_QUEUE_SIZE) //0x234 302#define PORT_DESC_Q7_OFFSET_SIZE (NRT_PORT_DESC_QUEUE_SIZE) //0x734
303#define HOST_DESC_Q2_OFFSET 0x61DC //packet descriptor Q reserved memory for Host Tx queues 303#define HOST_DESC_Q0_OFFSET 0x5D74 //packet descriptor Q reserved memory for Host Tx queues
304#define HOST_DESC_Q2_OFFSET_SIZE (NRT_HOST_DESC_QUEUE_SIZE) //0x234 304#define HOST_DESC_Q0_OFFSET_SIZE (NRT_HOST_DESC_QUEUE_SIZE) //0x234
305#define HOST_DESC_Q3_OFFSET 0x6410 //packet descriptor Q reserved memory for Host Tx queues 305#define HOST_DESC_Q1_OFFSET 0x5FA8 //packet descriptor Q reserved memory for Host Tx queues
306#define HOST_DESC_Q3_OFFSET_SIZE (NRT_HOST_DESC_QUEUE_SIZE) //0x234 306#define HOST_DESC_Q1_OFFSET_SIZE (NRT_HOST_DESC_QUEUE_SIZE) //0x234
307#define HOST_DESC_Q4_OFFSET 0x6644 //packet descriptor Q reserved memory for Host Tx queues 307#define HOST_DESC_Q2_OFFSET 0x61DC //packet descriptor Q reserved memory for Host Tx queues
308#define HOST_DESC_Q4_OFFSET_SIZE (NRT_HOST_DESC_QUEUE_SIZE) //0x234 308#define HOST_DESC_Q2_OFFSET_SIZE (NRT_HOST_DESC_QUEUE_SIZE) //0x234
309#define HOST_DESC_Q5_OFFSET 0x6878 //packet descriptor Q reserved memory for Host Tx queues 309#define HOST_DESC_Q3_OFFSET 0x6410 //packet descriptor Q reserved memory for Host Tx queues
310#define HOST_DESC_Q5_OFFSET_SIZE (NRT_HOST_DESC_QUEUE_SIZE) //0x234 310#define HOST_DESC_Q3_OFFSET_SIZE (NRT_HOST_DESC_QUEUE_SIZE) //0x234
311#define HOST_DESC_Q6_OFFSET 0x6AAC //packet descriptor Q reserved memory for Host Tx queues 311#define HOST_DESC_Q4_OFFSET 0x6644 //packet descriptor Q reserved memory for Host Tx queues
312#define HOST_DESC_Q6_OFFSET_SIZE (NRT_HOST_DESC_QUEUE_SIZE) //0x234 312#define HOST_DESC_Q4_OFFSET_SIZE (NRT_HOST_DESC_QUEUE_SIZE) //0x234
313#define HOST_DESC_Q7_OFFSET 0x6CE0 //packet descriptor Q reserved memory for Host Tx queues 313#define HOST_DESC_Q5_OFFSET 0x6878 //packet descriptor Q reserved memory for Host Tx queues
314#define HOST_DESC_Q7_OFFSET_SIZE (NRT_HOST_DESC_QUEUE_SIZE) //0x234 314#define HOST_DESC_Q5_OFFSET_SIZE (NRT_HOST_DESC_QUEUE_SIZE) //0x234
315#define HOST_RX_DESC_Q_PRE_OFFSET 0x6F14 //packet descriptor Q reserved memory for Host Egress (Pre-emptible) queues 315#define HOST_DESC_Q6_OFFSET 0x6AAC //packet descriptor Q reserved memory for Host Tx queues
316#define HOST_RX_DESC_Q_PRE_OFFSET_SIZE (NRT_PORT_DESC_QUEUE_SIZE) //0x734 316#define HOST_DESC_Q6_OFFSET_SIZE (NRT_HOST_DESC_QUEUE_SIZE) //0x234
317#define HOST_RX_DESC_Q_EXP_OFFSET 0x7648 //packet descriptor Q reserved memory for Host Egress (Pre-emptible) queues. redundant 317#define HOST_DESC_Q7_OFFSET 0x6CE0 //packet descriptor Q reserved memory for Host Tx queues
318#define HOST_RX_DESC_Q_EXP_OFFSET_SIZE (NRT_PORT_DESC_QUEUE_SIZE) //0x734 318#define HOST_DESC_Q7_OFFSET_SIZE (NRT_HOST_DESC_QUEUE_SIZE) //0x234
319#define SHARED_MEMORY_END_OFFSET 0x7D7C 319#define HOST_RX_DESC_Q_PRE_OFFSET 0x6F14 //packet descriptor Q reserved memory for Host Egress (Pre-emptible) queues
320 320#define HOST_RX_DESC_Q_PRE_OFFSET_SIZE (NRT_PORT_DESC_QUEUE_SIZE) //0x734
321// total SHARED_MEMORY memory usage : 31.37109375 KB from total of 64.0KB 321#define HOST_RX_DESC_Q_EXP_OFFSET 0x7648 //packet descriptor Q reserved memory for Host Egress (Pre-emptible) queues. redundant
322 322#define HOST_RX_DESC_Q_EXP_OFFSET_SIZE (NRT_PORT_DESC_QUEUE_SIZE) //0x734
323//************************************************************************************ 323#define SHARED_MEMORY_END_OFFSET 0x7D7C
324// 324
325// Memory Usage of : MSMC 325// total SHARED_MEMORY memory usage : 31.37109375 KB from total of 64.0KB
326// 326
327//************************************************************************************ 327//************************************************************************************
328 328//
329#define MSMC_START_OFFSET 0x0000 329// Memory Usage of : MSMC
330#define MSMC_END_OFFSET 0x0000 330//
331 331//************************************************************************************
332// total MSMC memory usage : 0.0 KB from total of 2048.0KB 332
333 333#define MSMC_START_OFFSET 0x0000
334//************************************************************************************ 334#define MSMC_END_OFFSET 0x0000
335// 335
336// Memory Usage of : DMEM0 336// total MSMC memory usage : 0.0 KB from total of 2048.0KB
337// 337
338//************************************************************************************ 338//************************************************************************************
339 339//
340#define DMEM0_START_OFFSET 0x0000 340// Memory Usage of : DMEM0
341#define PORT_Q_PRIORITY_REGEN_OFFSET 0x0000 //Stores the table used for priority regeneration. 4B per PCP/Queue. Only 1B is used 341//
342#define PORT_Q_PRIORITY_REGEN_OFFSET_SIZE 0x20 342//************************************************************************************
343#define EXPRESS_PRE_EMPTIVE_Q_MAP 0x0020 //For marking packet as priority/express (this feature is disabled) or cut-through/S&F. One per slice 343
344#define EXPRESS_PRE_EMPTIVE_Q_MAP_SIZE 0x20 344#define DMEM0_START_OFFSET 0x0000
345#define TAS_CONFIG_CHANGE_TIME 0x0040 //New list is copied at this time 345#define PORT_Q_PRIORITY_REGEN_OFFSET 0x0000 //Stores the table used for priority regeneration. 4B per PCP/Queue. Only 1B is used
346#define TAS_CONFIG_CHANGE_TIME_SIZE 0x8 346#define PORT_Q_PRIORITY_REGEN_OFFSET_SIZE 0x20
347#define TAS_CONFIG_CHANGE_ERROR_COUNTER 0x0048 //config change error counter 347#define EXPRESS_PRE_EMPTIVE_Q_MAP 0x0020 //For marking packet as priority/express (this feature is disabled) or cut-through/S&F. One per slice
348#define TAS_CONFIG_CHANGE_ERROR_COUNTER_SIZE 0x4 348#define EXPRESS_PRE_EMPTIVE_Q_MAP_SIZE 0x20
349#define TAS_CONFIG_PENDING 0x004C //TAS List update pending flag 349#define TAS_CONFIG_CHANGE_TIME 0x0040 //New list is copied at this time
350#define TAS_CONFIG_PENDING_SIZE 0x1 350#define TAS_CONFIG_CHANGE_TIME_SIZE 0x8
351#define TAS_CONFIG_CHANGE 0x004D //TAS list update trigger flag 351#define TAS_CONFIG_CHANGE_ERROR_COUNTER 0x0048 //config change error counter
352#define TAS_CONFIG_CHANGE_SIZE 0x1 352#define TAS_CONFIG_CHANGE_ERROR_COUNTER_SIZE 0x4
353//Padding of 2 bytes 353#define TAS_CONFIG_PENDING 0x004C //TAS List update pending flag
354#define TAS_ADMIN_CYCLE_TIME 0x0050 //Cycle time for the new TAS schedule 354#define TAS_CONFIG_PENDING_SIZE 0x1
355#define TAS_ADMIN_CYCLE_TIME_SIZE 0x4 355#define TAS_CONFIG_CHANGE 0x004D //TAS list update trigger flag
356#define TAS_CONFIG_CHANGE_CYCLE_COUNT 0x0054 //Cycle counts remaining till the TAS list update 356#define TAS_CONFIG_CHANGE_SIZE 0x1
357#define TAS_CONFIG_CHANGE_CYCLE_COUNT_SIZE 0x4 357//Padding of 2 bytes
358#define TAS_SHADOW_EXPIRY_LIST_GATE0 0x0100 //TAS gate expiry list for gate0 358#define TAS_ADMIN_CYCLE_TIME 0x0050 //Cycle time for the new TAS schedule
359#define TAS_SHADOW_EXPIRY_LIST_GATE0_SIZE 0x20 359#define TAS_ADMIN_CYCLE_TIME_SIZE 0x4
360#define TAS_SHADOW_EXPIRY_LIST_GATE1 0x0120 //TAS gate expiry list for gate1 360#define TAS_CONFIG_CHANGE_CYCLE_COUNT 0x0054 //Cycle counts remaining till the TAS list update
361#define TAS_SHADOW_EXPIRY_LIST_GATE1_SIZE 0x20 361#define TAS_CONFIG_CHANGE_CYCLE_COUNT_SIZE 0x4
362#define TAS_SHADOW_EXPIRY_LIST_GATE2 0x0140 //TAS gate expiry list for gate2 362#define PORT_Q_PRIORITY_MAPPING_OFFSET 0x0058 //Stores the table used for priority mapping. 1B per PCP/Queue
363#define TAS_SHADOW_EXPIRY_LIST_GATE2_SIZE 0x20 363#define PORT_Q_PRIORITY_MAPPING_OFFSET_SIZE 0x8
364#define TAS_SHADOW_EXPIRY_LIST_GATE3 0x0160 //TAS gate expiry list for gate3 364#define TAS_SHADOW_EXPIRY_LIST_GATE0 0x0100 //TAS gate expiry list for gate0
365#define TAS_SHADOW_EXPIRY_LIST_GATE3_SIZE 0x20 365#define TAS_SHADOW_EXPIRY_LIST_GATE0_SIZE 0x20
366#define TAS_SHADOW_EXPIRY_LIST_GATE4 0x0180 //TAS gate expiry list for gate4 366#define TAS_SHADOW_EXPIRY_LIST_GATE1 0x0120 //TAS gate expiry list for gate1
367#define TAS_SHADOW_EXPIRY_LIST_GATE4_SIZE 0x20 367#define TAS_SHADOW_EXPIRY_LIST_GATE1_SIZE 0x20
368#define TAS_SHADOW_EXPIRY_LIST_GATE5 0x01A0 //TAS gate expiry list for gate5 368#define TAS_SHADOW_EXPIRY_LIST_GATE2 0x0140 //TAS gate expiry list for gate2
369#define TAS_SHADOW_EXPIRY_LIST_GATE5_SIZE 0x20 369#define TAS_SHADOW_EXPIRY_LIST_GATE2_SIZE 0x20
370#define TAS_SHADOW_EXPIRY_LIST_GATE6 0x01C0 //TAS gate expiry list for gate6 370#define TAS_SHADOW_EXPIRY_LIST_GATE3 0x0160 //TAS gate expiry list for gate3
371#define TAS_SHADOW_EXPIRY_LIST_GATE6_SIZE 0x20 371#define TAS_SHADOW_EXPIRY_LIST_GATE3_SIZE 0x20
372#define TAS_SHADOW_EXPIRY_LIST_GATE7 0x01E0 //TAS gate expiry list for gate7 372#define TAS_SHADOW_EXPIRY_LIST_GATE4 0x0180 //TAS gate expiry list for gate4
373#define TAS_SHADOW_EXPIRY_LIST_GATE7_SIZE 0x20 373#define TAS_SHADOW_EXPIRY_LIST_GATE4_SIZE 0x20
374#define PRE_EMPTION_ENABLE_TX 0x0200 //Memory to Enable/Disable Preemption on TX side 374#define TAS_SHADOW_EXPIRY_LIST_GATE5 0x01A0 //TAS gate expiry list for gate5
375#define PRE_EMPTION_ENABLE_TX_SIZE 0x1 375#define TAS_SHADOW_EXPIRY_LIST_GATE5_SIZE 0x20
376#define PRE_EMPTION_ACTIVE_TX 0x0201 //Active State of Preemption on TX side 376#define TAS_SHADOW_EXPIRY_LIST_GATE6 0x01C0 //TAS gate expiry list for gate6
377#define PRE_EMPTION_ACTIVE_TX_SIZE 0x1 377#define TAS_SHADOW_EXPIRY_LIST_GATE6_SIZE 0x20
378#define PRE_EMPTION_ENABLE_VERIFY 0x0202 //Memory to Enable/Disable Verify State Machine Preemption 378#define TAS_SHADOW_EXPIRY_LIST_GATE7 0x01E0 //TAS gate expiry list for gate7
379#define PRE_EMPTION_ENABLE_VERIFY_SIZE 0x1 379#define TAS_SHADOW_EXPIRY_LIST_GATE7_SIZE 0x20
380#define PRE_EMPTION_VERIFY_STATUS 0x0203 //Verify Status of State Machine 380#define PRE_EMPTION_ENABLE_TX 0x0200 //Memory to Enable/Disable Preemption on TX side
381#define PRE_EMPTION_VERIFY_STATUS_SIZE 0x1 381#define PRE_EMPTION_ENABLE_TX_SIZE 0x1
382#define PRE_EMPTION_ADD_FRAG_SIZE_REMOTE 0x0204 //Non Final Fragment Size supported by Link Partner 382#define PRE_EMPTION_ACTIVE_TX 0x0201 //Active State of Preemption on TX side
383#define PRE_EMPTION_ADD_FRAG_SIZE_REMOTE_SIZE 0x2 383#define PRE_EMPTION_ACTIVE_TX_SIZE 0x1
384#define PRE_EMPTION_ADD_FRAG_SIZE_LOCAL 0x0206 //Non Final Fragment Size supported by Firmware 384#define PRE_EMPTION_ENABLE_VERIFY 0x0202 //Memory to Enable/Disable Verify State Machine Preemption
385#define PRE_EMPTION_ADD_FRAG_SIZE_LOCAL_SIZE 0x1 385#define PRE_EMPTION_ENABLE_VERIFY_SIZE 0x1
386//Padding of 1 bytes 386#define PRE_EMPTION_VERIFY_STATUS 0x0203 //Verify Status of State Machine
387#define PRE_EMPTION_VERIFY_TIME 0x0208 //Time in ms the State machine waits for respond packet 387#define PRE_EMPTION_VERIFY_STATUS_SIZE 0x1
388#define PRE_EMPTION_VERIFY_TIME_SIZE 0x2 388#define PRE_EMPTION_ADD_FRAG_SIZE_REMOTE 0x0204 //Non Final Fragment Size supported by Link Partner
389#define DMEM0_END_OFFSET 0x020A 389#define PRE_EMPTION_ADD_FRAG_SIZE_REMOTE_SIZE 0x2
390 390#define PRE_EMPTION_ADD_FRAG_SIZE_LOCAL 0x0206 //Non Final Fragment Size supported by Firmware
391// total DMEM0 memory usage : 0.509765625 KB from total of 8.0KB 391#define PRE_EMPTION_ADD_FRAG_SIZE_LOCAL_SIZE 0x1
392 392//Padding of 1 bytes
393//************************************************************************************ 393#define PRE_EMPTION_VERIFY_TIME 0x0208 //Time in ms the State machine waits for respond packet
394// 394#define PRE_EMPTION_VERIFY_TIME_SIZE 0x2
395// Memory Usage of : DMEM1 395#define DMEM0_END_OFFSET 0x020A
396// 396
397//************************************************************************************ 397// total DMEM0 memory usage : 0.509765625 KB from total of 8.0KB
398 398
399#define DMEM1_START_OFFSET 0x0000 399//************************************************************************************
400#define ICSS_FIRMWARE_VERSION_OFFSET 0x0000 //ICSSG Firmware version details 400//
401#define ICSS_FIRMWARE_VERSION_OFFSET_SIZE 0xc 401// Memory Usage of : DMEM1
402#define NRT_FRAME_PREEMPTION_ENABLE_OFFSET 0x000C //Memory used for Global enable and disable Frame Preemption 402//
403#define NRT_FRAME_PREEMPTION_ENABLE_OFFSET_SIZE 0x4 403//************************************************************************************
404#define NRT_STASHED_Q_NUM_OFFSET 0x0010 //Memory used for Stashing queue number during Host Egress in BG Task 404
405#define NRT_STASHED_Q_NUM_OFFSET_SIZE 0x4 405#define DMEM1_START_OFFSET 0x0000
406#define PSI_TX_PKT_DATA_OFFSET 0x0014 //Used Internally by FW. 406#define ICSS_FIRMWARE_VERSION_OFFSET 0x0000 //ICSSG Firmware version details
407#define PSI_TX_PKT_DATA_OFFSET_SIZE 0x24 407#define ICSS_FIRMWARE_VERSION_OFFSET_SIZE 0xc
408#define LEARNING_WR_RD_COUNT_OFFSET 0x0038 //Used Internally by FW to synchronize FDB Learning between RTU0 and PRU0 408#define NRT_FRAME_PREEMPTION_ENABLE_OFFSET 0x000C //Memory used for Global enable and disable Frame Preemption
409#define LEARNING_WR_RD_COUNT_OFFSET_SIZE 0x4 409#define NRT_FRAME_PREEMPTION_ENABLE_OFFSET_SIZE 0x4
410#define FDB_G0_M_G1_SLV_OFFSET 0x003C //Used Internally by FW to synchronize FDB Learning between two ICSSG's 410#define NRT_STASHED_Q_NUM_OFFSET 0x0010 //Memory used for Stashing queue number during Host Egress in BG Task
411#define FDB_G0_M_G1_SLV_OFFSET_SIZE 0x4 411#define NRT_STASHED_Q_NUM_OFFSET_SIZE 0x4
412#define FDB_G1_M_G0_SLV_OFFSET 0x0040 //Used Internally by FW to synchronize FDB Learning between two ICSSG's 412#define PSI_TX_PKT_DATA_OFFSET 0x0014 //Used Internally by FW.
413#define FDB_G1_M_G0_SLV_OFFSET_SIZE 0x4 413#define PSI_TX_PKT_DATA_OFFSET_SIZE 0x24
414#define FDB_SYNC_ENTRY 0x0044 //Used to store the FDB entry one ICSSG learnt and one that needs to be communicated to other ICSSG 414#define LEARNING_WR_RD_COUNT_OFFSET 0x0038 //Used Internally by FW to synchronize FDB Learning between RTU0 and PRU0
415#define FDB_SYNC_ENTRY_SIZE 0x10 415#define LEARNING_WR_RD_COUNT_OFFSET_SIZE 0x4
416#define DEBUG_FDB_COMPARISON_MAC_VLAN 0x0054 //Used for debugging FDB lookups, write the MAC and VLAN combination that is suspect. Currently disabled 416#define FDB_G0_M_G1_SLV_OFFSET 0x003C //Used Internally by FW to synchronize FDB Learning between two ICSSG's
417#define DEBUG_FDB_COMPARISON_MAC_VLAN_SIZE 0x8 417#define FDB_G0_M_G1_SLV_OFFSET_SIZE 0x4
418#define DEBUG_FDB_RESULTS 0x005C //The results of FBD lookup for Local injection are dumped here 418#define FDB_G1_M_G0_SLV_OFFSET 0x0040 //Used Internally by FW to synchronize FDB Learning between two ICSSG's
419#define DEBUG_FDB_RESULTS_SIZE 0xc 419#define FDB_G1_M_G0_SLV_OFFSET_SIZE 0x4
420#define FDB_AGEING_TIMEOUT_OFFSET 0x0068 //Time after which FDB entries are checked for aged out values. Value in nanoseconds 420#define FDB_SYNC_ENTRY 0x0044 //Used to store the FDB entry one ICSSG learnt and one that needs to be communicated to other ICSSG
421#define FDB_AGEING_TIMEOUT_OFFSET_SIZE 0x8 421#define FDB_SYNC_ENTRY_SIZE 0x10
422#define DMEM1_END_OFFSET 0x0100 422#define DEBUG_FDB_COMPARISON_MAC_VLAN 0x0054 //Used for debugging FDB lookups, write the MAC and VLAN combination that is suspect. Currently disabled
423 423#define DEBUG_FDB_COMPARISON_MAC_VLAN_SIZE 0x8
424// total DMEM1 memory usage : 0.25 KB from total of 8.0KB 424#define DEBUG_FDB_RESULTS 0x005C //The results of FBD lookup for Local injection are dumped here
425 425#define DEBUG_FDB_RESULTS_SIZE 0xc
426//************************************************************************************ 426#define FDB_AGEING_TIMEOUT_OFFSET 0x0068 //Time after which FDB entries are checked for aged out values. Value in nanoseconds
427// 427#define FDB_AGEING_TIMEOUT_OFFSET_SIZE 0x8
428// Memory Usage of : PRU0_BSRAM 428#define L2_2_L1_BYTES_SENT_COUNT_OFFSET 0x0070 //Number of bytes sent by Tx L2 FIFO to L1 FIFO. Only 2 out of 4 bytes used.
429// 429#define L2_2_L1_BYTES_SENT_COUNT_OFFSET_SIZE 0x4
430//************************************************************************************ 430#define DMEM1_END_OFFSET 0x0100
431 431
432#define PRU0_BSRAM_START_OFFSET 0x0000 432// total DMEM1 memory usage : 0.25 KB from total of 8.0KB
433#define PSI_TX_INFO_SLOT_PRU0 0x0000 //Store PSI template for INFO chunk 433
434#define PSI_TX_INFO_SLOT_PRU0_SIZE 0x1 434//************************************************************************************
435#define HOST_RX_PACKET_DESC_SLOT_PRU0 0x0001 //Stores the PSI descriptor for packet being sent to Host 435//
436#define HOST_RX_PACKET_DESC_SLOT_PRU0_SIZE 0x1 436// Memory Usage of : PRU0_BSRAM
437#define HOST_RX_PRE_CONTEXT_RD_SLOT_PRU0 0x0002 //Contains context info for Host Egress Queue (pre-emptible). Used by read task 437//
438#define HOST_RX_PRE_CONTEXT_RD_SLOT_PRU0_SIZE 0x1 438//************************************************************************************
439#define HOST_RX_PRE_CONTEXT_WR_SLOT_PRU0 0x0003 //Contains context info for Host Egress Queue (pre-emptible). Used by write task 439
440#define HOST_RX_PRE_CONTEXT_WR_SLOT_PRU0_SIZE 0x1 440#define PRU0_BSRAM_START_OFFSET 0x0000
441#define HOST_RX_EXP_CONTEXT_RD_SLOT_PRU0 0x0004 //Contains context info for Host Egress Queue (express). redundant 441#define PSI_TX_INFO_SLOT_PRU0 0x0000 //Store PSI template for INFO chunk
442#define HOST_RX_EXP_CONTEXT_RD_SLOT_PRU0_SIZE 0x1 442#define PSI_TX_INFO_SLOT_PRU0_SIZE 0x1
443#define HOST_RX_EXP_CONTEXT_WR_SLOT_PRU0 0x0005 //Contains context info for Host Egress Queue (express). redundant 443#define HOST_RX_PACKET_DESC_SLOT_PRU0 0x0001 //Stores the PSI descriptor for packet being sent to Host
444#define HOST_RX_EXP_CONTEXT_WR_SLOT_PRU0_SIZE 0x1 444#define HOST_RX_PACKET_DESC_SLOT_PRU0_SIZE 0x1
445#define P0_FIRST_32B_PACKET_DATA 0x0006 //Used to store 32B at the start of SOF 445#define HOST_RX_PRE_CONTEXT_RD_SLOT_PRU0 0x0002 //Contains context info for Host Egress Queue (pre-emptible). Used by read task
446#define P0_FIRST_32B_PACKET_DATA_SIZE 0x1 446#define HOST_RX_PRE_CONTEXT_RD_SLOT_PRU0_SIZE 0x1
447#define PRU0_BSRAM_END_OFFSET 0x0007 447#define HOST_RX_PRE_CONTEXT_WR_SLOT_PRU0 0x0003 //Contains context info for Host Egress Queue (pre-emptible). Used by write task
448 448#define HOST_RX_PRE_CONTEXT_WR_SLOT_PRU0_SIZE 0x1
449// total PRU0_BSRAM memory usage : 0.21875 KB from total of 4.0KB 449#define HOST_RX_EXP_CONTEXT_RD_SLOT_PRU0 0x0004 //Contains context info for Host Egress Queue (express). redundant
450 450#define HOST_RX_EXP_CONTEXT_RD_SLOT_PRU0_SIZE 0x1
451//************************************************************************************ 451#define HOST_RX_EXP_CONTEXT_WR_SLOT_PRU0 0x0005 //Contains context info for Host Egress Queue (express). redundant
452// 452#define HOST_RX_EXP_CONTEXT_WR_SLOT_PRU0_SIZE 0x1
453// Memory Usage of : PRU1_BSRAM 453#define P0_FIRST_32B_PACKET_DATA 0x0006 //Used to store 32B at the start of SOF
454// 454#define P0_FIRST_32B_PACKET_DATA_SIZE 0x1
455//************************************************************************************ 455#define PRU0_BSRAM_END_OFFSET 0x0007
456 456
457#define PRU1_BSRAM_START_OFFSET 0x0000 457// total PRU0_BSRAM memory usage : 0.21875 KB from total of 4.0KB
458#define P1_FIRST_32B_PACKET_DATA 0x0000 //redundant 458
459#define P1_FIRST_32B_PACKET_DATA_SIZE 0x1 459//************************************************************************************
460#define TAS_BSRAM_EXPIRY_LIST0_GATE0 0x0001 //32B total for one gate. 460//
461#define TAS_BSRAM_EXPIRY_LIST0_GATE0_SIZE 0x1 461// Memory Usage of : PRU1_BSRAM
462#define TAS_BSRAM_EXPIRY_LIST0_GATE1 0x0002 //32B total for one gate. 462//
463#define TAS_BSRAM_EXPIRY_LIST0_GATE1_SIZE 0x1 463//************************************************************************************
464#define TAS_BSRAM_EXPIRY_LIST0_GATE2 0x0003 //32B total for one gate. 464
465#define TAS_BSRAM_EXPIRY_LIST0_GATE2_SIZE 0x1 465#define PRU1_BSRAM_START_OFFSET 0x0000
466#define TAS_BSRAM_EXPIRY_LIST0_GATE3 0x0004 //32B total for one gate. 466#define P1_FIRST_32B_PACKET_DATA 0x0000 //redundant
467#define TAS_BSRAM_EXPIRY_LIST0_GATE3_SIZE 0x1 467#define P1_FIRST_32B_PACKET_DATA_SIZE 0x1
468#define TAS_BSRAM_EXPIRY_LIST0_GATE4 0x0005 //32B total for one gate. 468#define TAS_BSRAM_EXPIRY_LIST0_GATE0 0x0001 //32B total for one gate.
469#define TAS_BSRAM_EXPIRY_LIST0_GATE4_SIZE 0x1 469#define TAS_BSRAM_EXPIRY_LIST0_GATE0_SIZE 0x1
470#define TAS_BSRAM_EXPIRY_LIST0_GATE5 0x0006 //32B total for one gate. 470#define TAS_BSRAM_EXPIRY_LIST0_GATE1 0x0002 //32B total for one gate.
471#define TAS_BSRAM_EXPIRY_LIST0_GATE5_SIZE 0x1 471#define TAS_BSRAM_EXPIRY_LIST0_GATE1_SIZE 0x1
472#define TAS_BSRAM_EXPIRY_LIST0_GATE6 0x0007 //32B total for one gate. 472#define TAS_BSRAM_EXPIRY_LIST0_GATE2 0x0003 //32B total for one gate.
473#define TAS_BSRAM_EXPIRY_LIST0_GATE6_SIZE 0x1 473#define TAS_BSRAM_EXPIRY_LIST0_GATE2_SIZE 0x1
474#define TAS_BSRAM_EXPIRY_LIST0_GATE7 0x0008 //32B total for one gate. 474#define TAS_BSRAM_EXPIRY_LIST0_GATE3 0x0004 //32B total for one gate.
475#define TAS_BSRAM_EXPIRY_LIST0_GATE7_SIZE 0x1 475#define TAS_BSRAM_EXPIRY_LIST0_GATE3_SIZE 0x1
476#define TAS_BSRAM_EXPIRY_LIST1_GATE0 0x0009 //32B total for one gate. 476#define TAS_BSRAM_EXPIRY_LIST0_GATE4 0x0005 //32B total for one gate.
477#define TAS_BSRAM_EXPIRY_LIST1_GATE0_SIZE 0x1 477#define TAS_BSRAM_EXPIRY_LIST0_GATE4_SIZE 0x1
478#define TAS_BSRAM_EXPIRY_LIST1_GATE1 0x000A //32B total for one gate. 478#define TAS_BSRAM_EXPIRY_LIST0_GATE5 0x0006 //32B total for one gate.
479#define TAS_BSRAM_EXPIRY_LIST1_GATE1_SIZE 0x1 479#define TAS_BSRAM_EXPIRY_LIST0_GATE5_SIZE 0x1
480#define TAS_BSRAM_EXPIRY_LIST1_GATE2 0x000B //32B total for one gate. 480#define TAS_BSRAM_EXPIRY_LIST0_GATE6 0x0007 //32B total for one gate.
481#define TAS_BSRAM_EXPIRY_LIST1_GATE2_SIZE 0x1 481#define TAS_BSRAM_EXPIRY_LIST0_GATE6_SIZE 0x1
482#define TAS_BSRAM_EXPIRY_LIST1_GATE3 0x000C //32B total for one gate. 482#define TAS_BSRAM_EXPIRY_LIST0_GATE7 0x0008 //32B total for one gate.
483#define TAS_BSRAM_EXPIRY_LIST1_GATE3_SIZE 0x1 483#define TAS_BSRAM_EXPIRY_LIST0_GATE7_SIZE 0x1
484#define TAS_BSRAM_EXPIRY_LIST1_GATE4 0x000D //32B total for one gate. 484#define TAS_BSRAM_EXPIRY_LIST1_GATE0 0x0009 //32B total for one gate.
485#define TAS_BSRAM_EXPIRY_LIST1_GATE4_SIZE 0x1 485#define TAS_BSRAM_EXPIRY_LIST1_GATE0_SIZE 0x1
486#define TAS_BSRAM_EXPIRY_LIST1_GATE5 0x000E //32B total for one gate. 486#define TAS_BSRAM_EXPIRY_LIST1_GATE1 0x000A //32B total for one gate.
487#define TAS_BSRAM_EXPIRY_LIST1_GATE5_SIZE 0x1 487#define TAS_BSRAM_EXPIRY_LIST1_GATE1_SIZE 0x1
488#define TAS_BSRAM_EXPIRY_LIST1_GATE6 0x000F //32B total for one gate. 488#define TAS_BSRAM_EXPIRY_LIST1_GATE2 0x000B //32B total for one gate.
489#define TAS_BSRAM_EXPIRY_LIST1_GATE6_SIZE 0x1 489#define TAS_BSRAM_EXPIRY_LIST1_GATE2_SIZE 0x1
490#define TAS_BSRAM_EXPIRY_LIST1_GATE7 0x0010 //32B total for one gate. 490#define TAS_BSRAM_EXPIRY_LIST1_GATE3 0x000C //32B total for one gate.
491#define TAS_BSRAM_EXPIRY_LIST1_GATE7_SIZE 0x1 491#define TAS_BSRAM_EXPIRY_LIST1_GATE3_SIZE 0x1
492#define PORT_Q0_CONTEXT_SLOT_PRU1 0x0011 //Combined context (MSMC + Desc) for Port Tx queue 492#define TAS_BSRAM_EXPIRY_LIST1_GATE4 0x000D //32B total for one gate.
493#define PORT_Q0_CONTEXT_SLOT_PRU1_SIZE 0x1 493#define TAS_BSRAM_EXPIRY_LIST1_GATE4_SIZE 0x1
494#define PORT_Q1_CONTEXT_SLOT_PRU1 0x0012 //Combined context (MSMC + Desc) for Port Tx queue 494#define TAS_BSRAM_EXPIRY_LIST1_GATE5 0x000E //32B total for one gate.
495#define PORT_Q1_CONTEXT_SLOT_PRU1_SIZE 0x1 495#define TAS_BSRAM_EXPIRY_LIST1_GATE5_SIZE 0x1
496#define PORT_Q2_CONTEXT_SLOT_PRU1 0x0013 //Combined context (MSMC + Desc) for Port Tx queue 496#define TAS_BSRAM_EXPIRY_LIST1_GATE6 0x000F //32B total for one gate.
497#define PORT_Q2_CONTEXT_SLOT_PRU1_SIZE 0x1 497#define TAS_BSRAM_EXPIRY_LIST1_GATE6_SIZE 0x1
498#define PORT_Q3_CONTEXT_SLOT_PRU1 0x0014 //Combined context (MSMC + Desc) for Port Tx queue 498#define TAS_BSRAM_EXPIRY_LIST1_GATE7 0x0010 //32B total for one gate.
499#define PORT_Q3_CONTEXT_SLOT_PRU1_SIZE 0x1 499#define TAS_BSRAM_EXPIRY_LIST1_GATE7_SIZE 0x1
500#define PORT_Q4_CONTEXT_SLOT_PRU1 0x0015 //Combined context (MSMC + Desc) for Port Tx queue 500#define PORT_Q0_CONTEXT_SLOT_PRU1 0x0011 //Combined context (MSMC + Desc) for Port Tx queue
501#define PORT_Q4_CONTEXT_SLOT_PRU1_SIZE 0x1 501#define PORT_Q0_CONTEXT_SLOT_PRU1_SIZE 0x1
502#define PORT_Q5_CONTEXT_SLOT_PRU1 0x0016 //Combined context (MSMC + Desc) for Port Tx queue 502#define PORT_Q1_CONTEXT_SLOT_PRU1 0x0012 //Combined context (MSMC + Desc) for Port Tx queue
503#define PORT_Q5_CONTEXT_SLOT_PRU1_SIZE 0x1 503#define PORT_Q1_CONTEXT_SLOT_PRU1_SIZE 0x1
504#define PORT_Q6_CONTEXT_SLOT_PRU1 0x0017 //Combined context (MSMC + Desc) for Port Tx queue 504#define PORT_Q2_CONTEXT_SLOT_PRU1 0x0013 //Combined context (MSMC + Desc) for Port Tx queue
505#define PORT_Q6_CONTEXT_SLOT_PRU1_SIZE 0x1 505#define PORT_Q2_CONTEXT_SLOT_PRU1_SIZE 0x1
506#define PORT_Q7_CONTEXT_SLOT_PRU1 0x0018 //Combined context (MSMC + Desc) for Port Tx queue 506#define PORT_Q3_CONTEXT_SLOT_PRU1 0x0014 //Combined context (MSMC + Desc) for Port Tx queue
507#define PORT_Q7_CONTEXT_SLOT_PRU1_SIZE 0x1 507#define PORT_Q3_CONTEXT_SLOT_PRU1_SIZE 0x1
508#define HOST_Q0_CONTEXT_SLOT_PRU1 0x0019 //Combined context (MSMC + Desc) for Port Tx queue 508#define PORT_Q4_CONTEXT_SLOT_PRU1 0x0015 //Combined context (MSMC + Desc) for Port Tx queue
509#define HOST_Q0_CONTEXT_SLOT_PRU1_SIZE 0x1 509#define PORT_Q4_CONTEXT_SLOT_PRU1_SIZE 0x1
510#define HOST_Q1_CONTEXT_SLOT_PRU1 0x001A //Combined context (MSMC + Desc) for Host Tx queue 510#define PORT_Q5_CONTEXT_SLOT_PRU1 0x0016 //Combined context (MSMC + Desc) for Port Tx queue
511#define HOST_Q1_CONTEXT_SLOT_PRU1_SIZE 0x1 511#define PORT_Q5_CONTEXT_SLOT_PRU1_SIZE 0x1
512#define HOST_Q2_CONTEXT_SLOT_PRU1 0x001B //Combined context (MSMC + Desc) for Host Tx queue 512#define PORT_Q6_CONTEXT_SLOT_PRU1 0x0017 //Combined context (MSMC + Desc) for Port Tx queue
513#define HOST_Q2_CONTEXT_SLOT_PRU1_SIZE 0x1 513#define PORT_Q6_CONTEXT_SLOT_PRU1_SIZE 0x1
514#define HOST_Q3_CONTEXT_SLOT_PRU1 0x001C //Combined context (MSMC + Desc) for Host Tx queue 514#define PORT_Q7_CONTEXT_SLOT_PRU1 0x0018 //Combined context (MSMC + Desc) for Port Tx queue
515#define HOST_Q3_CONTEXT_SLOT_PRU1_SIZE 0x1 515#define PORT_Q7_CONTEXT_SLOT_PRU1_SIZE 0x1
516#define HOST_Q4_CONTEXT_SLOT_PRU1 0x001D //Combined context (MSMC + Desc) for Host Tx queue 516#define HOST_Q0_CONTEXT_SLOT_PRU1 0x0019 //Combined context (MSMC + Desc) for Port Tx queue
517#define HOST_Q4_CONTEXT_SLOT_PRU1_SIZE 0x1 517#define HOST_Q0_CONTEXT_SLOT_PRU1_SIZE 0x1
518#define HOST_Q5_CONTEXT_SLOT_PRU1 0x001E //Combined context (MSMC + Desc) for Host Tx queue 518#define HOST_Q1_CONTEXT_SLOT_PRU1 0x001A //Combined context (MSMC + Desc) for Host Tx queue
519#define HOST_Q5_CONTEXT_SLOT_PRU1_SIZE 0x1 519#define HOST_Q1_CONTEXT_SLOT_PRU1_SIZE 0x1
520#define HOST_Q6_CONTEXT_SLOT_PRU1 0x001F //Combined context (MSMC + Desc) for Host Tx queue 520#define HOST_Q2_CONTEXT_SLOT_PRU1 0x001B //Combined context (MSMC + Desc) for Host Tx queue
521#define HOST_Q6_CONTEXT_SLOT_PRU1_SIZE 0x1 521#define HOST_Q2_CONTEXT_SLOT_PRU1_SIZE 0x1
522#define HOST_Q7_CONTEXT_SLOT_PRU1 0x0020 //Combined context (MSMC + Desc) for Host Tx queue 522#define HOST_Q3_CONTEXT_SLOT_PRU1 0x001C //Combined context (MSMC + Desc) for Host Tx queue
523#define HOST_Q7_CONTEXT_SLOT_PRU1_SIZE 0x1 523#define HOST_Q3_CONTEXT_SLOT_PRU1_SIZE 0x1
524#define PSI_TXTS_INFO_SLOT_PRU1 0x0021 //Store Info chunk for Tx TS PSI transaction 524#define HOST_Q4_CONTEXT_SLOT_PRU1 0x001D //Combined context (MSMC + Desc) for Host Tx queue
525#define PSI_TXTS_INFO_SLOT_PRU1_SIZE 0x1 525#define HOST_Q4_CONTEXT_SLOT_PRU1_SIZE 0x1
526#define PRU1_BS_OFFSETS_END 0x0022 //_Small_Description_ 526#define HOST_Q5_CONTEXT_SLOT_PRU1 0x001E //Combined context (MSMC + Desc) for Host Tx queue
527#define PRU1_BSRAM_END_OFFSET 0x0022 527#define HOST_Q5_CONTEXT_SLOT_PRU1_SIZE 0x1
528 528#define HOST_Q6_CONTEXT_SLOT_PRU1 0x001F //Combined context (MSMC + Desc) for Host Tx queue
529// total PRU1_BSRAM memory usage : 1.0625 KB from total of 4.0KB 529#define HOST_Q6_CONTEXT_SLOT_PRU1_SIZE 0x1
530 530#define HOST_Q7_CONTEXT_SLOT_PRU1 0x0020 //Combined context (MSMC + Desc) for Host Tx queue
531//************************************************************************************ 531#define HOST_Q7_CONTEXT_SLOT_PRU1_SIZE 0x1
532// 532#define PSI_TXTS_INFO_SLOT_PRU1 0x0021 //Store Info chunk for Tx TS PSI transaction
533// Memory Usage of : RTU0_BSRAM 533#define PSI_TXTS_INFO_SLOT_PRU1_SIZE 0x1
534// 534#define PRU1_BS_OFFSETS_END 0x0022 //_Small_Description_
535//************************************************************************************ 535#define PRU1_BSRAM_END_OFFSET 0x0022
536 536
537#define RTU0_BSRAM_START_OFFSET 0x0000 537// total PRU1_BSRAM memory usage : 1.0625 KB from total of 4.0KB
538#define PSI_MGR_INFO_SLOT_RTU0 0x0000 //Stores Management Frame PSI Info chunk 538
539#define PSI_MGR_INFO_SLOT_RTU0_SIZE 0x1 539//************************************************************************************
540#define PORT_Q0_CONTEXT_SLOT_RTU0 0x0001 //Combined context (MSMC + Desc) for Port Tx queue 540//
541#define PORT_Q0_CONTEXT_SLOT_RTU0_SIZE 0x1 541// Memory Usage of : RTU0_BSRAM
542#define PORT_Q1_CONTEXT_SLOT_RTU0 0x0002 //Combined context (MSMC + Desc) for Port Tx queue 542//
543#define PORT_Q1_CONTEXT_SLOT_RTU0_SIZE 0x1 543//************************************************************************************
544#define PORT_Q2_CONTEXT_SLOT_RTU0 0x0003 //Combined context (MSMC + Desc) for Port Tx queue 544
545#define PORT_Q2_CONTEXT_SLOT_RTU0_SIZE 0x1 545#define RTU0_BSRAM_START_OFFSET 0x0000
546#define PORT_Q3_CONTEXT_SLOT_RTU0 0x0004 //Combined context (MSMC + Desc) for Port Tx queue 546#define PSI_MGR_INFO_SLOT_RTU0 0x0000 //Stores Management Frame PSI Info chunk
547#define PORT_Q3_CONTEXT_SLOT_RTU0_SIZE 0x1 547#define PSI_MGR_INFO_SLOT_RTU0_SIZE 0x1
548#define PORT_Q4_CONTEXT_SLOT_RTU0 0x0005 //Combined context (MSMC + Desc) for Port Tx queue 548#define PORT_Q0_CONTEXT_SLOT_RTU0 0x0001 //Combined context (MSMC + Desc) for Port Tx queue
549#define PORT_Q4_CONTEXT_SLOT_RTU0_SIZE 0x1 549#define PORT_Q0_CONTEXT_SLOT_RTU0_SIZE 0x1
550#define PORT_Q5_CONTEXT_SLOT_RTU0 0x0006 //Combined context (MSMC + Desc) for Port Tx queue 550#define PORT_Q1_CONTEXT_SLOT_RTU0 0x0002 //Combined context (MSMC + Desc) for Port Tx queue
551#define PORT_Q5_CONTEXT_SLOT_RTU0_SIZE 0x1 551#define PORT_Q1_CONTEXT_SLOT_RTU0_SIZE 0x1
552#define PORT_Q6_CONTEXT_SLOT_RTU0 0x0007 //Combined context (MSMC + Desc) for Port Tx queue 552#define PORT_Q2_CONTEXT_SLOT_RTU0 0x0003 //Combined context (MSMC + Desc) for Port Tx queue
553#define PORT_Q6_CONTEXT_SLOT_RTU0_SIZE 0x1 553#define PORT_Q2_CONTEXT_SLOT_RTU0_SIZE 0x1
554#define PORT_Q7_CONTEXT_SLOT_RTU0 0x0008 //Combined context (MSMC + Desc) for Port Tx queue 554#define PORT_Q3_CONTEXT_SLOT_RTU0 0x0004 //Combined context (MSMC + Desc) for Port Tx queue
555#define PORT_Q7_CONTEXT_SLOT_RTU0_SIZE 0x1 555#define PORT_Q3_CONTEXT_SLOT_RTU0_SIZE 0x1
556#define HOST_Q0_CONTEXT_SLOT_RTU0 0x0009 //Combined context (MSMC + Desc) for Host Tx queue 556#define PORT_Q4_CONTEXT_SLOT_RTU0 0x0005 //Combined context (MSMC + Desc) for Port Tx queue
557#define HOST_Q0_CONTEXT_SLOT_RTU0_SIZE 0x1 557#define PORT_Q4_CONTEXT_SLOT_RTU0_SIZE 0x1
558#define HOST_Q1_CONTEXT_SLOT_RTU0 0x000A //Combined context (MSMC + Desc) for Host Tx queue 558#define PORT_Q5_CONTEXT_SLOT_RTU0 0x0006 //Combined context (MSMC + Desc) for Port Tx queue
559#define HOST_Q1_CONTEXT_SLOT_RTU0_SIZE 0x1 559#define PORT_Q5_CONTEXT_SLOT_RTU0_SIZE 0x1
560#define HOST_Q2_CONTEXT_SLOT_RTU0 0x000B //Combined context (MSMC + Desc) for Host Tx queue 560#define PORT_Q6_CONTEXT_SLOT_RTU0 0x0007 //Combined context (MSMC + Desc) for Port Tx queue
561#define HOST_Q2_CONTEXT_SLOT_RTU0_SIZE 0x1 561#define PORT_Q6_CONTEXT_SLOT_RTU0_SIZE 0x1
562#define HOST_Q3_CONTEXT_SLOT_RTU0 0x000C //Combined context (MSMC + Desc) for Host Tx queue 562#define PORT_Q7_CONTEXT_SLOT_RTU0 0x0008 //Combined context (MSMC + Desc) for Port Tx queue
563#define HOST_Q3_CONTEXT_SLOT_RTU0_SIZE 0x1 563#define PORT_Q7_CONTEXT_SLOT_RTU0_SIZE 0x1
564#define HOST_Q4_CONTEXT_SLOT_RTU0 0x000D //Combined context (MSMC + Desc) for Host Tx queue 564#define HOST_Q0_CONTEXT_SLOT_RTU0 0x0009 //Combined context (MSMC + Desc) for Host Tx queue
565#define HOST_Q4_CONTEXT_SLOT_RTU0_SIZE 0x1 565#define HOST_Q0_CONTEXT_SLOT_RTU0_SIZE 0x1
566#define HOST_Q5_CONTEXT_SLOT_RTU0 0x000E //Combined context (MSMC + Desc) for Host Tx queue 566#define HOST_Q1_CONTEXT_SLOT_RTU0 0x000A //Combined context (MSMC + Desc) for Host Tx queue
567#define HOST_Q5_CONTEXT_SLOT_RTU0_SIZE 0x1 567#define HOST_Q1_CONTEXT_SLOT_RTU0_SIZE 0x1
568#define HOST_Q6_CONTEXT_SLOT_RTU0 0x000F //Combined context (MSMC + Desc) for Host Tx queue 568#define HOST_Q2_CONTEXT_SLOT_RTU0 0x000B //Combined context (MSMC + Desc) for Host Tx queue
569#define HOST_Q6_CONTEXT_SLOT_RTU0_SIZE 0x1 569#define HOST_Q2_CONTEXT_SLOT_RTU0_SIZE 0x1
570#define HOST_Q7_CONTEXT_SLOT_RTU0 0x0010 //Combined context (MSMC + Desc) for Host Tx queue 570#define HOST_Q3_CONTEXT_SLOT_RTU0 0x000C //Combined context (MSMC + Desc) for Host Tx queue
571#define HOST_Q7_CONTEXT_SLOT_RTU0_SIZE 0x1 571#define HOST_Q3_CONTEXT_SLOT_RTU0_SIZE 0x1
572#define RTU0_BSRAM_END_OFFSET 0x0011 572#define HOST_Q4_CONTEXT_SLOT_RTU0 0x000D //Combined context (MSMC + Desc) for Host Tx queue
573 573#define HOST_Q4_CONTEXT_SLOT_RTU0_SIZE 0x1
574// total RTU0_BSRAM memory usage : 0.53125 KB from total of 16.0KB 574#define HOST_Q5_CONTEXT_SLOT_RTU0 0x000E //Combined context (MSMC + Desc) for Host Tx queue
575 575#define HOST_Q5_CONTEXT_SLOT_RTU0_SIZE 0x1
576//************************************************************************************ 576#define HOST_Q6_CONTEXT_SLOT_RTU0 0x000F //Combined context (MSMC + Desc) for Host Tx queue
577// 577#define HOST_Q6_CONTEXT_SLOT_RTU0_SIZE 0x1
578// Memory Usage of : RTU1_BSRAM 578#define HOST_Q7_CONTEXT_SLOT_RTU0 0x0010 //Combined context (MSMC + Desc) for Host Tx queue
579// 579#define HOST_Q7_CONTEXT_SLOT_RTU0_SIZE 0x1
580//************************************************************************************ 580#define RTU0_BSRAM_END_OFFSET 0x0011
581 581
582#define RTU1_BSRAM_START_OFFSET 0x0000 582// total RTU0_BSRAM memory usage : 0.53125 KB from total of 16.0KB
583#define RTU1_BS_OFFSETS_END 0x0000 //_Small_Description_ 583
584#define RTU1_BSRAM_END_OFFSET 0x0000 584//************************************************************************************
585 585//
586// total RTU1_BSRAM memory usage : 0.0 KB from total of 16.0KB 586// Memory Usage of : RTU1_BSRAM
587 587//
588//************************************************************************************ 588//************************************************************************************
589// 589
590// Memory Usage of : PA_STAT 590#define RTU1_BSRAM_START_OFFSET 0x0000
591// 591#define RTU1_BS_OFFSETS_END 0x0000 //_Small_Description_
592//************************************************************************************ 592#define RTU1_BSRAM_END_OFFSET 0x0000
593 593
594#define PA_STAT_START_OFFSET 0x0000 594// total RTU1_BSRAM memory usage : 0.0 KB from total of 16.0KB
595#define PA_STAT_64b_START_OFFSET 0x0000 //Start of 64 bits PA_STAT counters 595
596#define NRT_HOST_RX_BYTE_COUNT_PASTATID 0x0000 //Number of valid bytes sent by Rx PRU to Host on PSI. Currently disabled 596//************************************************************************************
597#define NRT_HOST_RX_BYTE_COUNT_PASTATID_SIZE 0x2 597//
598#define NRT_HOST_TX_BYTE_COUNT_PASTATID 0x0002 //Number of valid bytes copied by RTU0 to Tx queues. Currently disabled 598// Memory Usage of : PA_STAT
599#define NRT_HOST_TX_BYTE_COUNT_PASTATID_SIZE 0x2 599//
600#define PA_STAT_32b_START_OFFSET 0x0080 //Start of 32 bits PA_STAT counters 600//************************************************************************************
601#define NRT_HOST_RX_PKT_COUNT_PASTATID 0x0080 //Number of valid packets sent by Rx PRU to Host on PSI 601
602#define NRT_HOST_RX_PKT_COUNT_PASTATID_SIZE 0x4 602#define PA_STAT_START_OFFSET 0x0000
603#define NRT_HOST_TX_PKT_COUNT_PASTATID 0x0084 //Number of valid packets copied by RTU0 to Tx queues 603#define PA_STAT_64b_START_OFFSET 0x0000 //Start of 64 bits PA_STAT counters
604#define NRT_HOST_TX_PKT_COUNT_PASTATID_SIZE 0x4 604#define NRT_HOST_RX_BYTE_COUNT_PASTATID 0x0000 //Number of valid bytes sent by Rx PRU to Host on PSI. Currently disabled
605#define NRT_RTU0_PACKET_DROPPED_PASTATID 0x0088 //PRU diagnostic error counter which increments when RTU0 drops a locally injected packet due to port disabled or rule violation 605#define NRT_HOST_RX_BYTE_COUNT_PASTATID_SIZE 0x2
606#define NRT_RTU0_PACKET_DROPPED_PASTATID_SIZE 0x4 606#define NRT_HOST_TX_BYTE_COUNT_PASTATID 0x0002 //Number of valid bytes copied by RTU0 to Tx queues. Currently disabled
607#define NRT_PORT_Q0_OVERFLOW_PASTATID 0x008C //Port Tx Q Overflow Counters 607#define NRT_HOST_TX_BYTE_COUNT_PASTATID_SIZE 0x2
608#define NRT_PORT_Q0_OVERFLOW_PASTATID_SIZE 0x4 608#define PA_STAT_32b_START_OFFSET 0x0080 //Start of 32 bits PA_STAT counters
609#define NRT_PORT_Q1_OVERFLOW_PASTATID 0x0090 //Port Tx Q Overflow Counters 609#define NRT_HOST_RX_PKT_COUNT_PASTATID 0x0080 //Number of valid packets sent by Rx PRU to Host on PSI
610#define NRT_PORT_Q1_OVERFLOW_PASTATID_SIZE 0x4 610#define NRT_HOST_RX_PKT_COUNT_PASTATID_SIZE 0x4
611#define NRT_PORT_Q2_OVERFLOW_PASTATID 0x0094 //Port Tx Q Overflow Counters 611#define NRT_HOST_TX_PKT_COUNT_PASTATID 0x0084 //Number of valid packets copied by RTU0 to Tx queues
612#define NRT_PORT_Q2_OVERFLOW_PASTATID_SIZE 0x4 612#define NRT_HOST_TX_PKT_COUNT_PASTATID_SIZE 0x4
613#define NRT_PORT_Q3_OVERFLOW_PASTATID 0x0098 //Port Tx Q Overflow Counters 613#define NRT_RTU0_PACKET_DROPPED_PASTATID 0x0088 //PRU diagnostic error counter which increments when RTU0 drops a locally injected packet due to port disabled or rule violation
614#define NRT_PORT_Q3_OVERFLOW_PASTATID_SIZE 0x4 614#define NRT_RTU0_PACKET_DROPPED_PASTATID_SIZE 0x4
615#define NRT_PORT_Q4_OVERFLOW_PASTATID 0x009C //Port Tx Q Overflow Counters 615#define NRT_PORT_Q0_OVERFLOW_PASTATID 0x008C //Port Tx Q Overflow Counters
616#define NRT_PORT_Q4_OVERFLOW_PASTATID_SIZE 0x4 616#define NRT_PORT_Q0_OVERFLOW_PASTATID_SIZE 0x4
617#define NRT_PORT_Q5_OVERFLOW_PASTATID 0x00A0 //Port Tx Q Overflow Counters 617#define NRT_PORT_Q1_OVERFLOW_PASTATID 0x0090 //Port Tx Q Overflow Counters
618#define NRT_PORT_Q5_OVERFLOW_PASTATID_SIZE 0x4 618#define NRT_PORT_Q1_OVERFLOW_PASTATID_SIZE 0x4
619#define NRT_PORT_Q6_OVERFLOW_PASTATID 0x00A4 //Port Tx Q Overflow Counters 619#define NRT_PORT_Q2_OVERFLOW_PASTATID 0x0094 //Port Tx Q Overflow Counters
620#define NRT_PORT_Q6_OVERFLOW_PASTATID_SIZE 0x4 620#define NRT_PORT_Q2_OVERFLOW_PASTATID_SIZE 0x4
621#define NRT_PORT_Q7_OVERFLOW_PASTATID 0x00A8 //Port Tx Q Overflow Counters 621#define NRT_PORT_Q3_OVERFLOW_PASTATID 0x0098 //Port Tx Q Overflow Counters
622#define NRT_PORT_Q7_OVERFLOW_PASTATID_SIZE 0x4 622#define NRT_PORT_Q3_OVERFLOW_PASTATID_SIZE 0x4
623#define NRT_HOST_Q0_OVERFLOW_PASTATID 0x00AC //Host Tx Q Overflow Counters 623#define NRT_PORT_Q4_OVERFLOW_PASTATID 0x009C //Port Tx Q Overflow Counters
624#define NRT_HOST_Q0_OVERFLOW_PASTATID_SIZE 0x4 624#define NRT_PORT_Q4_OVERFLOW_PASTATID_SIZE 0x4
625#define NRT_HOST_Q1_OVERFLOW_PASTATID 0x00B0 //Host Tx Q Overflow Counters 625#define NRT_PORT_Q5_OVERFLOW_PASTATID 0x00A0 //Port Tx Q Overflow Counters
626#define NRT_HOST_Q1_OVERFLOW_PASTATID_SIZE 0x4 626#define NRT_PORT_Q5_OVERFLOW_PASTATID_SIZE 0x4
627#define NRT_HOST_Q2_OVERFLOW_PASTATID 0x00B4 //Host Tx Q Overflow Counters 627#define NRT_PORT_Q6_OVERFLOW_PASTATID 0x00A4 //Port Tx Q Overflow Counters
628#define NRT_HOST_Q2_OVERFLOW_PASTATID_SIZE 0x4 628#define NRT_PORT_Q6_OVERFLOW_PASTATID_SIZE 0x4
629#define NRT_HOST_Q3_OVERFLOW_PASTATID 0x00B8 //Host Tx Q Overflow Counters 629#define NRT_PORT_Q7_OVERFLOW_PASTATID 0x00A8 //Port Tx Q Overflow Counters
630#define NRT_HOST_Q3_OVERFLOW_PASTATID_SIZE 0x4 630#define NRT_PORT_Q7_OVERFLOW_PASTATID_SIZE 0x4
631#define NRT_HOST_Q4_OVERFLOW_PASTATID 0x00BC //Host Tx Q Overflow Counters 631#define NRT_HOST_Q0_OVERFLOW_PASTATID 0x00AC //Host Tx Q Overflow Counters
632#define NRT_HOST_Q4_OVERFLOW_PASTATID_SIZE 0x4 632#define NRT_HOST_Q0_OVERFLOW_PASTATID_SIZE 0x4
633#define NRT_HOST_Q5_OVERFLOW_PASTATID 0x00C0 //Host Tx Q Overflow Counters 633#define NRT_HOST_Q1_OVERFLOW_PASTATID 0x00B0 //Host Tx Q Overflow Counters
634#define NRT_HOST_Q5_OVERFLOW_PASTATID_SIZE 0x4 634#define NRT_HOST_Q1_OVERFLOW_PASTATID_SIZE 0x4
635#define NRT_HOST_Q6_OVERFLOW_PASTATID 0x00C4 //Host Tx Q Overflow Counters 635#define NRT_HOST_Q2_OVERFLOW_PASTATID 0x00B4 //Host Tx Q Overflow Counters
636#define NRT_HOST_Q6_OVERFLOW_PASTATID_SIZE 0x4 636#define NRT_HOST_Q2_OVERFLOW_PASTATID_SIZE 0x4
637#define NRT_HOST_Q7_OVERFLOW_PASTATID 0x00C8 //Host Tx Q Overflow Counters 637#define NRT_HOST_Q3_OVERFLOW_PASTATID 0x00B8 //Host Tx Q Overflow Counters
638#define NRT_HOST_Q7_OVERFLOW_PASTATID_SIZE 0x4 638#define NRT_HOST_Q3_OVERFLOW_PASTATID_SIZE 0x4
639#define NRT_HOST_EGRESS_Q_PRE_OVERFLOW_PASTATID 0x00CC //Host Egress Q (Pre-emptible) Overflow Counter 639#define NRT_HOST_Q4_OVERFLOW_PASTATID 0x00BC //Host Tx Q Overflow Counters
640#define NRT_HOST_EGRESS_Q_PRE_OVERFLOW_PASTATID_SIZE 0x4 640#define NRT_HOST_Q4_OVERFLOW_PASTATID_SIZE 0x4
641#define NRT_HOST_EGRESS_Q_EXP_OVERFLOW_PASTATID 0x00D0 //Host Egress Q (Express) Overflow Counter. redundant 641#define NRT_HOST_Q5_OVERFLOW_PASTATID 0x00C0 //Host Tx Q Overflow Counters
642#define NRT_HOST_EGRESS_Q_EXP_OVERFLOW_PASTATID_SIZE 0x4 642#define NRT_HOST_Q5_OVERFLOW_PASTATID_SIZE 0x4
643#define NRT_PSI_ABORT_CNT_PASTATID 0x00D4 //_Small_Description_ 643#define NRT_HOST_Q6_OVERFLOW_PASTATID 0x00C4 //Host Tx Q Overflow Counters
644#define NRT_PSI_ABORT_CNT_PASTATID_SIZE 0x4 644#define NRT_HOST_Q6_OVERFLOW_PASTATID_SIZE 0x4
645#define NRT_WRONG_Q_STATUS_PASTATID 0x00D8 //Not Used, will be removed 645#define NRT_HOST_Q7_OVERFLOW_PASTATID 0x00C8 //Host Tx Q Overflow Counters
646#define NRT_WRONG_Q_STATUS_PASTATID_SIZE 0x4 646#define NRT_HOST_Q7_OVERFLOW_PASTATID_SIZE 0x4
647#define NRT_DROPPED_PKT_PASTATID 0x00DC //Incremented if a packet is dropped because of a rule violation 647#define NRT_HOST_EGRESS_Q_PRE_OVERFLOW_PASTATID 0x00CC //Host Egress Q (Pre-emptible) Overflow Counter
648#define NRT_DROPPED_PKT_PASTATID_SIZE 0x4 648#define NRT_HOST_EGRESS_Q_PRE_OVERFLOW_PASTATID_SIZE 0x4
649#define NRT_RX_ERROR_PASTATID 0x00E0 //Incremented if there was a CRC error or Min/Max frame error 649#define NRT_HOST_EGRESS_Q_EXP_OVERFLOW_PASTATID 0x00D0 //Host Egress Q (Express) Overflow Counter. redundant
650#define NRT_RX_ERROR_PASTATID_SIZE 0x4 650#define NRT_HOST_EGRESS_Q_EXP_OVERFLOW_PASTATID_SIZE 0x4
651#define RX_EOF_RTU_DS_INVALID_PASTATID 0x00E4 //RTU diagnostic counter increments when RTU detects Data Status invalid condition 651#define NRT_PSI_ABORT_CNT_PASTATID 0x00D4 //_Small_Description_
652#define RX_EOF_RTU_DS_INVALID_PASTATID_SIZE 0x4 652#define NRT_PSI_ABORT_CNT_PASTATID_SIZE 0x4
653#define RX_B1_NRT_ENTRY_PASTATID 0x00E8 //[DEBUG_L2_DIAGNOSTICS | not in release binary] PRU diagnostic counter which increments when NRT path of RX_B1 handling is invoked 653#define NRT_WRONG_Q_STATUS_PASTATID 0x00D8 //Not Used, will be removed
654#define RX_B1_NRT_ENTRY_PASTATID_SIZE 0x4 654#define NRT_WRONG_Q_STATUS_PASTATID_SIZE 0x4
655#define RX_Bn_NRT_ENTRY_PASTATID 0x00EC //[DEBUG_L2_DIAGNOSTICS | not in release binary] PRU diagnostic counter which increments when NRT path of RX_Bn handling is invoked 655#define NRT_DROPPED_PKT_PASTATID 0x00DC //Incremented if a packet is dropped because of a rule violation
656#define RX_Bn_NRT_ENTRY_PASTATID_SIZE 0x4 656#define NRT_DROPPED_PKT_PASTATID_SIZE 0x4
657#define RX_EOF_NRT_ENTRY_PASTATID 0x00F0 //[DEBUG_L2_DIAGNOSTICS | not in release binary] PRU diagnostic counter which increments when NRT path of RX_EOF handling is invoked 657#define NRT_RX_ERROR_PASTATID 0x00E0 //Incremented if there was a CRC error or Min/Max frame error
658#define RX_EOF_NRT_ENTRY_PASTATID_SIZE 0x4 658#define NRT_RX_ERROR_PASTATID_SIZE 0x4
659#define NRT_TX_DROPPED_PACKET_PASTATID 0x00F4 //Counter for packets dropped via NRT TX path 659#define RX_EOF_RTU_DS_INVALID_PASTATID 0x00E4 //RTU diagnostic counter increments when RTU detects Data Status invalid condition
660#define NRT_TX_DROPPED_PACKET_PASTATID_SIZE 0x4 660#define RX_EOF_RTU_DS_INVALID_PASTATID_SIZE 0x4
661#define NRT_TX_TS_DROPPED_PACKET_PASTATID 0x00F8 //Counter for packets with TS flag dropped via NRT TX path 661#define RX_B1_NRT_ENTRY_PASTATID 0x00E8 //[DEBUG_L2_DIAGNOSTICS | not in release binary] PRU diagnostic counter which increments when NRT path of RX_B1 handling is invoked
662#define NRT_TX_TS_DROPPED_PACKET_PASTATID_SIZE 0x4 662#define RX_B1_NRT_ENTRY_PASTATID_SIZE 0x4
663#define NRT_INF_PORT_DISABLED_PASTATID 0x00FC //PRU diagnostic error counter which increments when RX frame is dropped due to port is disabled 663#define RX_Bn_NRT_ENTRY_PASTATID 0x00EC //[DEBUG_L2_DIAGNOSTICS | not in release binary] PRU diagnostic counter which increments when NRT path of RX_Bn handling is invoked
664#define NRT_INF_PORT_DISABLED_PASTATID_SIZE 0x4 664#define RX_Bn_NRT_ENTRY_PASTATID_SIZE 0x4
665#define NRT_INF_SAV_PASTATID 0x0100 //PRU diagnostic error counter which increments when RX frame is dropped due to SA violation 665#define RX_EOF_NRT_ENTRY_PASTATID 0x00F0 //[DEBUG_L2_DIAGNOSTICS | not in release binary] PRU diagnostic counter which increments when NRT path of RX_EOF handling is invoked
666#define NRT_INF_SAV_PASTATID_SIZE 0x4 666#define RX_EOF_NRT_ENTRY_PASTATID_SIZE 0x4
667#define NRT_INF_SA_BL_PASTATID 0x0104 //PRU diagnostic error counter which increments when RX frame is dropped due to SA black listed 667#define NRT_TX_DROPPED_PACKET_PASTATID 0x00F4 //Counter for packets dropped via NRT TX path
668#define NRT_INF_SA_BL_PASTATID_SIZE 0x4 668#define NRT_TX_DROPPED_PACKET_PASTATID_SIZE 0x4
669#define NRT_INF_PORT_BLOCKED_PASTATID 0x0108 //PRU diagnostic error counter which increments when RX frame is dropped due to port blocked and not a special frame 669#define NRT_TX_TS_DROPPED_PACKET_PASTATID 0x00F8 //Counter for packets with TS flag dropped via NRT TX path
670#define NRT_INF_PORT_BLOCKED_PASTATID_SIZE 0x4 670#define NRT_TX_TS_DROPPED_PACKET_PASTATID_SIZE 0x4
671#define NRT_INF_AFT_DROP_TAGGED_PASTATID 0x010C //PRU diagnostic error counter which increments when RX frame is dropped due to tagged 671#define NRT_INF_PORT_DISABLED_PASTATID 0x00FC //PRU diagnostic error counter which increments when RX frame is dropped due to port is disabled
672#define NRT_INF_AFT_DROP_TAGGED_PASTATID_SIZE 0x4 672#define NRT_INF_PORT_DISABLED_PASTATID_SIZE 0x4
673#define NRT_INF_AFT_DROP_PRIOTAGGED_PASTATID 0x0110 //PRU diagnostic error counter which increments when RX frame is dropped due to priority tagged 673#define NRT_INF_SAV_PASTATID 0x0100 //PRU diagnostic error counter which increments when RX frame is dropped due to SA violation
674#define NRT_INF_AFT_DROP_PRIOTAGGED_PASTATID_SIZE 0x4 674#define NRT_INF_SAV_PASTATID_SIZE 0x4
675#define NRT_INF_AFT_DROP_NOTAG_PASTATID 0x0114 //PRU diagnostic error counter which increments when RX frame is dropped due to untagged 675#define NRT_INF_SA_BL_PASTATID 0x0104 //PRU diagnostic error counter which increments when RX frame is dropped due to SA black listed
676#define NRT_INF_AFT_DROP_NOTAG_PASTATID_SIZE 0x4 676#define NRT_INF_SA_BL_PASTATID_SIZE 0x4
677#define NRT_INF_AFT_DROP_NOTMEMBER_PASTATID 0x0118 //PRU diagnostic error counter which increments when RX frame is dropped due to port not member of VLAN 677#define NRT_INF_PORT_BLOCKED_PASTATID 0x0108 //PRU diagnostic error counter which increments when RX frame is dropped due to port blocked and not a special frame
678#define NRT_INF_AFT_DROP_NOTMEMBER_PASTATID_SIZE 0x4 678#define NRT_INF_PORT_BLOCKED_PASTATID_SIZE 0x4
679#define NRT_FDB_NO_SPACE_TO_LEARN 0x011C //PRU diagnostic error counter which increments when an entry couldn't be learned 679#define NRT_INF_AFT_DROP_TAGGED_PASTATID 0x010C //PRU diagnostic error counter which increments when RX frame is dropped due to tagged
680#define NRT_FDB_NO_SPACE_TO_LEARN_SIZE 0x4 680#define NRT_INF_AFT_DROP_TAGGED_PASTATID_SIZE 0x4
681#define NRT_FDB_LAST_ENTRY_OVERWRITTEN_FOR_LEARNING 0x0120 //[DEBUG_L2_DIAGNOSTICS | not in release binary] PRU diagnostic error counter which increments when the fourth entry is overwritten to accomodate leart MAC 681#define NRT_INF_AFT_DROP_PRIOTAGGED_PASTATID 0x0110 //PRU diagnostic error counter which increments when RX frame is dropped due to priority tagged
682#define NRT_FDB_LAST_ENTRY_OVERWRITTEN_FOR_LEARNING_SIZE 0x4 682#define NRT_INF_AFT_DROP_PRIOTAGGED_PASTATID_SIZE 0x4
683#define NRT_PREEMPT_BAD_FRAG_PASTATID 0x0124 //Bad fragment Error Counter 683#define NRT_INF_AFT_DROP_NOTAG_PASTATID 0x0114 //PRU diagnostic error counter which increments when RX frame is dropped due to untagged
684#define NRT_PREEMPT_BAD_FRAG_PASTATID_SIZE 0x4 684#define NRT_INF_AFT_DROP_NOTAG_PASTATID_SIZE 0x4
685#define NRT_PREEMPT_ASSEMBLY_ERROR_PASTATID 0x0128 //Fragment assembly Error Counter 685#define NRT_INF_AFT_DROP_NOTMEMBER_PASTATID 0x0118 //PRU diagnostic error counter which increments when RX frame is dropped due to port not member of VLAN
686#define NRT_PREEMPT_ASSEMBLY_ERROR_PASTATID_SIZE 0x4 686#define NRT_INF_AFT_DROP_NOTMEMBER_PASTATID_SIZE 0x4
687#define NRT_PREEMPT_FRAG_COUNT_TX_PASTATID 0x012C //Fragment count in TX 687#define NRT_FDB_NO_SPACE_TO_LEARN 0x011C //PRU diagnostic error counter which increments when an entry couldn't be learned
688#define NRT_PREEMPT_FRAG_COUNT_TX_PASTATID_SIZE 0x4 688#define NRT_FDB_NO_SPACE_TO_LEARN_SIZE 0x4
689#define NRT_PREEMPT_ASSEMBLY_OK_PASTATID 0x0130 //Assembly Completed 689#define NRT_FDB_LAST_ENTRY_OVERWRITTEN_FOR_LEARNING 0x0120 //[DEBUG_L2_DIAGNOSTICS | not in release binary] PRU diagnostic error counter which increments when the fourth entry is overwritten to accomodate leart MAC
690#define NRT_PREEMPT_ASSEMBLY_OK_PASTATID_SIZE 0x4 690#define NRT_FDB_LAST_ENTRY_OVERWRITTEN_FOR_LEARNING_SIZE 0x4
691#define NRT_PREEMPT_FRAG_COUNT_RX_PASTATID 0x0134 //Fragments received 691#define NRT_PREEMPT_BAD_FRAG_PASTATID 0x0124 //Bad fragment Error Counter
692#define NRT_PREEMPT_FRAG_COUNT_RX_PASTATID_SIZE 0x4 692#define NRT_PREEMPT_BAD_FRAG_PASTATID_SIZE 0x4
693#define NRT_PREEMPT_DEBUG_GLOBAL_ERROR 0x0138 //[DEBUG_L2_DIAGNOSTICS | not in release binary] Global Debug Error Counter 693#define NRT_PREEMPT_ASSEMBLY_ERROR_PASTATID 0x0128 //Fragment assembly Error Counter
694#define NRT_PREEMPT_DEBUG_GLOBAL_ERROR_SIZE 0x4 694#define NRT_PREEMPT_ASSEMBLY_ERROR_PASTATID_SIZE 0x4
695#define NRT_PREEMPT_DEBUG_SMDCx_PASTATID 0x013C //[DEBUG_L2_DIAGNOSTICS | not in release binary] Debug counter SMDCx 695#define NRT_PREEMPT_FRAG_COUNT_TX_PASTATID 0x012C //Fragment count in TX
696#define NRT_PREEMPT_DEBUG_SMDCx_PASTATID_SIZE 0x4 696#define NRT_PREEMPT_FRAG_COUNT_TX_PASTATID_SIZE 0x4
697#define NRT_PREEMPT_DEBUG_SMDSx_PASTATID 0x0140 //[DEBUG_L2_DIAGNOSTICS | not in release binary] Debug counter SMDSx 697#define NRT_PREEMPT_ASSEMBLY_OK_PASTATID 0x0130 //Assembly Completed
698#define NRT_PREEMPT_DEBUG_SMDSx_PASTATID_SIZE 0x4 698#define NRT_PREEMPT_ASSEMBLY_OK_PASTATID_SIZE 0x4
699#define NRT_PREEMPT_DEBUG_EOF_MPKT_FRAG0_ERROR_PASTATID 0x0144 //[DEBUG_L2_DIAGNOSTICS | not in release binary] Debug counter - Error in SMDSx 699#define NRT_PREEMPT_FRAG_COUNT_RX_PASTATID 0x0134 //Fragments received
700#define NRT_PREEMPT_DEBUG_EOF_MPKT_FRAG0_ERROR_PASTATID_SIZE 0x4 700#define NRT_PREEMPT_FRAG_COUNT_RX_PASTATID_SIZE 0x4
701#define NRT_PREEMPT_DEBUG_EOF_MPKT_FRAGX_ERROR_PASTATID 0x0148 //[DEBUG_L2_DIAGNOSTICS | not in release binary] Debug counter - Error in SMDCx 701#define NRT_PREEMPT_DEBUG_GLOBAL_ERROR 0x0138 //[DEBUG_L2_DIAGNOSTICS | not in release binary] Global Debug Error Counter
702#define NRT_PREEMPT_DEBUG_EOF_MPKT_FRAGX_ERROR_PASTATID_SIZE 0x4 702#define NRT_PREEMPT_DEBUG_GLOBAL_ERROR_SIZE 0x4
703#define PA_STAT_END_OFFSET 0x014C 703#define NRT_PREEMPT_DEBUG_SMDCx_PASTATID 0x013C //[DEBUG_L2_DIAGNOSTICS | not in release binary] Debug counter SMDCx
704 704#define NRT_PREEMPT_DEBUG_SMDCx_PASTATID_SIZE 0x4
705// total PA_STAT memory usage : 0.32421875 KB from total of 2.0KB 705#define NRT_PREEMPT_DEBUG_SMDSx_PASTATID 0x0140 //[DEBUG_L2_DIAGNOSTICS | not in release binary] Debug counter SMDSx
706 706#define NRT_PREEMPT_DEBUG_SMDSx_PASTATID_SIZE 0x4
707 707#define NRT_PREEMPT_DEBUG_EOF_MPKT_FRAG0_ERROR_PASTATID 0x0144 //[DEBUG_L2_DIAGNOSTICS | not in release binary] Debug counter - Error in SMDSx
708#endif // ____switch_mem_map_h 708#define NRT_PREEMPT_DEBUG_EOF_MPKT_FRAG0_ERROR_PASTATID_SIZE 0x4
709#define NRT_PREEMPT_DEBUG_EOF_MPKT_FRAGX_ERROR_PASTATID 0x0148 //[DEBUG_L2_DIAGNOSTICS | not in release binary] Debug counter - Error in SMDCx
710#define NRT_PREEMPT_DEBUG_EOF_MPKT_FRAGX_ERROR_PASTATID_SIZE 0x4
711#define PA_STAT_END_OFFSET 0x014C
712
713// total PA_STAT memory usage : 0.32421875 KB from total of 2.0KB
714
715
716#endif // ____switch_mem_map_h
diff --git a/firmware/icss_switch/config/emac_fw_config_switch.c b/firmware/icss_switch/config/emac_fw_config_switch.c
index 80ce934..b3845ec 100644
--- a/firmware/icss_switch/config/emac_fw_config_switch.c
+++ b/firmware/icss_switch/config/emac_fw_config_switch.c
@@ -92,12 +92,19 @@ EMAC_ICSSG_SWITCH_FW_CFG emac_switch_cfg = {
92 NRT_HOST_DESC_QUEUE_SIZE, 92 NRT_HOST_DESC_QUEUE_SIZE,
93 EXPRESS_PRE_EMPTIVE_Q_MAP, 93 EXPRESS_PRE_EMPTIVE_Q_MAP,
94 SPL_PKT_DEFAULT_PRIORITY, 94 SPL_PKT_DEFAULT_PRIORITY,
95 FDB_AGEING_TIMEOUT_OFFSET,
95 PRE_EMPTION_ENABLE_TX, //placeholder for premptionTxEnabledStatusOffset 96 PRE_EMPTION_ENABLE_TX, //placeholder for premptionTxEnabledStatusOffset
96 PRE_EMPTION_ACTIVE_TX, //placeholder for premptionTxActiveStatusOffset 97 PRE_EMPTION_ACTIVE_TX, //placeholder for premptionTxActiveStatusOffset
97 PRE_EMPTION_ENABLE_VERIFY, //placeholder for premptionVerifyStateStatusOffset 98 PRE_EMPTION_ENABLE_VERIFY, //placeholder for premptionVerifyStateStatusOffset
98 PRE_EMPTION_VERIFY_STATUS, //placeholder for premptionVerifyStateValueOffset 99 PRE_EMPTION_VERIFY_STATUS, //placeholder for premptionVerifyStateValueOffset
99 PRE_EMPTION_ADD_FRAG_SIZE_LOCAL, //placeholder for premptionMinFragSizeOffset 100 PRE_EMPTION_ADD_FRAG_SIZE_LOCAL, //placeholder for premptionMinFragSizeOffset
100 PRE_EMPTION_ADD_FRAG_SIZE_REMOTE //placeholder for premptionMinFragAddOffset 101 PRE_EMPTION_ADD_FRAG_SIZE_REMOTE, //placeholder for premptionMinFragAddOffset
102 DEFAULT_FDB_AGEING_INTERVAL, // Default ageing timeout value
103 NUMBER_OF_FDB_BUCKET_ENTRIES, // Number of entries in FDB bucket
104 SIZE_OF_FDB, // FDB size
105 PORT_Q_PRIORITY_MAPPING_OFFSET, //Port Priority Mapping offset
106 P1_QUEUE_NUM_UNTAGGED, // Untagged packet default Queue num offset Port1
107 P2_QUEUE_NUM_UNTAGGED // Untagged packet default Queue num offset Port1
101}; 108};
102 109
103 110
diff --git a/soc/am65xx/emac_soc.c b/soc/am65xx/emac_soc.c
index 22260b2..3cabbba 100644
--- a/soc/am65xx/emac_soc.c
+++ b/soc/am65xx/emac_soc.c
@@ -94,6 +94,7 @@ EMAC_HwAttrs_V5 EMACInitCfg[1] =
94 CSL_PRU_ICSSG0_RAM_SLV_RAM_BASE, 94 CSL_PRU_ICSSG0_RAM_SLV_RAM_BASE,
95 CSL_PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_BASE, 95 CSL_PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_BASE,
96 CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE, 96 CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE,
97 CSL_PRU_ICSSG0_DRAM1_SLV_RAM_BASE,
97 { /* PER_CHANNEL_CFG_TX upto 4 */ 98 { /* PER_CHANNEL_CFG_TX upto 4 */
98 EMAC_TX_CHANNEL_CONFIG(CSL_PSILCFG_NAVSS_MAIN_ICSS_G0_PSILD_THREAD_OFFSET + 0), 99 EMAC_TX_CHANNEL_CONFIG(CSL_PSILCFG_NAVSS_MAIN_ICSS_G0_PSILD_THREAD_OFFSET + 0),
99 EMAC_TX_CHANNEL_CONFIG(CSL_PSILCFG_NAVSS_MAIN_ICSS_G0_PSILD_THREAD_OFFSET + 1u), 100 EMAC_TX_CHANNEL_CONFIG(CSL_PSILCFG_NAVSS_MAIN_ICSS_G0_PSILD_THREAD_OFFSET + 1u),
@@ -162,6 +163,7 @@ EMAC_HwAttrs_V5 EMACInitCfg[1] =
162 CSL_PRU_ICSSG0_RAM_SLV_RAM_BASE + EMAC_SLICE1_HANDSHAKE_OFFSET, 163 CSL_PRU_ICSSG0_RAM_SLV_RAM_BASE + EMAC_SLICE1_HANDSHAKE_OFFSET,
163 CSL_PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_BASE, 164 CSL_PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_BASE,
164 CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE, 165 CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE,
166 CSL_PRU_ICSSG0_DRAM1_SLV_RAM_BASE,
165 { 167 {
166 EMAC_TX_CHANNEL_CONFIG(CSL_PSILCFG_NAVSS_MAIN_ICSS_G0_PSILD_THREAD_OFFSET + 4u), 168 EMAC_TX_CHANNEL_CONFIG(CSL_PSILCFG_NAVSS_MAIN_ICSS_G0_PSILD_THREAD_OFFSET + 4u),
167 EMAC_TX_CHANNEL_CONFIG(CSL_PSILCFG_NAVSS_MAIN_ICSS_G0_PSILD_THREAD_OFFSET + 5u), 169 EMAC_TX_CHANNEL_CONFIG(CSL_PSILCFG_NAVSS_MAIN_ICSS_G0_PSILD_THREAD_OFFSET + 5u),
@@ -229,6 +231,7 @@ EMAC_HwAttrs_V5 EMACInitCfg[1] =
229 CSL_PRU_ICSSG1_RAM_SLV_RAM_BASE, 231 CSL_PRU_ICSSG1_RAM_SLV_RAM_BASE,
230 CSL_PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_BASE, 232 CSL_PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_BASE,
231 CSL_PRU_ICSSG1_DRAM0_SLV_RAM_BASE, 233 CSL_PRU_ICSSG1_DRAM0_SLV_RAM_BASE,
234 CSL_PRU_ICSSG1_DRAM1_SLV_RAM_BASE,
232 { 235 {
233 EMAC_TX_CHANNEL_CONFIG(CSL_PSILCFG_NAVSS_MAIN_ICSS_G1_PSILD_THREAD_OFFSET + 0), 236 EMAC_TX_CHANNEL_CONFIG(CSL_PSILCFG_NAVSS_MAIN_ICSS_G1_PSILD_THREAD_OFFSET + 0),
234 EMAC_TX_CHANNEL_CONFIG(CSL_PSILCFG_NAVSS_MAIN_ICSS_G1_PSILD_THREAD_OFFSET + 1u), 237 EMAC_TX_CHANNEL_CONFIG(CSL_PSILCFG_NAVSS_MAIN_ICSS_G1_PSILD_THREAD_OFFSET + 1u),
@@ -296,6 +299,7 @@ EMAC_HwAttrs_V5 EMACInitCfg[1] =
296 CSL_PRU_ICSSG1_RAM_SLV_RAM_BASE + EMAC_SLICE1_HANDSHAKE_OFFSET, 299 CSL_PRU_ICSSG1_RAM_SLV_RAM_BASE + EMAC_SLICE1_HANDSHAKE_OFFSET,
297 CSL_PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_BASE, 300 CSL_PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_BASE,
298 CSL_PRU_ICSSG1_DRAM0_SLV_RAM_BASE, 301 CSL_PRU_ICSSG1_DRAM0_SLV_RAM_BASE,
302 CSL_PRU_ICSSG1_DRAM1_SLV_RAM_BASE,
299 { 303 {
300 EMAC_TX_CHANNEL_CONFIG(CSL_PSILCFG_NAVSS_MAIN_ICSS_G1_PSILD_THREAD_OFFSET + 4u), 304 EMAC_TX_CHANNEL_CONFIG(CSL_PSILCFG_NAVSS_MAIN_ICSS_G1_PSILD_THREAD_OFFSET + 4u),
301 EMAC_TX_CHANNEL_CONFIG(CSL_PSILCFG_NAVSS_MAIN_ICSS_G1_PSILD_THREAD_OFFSET + 5u), 305 EMAC_TX_CHANNEL_CONFIG(CSL_PSILCFG_NAVSS_MAIN_ICSS_G1_PSILD_THREAD_OFFSET + 5u),
@@ -364,6 +368,7 @@ EMAC_HwAttrs_V5 EMACInitCfg[1] =
364 CSL_PRU_ICSSG2_RAM_SLV_RAM_BASE, 368 CSL_PRU_ICSSG2_RAM_SLV_RAM_BASE,
365 CSL_PRU_ICSSG2_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_BASE, 369 CSL_PRU_ICSSG2_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_BASE,
366 CSL_PRU_ICSSG2_DRAM0_SLV_RAM_BASE, 370 CSL_PRU_ICSSG2_DRAM0_SLV_RAM_BASE,
371 CSL_PRU_ICSSG2_DRAM1_SLV_RAM_BASE,
367 { 372 {
368 EMAC_TX_CHANNEL_CONFIG(CSL_PSILCFG_NAVSS_MAIN_ICSS_G2_PSILD_THREAD_OFFSET + 0), 373 EMAC_TX_CHANNEL_CONFIG(CSL_PSILCFG_NAVSS_MAIN_ICSS_G2_PSILD_THREAD_OFFSET + 0),
369 EMAC_TX_CHANNEL_CONFIG(CSL_PSILCFG_NAVSS_MAIN_ICSS_G2_PSILD_THREAD_OFFSET + 1u), 374 EMAC_TX_CHANNEL_CONFIG(CSL_PSILCFG_NAVSS_MAIN_ICSS_G2_PSILD_THREAD_OFFSET + 1u),
@@ -431,6 +436,7 @@ EMAC_HwAttrs_V5 EMACInitCfg[1] =
431 CSL_PRU_ICSSG2_RAM_SLV_RAM_BASE + EMAC_SLICE1_HANDSHAKE_OFFSET, 436 CSL_PRU_ICSSG2_RAM_SLV_RAM_BASE + EMAC_SLICE1_HANDSHAKE_OFFSET,
432 CSL_PRU_ICSSG2_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_BASE, 437 CSL_PRU_ICSSG2_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_BASE,
433 CSL_PRU_ICSSG2_DRAM0_SLV_RAM_BASE, 438 CSL_PRU_ICSSG2_DRAM0_SLV_RAM_BASE,
439 CSL_PRU_ICSSG2_DRAM1_SLV_RAM_BASE,
434 { 440 {
435 EMAC_TX_CHANNEL_CONFIG(CSL_PSILCFG_NAVSS_MAIN_ICSS_G2_PSILD_THREAD_OFFSET + 4u), 441 EMAC_TX_CHANNEL_CONFIG(CSL_PSILCFG_NAVSS_MAIN_ICSS_G2_PSILD_THREAD_OFFSET + 4u),
436 EMAC_TX_CHANNEL_CONFIG(CSL_PSILCFG_NAVSS_MAIN_ICSS_G2_PSILD_THREAD_OFFSET + 5u), 442 EMAC_TX_CHANNEL_CONFIG(CSL_PSILCFG_NAVSS_MAIN_ICSS_G2_PSILD_THREAD_OFFSET + 5u),
@@ -498,6 +504,7 @@ EMAC_HwAttrs_V5 EMACInitCfg[1] =
498 EMAC_NOT_CONFIGURED, 504 EMAC_NOT_CONFIGURED,
499 EMAC_NOT_CONFIGURED, 505 EMAC_NOT_CONFIGURED,
500 EMAC_NOT_CONFIGURED, 506 EMAC_NOT_CONFIGURED,
507 EMAC_NOT_CONFIGURED,
501 { 508 {
502 EMAC_TX_CHANNEL_CONFIG(CSL_PSILCFG_NAVSS_MCU_CPSW0_PSILD_THREAD_OFFSET), 509 EMAC_TX_CHANNEL_CONFIG(CSL_PSILCFG_NAVSS_MCU_CPSW0_PSILD_THREAD_OFFSET),
503 EMAC_TX_CHANNEL_UNCONFIGURED, 510 EMAC_TX_CHANNEL_UNCONFIGURED,
diff --git a/soc/j721e/emac_soc.c b/soc/j721e/emac_soc.c
index adba201..7c3f1ce 100644
--- a/soc/j721e/emac_soc.c
+++ b/soc/j721e/emac_soc.c
@@ -92,6 +92,7 @@ EMAC_HwAttrs_V5 EMACInitCfg[1] =
92 CSL_PRU_ICSSG0_RAM_SLV_RAM_BASE, 92 CSL_PRU_ICSSG0_RAM_SLV_RAM_BASE,
93 CSL_PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_BASE, 93 CSL_PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_BASE,
94 CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE, 94 CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE,
95 CSL_PRU_ICSSG0_DRAM1_SLV_RAM_BASE,
95 { /* PER_CHANNEL_CFG_TX upto 4 */ 96 { /* PER_CHANNEL_CFG_TX upto 4 */
96 EMAC_TX_CHANNEL_CONFIG(CSL_PSILCFG_NAVSS_MAIN_ICSS_G0_PSILD_THREAD_OFFSET + 0), 97 EMAC_TX_CHANNEL_CONFIG(CSL_PSILCFG_NAVSS_MAIN_ICSS_G0_PSILD_THREAD_OFFSET + 0),
97 EMAC_TX_CHANNEL_CONFIG(CSL_PSILCFG_NAVSS_MAIN_ICSS_G0_PSILD_THREAD_OFFSET + 1u), 98 EMAC_TX_CHANNEL_CONFIG(CSL_PSILCFG_NAVSS_MAIN_ICSS_G0_PSILD_THREAD_OFFSET + 1u),
@@ -160,6 +161,7 @@ EMAC_HwAttrs_V5 EMACInitCfg[1] =
160 CSL_PRU_ICSSG0_RAM_SLV_RAM_BASE + EMAC_SLICE1_HANDSHAKE_OFFSET, 161 CSL_PRU_ICSSG0_RAM_SLV_RAM_BASE + EMAC_SLICE1_HANDSHAKE_OFFSET,
161 CSL_PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_BASE, 162 CSL_PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_BASE,
162 CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE, 163 CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE,
164 CSL_PRU_ICSSG0_DRAM1_SLV_RAM_BASE,
163 { 165 {
164 EMAC_TX_CHANNEL_CONFIG(CSL_PSILCFG_NAVSS_MAIN_ICSS_G0_PSILD_THREAD_OFFSET + 4u), 166 EMAC_TX_CHANNEL_CONFIG(CSL_PSILCFG_NAVSS_MAIN_ICSS_G0_PSILD_THREAD_OFFSET + 4u),
165 EMAC_TX_CHANNEL_CONFIG(CSL_PSILCFG_NAVSS_MAIN_ICSS_G0_PSILD_THREAD_OFFSET + 5u), 167 EMAC_TX_CHANNEL_CONFIG(CSL_PSILCFG_NAVSS_MAIN_ICSS_G0_PSILD_THREAD_OFFSET + 5u),
@@ -227,6 +229,7 @@ EMAC_HwAttrs_V5 EMACInitCfg[1] =
227 CSL_PRU_ICSSG1_RAM_SLV_RAM_BASE, 229 CSL_PRU_ICSSG1_RAM_SLV_RAM_BASE,
228 CSL_PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_BASE, 230 CSL_PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_BASE,
229 CSL_PRU_ICSSG1_DRAM0_SLV_RAM_BASE, 231 CSL_PRU_ICSSG1_DRAM0_SLV_RAM_BASE,
232 CSL_PRU_ICSSG1_DRAM1_SLV_RAM_BASE,
230 { 233 {
231 EMAC_TX_CHANNEL_CONFIG(CSL_PSILCFG_NAVSS_MAIN_ICSS_G1_PSILD_THREAD_OFFSET + 0), 234 EMAC_TX_CHANNEL_CONFIG(CSL_PSILCFG_NAVSS_MAIN_ICSS_G1_PSILD_THREAD_OFFSET + 0),
232 EMAC_TX_CHANNEL_CONFIG(CSL_PSILCFG_NAVSS_MAIN_ICSS_G1_PSILD_THREAD_OFFSET + 1u), 235 EMAC_TX_CHANNEL_CONFIG(CSL_PSILCFG_NAVSS_MAIN_ICSS_G1_PSILD_THREAD_OFFSET + 1u),
@@ -294,6 +297,7 @@ EMAC_HwAttrs_V5 EMACInitCfg[1] =
294 CSL_PRU_ICSSG1_RAM_SLV_RAM_BASE + EMAC_SLICE1_HANDSHAKE_OFFSET, 297 CSL_PRU_ICSSG1_RAM_SLV_RAM_BASE + EMAC_SLICE1_HANDSHAKE_OFFSET,
295 CSL_PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_BASE, 298 CSL_PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_BASE,
296 CSL_PRU_ICSSG1_DRAM0_SLV_RAM_BASE, 299 CSL_PRU_ICSSG1_DRAM0_SLV_RAM_BASE,
300 CSL_PRU_ICSSG1_DRAM1_SLV_RAM_BASE,
297 { 301 {
298 EMAC_TX_CHANNEL_CONFIG(CSL_PSILCFG_NAVSS_MAIN_ICSS_G1_PSILD_THREAD_OFFSET + 4u), 302 EMAC_TX_CHANNEL_CONFIG(CSL_PSILCFG_NAVSS_MAIN_ICSS_G1_PSILD_THREAD_OFFSET + 4u),
299 EMAC_TX_CHANNEL_CONFIG(CSL_PSILCFG_NAVSS_MAIN_ICSS_G1_PSILD_THREAD_OFFSET + 5u), 303 EMAC_TX_CHANNEL_CONFIG(CSL_PSILCFG_NAVSS_MAIN_ICSS_G1_PSILD_THREAD_OFFSET + 5u),
@@ -362,6 +366,7 @@ EMAC_HwAttrs_V5 EMACInitCfg[1] =
362 CSL_PRU_ICSSG0_RAM_SLV_RAM_BASE + EMAC_SLICE1_HANDSHAKE_OFFSET, 366 CSL_PRU_ICSSG0_RAM_SLV_RAM_BASE + EMAC_SLICE1_HANDSHAKE_OFFSET,
363 CSL_PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_BASE, 367 CSL_PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_BASE,
364 CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE, 368 CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE,
369 CSL_PRU_ICSSG0_DRAM1_SLV_RAM_BASE,
365 { 370 {
366 EMAC_TX_CHANNEL_CONFIG(CSL_PSILCFG_NAVSS_MAIN_ICSS_G0_PSILD_THREAD_OFFSET + 4u), 371 EMAC_TX_CHANNEL_CONFIG(CSL_PSILCFG_NAVSS_MAIN_ICSS_G0_PSILD_THREAD_OFFSET + 4u),
367 EMAC_TX_CHANNEL_CONFIG(CSL_PSILCFG_NAVSS_MAIN_ICSS_G0_PSILD_THREAD_OFFSET + 5u), 372 EMAC_TX_CHANNEL_CONFIG(CSL_PSILCFG_NAVSS_MAIN_ICSS_G0_PSILD_THREAD_OFFSET + 5u),
@@ -429,6 +434,7 @@ EMAC_HwAttrs_V5 EMACInitCfg[1] =
429 CSL_PRU_ICSSG0_RAM_SLV_RAM_BASE + EMAC_SLICE1_HANDSHAKE_OFFSET, 434 CSL_PRU_ICSSG0_RAM_SLV_RAM_BASE + EMAC_SLICE1_HANDSHAKE_OFFSET,
430 CSL_PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_BASE, 435 CSL_PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_BASE,
431 CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE, 436 CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE,
437 CSL_PRU_ICSSG0_DRAM1_SLV_RAM_BASE,
432 { 438 {
433 EMAC_TX_CHANNEL_CONFIG(CSL_PSILCFG_NAVSS_MAIN_ICSS_G0_PSILD_THREAD_OFFSET + 4u), 439 EMAC_TX_CHANNEL_CONFIG(CSL_PSILCFG_NAVSS_MAIN_ICSS_G0_PSILD_THREAD_OFFSET + 4u),
434 EMAC_TX_CHANNEL_CONFIG(CSL_PSILCFG_NAVSS_MAIN_ICSS_G0_PSILD_THREAD_OFFSET + 5u), 440 EMAC_TX_CHANNEL_CONFIG(CSL_PSILCFG_NAVSS_MAIN_ICSS_G0_PSILD_THREAD_OFFSET + 5u),
@@ -496,6 +502,7 @@ EMAC_HwAttrs_V5 EMACInitCfg[1] =
496 EMAC_NOT_CONFIGURED, 502 EMAC_NOT_CONFIGURED,
497 EMAC_NOT_CONFIGURED, 503 EMAC_NOT_CONFIGURED,
498 EMAC_NOT_CONFIGURED, 504 EMAC_NOT_CONFIGURED,
505 EMAC_NOT_CONFIGURED,
499 { 506 {
500 EMAC_TX_CHANNEL_CONFIG(CSL_PSILCFG_NAVSS_MCU_CPSW0_PSILD_THREAD_OFFSET), 507 EMAC_TX_CHANNEL_CONFIG(CSL_PSILCFG_NAVSS_MCU_CPSW0_PSILD_THREAD_OFFSET),
501 EMAC_TX_CHANNEL_UNCONFIGURED, 508 EMAC_TX_CHANNEL_UNCONFIGURED,
diff --git a/src/v5/emac_drv_v5.c b/src/v5/emac_drv_v5.c
index a8c3a27..f8ace13 100644
--- a/src/v5/emac_drv_v5.c
+++ b/src/v5/emac_drv_v5.c
@@ -1598,6 +1598,7 @@ static EMAC_DRV_ERR_E emac_open_v5_local(uint32_t port_num, uint32_t virt_port_
1598 emac_mcb.port_cb[port_num].icssSharedRamBaseAddr = hwAttrs->portCfg[port_num].icssSharedRamBaseAddr; 1598 emac_mcb.port_cb[port_num].icssSharedRamBaseAddr = hwAttrs->portCfg[port_num].icssSharedRamBaseAddr;
1599 emac_mcb.port_cb[port_num].icssgCfgRegBaseAddr = hwAttrs->portCfg[port_num].icssgCfgRegBaseAddr; 1599 emac_mcb.port_cb[port_num].icssgCfgRegBaseAddr = hwAttrs->portCfg[port_num].icssgCfgRegBaseAddr;
1600 emac_mcb.port_cb[port_num].icssDram0BaseAddr = hwAttrs->portCfg[port_num].icssDram0BaseAddr; 1600 emac_mcb.port_cb[port_num].icssDram0BaseAddr = hwAttrs->portCfg[port_num].icssDram0BaseAddr;
1601 emac_mcb.port_cb[port_num].icssDram1BaseAddr = hwAttrs->portCfg[port_num].icssDram1BaseAddr;
1601 /* disable all classifiers */ 1602 /* disable all classifiers */
1602 emac_classifier_disable(port_num); 1603 emac_classifier_disable(port_num);
1603 1604
@@ -2584,6 +2585,9 @@ static EMAC_DRV_ERR_E EMAC_ioctl_v5(uint32_t port_num, EMAC_IOCTL_CMD emacIoctlC
2584 case EMAC_IOCTL_SPECIAL_FRAME_PRIO_CONFIG: 2585 case EMAC_IOCTL_SPECIAL_FRAME_PRIO_CONFIG:
2585 emac_ioctl_configure_special_frame_prio_ctrl(i, port_num, (void*)emacIoctlParams); 2586 emac_ioctl_configure_special_frame_prio_ctrl(i, port_num, (void*)emacIoctlParams);
2586 break; 2587 break;
2588 case EMAC_IOCTL_FDB_AGEING_TIMEOUT_CTRL:
2589 emac_ioctl_configure_fdb_ageing_interval(i, port_num, (void*)emacIoctlParams);
2590 break;
2587 case EMAC_IOCTL_TEST_MULTI_FLOW: 2591 case EMAC_IOCTL_TEST_MULTI_FLOW:
2588 emac_ioctl_test_multi_flow(i, ioctlData); 2592 emac_ioctl_test_multi_flow(i, ioctlData);
2589 break; 2593 break;
@@ -2722,6 +2726,11 @@ static void EMAC_get_cpsw_stats(CSL_Xge_cpswRegs *hCpswRegs, EMAC_STATISTICS_T*
2722void emac_icssg_switch_eth_setup (uint32_t portNum) 2726void emac_icssg_switch_eth_setup (uint32_t portNum)
2723{ 2727{
2724 uint32_t reg_val; 2728 uint32_t reg_val;
2729 uint32_t numFDBBuckets =0;
2730 uintptr_t fdbAgeingIntervalAddr;
2731 EMAC_PER_PORT_ICSSG_FW_CFG *pEmacFwCfg;
2732 EMAC_ICSSG_SWITCH_FW_CFG *pSwitchFwCfg;
2733
2725 uintptr_t icssgBaseAddr = emac_mcb.port_cb[portNum].icssDram0BaseAddr; 2734 uintptr_t icssgBaseAddr = emac_mcb.port_cb[portNum].icssDram0BaseAddr;
2726 2735
2727 /* Program c28_pointer to 0x100, so that firmware can access 0x10000 via C28 */ 2736 /* Program c28_pointer to 0x100, so that firmware can access 0x10000 via C28 */
@@ -2870,6 +2879,22 @@ void emac_icssg_switch_eth_setup (uint32_t portNum)
2870 /* Enable stats block, 0 64-bit counters */ 2879 /* Enable stats block, 0 64-bit counters */
2871 CSL_REG32_WR (icssgBaseAddr + CSL_ICSS_G_PA_STAT_WRAP_PA_SLV_REGS_BASE + 8, EMAC_BIT(31)); 2880 CSL_REG32_WR (icssgBaseAddr + CSL_ICSS_G_PA_STAT_WRAP_PA_SLV_REGS_BASE + 8, EMAC_BIT(31));
2872 2881
2882
2883 /* Configure Default Ageing value for firmware to use*/
2884 /* The actual value written to memory is ageing timeout divided by number of buckets
2885 * because in firmware we iterate per bucket not for entire FDB. See NRT design doc for more details */
2886 if (emac_mcb.port_cb[portNum].getFwCfg)
2887 {
2888 emac_mcb.port_cb[portNum].getFwCfg(portNum,&pEmacFwCfg);
2889 pSwitchFwCfg = (EMAC_ICSSG_SWITCH_FW_CFG*) pEmacFwCfg->pFwPortCfg;
2890 /*Calculate number of buckets*/
2891 numFDBBuckets = pSwitchFwCfg->fdbSize / pSwitchFwCfg->numFdbBucketEntries;
2892
2893 fdbAgeingIntervalAddr = emac_mcb.port_cb[portNum].icssDram1BaseAddr + pSwitchFwCfg->fdbAgeingTimeoutOffset;
2894 /*The actual value written to memory is ageing timeout divided by number of buckets
2895 because in firmware we iterate per bucket not for entire FDB. See NRT design doc for more details*/
2896 CSL_REG64_WR(fdbAgeingIntervalAddr, pSwitchFwCfg->defaultAgeingTimeout/(uint64_t)numFDBBuckets);
2897 }
2873} 2898}
2874 2899
2875/* 2900/*
diff --git a/src/v5/emac_drv_v5.h b/src/v5/emac_drv_v5.h
index 7441c46..ab22ce4 100644
--- a/src/v5/emac_drv_v5.h
+++ b/src/v5/emac_drv_v5.h
@@ -305,12 +305,19 @@ uint32_t txPortQueueDescSize; /* Size of each TX port
305uint32_t txHostQueueDescSize; /* Size of each TX host descriptor queue */ 305uint32_t txHostQueueDescSize; /* Size of each TX host descriptor queue */
306uint32_t expressPremptiveQueueOffset; /* DEM0 offset to priority regen tab */ 306uint32_t expressPremptiveQueueOffset; /* DEM0 offset to priority regen tab */
307uint32_t splPacketDefaultPrioOffset; /* SHARED MEM OFFSET offset to special pkt default priority */ 307uint32_t splPacketDefaultPrioOffset; /* SHARED MEM OFFSET offset to special pkt default priority */
308uint64_t fdbAgeingTimeoutOffset; /* DMEM1 offset for storing FDB ageing timeout interval */
308uint32_t premptionTxEnabledStatusOffset; /* DEM0 offset for status of premption on Tx enabled */ 309uint32_t premptionTxEnabledStatusOffset; /* DEM0 offset for status of premption on Tx enabled */
309uint32_t premptionTxActiveStatusOffset; /* DEM0 offset for status of premption on Tx active */ 310uint32_t premptionTxActiveStatusOffset; /* DEM0 offset for status of premption on Tx active */
310uint32_t premptionVerifyStateStatusOffset; /* DEM0 offset for status of premption verify state machine*/ 311uint32_t premptionVerifyStateStatusOffset; /* DEM0 offset for status of premption verify state machine*/
311uint32_t premptionVerifyStateValueOffset; /* DEM0 offset for value of premption verify state machine*/ 312uint32_t premptionVerifyStateValueOffset; /* DEM0 offset for value of premption verify state machine*/
312uint32_t premptionMinFragSizeOffset; /* DEM0 offset for min fragment size supported by firmware */ 313uint32_t premptionMinFragSizeOffset; /* DEM0 offset for min fragment size supported by firmware */
313uint32_t premptionMinFragAddOffset; /* DEM0 offset to configure min fragment size during premption */ 314uint32_t premptionMinFragAddOffset; /* DEM0 offset to configure min fragment size during premption */
315uint64_t defaultAgeingTimeout; /* Default ageing timeout value */
316uint32_t numFdbBucketEntries; /* Number of entries in FDB bucket */
317uint32_t fdbSize; /* FDB size */
318uint32_t prioMappingTableOffset; /* DEM0 offset to priority mapping table */
319uint32_t switchPort1UntaggedQueue; /* SHARED MEM OFFSET to switch port 1 untagged packet queue number */
320uint32_t switchPort2UntaggedQueue; /* SHARED MEM OFFSET to switch port 2 untagged packet queue number */
314} EMAC_ICSSG_SWITCH_FW_CFG; 321} EMAC_ICSSG_SWITCH_FW_CFG;
315 322
316/** 323/**
@@ -352,6 +359,8 @@ typedef struct EMAC_PER_PORT_CFG_s{
352 uintptr_t icssgCfgRegBaseAddr; 359 uintptr_t icssgCfgRegBaseAddr;
353 /* base address of ICSSG data ram 0 registers, N/A for CPSW2G */ 360 /* base address of ICSSG data ram 0 registers, N/A for CPSW2G */
354 uintptr_t icssDram0BaseAddr; 361 uintptr_t icssDram0BaseAddr;
362 /* base address of ICSSG data ram 1 registers, N/A for CPSW2G */
363 uintptr_t icssDram1BaseAddr;
355 /**< base address of ICSSG shared memory, N/A for CPSW2G */ 364 /**< base address of ICSSG shared memory, N/A for CPSW2G */
356 EMAC_PER_CHANNEL_CFG_TX txChannel[EMAC_TX_MAX_CHANNELS_PER_PORT]; 365 EMAC_PER_CHANNEL_CFG_TX txChannel[EMAC_TX_MAX_CHANNELS_PER_PORT];
357 EMAC_PER_CHANNEL_CFG_RX rxChannel; 366 EMAC_PER_CHANNEL_CFG_RX rxChannel;
@@ -434,7 +443,8 @@ typedef struct EMAC_PORT_CB_V5_S
434 uintptr_t icssSharedRamBaseAddr; 443 uintptr_t icssSharedRamBaseAddr;
435 uintptr_t icssgCfgRegBaseAddr; 444 uintptr_t icssgCfgRegBaseAddr;
436 uintptr_t icssDram0BaseAddr; 445 uintptr_t icssDram0BaseAddr;
437 int32_t ioctlInProgress; 446 uintptr_t icssDram1BaseAddr;
447 int32_t ioctlInProgress;
438 EMAC_POLLING_TABLE_T pollTable; 448 EMAC_POLLING_TABLE_T pollTable;
439 CSL_Xge_cpswRegs *hCpswRegs; 449 CSL_Xge_cpswRegs *hCpswRegs;
440 CSL_AleRegs *hCpswAleRegs; 450 CSL_AleRegs *hCpswAleRegs;
diff --git a/src/v5/emac_ioctl.c b/src/v5/emac_ioctl.c
index 4a59ff8..f9842d5 100644
--- a/src/v5/emac_ioctl.c
+++ b/src/v5/emac_ioctl.c
@@ -666,7 +666,7 @@ EMAC_DRV_ERR_E emac_ioctl_vlan_ctrl_set_default_vlan_id(uint32_t port_num, void*
666 EMAC_DRV_ERR_E retVal = EMAC_DRV_RESULT_OK; 666 EMAC_DRV_ERR_E retVal = EMAC_DRV_RESULT_OK;
667 uint8_t tempByte1 = 0; 667 uint8_t tempByte1 = 0;
668 uint8_t tempByte2 = 0; 668 uint8_t tempByte2 = 0;
669 669 uint32_t prioMapOffset;
670 EMAC_IOCTL_VLAN_DEFAULT_ENTRY *vlanDefaultEntry= (EMAC_IOCTL_VLAN_DEFAULT_ENTRY*)ctrl; 670 EMAC_IOCTL_VLAN_DEFAULT_ENTRY *vlanDefaultEntry= (EMAC_IOCTL_VLAN_DEFAULT_ENTRY*)ctrl;
671 EMAC_PER_PORT_ICSSG_FW_CFG *pEmacFwCfg; 671 EMAC_PER_PORT_ICSSG_FW_CFG *pEmacFwCfg;
672 EMAC_ICSSG_SWITCH_FW_CFG *pSwitchFwCfg; 672 EMAC_ICSSG_SWITCH_FW_CFG *pSwitchFwCfg;
@@ -704,6 +704,19 @@ EMAC_DRV_ERR_E emac_ioctl_vlan_ctrl_set_default_vlan_id(uint32_t port_num, void*
704 regAddr = emac_mcb.port_cb[port_num].icssSharedRamBaseAddr + pSwitchFwCfg->switchPort2DefaultVlanOffset; 704 regAddr = emac_mcb.port_cb[port_num].icssSharedRamBaseAddr + pSwitchFwCfg->switchPort2DefaultVlanOffset;
705 } 705 }
706 CSL_REG32_WR (regAddr, regVal); 706 CSL_REG32_WR (regAddr, regVal);
707
708 /* Update Deafult Queue number for untagged packet*/
709 prioMapOffset = pSwitchFwCfg->prioMappingTableOffset;
710 tempByte1 = CSL_REG8_RD(emac_mcb.port_cb[port_num].icssDram0BaseAddr + prioMapOffset + vlanDefaultEntry->pcp);
711 if(port_num == 0)
712 {
713 regAddr = emac_mcb.port_cb[port_num].icssSharedRamBaseAddr + pSwitchFwCfg->switchPort1UntaggedQueue;
714 }
715 else
716 {
717 regAddr = emac_mcb.port_cb[port_num].icssSharedRamBaseAddr + pSwitchFwCfg->switchPort2UntaggedQueue;
718 }
719 CSL_REG8_WR (regAddr, tempByte1);
707 } 720 }
708 UTILS_trace(UTIL_TRACE_LEVEL_INFO, emac_mcb.drv_trace_cb, "port: %d: EXIT with status: %d",port_num, retVal); 721 UTILS_trace(UTIL_TRACE_LEVEL_INFO, emac_mcb.drv_trace_cb, "port: %d: EXIT with status: %d",port_num, retVal);
709 return retVal; 722 return retVal;
@@ -746,13 +759,17 @@ EMAC_DRV_ERR_E emac_icssg_filter3_config (uint32_t port_num, uint32_t pruNum, ui
746 */ 759 */
747void emac_ioctl_port_prio_mapping_ctrl(uint32_t port_num, void* ctrl) 760void emac_ioctl_port_prio_mapping_ctrl(uint32_t port_num, void* ctrl)
748{ 761{
749 EMAC_IOCTL_PORT_PRIO_MAP *pTciMap = (EMAC_IOCTL_PORT_PRIO_MAP*)ctrl; 762 uint8_t index;
763 EMAC_DRV_ERR_E retVal = EMAC_DRV_RESULT_INVALID_PORT;
764 uintptr_t icssgBaseAddr;
765 uint32_t prioMapOffset;
766 uint8_t tempVal;
767 EMAC_PER_PORT_ICSSG_FW_CFG *pEmacFwCfg;
768 EMAC_ICSSG_SWITCH_FW_CFG *pSwitchFwCfg;
769 EMAC_IOCTL_PORT_PRIO_MAP *pPrioMap;
770 uint8_t untaggedQueueNum;
771 uint32_t prioRegenMapOffset;
750 772
751 UTILS_trace(UTIL_TRACE_LEVEL_INFO, emac_mcb.drv_trace_cb, "port: %d: ENTER",port_num);
752 /*
753 One-to-one mapping from PCP -> Traffic Class.
754 Managed using FT3[0:7] and Classifier[0:7].
755 */
756 uintptr_t baseAddr = emac_mcb.port_cb[port_num].icssDram0BaseAddr + CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_REGS_BASE; 773 uintptr_t baseAddr = emac_mcb.port_cb[port_num].icssDram0BaseAddr + CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_REGS_BASE;
757 uint32_t ft3Type = 0; 774 uint32_t ft3Type = 0;
758 uint32_t classSelect = 0; 775 uint32_t classSelect = 0;
@@ -765,50 +782,118 @@ void emac_ioctl_port_prio_mapping_ctrl(uint32_t port_num, void* ctrl)
765 EMAC_FILTER3_CONFIG ft3ConfigPcp = {0xc, 0, 0, 0, 0, 5, 0, 0xff1f0000, 0, 0, 0xffffffff, 0xffffffff}; 782 EMAC_FILTER3_CONFIG ft3ConfigPcp = {0xc, 0, 0, 0, 0, 5, 0, 0xff1f0000, 0, 0, 0xffffffff, 0xffffffff};
766 int8_t p; 783 int8_t p;
767 int8_t c; 784 int8_t c;
785 uint8_t finalPrioQueueMap[EMAC_IOCTL_PRIO_MAX]={0};
768 786
769 /* set up filter type 3's to match pcp bits */ 787 UTILS_trace(UTIL_TRACE_LEVEL_INFO, emac_mcb.drv_trace_cb, "port: %d: ENTER",port_num);
770 for (p = 0; p < EMAC_IOCTL_PRIO_MAX; p++)
771 {
772 /*Setup FT3[0:7] to detect PCP0 - PCP7 */
773 ft3Type = (uint32_t)((((uint32_t)p) << 21) | 0x00000081);
774 ft3ConfigPcp.ft3Type = ft3Type;
775 emac_icssg_filter3_config(port_num, 0, p, &ft3ConfigPcp);
776 }
777 788
778 /* Build up the or lists */ 789 if ((port_num == 0) || (port_num == 2U))
779 for (p = 0; p < EMAC_IOCTL_PRIO_MAX; p++)
780 { 790 {
781 classSelect = (pTciMap->portPrioMap[p]); 791 emac_ioctl_get_fw_config(port_num, &pEmacFwCfg);
782 orEnable[classSelect] |= (1 << p); 792 pSwitchFwCfg = (EMAC_ICSSG_SWITCH_FW_CFG*) pEmacFwCfg->pFwPortCfg;
783 } 793 prioMapOffset = pSwitchFwCfg->prioMappingTableOffset;
784 794
785 /* now program classifier c */ 795 pPrioMap = (EMAC_IOCTL_PORT_PRIO_MAP*)ctrl;
786 for (c = 0; c<EMAC_IOCTL_PRIO_MAX;c++ ) 796 icssgBaseAddr = emac_mcb.port_cb[port_num].icssDram0BaseAddr;
787 { 797 for (index = 0; index < EMAC_IOCTL_PRIO_MAX;index++)
788 /* Configure OR Enable*/ 798 {
789 CSL_REG32_WR((baseAddr + CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_RX_CLASS0_OR_EN_PRU0 + (8*c)), orEnable[c]); 799 tempVal = (uint8_t)pPrioMap->portPrioMap[index];
790 /* Configure AND Enable */ 800 CSL_REG8_WR(icssgBaseAddr + prioMapOffset + index, tempVal);
791 CSL_REG32_WR((baseAddr + CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_RX_CLASS0_AND_EN_PRU0 + (8*c)), andEnable[c]); 801 }
792 tempReg = CSL_REG32_RD(baseAddr + CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_RX_CLASS_CFG1_PRU0); 802
793 tempReg &= ~(0x3 << (c * 2)); 803 /* Re configure classifier to map incoming pcp to Queue. Take into account Prio regen config also */
794 CSL_REG32_WR((baseAddr + CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_RX_CLASS_CFG1_PRU0), tempReg); 804 /*
795 /* Configure NV Enable */ 805 One-to-one mapping from PCP -> Traffic Class.
796 /* Configure NV Enable bits (1 bit in upper16, 1bit in lower16 */ 806 Managed using FT3[0:7] and Classifier[0:7].
797 tempReg = CSL_REG32_RD(baseAddr + CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_RX_CLASS_CFG2_PRU0); 807 */
798 if (orNvEnable[c]) 808
799 tempReg |= 1 << (c + 16); 809 /* set up filter type 3's to match pcp bits */
810 for (p = 0; p < EMAC_IOCTL_PRIO_MAX; p++)
811 {
812 /*Setup FT3[0:7] to detect PCP0 - PCP7 */
813 ft3Type = (uint32_t)((((uint32_t)p) << 21) | 0x00000081);
814 ft3ConfigPcp.ft3Type = ft3Type;
815 emac_icssg_filter3_config(port_num, 0, p, &ft3ConfigPcp);
816 }
817
818 /*Get the Queue mapping value from DRAM0 and calculate incoming PCP to Queue mapping*/
819 emac_ioctl_get_fw_config(port_num, &pEmacFwCfg);
820 pSwitchFwCfg = (EMAC_ICSSG_SWITCH_FW_CFG*) pEmacFwCfg->pFwPortCfg;
821 prioRegenMapOffset = pSwitchFwCfg->prioRegenTableOffset;
822
823 for(p = 0; p < EMAC_IOCTL_PRIO_MAX; p++)
824 {
825 /* Get regenerated value for PCP = p*/
826 tempVal = CSL_REG8_RD(icssgBaseAddr + prioRegenMapOffset + (p*4));
827 /*Shift PCP value by 5 to get the value*/
828 tempVal = tempVal >> 5;
829
830 finalPrioQueueMap[p] = (uint8_t)pPrioMap->portPrioMap[tempVal];
831 }
832
833 /* Build up the or lists */
834 for (p = 0; p < EMAC_IOCTL_PRIO_MAX; p++)
835 {
836 classSelect = finalPrioQueueMap[p];
837 orEnable[classSelect] |= (1 << p);
838 }
839
840 /* now program classifier c */
841 for (c = 0; c<EMAC_IOCTL_PRIO_MAX;c++ )
842 {
843 /* Configure OR Enable*/
844 CSL_REG32_WR((baseAddr + CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_RX_CLASS0_OR_EN_PRU0 + (8*c)), orEnable[c]);
845 /* Configure AND Enable */
846 CSL_REG32_WR((baseAddr + CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_RX_CLASS0_AND_EN_PRU0 + (8*c)), andEnable[c]);
847 tempReg = CSL_REG32_RD(baseAddr + CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_RX_CLASS_CFG1_PRU0);
848 tempReg &= ~(0x3 << (c * 2));
849 CSL_REG32_WR((baseAddr + CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_RX_CLASS_CFG1_PRU0), tempReg);
850 /* Configure NV Enable */
851 /* Configure NV Enable bits (1 bit in upper16, 1bit in lower16 */
852 tempReg = CSL_REG32_RD(baseAddr + CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_RX_CLASS_CFG2_PRU0);
853 if (orNvEnable[c])
854 tempReg |= 1 << (c + 16);
855 else
856 tempReg &= ~(1 << (c + 16));
857 if (andNvEnable[c])
858 tempReg |= 1 << (c);
859 else
860 tempReg &= ~(1 << (c));
861 CSL_REG32_WR((baseAddr + CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_RX_CLASS_CFG2_PRU0), tempReg);
862 /* Configure class gate */
863 CSL_REG32_WR((baseAddr + CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_RX_CLASS_GATES0_PRU0 + (4*c)), gateConfig);
864 }
865
866 /* Update Deafult Queue number for untagged packet*/
867 /*Read the configured PCP value*/
868 if(port_num == 0)
869 {
870 baseAddr = emac_mcb.port_cb[port_num].icssSharedRamBaseAddr + pSwitchFwCfg->switchPort1DefaultVlanOffset;
871 }
800 else 872 else
801 tempReg &= ~(1 << (c + 16)); 873 {
802 if (andNvEnable[c]) 874 baseAddr = emac_mcb.port_cb[port_num].icssSharedRamBaseAddr + pSwitchFwCfg->switchPort2DefaultVlanOffset;
803 tempReg |= 1 << (c); 875 }
876 tempVal = CSL_REG8_RD(baseAddr + 2); /*Read PCP value*/
877 tempVal = tempVal >> 5; /*Shif to get the value in correct format*/
878 untaggedQueueNum = pPrioMap->portPrioMap[tempVal];
879
880 if(port_num == 0)
881 {
882 baseAddr = emac_mcb.port_cb[port_num].icssSharedRamBaseAddr + pSwitchFwCfg->switchPort1UntaggedQueue;
883 }
804 else 884 else
805 tempReg &= ~(1 << (c)); 885 {
806 CSL_REG32_WR((baseAddr + CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_RX_CLASS_CFG2_PRU0), tempReg); 886 baseAddr = emac_mcb.port_cb[port_num].icssSharedRamBaseAddr + pSwitchFwCfg->switchPort2UntaggedQueue;
807 /* Configure class gate */ 887 }
808 CSL_REG32_WR((baseAddr + CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_RX_CLASS_GATES0_PRU0 + (4*c)), gateConfig); 888 CSL_REG8_WR (baseAddr, untaggedQueueNum);
889 retVal = EMAC_DRV_RESULT_OK;
809 } 890 }
810 891 else
811 UTILS_trace(UTIL_TRACE_LEVEL_INFO, emac_mcb.drv_trace_cb, "port: %d: EXIT",port_num); 892 {
893 UTILS_trace(UTIL_TRACE_LEVEL_ERR, emac_mcb.drv_trace_cb, "invalid port number specified: %d, ",port_num);
894 }
895 UTILS_trace(UTIL_TRACE_LEVEL_INFO, emac_mcb.drv_trace_cb, "port: %d: EXIT with status: %d",port_num, retVal);
896 //return retVal;
812} 897}
813 898
814/* 899/*
@@ -1098,19 +1183,92 @@ EMAC_DRV_ERR_E emac_ioctl_prio_regen_mapping_ctrl(uint32_t port_num, void* ctrl
1098 EMAC_DRV_ERR_E retVal = EMAC_DRV_RESULT_INVALID_PORT; 1183 EMAC_DRV_ERR_E retVal = EMAC_DRV_RESULT_INVALID_PORT;
1099 uintptr_t icssgBaseAddr; 1184 uintptr_t icssgBaseAddr;
1100 uint32_t prioRegenMapOffset; 1185 uint32_t prioRegenMapOffset;
1186 uint32_t prioMapOffset;
1101 uint32_t tempVal; 1187 uint32_t tempVal;
1102 EMAC_PER_PORT_ICSSG_FW_CFG *pEmacFwCfg; 1188 EMAC_PER_PORT_ICSSG_FW_CFG *pEmacFwCfg;
1103 EMAC_ICSSG_SWITCH_FW_CFG *pSwitchFwCfg; 1189 EMAC_ICSSG_SWITCH_FW_CFG *pSwitchFwCfg;
1104 EMAC_IOCTL_PRIO_REGEN_MAP *pPrioRegenMap; 1190 EMAC_IOCTL_PRIO_REGEN_MAP *pPrioRegenMap;
1105 1191
1192
1106 UTILS_trace(UTIL_TRACE_LEVEL_INFO, emac_mcb.drv_trace_cb, "port: %d: ENTER",port_num); 1193 UTILS_trace(UTIL_TRACE_LEVEL_INFO, emac_mcb.drv_trace_cb, "port: %d: ENTER",port_num);
1194
1107 if ((port_num == 0) || (port_num == 2U)) 1195 if ((port_num == 0) || (port_num == 2U))
1108 { 1196 {
1197 pPrioRegenMap = (EMAC_IOCTL_PRIO_REGEN_MAP*)ctrl;
1198
1199 /*
1200 One-to-one mapping from PCP -> Traffic Class.
1201 Managed using FT3[0:7] and Classifier[0:7].
1202 */
1203 uintptr_t baseAddr = emac_mcb.port_cb[port_num].icssDram0BaseAddr + CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_REGS_BASE;
1204 uint32_t ft3Type = 0;
1205 uint32_t classSelect = 0;
1206 uint32_t orEnable[EMAC_IOCTL_PRIO_MAX] = {0,};
1207 uint32_t andEnable[EMAC_IOCTL_PRIO_MAX] = {0,};
1208 uint16_t orNvEnable[EMAC_IOCTL_PRIO_MAX] = {0,};
1209 uint16_t andNvEnable[EMAC_IOCTL_PRIO_MAX] = {0,};
1210 uint32_t gateConfig = 0x50;
1211 uint32_t tempReg = 0;
1212 EMAC_FILTER3_CONFIG ft3ConfigPcp = {0xc, 0, 0, 0, 0, 5, 0, 0xff1f0000, 0, 0, 0xffffffff, 0xffffffff};
1213 int8_t p;
1214 int8_t c;
1215 uint8_t finalPrioQueueMap[EMAC_IOCTL_PRIO_MAX]={0};
1216
1217 /* set up filter type 3's to match pcp bits */
1218 for (p = 0; p < EMAC_IOCTL_PRIO_MAX; p++)
1219 {
1220 /*Setup FT3[0:7] to detect PCP0 - PCP7 */
1221 ft3Type = (uint32_t)((((uint32_t)p) << 21) | 0x00000081);
1222 ft3ConfigPcp.ft3Type = ft3Type;
1223 emac_icssg_filter3_config(port_num, 0, p, &ft3ConfigPcp);
1224 }
1225
1226 /*Get the Queue mapping value from DRAM0 and calculate incoming PCP to Queue mapping*/
1227 emac_ioctl_get_fw_config(port_num, &pEmacFwCfg);
1228 pSwitchFwCfg = (EMAC_ICSSG_SWITCH_FW_CFG*) pEmacFwCfg->pFwPortCfg;
1229 prioMapOffset = pSwitchFwCfg->prioMappingTableOffset;
1230 icssgBaseAddr = emac_mcb.port_cb[port_num].icssDram0BaseAddr;
1231 for(p = 0; p < EMAC_IOCTL_PRIO_MAX; p++)
1232 {
1233 finalPrioQueueMap[p] = CSL_REG8_RD(icssgBaseAddr + prioMapOffset + (pPrioRegenMap->prioRegenMap[p]));
1234 }
1235 /* Build up the or lists */
1236 for (p = 0; p < EMAC_IOCTL_PRIO_MAX; p++)
1237 {
1238 classSelect = finalPrioQueueMap[p];
1239 orEnable[classSelect] |= (1 << p);
1240 }
1241
1242 /* now program classifier c */
1243 for (c = 0; c<EMAC_IOCTL_PRIO_MAX;c++ )
1244 {
1245 /* Configure OR Enable*/
1246 CSL_REG32_WR((baseAddr + CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_RX_CLASS0_OR_EN_PRU0 + (8*c)), orEnable[c]);
1247 /* Configure AND Enable */
1248 CSL_REG32_WR((baseAddr + CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_RX_CLASS0_AND_EN_PRU0 + (8*c)), andEnable[c]);
1249 tempReg = CSL_REG32_RD(baseAddr + CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_RX_CLASS_CFG1_PRU0);
1250 tempReg &= ~(0x3 << (c * 2));
1251 CSL_REG32_WR((baseAddr + CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_RX_CLASS_CFG1_PRU0), tempReg);
1252 /* Configure NV Enable */
1253 /* Configure NV Enable bits (1 bit in upper16, 1bit in lower16 */
1254 tempReg = CSL_REG32_RD(baseAddr + CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_RX_CLASS_CFG2_PRU0);
1255 if (orNvEnable[c])
1256 tempReg |= 1 << (c + 16);
1257 else
1258 tempReg &= ~(1 << (c + 16));
1259 if (andNvEnable[c])
1260 tempReg |= 1 << (c);
1261 else
1262 tempReg &= ~(1 << (c));
1263 CSL_REG32_WR((baseAddr + CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_RX_CLASS_CFG2_PRU0), tempReg);
1264 /* Configure class gate */
1265 CSL_REG32_WR((baseAddr + CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_RX_CLASS_GATES0_PRU0 + (4*c)), gateConfig);
1266 }
1267
1109 emac_ioctl_get_fw_config(port_num, &pEmacFwCfg); 1268 emac_ioctl_get_fw_config(port_num, &pEmacFwCfg);
1110 pSwitchFwCfg = (EMAC_ICSSG_SWITCH_FW_CFG*) pEmacFwCfg->pFwPortCfg; 1269 pSwitchFwCfg = (EMAC_ICSSG_SWITCH_FW_CFG*) pEmacFwCfg->pFwPortCfg;
1111 prioRegenMapOffset = pSwitchFwCfg->prioRegenTableOffset; 1270 prioRegenMapOffset = pSwitchFwCfg->prioRegenTableOffset;
1112 1271
1113 pPrioRegenMap = (EMAC_IOCTL_PRIO_REGEN_MAP*)ctrl;
1114 icssgBaseAddr = emac_mcb.port_cb[port_num].icssDram0BaseAddr; 1272 icssgBaseAddr = emac_mcb.port_cb[port_num].icssDram0BaseAddr;
1115 for (index = 0; index < EMAC_IOCTL_PRIO_MAX;index++) 1273 for (index = 0; index < EMAC_IOCTL_PRIO_MAX;index++)
1116 { 1274 {
@@ -1222,23 +1380,37 @@ EMAC_DRV_ERR_E emac_ioctl_configure_interface_mac_ctrl(uint32_t port_num, uint32
1222 if(switch_port == EMAC_SWITCH_PORT1) 1380 if(switch_port == EMAC_SWITCH_PORT1)
1223 { 1381 {
1224 /* add mac */ 1382 /* add mac */
1383 baseAddr = emac_mcb.port_cb[1].icssDram0BaseAddr + CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_REGS_BASE;
1384
1225 CSL_REG32_WR(baseAddr+CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_MAC_PRU0_0, macLo); 1385 CSL_REG32_WR(baseAddr+CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_MAC_PRU0_0, macLo);
1226 CSL_REG32_WR(baseAddr+CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_MAC_PRU0_1, macHi); 1386 CSL_REG32_WR(baseAddr+CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_MAC_PRU0_1, macHi);
1387
1388 baseAddr = emac_mcb.port_cb[2].icssDram0BaseAddr + CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_REGS_BASE;
1389
1390 CSL_REG32_WR(baseAddr+CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_MAC_PRU1_0, macLo);
1391 CSL_REG32_WR(baseAddr+CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_MAC_PRU1_1, macHi);
1227 } 1392 }
1228 if(switch_port == EMAC_SWITCH_PORT2) 1393 if(switch_port == EMAC_SWITCH_PORT2)
1229 { 1394 {
1230 /* add mac */ 1395 /* add mac */
1396 baseAddr = emac_mcb.port_cb[1].icssDram0BaseAddr + CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_REGS_BASE;
1397
1231 CSL_REG32_WR(baseAddr+CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_MAC_PRU1_0, macLo); 1398 CSL_REG32_WR(baseAddr+CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_MAC_PRU1_0, macLo);
1232 CSL_REG32_WR(baseAddr+CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_MAC_PRU1_1, macHi); 1399 CSL_REG32_WR(baseAddr+CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_MAC_PRU1_1, macHi);
1400
1401 baseAddr = emac_mcb.port_cb[2].icssDram0BaseAddr + CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_REGS_BASE;
1402
1403 CSL_REG32_WR(baseAddr+CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_MAC_PRU0_0, macLo);
1404 CSL_REG32_WR(baseAddr+CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_MAC_PRU0_1, macHi);
1233 } 1405 }
1234 if(switch_port == EMAC_SWITCH_PORT0) /*host port*/ 1406 if(switch_port == EMAC_SWITCH_PORT0) /*host port*/
1235 { 1407 {
1236 baseAddr = emac_mcb.port_cb[0].icssDram0BaseAddr + CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_REGS_BASE; 1408 baseAddr = emac_mcb.port_cb[1].icssDram0BaseAddr + CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_REGS_BASE;
1237 /* add mac */ 1409 /* add mac */
1238 CSL_REG32_WR(baseAddr+CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_MAC_INTERFACE_0, macLo); 1410 CSL_REG32_WR(baseAddr+CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_MAC_INTERFACE_0, macLo);
1239 CSL_REG32_WR(baseAddr+CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_MAC_INTERFACE_1, macHi); 1411 CSL_REG32_WR(baseAddr+CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_MAC_INTERFACE_1, macHi);
1240 1412
1241 baseAddr = emac_mcb.port_cb[1].icssDram0BaseAddr + CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_REGS_BASE; 1413 baseAddr = emac_mcb.port_cb[2].icssDram0BaseAddr + CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_REGS_BASE;
1242 /* add mac */ 1414 /* add mac */
1243 CSL_REG32_WR(baseAddr+CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_MAC_INTERFACE_0, macLo); 1415 CSL_REG32_WR(baseAddr+CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_MAC_INTERFACE_0, macLo);
1244 CSL_REG32_WR(baseAddr+CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_MAC_INTERFACE_1, macHi); 1416 CSL_REG32_WR(baseAddr+CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_MAC_INTERFACE_1, macHi);
@@ -1484,5 +1656,41 @@ EMAC_DRV_ERR_E emac_ioctl_send_mgmt_msg(uint32_t port_num, EMAC_IOCTL_CMD_T* p_
1484 return retVal; 1656 return retVal;
1485} /* emac_ioctl_send_mgmt_msg */ 1657} /* emac_ioctl_send_mgmt_msg */
1486 1658
1659/*
1660 * ======== emac_ioctl_configure_fdb_ageing_interval ========
1661 */
1662EMAC_DRV_ERR_E emac_ioctl_configure_fdb_ageing_interval(uint32_t port_num, uint32_t switch_port, void* p_params)
1663{
1664 EMAC_DRV_ERR_E retVal = EMAC_DRV_RESULT_OK;
1665
1666 if((switch_port != EMAC_SWITCH_PORT1) && (switch_port != EMAC_SWITCH_PORT2))
1667 {
1668 retVal = EMAC_DRV_RESULT_INVALID_PORT;
1669 }
1670 if(retVal == EMAC_DRV_RESULT_OK)
1671 {
1672 uintptr_t fdbAgeingIntervalAddr;
1673 uint32_t numFDBBuckets =0;
1674
1675 EMAC_IOCTL_PARAMS *pParams = (EMAC_IOCTL_PARAMS*) p_params;
1676 EMAC_IOCTL_FDB_AGEING_INTERVAL *entry = (EMAC_IOCTL_FDB_AGEING_INTERVAL*)pParams->ioctlVal;
1677 EMAC_PER_PORT_ICSSG_FW_CFG *pEmacFwCfg;
1678 EMAC_ICSSG_SWITCH_FW_CFG *pSwitchFwCfg;
1679 if (emac_mcb.port_cb[port_num].getFwCfg)
1680 {
1681 emac_mcb.port_cb[port_num].getFwCfg(port_num,&pEmacFwCfg);
1682 pSwitchFwCfg = (EMAC_ICSSG_SWITCH_FW_CFG*) pEmacFwCfg->pFwPortCfg;
1683 /*Calculate number of buckets*/
1684 numFDBBuckets = pSwitchFwCfg->fdbSize / pSwitchFwCfg->numFdbBucketEntries;
1685
1686 fdbAgeingIntervalAddr = emac_mcb.port_cb[port_num].icssDram1BaseAddr + pSwitchFwCfg->fdbAgeingTimeoutOffset;
1687 /*The actual value written to memory is ageing timeout divided by number of buckets
1688 because in firmware we iterate per bucket not for entire FDB. See NRT design doc for more details*/
1689 CSL_REG64_WR(fdbAgeingIntervalAddr, entry->fdbAgeingInterval/(uint64_t)numFDBBuckets);
1690 }
1691 }
1692 return retVal;
1693}
1694
1487/* Nothing past this point */ 1695/* Nothing past this point */
1488 1696
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