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authorHao Zhang2016-06-08 12:48:12 -0500
committerHao Zhang2016-06-08 12:48:12 -0500
commitb7678fedf88a040c0558dd75d654d84027977019 (patch)
tree2c9044950271ac1374a4c65952316f2e2b027e0d
parentcd8add14f2fdc4f7af620d196ed43a162ac3af99 (diff)
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gpmc: PRSDK-51, PRSDK-52, PRSDK-53, PRSDK-54, PRSDK-55, PRSDK-58, PRSDK-59, PRSDK-60, PRSDK-61, PRSDK-63, to PRSDK-65, RSDK-72 of CATREQ-620
Create common GPMC driver and AM437x/AM335x SoC specific driver Signed-off-by: Hao Zhang <hzhang@ti.com>
Diffstat
-rwxr-xr-x[-rw-r--r--]GPMC.h191
-rwxr-xr-x[-rw-r--r--]config.bld17
-rwxr-xr-x[-rw-r--r--]package.xdc2
-rwxr-xr-xsoc/GPMC_soc.h48
-rw-r--r--soc/GPMC_v1.h208
-rwxr-xr-xsoc/am335x/GPMC_soc.c170
-rwxr-xr-x[-rw-r--r--]soc/am437x/GPMC_soc.c121
-rwxr-xr-x[-rw-r--r--]src/GPMC_drv.c44
-rwxr-xr-x[-rw-r--r--]src/Module.xs1
-rwxr-xr-x[-rw-r--r--]src/V1/GPMC_v1.c924
-rwxr-xr-xsrc/V1/GPMC_v1.h372
-rw-r--r--src/device/NAND.c1102
-rw-r--r--src/device/NAND.h437
-rw-r--r--src/hw_gpmc.h871
14 files changed, 1809 insertions, 2699 deletions
diff --git a/GPMC.h b/GPMC.h
index 49e8a33..9282285 100644..100755
--- a/GPMC.h
+++ b/GPMC.h
@@ -53,20 +53,107 @@ extern "C" {
53#include <stdbool.h> 53#include <stdbool.h>
54#include <stddef.h> 54#include <stddef.h>
55 55
56/*!
57 * Common GPMC_control command code reservation offset.
58 * GPMC driver implementations should offset command codes with GPMC_CMD_RESERVED
59 * growing positively
60 *
61 * Example implementation specific command codes:
62 * @code
63 * #define GPMCXYZ_COMMAND0 GPMC_CMD_RESERVED + 0
64 * #define GPMCXYZ_COMMAND1 GPMC_CMD_RESERVED + 1
65 * @endcode
66 */
67#define GPMC_CMD_RESERVED (32U)
68
69/*!
70 * Common GPMC_control status code reservation offset.
71 * GPMC driver implementations should offset status codes with
72 * GPMC_STATUS_RESERVED growing negatively.
73 *
74 * Example implementation specific status codes:
75 * @code
76 * #define GPMCXYZ_STATUS_ERROR0 GPMC_STATUS_RESERVED - 0
77 * #define GPMCXYZ_STATUS_ERROR1 GPMC_STATUS_RESERVED - 1
78 * #define GPMCXYZ_STATUS_ERROR2 GPMC_STATUS_RESERVED - 2
79 * @endcode
80 */
81#define GPMC_STATUS_RESERVED (-(32U))
82
83/*!
84 * \brief Successful status code returned by GPMC_control().
85 *
86 * GPMC_control() returns GPMC_STATUS_SUCCESS if the control code was executed
87 * successfully.
88 */
89#define GPMC_STATUS_SUCCESS (0U)
90
91/*!
92 * \brief Generic error status code returned by GPMC_control().
93 *
94 * GPMC_control() returns GPMC_STATUS_ERROR if the control code was not executed
95 * successfully.
96 */
97#define GPMC_STATUS_ERROR (-(1U))
98
99/*!
100 * \brief An error status code returned by GPMC_control() for undefined
101 * command codes.
102 *
103 * GPMC_control() returns GPMC_STATUS_UNDEFINEDCMD if the control code is not
104 * recognized by the driver implementation.
105 */
106#define GPMC_STATUS_UNDEFINEDCMD (-(2U))
107
108/*!
109 * @brief Wait forever define
110 */
111#define GPMC_WAIT_FOREVER (~(0U))
56 112
57#define GPMC_MAX_CONFIG_CNT 1 113/*!
114 * @brief Maximum GPMC config count
115 */
116#define GPMC_MAX_CONFIG_CNT (2U)
58/*! 117/*!
59 * @brief A handle that is returned from a GPMC_open() call. 118 * @brief A handle that is returned from a GPMC_open() call.
60 */ 119 */
61typedef struct GPMC_Config_s *GPMC_Handle; 120typedef struct GPMC_Config_s *GPMC_Handle;
62 121
122/*!
123 * @brief Type of the GPMC transaction.
124 */
125typedef enum GPMC_TransactionType_e {
126 GPMC_TRANSACTION_TYPE_READ = 0, /*!< Read transaction */
127 GPMC_TRANSACTION_TYPE_WRITE /*!< Write transaction */
128} GPMC_TransactionType;
129
130/*!
131 * @brief Status codes that are set by the GPMC driver.
132 */
133typedef enum GPMC_TransactionStatus_s {
134 GPMC_TRANSFER_COMPLETED = 0,
135 GPMC_TRANSFER_STARTED,
136 GPMC_TRANSFER_CANCELED,
137 GPMC_TRANSFER_FAILED,
138 GPMC_TRANSFER_CSN_DEASSERT
139
140} GPMC_TransactionStatus;
63 141
64/*! 142/*!
65 * @brief 143 * @brief
66 * A ::GPMC_Transaction data structure is used with GPMC_transfer(). 144 * A ::GPMC_Transaction data structure is used with GPMC_transfer().
67 */ 145 */
68typedef struct GPMC_Transaction_s { 146typedef struct GPMC_Transaction_s {
147 /* User input (write-only) fields */
148 GPMC_TransactionType transType; /*!< transaction type */
149 uint32_t offset; /*!< offset address of the memory device */
150 uint32_t count; /*!< Number of bytes for this transaction */
151 void *txBuf; /*!< void * to a buffer with data to be transmitted */
152 void *rxBuf; /*!< void * to a buffer to receive data */
153 void *arg; /*!< Argument to be passed to the callback function */
69 154
155 /* User output (read-only) fields */
156 GPMC_TransactionStatus status; /*!< Status code set by GPMC_transfer */
70 157
71} GPMC_Transaction; 158} GPMC_Transaction;
72 159
@@ -77,9 +164,32 @@ typedef struct GPMC_Transaction_s {
77 * @param GPMC_Handle GPMC_Handle 164 * @param GPMC_Handle GPMC_Handle
78 * @param GPMC_Transaction* GPMC_Transaction* 165 * @param GPMC_Transaction* GPMC_Transaction*
79 */ 166 */
80typedef void (*GPMC_CallbackFxn) (GPMC_Handle handle, 167typedef void (*GPMC_CallbackFxn)(GPMC_Handle handle,
81 GPMC_Transaction * transaction); 168 GPMC_Transaction * transaction);
82 169
170/*!
171 * @brief
172 *
173 * GPMC transfer mode determines the whether the GPMC controller operates
174 * synchronously or asynchronously. In ::GPMC_MODE_BLOCKING mode GPMC_transfer()
175 * blocks code execution until the GPMC transaction has completed. In
176 * ::GPMC_MODE_CALLBACK GPMC_transfer() does not block code execution and instead
177 * calls a ::GPMC_CallbackFxn callback function when the transaction has
178 * completed.
179 */
180typedef enum GPMC_TransferMode_s {
181 /*!
182 * GPMC_transfer() blocks execution. This mode can only be used when called
183 * within a Task context
184 */
185 GPMC_MODE_BLOCKING,
186 /*!
187 * GPMC_transfer() does not block code execution and will call a
188 * ::GPMC_CallbackFxn. This mode can be used in a Task, Swi, or Hwi context.
189 */
190 GPMC_MODE_CALLBACK
191
192} GPMC_TransferMode;
83 193
84/*! 194/*!
85 * @brief GPMC Parameters 195 * @brief GPMC Parameters
@@ -90,41 +200,47 @@ typedef void (*GPMC_CallbackFxn) (GPMC_Handle handle,
90 * @sa GPMC_Params_init() 200 * @sa GPMC_Params_init()
91 */ 201 */
92typedef struct GPMC_Params_s { 202typedef struct GPMC_Params_s {
93 GPMC_CallbackFxn transferCallbackFxn;/*!< Callback function pointer */ 203 GPMC_TransferMode transferMode; /*!< Blocking or Callback mode */
204 uint32_t transferTimeout; /*!< Transfer timeout in system
205 ticks (Not supported with all
206 implementations */
207 GPMC_CallbackFxn transferCallbackFxn; /*!< Callback function pointer */
94 208
95} GPMC_Params; 209} GPMC_Params;
96 210
97/*! 211/*!
98 * @brief A function pointer to a driver specific implementation of 212 * @brief A function pointer to a driver specific implementation of
99 * GPMC_close(). 213 * GPMC_init().
100 */ 214 */
101typedef void (*GPMC_CloseFxn) (GPMC_Handle handle); 215typedef void (*GPMC_InitFxn)(GPMC_Handle handle);
102 216
103/*! 217/*!
104 * @brief A function pointer to a driver specific implementation of 218 * @brief A function pointer to a driver specific implementation of
105 * GPMC_init(). 219 * GPMC_open().
106 */ 220 */
107typedef void (*GPMC_InitFxn) (GPMC_Handle handle); 221typedef GPMC_Handle (*GPMC_OpenFxn)(GPMC_Handle handle,
222 const GPMC_Params *params);
108 223
109/*! 224/*!
110 * @brief A function pointer to a driver specific implementation of 225 * @brief A function pointer to a driver specific implementation of
111 * GPMC_open(). 226 * GPMC_close().
112 */ 227 */
113typedef GPMC_Handle (*GPMC_OpenFxn) (GPMC_Handle handle, 228typedef void (*GPMC_CloseFxn)(GPMC_Handle handle);
114 const GPMC_Params *params);
115 229
116/*! 230/*!
117 * @brief A function pointer to a driver specific implementation of 231 * @brief A function pointer to a driver specific implementation of
118 * GPMC_serviceISR(). 232 * GPMC_transfer().
119 */ 233 */
120typedef void (*GPMC_ServiceISRFxn) (GPMC_Handle handle); 234typedef bool (*GPMC_TransferFxn)(GPMC_Handle handle,
235 GPMC_Transaction *transaction);
121 236
122/*! 237/*!
123 * @brief A function pointer to a driver specific implementation of 238 * @brief A function pointer to a driver specific implementation of
124 * GPMC_transfer(). 239 * GPMC_control().
125 */ 240 */
126typedef bool (*GPMC_TransferFxn) (GPMC_Handle handle, 241typedef int32_t (*GPMC_ControlFxn)(GPMC_Handle handle,
127 GPMC_Transaction *transaction); 242 uint32_t cmd,
243 void *arg);
128 244
129 245
130/*! 246/*!
@@ -133,20 +249,21 @@ typedef bool (*GPMC_TransferFxn) (GPMC_Handle handle,
133 * implementation. 249 * implementation.
134 */ 250 */
135typedef struct GPMC_FxnTable_s { 251typedef struct GPMC_FxnTable_s {
136 /*! Function to close the specified peripheral */
137 GPMC_CloseFxn closeFxn;
138
139 /*! Function to initialize the given data object */ 252 /*! Function to initialize the given data object */
140 GPMC_InitFxn initFxn; 253 GPMC_InitFxn initFxn;
141 254
142 /*! Function to open the specified peripheral */ 255 /*! Function to open the specified peripheral */
143 GPMC_OpenFxn openFxn; 256 GPMC_OpenFxn openFxn;
144 257
258 /*! Function to close the specified peripheral */
259 GPMC_CloseFxn closeFxn;
260
145 /*! Function to initiate a GPMC data transfer */ 261 /*! Function to initiate a GPMC data transfer */
146 GPMC_TransferFxn transferFxn; 262 GPMC_TransferFxn transferFxn;
147 263
148 /*! Function to service the GPMC instance */ 264 /*! Function to implementation specific control function */
149 GPMC_ServiceISRFxn serviceISRFxn; 265 GPMC_ControlFxn controlFxn;
266
150} GPMC_FxnTable; 267} GPMC_FxnTable;
151 268
152/*! 269/*!
@@ -165,10 +282,10 @@ typedef struct GPMC_Config_s {
165 GPMC_FxnTable const *fxnTablePtr; 282 GPMC_FxnTable const *fxnTablePtr;
166 283
167 /*! Pointer to a driver specific data object */ 284 /*! Pointer to a driver specific data object */
168 void *object; 285 void *object;
169 286
170 /*! Pointer to a driver specific hardware attributes structure */ 287 /*! Pointer to a driver specific hardware attributes structure */
171 void const *hwAttrs; 288 void const *hwAttrs;
172} GPMC_Config; 289} GPMC_Config;
173 290
174 291
@@ -214,14 +331,6 @@ extern GPMC_Handle GPMC_open(uint32_t index, GPMC_Params *params);
214extern void GPMC_Params_init(GPMC_Params *params); 331extern void GPMC_Params_init(GPMC_Params *params);
215 332
216/*! 333/*!
217 * @brief Function to service the GPMC module's interrupt service routine
218 *
219 *
220 * @param handle A GPMC_Handle
221 */
222extern void GPMC_serviceISR(GPMC_Handle handle);
223
224/*!
225 * @brief Function to perform GPMC transactions 334 * @brief Function to perform GPMC transactions
226 * 335 *
227 * @return true if started successfully; else false 336 * @return true if started successfully; else false
@@ -231,6 +340,26 @@ extern void GPMC_serviceISR(GPMC_Handle handle);
231 */ 340 */
232extern bool GPMC_transfer(GPMC_Handle handle, GPMC_Transaction *transaction); 341extern bool GPMC_transfer(GPMC_Handle handle, GPMC_Transaction *transaction);
233 342
343/*!
344 * @brief Function performs implementation specific features on a given
345 * GPMC_Handle.
346 *
347 * @pre GPMC_open() has to be called first.
348 *
349 * @param handle A GPMC handle returned from GPMC_open()
350 *
351 * @param cmd A command value defined by the driver specific
352 * implementation
353 *
354 * @param arg An optional R/W (read/write) argument that is
355 * accompanied with cmd
356 *
357 * @return Implementation specific return codes. Negative values indicate
358 * unsuccessful operations.
359 *
360 * @sa GPMC_open()
361 */
362extern int32_t GPMC_control(GPMC_Handle handle, uint32_t cmd, void *arg);
234 363
235#ifdef __cplusplus 364#ifdef __cplusplus
236} 365}
diff --git a/config.bld b/config.bld
index 0932b0e..ef60e27 100644..100755
--- a/config.bld
+++ b/config.bld
@@ -67,14 +67,14 @@ if(extDbgFlags_a15)
67/* ARMv7 A9 compiler configuration */ 67/* ARMv7 A9 compiler configuration */
68var A9LE = xdc.useModule('gnu.targets.arm.A9F'); 68var A9LE = xdc.useModule('gnu.targets.arm.A9F');
69A9LE.rootDir = a9ToolsBaseDir; 69A9LE.rootDir = a9ToolsBaseDir;
70A9LE.ccOpts.prefix = "-mno-unaligned-access -c -mtune=cortex-a9 -marm -DDRA7xx -DSOC_AM437X -gstrict-dwarf -Wall -D__ARMv7 -D_LITTLE_ENDIAN=1"; 70A9LE.ccOpts.prefix = "-mno-unaligned-access -c -mtune=cortex-a9 -marm -DDRA7xx -DSOC_AM437x -gstrict-dwarf -Wall -D__ARMv7 -D_LITTLE_ENDIAN=1";
71if(extDbgFlags_a9) 71if(extDbgFlags_a9)
72 A9LE.ccOpts.prefix = A9LE.ccOpts.prefix + " " + extDbgFlags_a9; 72 A9LE.ccOpts.prefix = A9LE.ccOpts.prefix + " " + extDbgFlags_a9;
73 73
74/* ARMv7 A8 compiler configuration */ 74/* ARMv7 A8 compiler configuration */
75var A8LE = xdc.useModule('gnu.targets.arm.A8F'); 75var A8LE = xdc.useModule('gnu.targets.arm.A8F');
76A8LE.rootDir = a8ToolsBaseDir; 76A8LE.rootDir = a8ToolsBaseDir;
77A8LE.ccOpts.prefix = "-mno-unaligned-access -c -mtune=cortex-a8 -marm -DDRA7xx -gstrict-dwarf -Wall -D__ARMv7 -D_LITTLE_ENDIAN=1"; 77A8LE.ccOpts.prefix = "-mno-unaligned-access -c -mtune=cortex-a8 -marm -DDRA7xx -DSOC_AM335x -gstrict-dwarf -Wall -D__ARMv7 -D_LITTLE_ENDIAN=1";
78if(extDbgFlags_a8) 78if(extDbgFlags_a8)
79 A8LE.ccOpts.prefix = A8LE.ccOpts.prefix + " " + extDbgFlags_a8; 79 A8LE.ccOpts.prefix = A8LE.ccOpts.prefix + " " + extDbgFlags_a8;
80 80
@@ -115,8 +115,19 @@ var socs = {
115 copts: " -DSOC_AM437x", 115 copts: " -DSOC_AM437x",
116 /* target list */ 116 /* target list */
117 targets: [ A9LE ] 117 targets: [ A9LE ]
118 } 118 },
119 119
120 am335x :
121 {
122 /* this variable would be reinitialized to true, if XDCARGS contains am335x */
123 build: "false",
124 /* SoC lib enabled */
125 socDevLib: "true",
126 /* Library options */
127 copts: " -DSOC_AM335x",
128 /* target list */
129 targets: [ A8LE ]
130 }
120}; 131};
121 132
122/************************************************************************** 133/**************************************************************************
diff --git a/package.xdc b/package.xdc
index c054676..e63f94a 100644..100755
--- a/package.xdc
+++ b/package.xdc
@@ -10,7 +10,7 @@
10 *****************************************************************************/ 10 *****************************************************************************/
11 11
12 12
13package ti.drv.gpmc[0, 0, 0, 0] { 13package ti.drv.gpmc[1, 0, 0, 0] {
14 module Settings; 14 module Settings;
15} 15}
16 16
diff --git a/soc/GPMC_soc.h b/soc/GPMC_soc.h
new file mode 100755
index 0000000..f107f6a
--- /dev/null
+++ b/soc/GPMC_soc.h
@@ -0,0 +1,48 @@
1/**
2 * @file GPMC_soc.h
3 *
4 * @brief GPMC SoC level driver
5 */
6/*
7 * Copyright (c) 2016, Texas Instruments Incorporated
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 *
14 * * Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 *
17 * * Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 *
21 * * Neither the name of Texas Instruments Incorporated nor the names of
22 * its contributors may be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
27 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
29 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
30 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
31 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
32 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
33 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
34 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
35 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37
38#include <ti/drv/gpmc/GPMC.h>
39#if defined(SOC_AM437x) || defined(SOC_AM335x) || defined(SOC_K2G)
40#include <ti/drv/gpmc/src/V1/GPMC_v1.h>
41#endif
42
43/* GPMC SoC level API */
44#if defined(SOC_AM437x) || defined(SOC_AM335x) || defined(SOC_K2G)
45extern int32_t GPMC_socGetInitCfg(uint32_t index, GPMC_v1_HwAttrs *cfg);
46extern int32_t GPMC_socSetInitCfg(uint32_t index, const GPMC_v1_HwAttrs *cfg);
47#endif
48
diff --git a/soc/GPMC_v1.h b/soc/GPMC_v1.h
deleted file mode 100644
index 08b4d3e..0000000
--- a/soc/GPMC_v1.h
+++ /dev/null
@@ -1,208 +0,0 @@
1/**
2 *
3 * \file GPMC_v1.h
4 *
5 * \brief This file contains the GPMC controller specific struct
6 * definition, macros and function prototypes.
7 *
8 ******************************************************************************/
9
10
11/*
12 * Copyright (c) 2016, Texas Instruments Incorporated
13 * All rights reserved.
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
17 * are met:
18 *
19 * * Redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer.
21 *
22 * * Redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution.
25 *
26 * * Neither the name of Texas Instruments Incorporated nor the names of
27 * its contributors may be used to endorse or promote products derived
28 * from this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
32 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
33 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
34 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
35 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
36 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
37 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
38 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
39 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
40 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 */
43
44
45
46#ifndef _GPMC_V1_H_
47#define _GPMC_V1_H_
48
49//#include <ti\drv\gpmc\src\nand_device.h>
50#include <ti/drv/gpmc/GPMC.h>
51/*****************************************************************************/
52/*
53** Macros which defines the number of NAND devices can be connected to system
54*/
55#define NAND_MAX_CHIP_SELECTS (4)
56
57/*****************************************************************************/
58/*
59** Macros which defines the ECC offset in OOB areaa, ecc byte count(size)
60** of diffrent ECC schemes.
61**
62*/
63#define NAND_ECC_1BIT_HAMMINGCODE_OOB_OFFSET (1)
64#define NAND_ECC_1BIT_HAMMINGCODE_BYTECNT (3)
65
66#define NAND_ECC_RS_4BIT_OOB_OFFSET (0)
67#define NAND_ECC_RS_4BIT_UNUSED_BYTECNT (6)
68#define NAND_ECC_RS_4BIT_BYTECNT (10)
69
70#define NAND_ECC_BCH_8BIT_OOB_OFFSET (2)
71#define NAND_ECC_BCH_8BIT_BYTECNT (14)
72#define NAND_ECC_BCH_8BIT_UNUSED_BYTECNT (2)
73#define NAND_ECC_BCH_8BIT_NIBBLECNT (26)
74
75/*****************************************************************************/
76/*
77** Macros which defines the last data and ecc bit in diffrent ECC schemes.
78**
79*/
80/* 512 bytes of data plus 13 bytes ECC */
81#define NAND_ECC_BCH_8BIT_LASTDATABIT ((512 + 13) * 8)
82/* 13 bytes of ECC data plus 1 byte of ECC for ECC data */
83#define NAND_ECC_BCH_8BIT_LASTECCBIT ((13 + 1) * 8)
84
85/*****************************************************************************/
86/*
87** Macro which defines the number of bytes sent/received per transfer.
88**
89*/
90#define NAND_BYTES_PER_TRNFS (512)
91#define NAND_MAX_ECC_BYTES_PER_TRNFS (16)
92
93
94/*****************************************************************************/
95/*
96** Macro which defines the values stored in OOB as bad block info.
97**
98*/
99#define NAND_BLK_GOOD_MARK (0xFF)
100#define NAND_BLK_BAD_MARK (0)
101
102/*
103** Macro which defines the shift value for chip select base address.
104*/
105#define NAND_BASE_ADDR_SHIFT (24)
106
107/*****************************************************************************/
108/*
109** Nand ECC alogorithm typedef
110**
111*/
112typedef enum GPMC_v1_nandEccAlgo
113{
114 GPMC_NAND_ECC_ALGO_NONE = (0x00),
115 GPMC_NAND_ECC_ALGO_HAMMING_1BIT = (0x01),
116 GPMC_NAND_ECC_ALGO_RS_4BIT = (0x02),
117 GPMC_NAND_ECC_ALGO_BCH_4BIT = (0x04),
118 GPMC_NAND_ECC_ALGO_BCH_8BIT = (0x08),
119 GPMC_NAND_ECC_ALGO_BCH_16BIT = (0x10)
120} GPMC_v1_nandEccAlgo_t;
121
122/*
123** Macros which can be used as 'busWidth' in NANDDevInfo structure.
124**
125*/
126typedef enum GPMC_v1_nandBusWidth
127{
128 GPMC_NAND_BUSWIDTH_INVALID = (0xFF),
129 GPMC_NAND_BUSWIDTH_8BIT = (0x00),
130 GPMC_NAND_BUSWIDTH_16BIT = (0x01)
131
132} GPMC_v1_nandBusWidth_t;
133
134
135
136/* Contains the controller information like ---
137** 1) chip select
138** 2) Location for data, command and address registers
139** 3) ECC supported by the controller and the default ecc to use.
140** 4) Wait pin onformation
141** 5) DMA related information and so on
142*/
143typedef struct GPMC_v1_nandCtrlInfo
144{
145 /* Timing info for the device and the controller */
146// nandTimingInfo_t nandTimingParams;
147 /* Base address of the controller */
148 unsigned int gpmcBaseAddress;
149 /* Wait pin where NAND dev R/B pin is connected */
150 unsigned int waitPin;
151 /* Wait pin polarity */
152 unsigned int waitPinPol;
153 /* Write protect pin polarity */
154 unsigned int wpPinPol;
155 /* Chip select base address */
156 unsigned int chipSelectBaseAddr[NAND_MAX_CHIP_SELECTS];
157 /* Chip select region size */
158 unsigned int chipSelectRegionSize[NAND_MAX_CHIP_SELECTS];
159 /* Curr chip select in use by the memory controller */
160 int currChipSelect;
161
162} GPMC_v1_nandCtrlInfo_t;
163
164
165typedef struct GPMC_v1_nandEccInfo
166{
167// elmHandle hElm; /* Base address of the ECC engine (ELM in GPMC for BCH ECC) */
168 unsigned int eccOffSet; /* Offset of the page from where ECC has to store.*/
169 unsigned int eccByteCnt; /* Total number of ecc bytes. */
170} GPMC_v1_nandEccInfo_t;
171
172
173/******************************************************************************
174* Structures to be passed to GPMC_soc
175******************************************************************************/
176
177/* GPMC function table pointer */
178extern const GPMC_FxnTable GPMC_v1_FxnTable;
179
180
181/*!
182 * @brief GPMC_v1 Object
183 *
184 * The application must not access any member variables of this structure!
185 */
186typedef struct GPMC_v1_Object_s {
187 /* GPMC OS specific objects */
188 void *commandMutex; /*! Grants exclusive access to GPMC */
189 void *transferMutex; /*! Grants exclusive access to GPMC */
190 void *commandComplete; /*! Notify finished GPMC command */
191 void *transferComplete; /*! Notify finished GPMC transfer */
192 void *hwi; /*! Hwi object */
193
194 uint32_t isOpen; /*! flag to indicate module is open */
195} GPMC_v1_Object;
196
197/*!
198 * @brief GPMC Hardware attributes
199 */
200typedef struct GPMC_v1_HwAttrs_s {
201 //GPMC_v1_nandCtrlInfo_t hGPMC_v1_nandCtrlInfo;
202 //GPMC_v1_nandEccInfo_t hGPMC_v1_nandEccInfo;
203 //GPMC_v1_nandEccAlgo_t eccType; /* ECC algorithm required by the NAND device */
204 //GPMC_v1_nandBusWidth_t busWidth; /* Bus width of the device. i,e 8 bit or 16 bit */
205} GPMC_v1_HwAttrs;
206
207
208#endif // _GPMC_V1_H_
diff --git a/soc/am335x/GPMC_soc.c b/soc/am335x/GPMC_soc.c
new file mode 100755
index 0000000..567b9df
--- /dev/null
+++ b/soc/am335x/GPMC_soc.c
@@ -0,0 +1,170 @@
1/**
2 * \file GPMC_soc.c
3 *
4 * \brief AM335x device specific hardware attributes.
5 *
6 */
7
8/*
9 * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 *
18 * Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the
21 * distribution.
22 *
23 * Neither the name of Texas Instruments Incorporated nor the names of
24 * its contributors may be used to endorse or promote products derived
25 * from this software without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 *
39 */
40
41#include <ti/csl/soc.h>
42#include <ti/drv/gpmc/GPMC.h>
43#include <ti/drv/gpmc/soc/GPMC_soc.h>
44
45#define CSL_GPMC_CNT (1U)
46
47#define CSL_GPMC_REG (0x50000000U)
48#define CSL_ELM_REG (0x48080000U)
49
50/* GPMC configuration structure */
51GPMC_v1_HwAttrs GPMCInitCfg[CSL_GPMC_CNT + 1] =
52{
53 {
54 CSL_GPMC_REG, /* gpmcBaseAddr */
55 GPMC_DEVICETYPE_NORLIKE, /* devType */
56 GPMC_DEVICESIZE_16BITS, /* devSize */
57 GPMC_MUXADDDATA_ADMUX, /* addrDataMux */
58 GPMC_TIMEPARAGRANULARITY_X1, /* timeLatency */
59 0, /* chipSel */
60 0x8000000U, /* chipSelBaseAddr */
61 GPMC_CS_SIZE_16MB, /* chipSelAddrSize */
62 132 + 32, /* intrNum */
63 0, /* eventId */
64 INVALID_INTC_MUX_NUM, /* intcMuxNum */
65 -1, /* intcMuxInEvent */
66 -1, /* intcMuxOutEvent */
67 false, /* intrEnable */
68 0, /* waitPinNum */
69 GPMC_WAIT_PIN_POLARITY_LOW, /* waitPinPol */
70 {
71 0U, /* csOnTime */
72 30U, /* csRdOffTime */
73 30U, /* csWrOffTime */
74 1U, /* advOnTime */
75 3U, /* advRdOffTime */
76 3U, /* advWrOffTime */
77 0U, /* advAadMuxOnTime */
78 0U, /* advAadMuxRdOffTime */
79 0U, /* advAadMuxWrOffTime */
80 13U, /* weOnTime */
81 28U, /* weOffTime */
82 5U, /* oeOnTime */
83 28U, /* oeOffTime */
84 0U, /* oeAadMuxOnTime */
85 0U, /* oeAadMuxOffTime */
86 0U, /* pageBurstAccessTime */
87 24U, /* rdAccessTime */
88 13U, /* wrAccessTime */
89 31U, /* rdCycleTime */
90 31U, /* wrCycleTime */
91 7U, /* wrDataOnMuxBusTime */
92 5U, /* cycle2CycleDelay */
93 GPMC_CYCLE2CYCLESAMECSEN_C2CDELAY, /* cycleDelaySameChipSel */
94 GPMC_CYCLE2CYCLEDIFFCSEN_NOC2CDELAY, /* cycleDelayDiffChipSel */
95 0U /* busTurnAroundTime */
96 },
97 CSL_ELM_REG, /* elmBaseAddr */
98 GPMC_NAND_ECC_ALGO_BCH_8BIT /* eccAlgo */
99 },
100};
101
102
103/* GPMC objects */
104GPMC_v1_Object GPMCObjects[CSL_GPMC_CNT + 1];
105
106
107/* GPMC configuration structure */
108const GPMC_config_list GPMC_config = {
109 {
110 &GPMC_FxnTable_v1,
111 &GPMCObjects[0],
112 &GPMCInitCfg[0]
113 },
114 {
115 NULL,
116 NULL,
117 NULL
118 }
119};
120
121/**
122 * \brief This API gets the SoC level of GPMC intial configuration
123 *
124 * \param index GPMC instance index.
125 * \param cfg Pointer to GPMC SOC initial config.
126 *
127 * \return 0 success: -1: error
128 *
129 */
130int32_t GPMC_socGetInitCfg(uint32_t index, GPMC_v1_HwAttrs *cfg)
131{
132 int32_t ret = 0;
133
134 if (index < CSL_GPMC_CNT)
135 {
136 *cfg = GPMCInitCfg[index];
137 }
138 else
139 {
140 ret = -1;
141 }
142
143 return ret;
144}
145
146/**
147 * \brief This API sets the SoC level of GPMC intial configuration
148 *
149 * \param index GPMC instance index.
150 * \param cfg Pointer to GPMC SOC initial config.
151 *
152 * \return 0 success: -1: error
153 *
154 */
155int32_t GPMC_socSetInitCfg(uint32_t index, const GPMC_v1_HwAttrs *cfg)
156{
157 int32_t ret = 0;
158
159 if (index < CSL_GPMC_CNT)
160 {
161 GPMCInitCfg[index] = *cfg;
162 }
163 else
164 {
165 ret = -1;
166 }
167
168 return ret;
169}
170
diff --git a/soc/am437x/GPMC_soc.c b/soc/am437x/GPMC_soc.c
index e09ceb4..204630d 100644..100755
--- a/soc/am437x/GPMC_soc.c
+++ b/soc/am437x/GPMC_soc.c
@@ -38,34 +38,133 @@
38 * 38 *
39 */ 39 */
40 40
41#include <ti/csl/soc.h>
41#include <ti/drv/gpmc/GPMC.h> 42#include <ti/drv/gpmc/GPMC.h>
42#include <ti/drv/gpmc/soc/GPMC_v1.h> 43#include <ti/drv/gpmc/soc/GPMC_soc.h>
43 44
44#define CSL_GPMC_PER_CNT 1U 45#define CSL_GPMC_CNT (1U)
46
47#define CSL_GPMC_REG (0x50000000U)
48#define CSL_ELM_REG (0x48080000U)
45 49
46/* GPMC configuration structure */ 50/* GPMC configuration structure */
47GPMC_v1_HwAttrs GPMCInitCfg[CSL_GPMC_PER_CNT] = 51GPMC_v1_HwAttrs GPMCInitCfg[CSL_GPMC_CNT + 1] =
48{ 52{
49/*
50 { 53 {
51 gpmcNandCtrlInfo_t ; 54 CSL_GPMC_REG, /* gpmcBaseAddr */
52 gpmcNandEccInfo_t; 55 GPMC_DEVICETYPE_NANDLIKE, /* devType */
53 gpmcNandEccAlgo_t ; 56 GPMC_DEVICESIZE_8BITS, /* devSize */
54 gpmcNandBusWidth_t; 57 GPMC_MUXADDDATA_NOMUX, /* addrDataMux */
58 GPMC_TIMEPARAGRANULARITY_X2, /* timeLatency */
59 0, /* chipSel */
60 0x10000000U, /* chipSelBaseAddr */
61 GPMC_CS_SIZE_256MB, /* chipSelAddrSize */
62 132 + 32, /* intrNum */
63 0, /* eventId */
64 INVALID_INTC_MUX_NUM, /* intcMuxNum */
65 -1, /* intcMuxInEvent */
66 -1, /* intcMuxOutEvent */
67 false, /* intrEnable */
68 0, /* waitPinNum */
69 GPMC_WAIT_PIN_POLARITY_LOW, /* waitPinPol */
70 {
71 0U, /* csOnTime */
72 7U, /* csRdOffTime */
73 7U, /* csWrOffTime */
74 0U, /* advOnTime */
75 0U, /* advRdOffTime */
76 7U, /* advWrOffTime */
77 0U, /* advAadMuxOnTime */
78 0U, /* advAadMuxRdOffTime */
79 0U, /* advAadMuxWrOffTime */
80 0U, /* weOnTime */
81 5U, /* weOffTime */
82 0U, /* oeOnTime */
83 5U, /* oeOffTime */
84 5U, /* oeAadMuxOnTime */
85 0U, /* oeAadMuxOffTime */
86 0U, /* pageBurstAccessTime */
87 6U, /* rdAccessTime */
88 6U, /* wrAccessTime */
89 7U, /* rdCycleTime */
90 7U, /* wrCycleTime */
91 7U, /* wrDataOnMuxBusTime */
92 0U, /* cycle2CycleDelay */
93 GPMC_CYCLE2CYCLESAMECSEN_NOC2CDELAY, /* cycleDelaySameChipSel */
94 GPMC_CYCLE2CYCLEDIFFCSEN_NOC2CDELAY, /* cycleDelayDiffChipSel */
95 0U /* busTurnAroundTime */
96 },
97 CSL_ELM_REG, /* elmBaseAddr */
98 GPMC_NAND_ECC_ALGO_BCH_8BIT /* eccAlgo */
55 }, 99 },
56*/
57}; 100};
58 101
59 102
60/* GPMC objects */ 103/* GPMC objects */
61GPMC_v1_Object GPMCObjects[CSL_GPMC_PER_CNT]; 104GPMC_v1_Object GPMCObjects[CSL_GPMC_CNT + 1];
62 105
63 106
64/* GPMC configuration structure */ 107/* GPMC configuration structure */
65const GPMC_config_list GPMC_config = { 108const GPMC_config_list GPMC_config = {
66 { 109 {
67 &GPMC_v1_FxnTable, 110 &GPMC_FxnTable_v1,
68 &GPMCObjects[0], 111 &GPMCObjects[0],
69 &GPMCInitCfg[0] 112 &GPMCInitCfg[0]
113 },
114 {
115 NULL,
116 NULL,
117 NULL
70 } 118 }
71}; 119};
120
121/**
122 * \brief This API gets the SoC level of GPMC intial configuration
123 *
124 * \param index GPMC instance index.
125 * \param cfg Pointer to GPMC SOC initial config.
126 *
127 * \return 0 success: -1: error
128 *
129 */
130int32_t GPMC_socGetInitCfg(uint32_t index, GPMC_v1_HwAttrs *cfg)
131{
132 int32_t ret = 0;
133
134 if (index < CSL_GPMC_CNT)
135 {
136 *cfg = GPMCInitCfg[index];
137 }
138 else
139 {
140 ret = -1;
141 }
142
143 return ret;
144}
145
146/**
147 * \brief This API sets the SoC level of GPMC intial configuration
148 *
149 * \param index GPMC instance index.
150 * \param cfg Pointer to GPMC SOC initial config.
151 *
152 * \return 0 success: -1: error
153 *
154 */
155int32_t GPMC_socSetInitCfg(uint32_t index, const GPMC_v1_HwAttrs *cfg)
156{
157 int32_t ret = 0;
158
159 if (index < CSL_GPMC_CNT)
160 {
161 GPMCInitCfg[index] = *cfg;
162 }
163 else
164 {
165 ret = -1;
166 }
167
168 return ret;
169}
170
diff --git a/src/GPMC_drv.c b/src/GPMC_drv.c
index 351cb44..c7d9ce8 100644..100755
--- a/src/GPMC_drv.c
+++ b/src/GPMC_drv.c
@@ -52,19 +52,12 @@ extern const GPMC_config_list GPMC_config;
52static int32_t GPMC_count = -1; 52static int32_t GPMC_count = -1;
53 53
54/* Default GPMC parameters structure */ 54/* Default GPMC parameters structure */
55const GPMC_Params GPMC_defaultParams = { 55const GPMC_Params GPMC_defaultParams =
56/* TBD */
57};
58
59/*
60 * ======== GPMC_close ========
61 */
62void GPMC_close(GPMC_Handle handle)
63{ 56{
64 OSAL_Assert(handle == NULL); 57 GPMC_MODE_BLOCKING, /* transferMode */
65 58 0U, /* transferTimeout */
66 handle->fxnTablePtr->closeFxn(handle); 59 NULL /* transferCallbackFxn */
67} 60};
68 61
69/* 62/*
70 * ======== GPMC_init ======== 63 * ======== GPMC_init ========
@@ -95,23 +88,23 @@ GPMC_Handle GPMC_open(uint32_t index, GPMC_Params *params)
95} 88}
96 89
97/* 90/*
98 * ======== GPMC_Params_init ======== 91 * ======== GPMC_close ========
99 */ 92 */
100void GPMC_Params_init(GPMC_Params *params) 93void GPMC_close(GPMC_Handle handle)
101{ 94{
102 OSAL_Assert(params == NULL); 95 OSAL_Assert(handle == NULL);
103 96
104 *params = GPMC_defaultParams; 97 handle->fxnTablePtr->closeFxn(handle);
105} 98}
106 99
107/* 100/*
108 * ======== GPMC_serviceISR ======== 101 * ======== GPMC_Params_init ========
109 */ 102 */
110void GPMC_serviceISR(GPMC_Handle handle) 103void GPMC_Params_init(GPMC_Params *params)
111{ 104{
112 OSAL_Assert(handle == NULL); 105 OSAL_Assert(params == NULL);
113 106
114 handle->fxnTablePtr->serviceISRFxn(handle); 107 *params = GPMC_defaultParams;
115} 108}
116 109
117/* 110/*
@@ -123,3 +116,14 @@ bool GPMC_transfer(GPMC_Handle handle, GPMC_Transaction *transaction)
123 116
124 return (handle->fxnTablePtr->transferFxn(handle, transaction)); 117 return (handle->fxnTablePtr->transferFxn(handle, transaction));
125} 118}
119
120/*
121 * ======== GPMC_control ========
122 */
123int32_t GPMC_control(GPMC_Handle handle, uint32_t cmd, void *arg)
124{
125 OSAL_Assert(handle == NULL);
126
127 return (handle->fxnTablePtr->controlFxn(handle, cmd, arg));
128}
129
diff --git a/src/Module.xs b/src/Module.xs
index 8c6d22b..07376a2 100644..100755
--- a/src/Module.xs
+++ b/src/Module.xs
@@ -16,7 +16,6 @@ var libUtility = xdc.loadCapsule ("../build/buildlib.xs");
16var gpmcSockLibFiles = [ 16var gpmcSockLibFiles = [
17 "src/GPMC_drv.c", 17 "src/GPMC_drv.c",
18 "src/v1/GPMC_v1.c", 18 "src/v1/GPMC_v1.c",
19 "src/device/NAND.c"
20]; 19];
21 20
22/************************************************************************** 21/**************************************************************************
diff --git a/src/V1/GPMC_v1.c b/src/V1/GPMC_v1.c
index 3a6008a..b2930a7 100644..100755
--- a/src/V1/GPMC_v1.c
+++ b/src/V1/GPMC_v1.c
@@ -7,7 +7,7 @@
7 */ 7 */
8 8
9/* 9/*
10 * Copyright (C) 2014-2015 Texas Instruments Incorporated - http://www.ti.com/ 10 * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/
11 * 11 *
12 * Redistribution and use in source and binary forms, with or without 12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions 13 * modification, are permitted provided that the following conditions
@@ -42,39 +42,113 @@
42#include <stdint.h> 42#include <stdint.h>
43#include <stddef.h> 43#include <stddef.h>
44#include <stdbool.h> 44#include <stdbool.h>
45#include <ti/drv/gpmc/GPMC.h> 45#include <ti/csl/hw_types.h>
46#include <ti/drv/gpmc/soc/GPMC_v1.h> 46#include <ti/drv/gpmc/src/V1/GPMC_v1.h>
47#include <ti/csl/src/ip/gpmc/v1/gpmc.h>
48#include <ti/drv/gpmc/src/GPMC_osal.h> 47#include <ti/drv/gpmc/src/GPMC_osal.h>
49 48
50/*#define WORD_INTERRUPT*/
51 49
52/* GPMC AM57x functions */ 50/* GPMC AM57x functions */
53static void GPMC_close_v1(GPMC_Handle handle); 51static void GPMC_init_v1(GPMC_Handle handle);
54static void GPMC_init_v1(GPMC_Handle handle);
55static GPMC_Handle GPMC_open_v1(GPMC_Handle handle, const GPMC_Params *params); 52static GPMC_Handle GPMC_open_v1(GPMC_Handle handle, const GPMC_Params *params);
53static void GPMC_close_v1(GPMC_Handle handle);
54static bool GPMC_transfer_v1(GPMC_Handle handle, GPMC_Transaction *transaction);
55static int32_t GPMC_control_v1(GPMC_Handle handle, uint32_t cmd, void *arg);
56 56
57/* GPMC function table for GPMC AM57x implementation */ 57/* GPMC function table for GPMC AM57x implementation */
58const GPMC_FxnTable GPMC_FxnTable_v1 = { 58const GPMC_FxnTable GPMC_FxnTable_v1 = {
59 &GPMC_close_v1,
60 &GPMC_init_v1, 59 &GPMC_init_v1,
61 &GPMC_open_v1, 60 &GPMC_open_v1,
61 &GPMC_close_v1,
62 &GPMC_transfer_v1,
63 &GPMC_control_v1
62}; 64};
63 65
64/* 66/*
65 * ======== GPMC_close_v1 ======== 67 * ======== GPMC_init_v1 ========
66 */ 68 */
67static void GPMC_close_v1(GPMC_Handle handle) 69static void GPMC_init_v1(GPMC_Handle handle)
68{ 70{
71 /* Input parameter validation */
72 OSAL_Assert(handle == NULL);
73
74 /* Mark the object as available */
75 ((GPMC_v1_Object *)(handle->object))->isOpen = (bool)false;
69 return; 76 return;
70} 77}
71 78
72/* 79/*
73 * ======== GPMC_init_v1 ======== 80 * ======== GPMC_transferCallback_v1 ========
74 */ 81 */
75static void GPMC_init_v1(GPMC_Handle handle) 82static void GPMC_transferCallback_v1(GPMC_Handle handle, GPMC_Transaction *msg)
76{ 83{
77 return; 84 GPMC_v1_Object *object; /* GPMC object */
85
86 /* Input parameter validation */
87 OSAL_Assert(handle == NULL);
88
89 /* Get the pointer to the object */
90 object = handle->object;
91
92 /* Indicate transfer complete */
93 GPMC_osalPostLock(object->transferComplete);
94}
95
96/*
97 * ======== GPMC_hwiFxn_v1 ========
98 * Hwi interrupt handler to service the GPMC peripheral
99 *
100 * The handler is a generic handler for a GPMC object.
101 */
102static void GPMC_hwiFxn_v1(uintptr_t arg)
103{
104 //GPMC_v1_Object *object = NULL;
105 GPMC_v1_HwAttrs const *hwAttrs = NULL;
106
107 /* Input parameter validation */
108 OSAL_Assert(NULL == (void *)arg);
109
110 /* Get the pointer to the object and hwAttrs */
111 //object = ((GPMC_Handle)arg)->object;
112 hwAttrs = ((GPMC_Handle)arg)->hwAttrs;
113
114 if (hwAttrs->intcMuxNum != INVALID_INTC_MUX_NUM)
115 {
116 GPMC_osalMuxIntcDisableHostInt(hwAttrs->intcMuxNum, hwAttrs->intcMuxOutEvent);
117 GPMC_osalMuxIntcClearSysInt(hwAttrs->intcMuxNum, hwAttrs->intcMuxInEvent);
118 }
119
120 /* TBD */
121
122 if (hwAttrs->intcMuxNum != INVALID_INTC_MUX_NUM)
123 {
124 GPMC_osalMuxIntcClearSysInt(hwAttrs->intcMuxNum, hwAttrs->intcMuxInEvent);
125 GPMC_osalHardwareIntrClear(hwAttrs->intrNum);
126 GPMC_osalMuxIntcEnableHostInt(hwAttrs->intcMuxNum, hwAttrs->intcMuxOutEvent);
127 }
128}
129
130static void GPMCIntDisableAll(baseAddr)
131{
132 GPMCIntDisable(baseAddr, GPMC_FIFOEVENT_INT);
133 GPMCIntDisable(baseAddr, GPMC_TERMINALCOUNT_INT);
134 GPMCIntDisable(baseAddr, GPMC_WAIT0EDGEDETECTION_INT);
135 GPMCIntDisable(baseAddr, GPMC_WAIT1EDGEDETECTION_INT);
136}
137
138static void GPMCIntEnableAll(baseAddr)
139{
140 GPMCIntEnable(baseAddr, GPMC_FIFOEVENT_INT);
141 GPMCIntEnable(baseAddr, GPMC_TERMINALCOUNT_INT);
142 GPMCIntEnable(baseAddr, GPMC_WAIT0EDGEDETECTION_INT);
143 GPMCIntEnable(baseAddr, GPMC_WAIT1EDGEDETECTION_INT);
144}
145
146static void GPMCIntClearAll(baseAddr)
147{
148 GPMCIntStatusClear(baseAddr, GPMC_FIFOEVENT_INT);
149 GPMCIntStatusClear(baseAddr, GPMC_TERMINALCOUNT_INT);
150 GPMCIntStatusClear(baseAddr, GPMC_WAIT0EDGEDETECTION_INT);
151 GPMCIntStatusClear(baseAddr, GPMC_WAIT1EDGEDETECTION_INT);
78} 152}
79 153
80/* 154/*
@@ -82,7 +156,829 @@ static void GPMC_init_v1(GPMC_Handle handle)
82 */ 156 */
83static GPMC_Handle GPMC_open_v1(GPMC_Handle handle, const GPMC_Params *params) 157static GPMC_Handle GPMC_open_v1(GPMC_Handle handle, const GPMC_Params *params)
84{ 158{
85 return handle; 159 SemaphoreP_Params semParams;
160 uint32_t key;
161 GPMC_v1_Object *object = NULL;
162 GPMC_v1_HwAttrs const *hwAttrs = NULL;
163 HwiP_Params hwiInputParams;
164 HwiP_Fxn hwiFxn;
165 MuxIntcP_inParams muxInParams;
166 MuxIntcP_outParams muxOutParams;
167 int32_t retFlag = 0U;
168 uint32_t timeConfig;
169
170 /* Input parameter validation */
171 OSAL_Assert(handle == NULL);
172
173 /* Get the pointer to the object and hwAttrs */
174 object = handle->object;
175 hwAttrs = handle->hwAttrs;
176
177 GPMC_osalHwiParamsInit(&hwiInputParams);
178
179 /* Determine if the device index was already opened */
180 key = GPMC_osalHardwareIntDisable();
181 if(object->isOpen == (bool)true)
182 {
183 GPMC_osalHardwareIntRestore(key);
184 handle = NULL;
185 }
186 else
187 {
188 /* Mark the handle as being used */
189 object->isOpen = (bool)true;
190 GPMC_osalHardwareIntRestore(key);
191
192 /* Store the GPMC parameters */
193 if (params == NULL)
194 {
195 /* No params passed in, so use the defaults */
196 GPMC_Params_init(&(object->gpmcParams));
197 }
198 else
199 {
200 /* Copy the params contents */
201 object->gpmcParams = *params;
202 }
203
204 /* Extract GPMC operating mode based on hwAttrs and input parameters */
205 if(GPMC_MODE_BLOCKING == object->gpmcParams.transferMode)
206 {
207 if(true == hwAttrs->intrEnable)
208 {
209 object->intrPollMode = GPMC_OPER_MODE_BLOCKING;
210 }
211 else
212 {
213 object->intrPollMode = GPMC_OPER_MODE_POLLING;
214 }
215 }
216 else
217 {
218 object->intrPollMode = GPMC_OPER_MODE_CALLBACK;
219 }
220
221 /* Extract the polling mode from hardware attributes. */
222 if(GPMC_OPER_MODE_POLLING != object->intrPollMode)
223 {
224 if (hwAttrs->intcMuxNum != INVALID_INTC_MUX_NUM)
225 {
226 /* Setup intc mux */
227 muxInParams.arg = (uintptr_t)handle;
228 muxInParams.muxNum = hwAttrs->intcMuxNum;
229 muxInParams.muxInEvent = hwAttrs->intcMuxInEvent;
230 muxInParams.muxOutEvent = hwAttrs->intcMuxOutEvent;
231 muxInParams.muxIntcFxn = (MuxIntcFxn)(&GPMC_hwiFxn_v1);
232 GPMC_osalMuxIntcSetup(&muxInParams, &muxOutParams);
233
234 hwiFxn = (HwiP_Fxn)muxOutParams.muxIntcFxn;
235 hwiInputParams.arg = muxOutParams.arg;
236 }
237 else
238 {
239 hwiFxn = (HwiP_Fxn)(&GPMC_hwiFxn_v1);
240 hwiInputParams.arg = (uintptr_t)handle;
241 }
242
243 /* Setup Hardware Interrupt Controller */
244 hwiInputParams.name = NULL;
245 hwiInputParams.priority = 0x20;
246#if defined (__ARM_ARCH_7A__)
247 hwiInputParams.evtId = 0; /* Event ID not used in GIC */
248 hwiInputParams.triggerSensitivity = 0x3; /* interrupt edge triggered */
249#else
250 hwiInputParams.evtId = hwAttrs->eventId;
251#endif
252 object->hwi = GPMC_osalRegisterInterrupt(hwAttrs->intrNum, hwiFxn, &hwiInputParams);
253
254 if(object->hwi == NULL)
255 {
256 GPMC_close_v1(handle);
257 handle = NULL;
258 retFlag = 1U;
259 }
260 }
261
262 if(retFlag == 0U)
263 {
264 /*
265 * Construct thread safe handles for this GPMC peripheral
266 * Semaphore to provide exclusive access to the GPMC peripheral
267 */
268 GPMC_osalSemParamsInit(&semParams);
269 semParams.mode = SemaphoreP_Mode_BINARY;
270 object->mutex = GPMC_osalCreateBlockingLock(1U, &semParams);
271
272 /*
273 * Store a callback function that posts the transfer complete
274 * semaphore for synchronous mode
275 */
276 if (object->intrPollMode == GPMC_OPER_MODE_BLOCKING)
277 {
278 /*
279 * Semaphore to cause the waiting task to block for the GPMC
280 * to finish
281 */
282 object->transferComplete = GPMC_osalCreateBlockingLock(0, &semParams);
283
284 /* Store internal callback function */
285 object->gpmcParams.transferCallbackFxn = &GPMC_transferCallback_v1;
286 }
287
288 if(object->intrPollMode == GPMC_OPER_MODE_CALLBACK)
289 {
290 /* Check to see if a callback function was defined for async mode */
291 OSAL_Assert(object->gpmcParams.transferCallbackFxn == NULL);
292 }
293
294 /* Reset GPMC */
295 GPMCModuleSoftReset(hwAttrs->gpmcBaseAddr);
296 while(!GPMCModuleResetStatusGet(hwAttrs->gpmcBaseAddr));
297 }
298
299 if(retFlag == 0U)
300 {
301 /* Set SYSCONFIG register to no idle mode */
302 GPMCIdleModeSelect(hwAttrs->gpmcBaseAddr, GPMC_IDLEMODE_NOIDLE);
303
304 /* Disable all interrupts */
305 GPMCIntDisableAll(hwAttrs->gpmcBaseAddr);
306
307 /* Timeout control disable */
308 GPMCTimeOutFeatureConfig(hwAttrs->gpmcBaseAddr, GPMC_TIMEOUTFEATURE_DISABLE);
309 GPMCTimeOutStartValSet(hwAttrs->gpmcBaseAddr, 0);
310
311 /* Set the wait pin polarity */
312 GPMCWaitPinSelect(hwAttrs->gpmcBaseAddr,
313 hwAttrs->chipSel,
314 hwAttrs->waitPinNum);
315 GPMCWaitPinPolaritySelect(hwAttrs->gpmcBaseAddr,
316 hwAttrs->waitPinNum,
317 hwAttrs->waitPinPol);
318
319 GPMCCSConfig(hwAttrs->gpmcBaseAddr, hwAttrs->chipSel, GPMC_CS_DISABLE);
320 GPMCTimeParaGranularitySelect(hwAttrs->gpmcBaseAddr,
321 hwAttrs->chipSel,
322 hwAttrs->timeLatency);
323
324 GPMCDevTypeSelect(hwAttrs->gpmcBaseAddr, hwAttrs->chipSel, hwAttrs->devType);
325
326 GPMCDevSizeSelect(hwAttrs->gpmcBaseAddr, hwAttrs->chipSel, hwAttrs->devSize);
327
328 GPMCAddrDataMuxProtocolSelect(hwAttrs->gpmcBaseAddr,
329 hwAttrs->chipSel,
330 hwAttrs->addrDataMux);
331
332 /* by default, read/write async single access */
333 GPMCReadTypeSelect(hwAttrs->gpmcBaseAddr,
334 hwAttrs->chipSel,
335 GPMC_READTYPE_ASYNC);
336 GPMCWriteTypeSelect(hwAttrs->gpmcBaseAddr,
337 hwAttrs->chipSel,
338 GPMC_WRITETYPE_ASYNC);
339
340 GPMCAccessTypeSelect(hwAttrs->gpmcBaseAddr,
341 hwAttrs->chipSel,
342 GPMC_MODE_READ,
343 GPMC_ACCESSTYPE_SINGLE);
344 GPMCAccessTypeSelect(hwAttrs->gpmcBaseAddr,
345 hwAttrs->chipSel,
346 GPMC_MODE_WRITE,
347 GPMC_ACCESSTYPE_SINGLE);
348
349 /* Set chip select address */
350 GPMCBaseAddrSet(hwAttrs->gpmcBaseAddr,
351 hwAttrs->chipSel,
352 hwAttrs->chipSelBaseAddr >> GPMC_CS_BASE_ADDR_SHIFT);
353 GPMCMaskAddrSet(hwAttrs->gpmcBaseAddr,
354 hwAttrs->chipSel,
355 hwAttrs->chipSelAddrSize);
356
357 /* CONFIG2 reister timing config, no extra delay */
358 timeConfig = GPMC_CS_TIMING_CONFIG(hwAttrs->timingParams.csWrOffTime,
359 hwAttrs->timingParams.csRdOffTime,
360 GPMC_CS_EXTRA_NODELAY,
361 hwAttrs->timingParams.csOnTime);
362 GPMCCSTimingConfig(hwAttrs->gpmcBaseAddr,
363 hwAttrs->chipSel,
364 timeConfig);
365
366 /* CONFIG3 reister timing config, no extra delay */
367 timeConfig = GPMC_ADV_TIMING_CONFIG(hwAttrs->timingParams.advAadMuxWrOffTime,
368 hwAttrs->timingParams.advAadMuxRdOffTime,
369 hwAttrs->timingParams.advWrOffTime,
370 hwAttrs->timingParams.advRdOffTime,
371 GPMC_ADV_EXTRA_NODELAY,
372 hwAttrs->timingParams.advAadMuxOnTime,
373 hwAttrs->timingParams.advOnTime);
374 GPMCADVTimingConfig(hwAttrs->gpmcBaseAddr,
375 hwAttrs->chipSel,
376 timeConfig);
377
378 /* CONFIG4 reister timing config, no extra delay */
379 timeConfig = GPMC_WE_OE_TIMING_CONFIG(hwAttrs->timingParams.weOffTime,
380 GPMC_WE_EXTRA_NODELAY,
381 hwAttrs->timingParams.weOnTtime,
382 hwAttrs->timingParams.oeAadMuxOffTime,
383 hwAttrs->timingParams.oeOffTime,
384 GPMC_OE_EXTRA_NODELAY,
385 hwAttrs->timingParams.oeAadMuxOnTime,
386 hwAttrs->timingParams.oeOnTime);
387 GPMCWEAndOETimingConfig(hwAttrs->gpmcBaseAddr,
388 hwAttrs->chipSel,
389 timeConfig);
390
391 /* CONFIG5 reister timing config */
392 timeConfig = GPMC_RDACCESS_CYCLETIME_TIMING_CONFIG(hwAttrs->timingParams.rdCycleTime,
393 hwAttrs->timingParams.wrCycleTime,
394 hwAttrs->timingParams.rdAccessTime,
395 hwAttrs->timingParams.pageBurstAccess);
396 GPMCRdAccessAndCycleTimeTimingConfig(hwAttrs->gpmcBaseAddr,
397 hwAttrs->chipSel,
398 timeConfig);
399
400 /* CONFIG6 reister timing config */
401 GPMCWrAccessAndWrDataOnADMUXBusTimingConfig(hwAttrs->gpmcBaseAddr,
402 hwAttrs->chipSel,
403 hwAttrs->timingParams.wrAcessTime,
404 hwAttrs->timingParams.wrDataOnMuxBusTime);
405
406 timeConfig = GPMC_CYCLE2CYCLE_BUSTURNAROUND_TIMING_CONFIG(hwAttrs->timingParams.cycle2CycleDelay,
407 hwAttrs->timingParams.cycleDelaySameChipSel,
408 hwAttrs->timingParams.cycleDelayDiffChipSel,
409 hwAttrs->timingParams.busTurnAroundTime);
410 GPMCycle2CycleAndTurnArndTimeTimingConfig(hwAttrs->gpmcBaseAddr,
411 hwAttrs->chipSel,
412 timeConfig);
413
414 GPMCCSConfig(hwAttrs->gpmcBaseAddr, hwAttrs->chipSel, GPMC_CS_ENABLE);
415 }
416 }
417 return(handle);
418}
419
420/*
421 * ======== GPMC_close_v1 ========
422 */
423static void GPMC_close_v1(GPMC_Handle handle)
424{
425 GPMC_v1_Object *object = NULL;
426 GPMC_v1_HwAttrs const *hwAttrs = NULL;
427
428 /* Input parameter validation */
429 OSAL_Assert(handle == NULL);
430
431 /* Get the pointer to the object and hwAttrs */
432 object = handle->object;
433 hwAttrs = handle->hwAttrs;
434
435 /* Mask I2C interrupts */
436 GPMCIntDisableAll(hwAttrs->gpmcBaseAddr);
437
438 /* Destruct the Hwi */
439 if(GPMC_OPER_MODE_POLLING != object->intrPollMode)
440 {
441 GPMC_osalHardwareIntDestruct(object->hwi);
442 }
443
444 /* Destruct the instance lock */
445 GPMC_osalDeleteBlockingLock(object->mutex);
446
447 /* Destruct the transfer completion lock */
448 if(GPMC_OPER_MODE_BLOCKING == object->intrPollMode)
449 {
450 GPMC_osalDeleteBlockingLock(object->transferComplete);
451 }
452
453 /* Open flag is set false */
454 object->isOpen = (bool)false;
455
456 return;
457}
458
459static void GPMC_ctrlNandReadData(GPMC_v1_HwAttrs const *hwAttrs,
460 uint8_t *pRxData,
461 uint32_t size)
462{
463 uint16_t *pData16 = (uint16_t *)pRxData;
464 uint8_t *pData8 = pRxData;
465
466 while(size > 0U)
467 {
468 if(hwAttrs->devSize == GPMC_DEVICESIZE_16BITS)
469 {
470 *pData16 = HW_RD_REG16(hwAttrs->gpmcBaseAddr + GPMC_NAND_DATA_N(hwAttrs->chipSel));
471 pData16++;
472 if (size == 1)
473 {
474 size = 0;
475 }
476 else
477 {
478 size -= 2;
479 }
480 }
481 else
482 {
483 *pData8 = HW_RD_REG8(hwAttrs->gpmcBaseAddr + GPMC_NAND_DATA_N(hwAttrs->chipSel));
484 pData8++;
485 size--;
486 }
487 }
488}
489
490static int32_t GPMC_nand_read_v1(GPMC_Handle handle,
491 const GPMC_Transaction *transaction)
492{
493 GPMC_v1_Object *object = NULL;
494 GPMC_v1_HwAttrs const *hwAttrs = NULL;
495 int32_t retVal = 0;
496
497 /* Input parameter validation */
498 OSAL_Assert(!((handle != NULL) && (transaction != NULL)));
499
500 object = handle->object;
501 hwAttrs = handle->hwAttrs;
502
503 if(GPMC_OPER_MODE_POLLING == object->intrPollMode)
504 {
505 GPMC_ctrlNandReadData(hwAttrs, object->readBufIdx,
506 object->readCountIdx);
507 }
508 else
509 {
510 }
511 return(retVal);
512}
513
514static int32_t GPMC_nor_read_v1(GPMC_Handle handle,
515 const GPMC_Transaction *transaction)
516{
517 GPMC_v1_Object *object = NULL;
518 GPMC_v1_HwAttrs const *hwAttrs = NULL;
519 uint16_t *pData16, *pAddr16;
520 uint8_t *pData8, *pAddr8;
521 uint32_t size;
522 int32_t retVal = 0;
523
524 /* Input parameter validation */
525 OSAL_Assert(!((handle != NULL) && (transaction != NULL)));
526
527 object = handle->object;
528 hwAttrs = handle->hwAttrs;
529
530 size = object->readCountIdx;
531 pData8 = (uint8_t *)(object->readBufIdx);
532 pAddr8 = (uint8_t *)(hwAttrs->chipSelBaseAddr + transaction->offset);
533 pData16 = (uint16_t *)(object->readBufIdx);
534 pAddr16 = (uint16_t *)(hwAttrs->chipSelBaseAddr + transaction->offset);
535
536 while(size > 0U)
537 {
538 if(hwAttrs->devSize == GPMC_DEVICESIZE_16BITS)
539 {
540 *pData16++ = *pAddr16++;
541 if (size == 1)
542 {
543 size = 0;
544 }
545 else
546 {
547 size -= 2;
548 }
549 }
550 else
551 {
552 *pData8++ = *pAddr8++;
553 size--;
554 }
555 }
556 return(retVal);
557}
558
559static void GPMC_ctrlNandWriteData(GPMC_v1_HwAttrs const *hwAttrs,
560 uint8_t *pTxData,
561 uint32_t size)
562{
563 uint16_t *pData16 = (uint16_t *)pTxData;
564 uint8_t *pData8 = pTxData;
565
566 while(size > 0U)
567 {
568 /* Check if writer buffer is empty */
569 while(!GPMCEmptyWriteBuffStatusGet(hwAttrs->gpmcBaseAddr));
570
571 if(hwAttrs->devSize == GPMC_DEVICESIZE_16BITS)
572 {
573 HW_WR_REG16(hwAttrs->gpmcBaseAddr + GPMC_NAND_DATA_N(hwAttrs->chipSel), *pData16);
574 pData16++;
575 if (size == 1)
576 {
577 size = 0;
578 }
579 else
580 {
581 size -= 2;
582 }
583 }
584 else
585 {
586 HW_WR_REG8(hwAttrs->gpmcBaseAddr + GPMC_NAND_DATA_N(hwAttrs->chipSel), *pData8);
587 pData8++;
588 size--;
589 }
590 }
591}
592
593static int32_t GPMC_nand_write_v1(GPMC_Handle handle,
594 const GPMC_Transaction *transaction)
595{
596 GPMC_v1_Object *object = NULL;
597 GPMC_v1_HwAttrs const *hwAttrs = NULL;
598 int32_t retVal = 0;
599
600 /* Input parameter validation */
601 OSAL_Assert(!((handle != NULL) && (transaction != NULL)));
602
603 object = handle->object;
604 hwAttrs = handle->hwAttrs;
605
606 if(GPMC_OPER_MODE_POLLING == object->intrPollMode)
607 {
608 GPMC_ctrlNandWriteData(hwAttrs, object->writeBufIdx,
609 object->writeCountIdx);
610 }
611 else
612 {
613 }
614 return(retVal);
615}
616
617static int32_t GPMC_nor_write_v1(GPMC_Handle handle,
618 const GPMC_Transaction *transaction)
619{
620 GPMC_v1_Object *object = NULL;
621 GPMC_v1_HwAttrs const *hwAttrs = NULL;
622 uint16_t *pData16, *pAddr16;
623 uint8_t *pData8, *pAddr8;
624 uint32_t size;
625 int32_t retVal = 0;
626
627 /* Input parameter validation */
628 OSAL_Assert(!((handle != NULL) && (transaction != NULL)));
629
630 object = handle->object;
631 hwAttrs = handle->hwAttrs;
632
633 size = object->writeCountIdx;
634 pData8 = (uint8_t *)(object->writeBufIdx);
635 pAddr8 = (uint8_t *)(hwAttrs->chipSelBaseAddr + transaction->offset);
636 pData16 = (uint16_t *)(object->writeBufIdx);
637 pAddr16 = (uint16_t *)(hwAttrs->chipSelBaseAddr + transaction->offset);
638
639 while(size > 0U)
640 {
641 if(hwAttrs->devSize == GPMC_DEVICESIZE_16BITS)
642 {
643 *pAddr16++ = *pData16++;
644 if (size == 1)
645 {
646 size = 0;
647 }
648 else
649 {
650 size -= 2;
651 }
652 }
653 else
654 {
655 *pAddr8++ = *pData8++;
656 size--;
657 }
658 }
659
660 return(retVal);
661}
662
663/*
664 * ======== GPMC_primeTransfer_v1 =======
665 */
666static int32_t GPMC_primeTransfer_v1(GPMC_Handle handle,
667 const GPMC_Transaction *transaction)
668{
669 GPMC_v1_Object *object = NULL;
670 GPMC_v1_HwAttrs const *hwAttrs = NULL;
671 int32_t retVal = 0;
672
673 /* Input parameter validation */
674 OSAL_Assert(!((handle != NULL) && (transaction != NULL)));
675
676 /* Get the pointer to the object and hwAttrs */
677 object = handle->object;
678 hwAttrs = handle->hwAttrs;
679
680 /* Disable and clear the interrupts */
681 GPMCIntDisableAll(hwAttrs->gpmcBaseAddr);
682 GPMCIntClearAll(hwAttrs->gpmcBaseAddr);
683
684 /* Interrupt mode */
685 if(object->intrPollMode != GPMC_OPER_MODE_POLLING)
686 {
687 GPMCIntEnableAll(hwAttrs->gpmcBaseAddr);
688 }
689
690 /* Identify the direction of transfer (whether read/write) */
691 if(transaction->rxBuf)
692 {
693 if(hwAttrs->devType == GPMC_DEVICETYPE_NANDLIKE)
694 {
695 retVal = GPMC_nand_read_v1(handle, transaction);
696 }
697 else if(hwAttrs->devType == GPMC_DEVICETYPE_NORLIKE)
698 {
699 retVal = GPMC_nor_read_v1(handle, transaction);
700 }
701 else
702 {
703 retVal = -1;
704 }
705 }
706 else if(transaction->txBuf)
707 {
708 if(hwAttrs->devType == GPMC_DEVICETYPE_NANDLIKE)
709 {
710 retVal = GPMC_nand_write_v1(handle, transaction);
711 }
712 else if(hwAttrs->devType == GPMC_DEVICETYPE_NORLIKE)
713 {
714 retVal = GPMC_nor_write_v1(handle, transaction);
715 }
716 else
717 {
718 retVal = -1;
719 }
720 }
721 else
722 {
723 retVal = -1;
724 }
725
726 return(retVal);
727}
728
729static bool GPMC_transfer_v1(GPMC_Handle handle, GPMC_Transaction *transaction)
730{
731 GPMC_v1_Object *object; /* GPMC object */
732 GPMC_v1_HwAttrs const *hwAttrs; /* GPMC hardware attributes */
733 bool ret = false; /* return value */
734
735 /* Input parameter validation */
736 OSAL_Assert(!((handle != NULL) && (transaction != NULL)));
737
738 /* Get the pointer to the object and hwAttrs */
739 object = handle->object;
740 hwAttrs = handle->hwAttrs;
741
742 /* Check if anything needs to be written or read */
743 if (0 != transaction->count)
744 {
745 /* Acquire the lock for this particular GPMC handle */
746 GPMC_osalPendLock(object->mutex, SemaphoreP_WAIT_FOREVER);
747
748 /* Book keeping of transmit and receive buffers. */
749 object->writeBufIdx = (uint8_t *)transaction->txBuf;
750 object->writeCountIdx = transaction->count;
751 object->readBufIdx = (uint8_t *)transaction->rxBuf;
752 object->readCountIdx = transaction->count;
753
754 /*
755 * GPMC_primeTransfer_v1 is a longer process and
756 * protection is needed from the GPMC interrupt
757 */
758 if (GPMC_OPER_MODE_POLLING != object->intrPollMode)
759 {
760 GPMC_osalHardwareIntrEnable(hwAttrs->intrNum);
761 }
762
763 if (GPMC_primeTransfer_v1(handle, transaction) == 0)
764 {
765 if (object->intrPollMode == GPMC_OPER_MODE_BLOCKING)
766 {
767 GPMC_osalPendLock(object->transferComplete, SemaphoreP_WAIT_FOREVER);
768
769 /* transfer is completed and semaphore is posted. */
770 }
771 else
772 {
773 /* Always return true if in Asynchronous mode */
774 }
775
776 ret = true;
777
778 /* Release the lock for this particular GPMC handle */
779 GPMC_osalPostLock(object->mutex);
780 }
781 }
782
783 /* Return the number of bytes transferred by the I2C */
784 return (ret);
785}
786
787static void GPMC_eccSizeSet(GPMC_v1_HwAttrs const *hwAttrs,
788 uint32_t *size)
789{
790 GPMCECCSizeValSet(hwAttrs->gpmcBaseAddr, GPMC_ECC_SIZE_0, size[0]);
791 GPMCECCSizeValSet(hwAttrs->gpmcBaseAddr, GPMC_ECC_SIZE_1, size[1]);
86} 792}
87 793
794static int32_t GPMC_control_v1(GPMC_Handle handle, uint32_t cmd, void *arg)
795{
796 GPMC_v1_HwAttrs const *hwAttrs; /* GPMC hardware attributes */
797 uint32_t *params = (uint32_t *)arg;
798 uint32_t dataAddr;
799 uint32_t dataSize;
800 int32_t retVal;
801
802 /* Input parameter validation */
803 OSAL_Assert(handle == NULL);
804
805 /* Get the pointer to the hwAttrs */
806 hwAttrs = handle->hwAttrs;
807
808 switch (cmd)
809 {
810 case GPMC_V1_CMD_GETDEVSIZE:
811 {
812 *params = hwAttrs->devSize;
813 retVal = GPMC_STATUS_SUCCESS;
814 break;
815 }
816
817 case GPMC_V1_CMD_GETDEVADDR:
818 {
819 *params = hwAttrs->chipSelBaseAddr;
820 retVal = GPMC_STATUS_SUCCESS;
821 break;
822 }
823
824 /* NAND device commands */
825 case GPMC_V1_CMD_SETNANDCMD:
826 {
827 HW_WR_REG8(hwAttrs->gpmcBaseAddr + GPMC_NAND_COMMAND_N(hwAttrs->chipSel),
828 (uint8_t)(*params));
829 retVal = GPMC_STATUS_SUCCESS;
830 break;
831 }
832
833 case GPMC_V1_CMD_SETNANDADDR:
834 {
835 HW_WR_REG8(hwAttrs->gpmcBaseAddr + GPMC_NAND_ADDRESS_N(hwAttrs->chipSel),
836 (uint8_t)(*params));
837 retVal = GPMC_STATUS_SUCCESS;
838 break;
839 }
840
841 case GPMC_V1_CMD_WRNANDDATA:
842 {
843 dataAddr = *params++;
844 dataSize = *params;
845
846 GPMC_ctrlNandWriteData(hwAttrs, (uint8_t *)dataAddr, dataSize);
847 retVal = GPMC_STATUS_SUCCESS;
848 break;
849 }
88 850
851 case GPMC_V1_CMD_RDNANDDATA:
852 {
853 dataAddr = *params++;
854 dataSize = *params;
855
856 GPMC_ctrlNandReadData(hwAttrs, (uint8_t *)dataAddr, dataSize);
857 retVal = GPMC_STATUS_SUCCESS;
858 break;
859 }
860
861 case GPMC_V1_CMD_GETWAITPINSTATUS:
862 {
863 *params = GPMCWaitPinStatusGet(hwAttrs->gpmcBaseAddr, hwAttrs->waitPinNum);
864 retVal = GPMC_STATUS_SUCCESS;
865 break;
866 }
867
868 case GPMC_V1_CMD_ECCCONTROL:
869 {
870 if (*params)
871 {
872 GPMCECCEnable(hwAttrs->gpmcBaseAddr);
873 }
874 else
875 {
876 GPMCECCDisable(hwAttrs->gpmcBaseAddr);
877 }
878 retVal = GPMC_STATUS_SUCCESS;
879 break;
880 }
881
882 case GPMC_V1_CMD_ECCGETINFO:
883 {
884 *params++ = hwAttrs->eccAlgo;
885 retVal = GPMC_STATUS_SUCCESS;
886 break;
887 }
888
889 case GPMC_V1_CMD_ECCSETSIZE:
890 {
891 GPMC_eccSizeSet(hwAttrs, params);
892 retVal = GPMC_STATUS_SUCCESS;
893 break;
894 }
895
896 case GPMC_V1_CMD_ECCGETRESULT:
897 {
898 uint32_t eccResIdx;
899
900 eccResIdx = *params++;
901 *params = GPMCECCResultGet(hwAttrs->gpmcBaseAddr, eccResIdx);
902 retVal = GPMC_STATUS_SUCCESS;
903 break;
904 }
905
906
907 case GPMC_V1_CMD_ECCGETBCHRESULT:
908 {
909 uint32_t eccResIdx;
910
911 eccResIdx = *params++;
912 *params = GPMCECCBCHResultGet(hwAttrs->gpmcBaseAddr,
913 eccResIdx, hwAttrs->chipSel);
914 retVal = GPMC_STATUS_SUCCESS;
915 break;
916 }
917
918 case GPMC_V1_CMD_ELMSETSYNDFRGMT:
919 {
920 uint32_t synFrgmtId = *params++;
921 uint32_t synFrgmtVal = *params;
922
923 elmSyndromeFrgmtSet(hwAttrs->elmBaseAddr, synFrgmtId,
924 synFrgmtVal, hwAttrs->chipSel);
925 retVal = GPMC_STATUS_SUCCESS;
926 break;
927 }
928
929 case GPMC_V1_CMD_ELMSTARTERRLOCPROC:
930 {
931 elmErrLocProcessingStart(hwAttrs->elmBaseAddr, hwAttrs->chipSel);
932 retVal = GPMC_STATUS_SUCCESS;
933 break;
934 }
935
936 case GPMC_V1_CMD_ELMGETINTSTATUS:
937 {
938 params[1] = elmIntStatusGet(hwAttrs->elmBaseAddr, params[0]);
939 retVal = GPMC_STATUS_SUCCESS;
940 break;
941 }
942
943 case GPMC_V1_CMD_ELMCLRINTSTATUS:
944 {
945 elmIntStatusClear(hwAttrs->elmBaseAddr, *params);
946 retVal = GPMC_STATUS_SUCCESS;
947 break;
948 }
949
950 case GPMC_V1_CMD_ELMGETERRLOCPROCSTATUS:
951 {
952 *params = elmErrLocProcessingStatusGet(hwAttrs->elmBaseAddr,
953 hwAttrs->chipSel);
954 retVal = GPMC_STATUS_SUCCESS;
955 break;
956 }
957
958 case GPMC_V1_CMD_ELMGETNUMERRS:
959 {
960 *params = elmNumOfErrsGet(hwAttrs->elmBaseAddr,
961 hwAttrs->chipSel);
962 retVal = GPMC_STATUS_SUCCESS;
963 break;
964 }
965
966 case GPMC_V1_CMD_ELMGETERRLOCADDR:
967 {
968 uint32_t errNum;
969
970 errNum = *params++;
971 *params = elmErrLocBitAddrGet(hwAttrs->elmBaseAddr,
972 errNum,
973 hwAttrs->chipSel);
974 retVal = GPMC_STATUS_SUCCESS;
975 break;
976 }
977
978 default:
979 retVal = GPMC_STATUS_UNDEFINEDCMD;
980 break;
981 }
982
983 return retVal;
984}
diff --git a/src/V1/GPMC_v1.h b/src/V1/GPMC_v1.h
new file mode 100755
index 0000000..1758ca9
--- /dev/null
+++ b/src/V1/GPMC_v1.h
@@ -0,0 +1,372 @@
1/**
2 *
3 * \file GPMC_v1.h
4 *
5 * \brief This file contains the GPMC controller specific struct
6 * definition, macros and function prototypes.
7 *
8 ******************************************************************************/
9
10
11/*
12 * Copyright (c) 2016, Texas Instruments Incorporated
13 * All rights reserved.
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
17 * are met:
18 *
19 * * Redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer.
21 *
22 * * Redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution.
25 *
26 * * Neither the name of Texas Instruments Incorporated nor the names of
27 * its contributors may be used to endorse or promote products derived
28 * from this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
32 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
33 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
34 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
35 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
36 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
37 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
38 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
39 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
40 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 */
43
44
45
46#ifndef _GPMC_V1_H_
47#define _GPMC_V1_H_
48
49#include <ti/csl/src/ip/gpmc/V1/gpmc.h>
50#include <ti/csl/src/ip/elm/V0/elm.h>
51#include <ti/drv/gpmc/GPMC.h>
52
53/*!
54 * \brief Get device size (bus width)
55 *
56 * Command code used with GPMC_control()
57 */
58#define GPMC_V1_CMD_GETDEVSIZE (GPMC_CMD_RESERVED + 0U)
59
60/*!
61 * \brief Get device chip select base address
62 *
63 * Command code used with GPMC_control()
64 */
65#define GPMC_V1_CMD_GETDEVADDR (GPMC_CMD_RESERVED + 1U)
66
67/* Below are NAND device commands */
68
69/*!
70 * \brief Set NAND command to GPMC controller
71 *
72 * Command code used with GPMC_control()
73 */
74#define GPMC_V1_CMD_SETNANDCMD (GPMC_CMD_RESERVED + 16U)
75
76/*!
77 * \brief Set NAND address to GPMC controller
78 *
79 * Command code used with GPMC_control()
80 */
81#define GPMC_V1_CMD_SETNANDADDR (GPMC_CMD_RESERVED + 17U)
82
83/*!
84 * \brief Write NAND DATA to GPMC controller
85 *
86 * Command code used with GPMC_control()
87 */
88#define GPMC_V1_CMD_WRNANDDATA (GPMC_CMD_RESERVED + 18U)
89
90/*!
91 * \brief Read NAND DATA from GPMC controller
92 *
93 * Command code used with GPMC_control()
94 */
95#define GPMC_V1_CMD_RDNANDDATA (GPMC_CMD_RESERVED + 19U)
96
97/*!
98 * \brief Get wait pin status from GPMC controller
99 *
100 * Command code used with GPMC_control()
101 */
102#define GPMC_V1_CMD_GETWAITPINSTATUS (GPMC_CMD_RESERVED + 20U)
103
104/*!
105 * \brief Enable or disable ECC
106 *
107 * Command code used with GPMC_control()
108 */
109#define GPMC_V1_CMD_ECCCONTROL (GPMC_CMD_RESERVED + 21U)
110
111/*
112 * \brief Get ECC configuration information
113 *
114 * Command code used with GPMC_control()
115 */
116#define GPMC_V1_CMD_ECCGETINFO (GPMC_CMD_RESERVED + 22U)
117
118/*!
119 * \brief Read/Write ECC size config
120 *
121 * Command code used with GPMC_control()
122 */
123#define GPMC_V1_CMD_ECCSETSIZE (GPMC_CMD_RESERVED + 23U)
124
125/*!
126 * \brief get ECC result
127 *
128 * Command code used with GPMC_control()
129 */
130#define GPMC_V1_CMD_ECCGETRESULT (GPMC_CMD_RESERVED + 24U)
131
132/*!
133 * \brief Get ECC BCH result
134 *
135 * Command code used with GPMC_control()
136 */
137#define GPMC_V1_CMD_ECCGETBCHRESULT (GPMC_CMD_RESERVED + 25U)
138
139/* Error Location Module commands */
140/*!
141 * \brief Sets the fragments of syndrome polynomial for
142 * error-location processing
143 *
144 * Command code used with GPMC_control()
145 */
146#define GPMC_V1_CMD_ELMSETSYNDFRGMT (GPMC_CMD_RESERVED + 32U)
147
148/*!
149 * \brief Start the error-location processing
150 *
151 * Command code used with GPMC_control()
152 */
153#define GPMC_V1_CMD_ELMSTARTERRLOCPROC (GPMC_CMD_RESERVED + 33U)
154
155/*!
156 * \brief Get the ELM interrupt status
157 *
158 * Command code used with GPMC_control()
159 */
160#define GPMC_V1_CMD_ELMGETINTSTATUS (GPMC_CMD_RESERVED + 34U)
161
162/*!
163 * \brief Clear the ELM interrupt status
164 *
165 * Command code used with GPMC_control()
166 */
167#define GPMC_V1_CMD_ELMCLRINTSTATUS (GPMC_CMD_RESERVED + 35U)
168
169/*!
170 * \brief Get the ELM error location processing status
171 *
172 * Command code used with GPMC_control()
173 */
174#define GPMC_V1_CMD_ELMGETERRLOCPROCSTATUS (GPMC_CMD_RESERVED + 36U)
175
176/*!
177 * \brief Get the number of errors
178 *
179 * Command code used with GPMC_control()
180 */
181#define GPMC_V1_CMD_ELMGETNUMERRS (GPMC_CMD_RESERVED + 37U)
182
183/*!
184 * \brief Get the ELM error location bit address
185 *
186 * Command code used with GPMC_control()
187 */
188#define GPMC_V1_CMD_ELMGETERRLOCADDR (GPMC_CMD_RESERVED + 38U)
189
190
191/*!
192 * \brief Macro which defines number of the shift bits
193 * of the chip select base address
194 */
195#define GPMC_CS_BASE_ADDR_SHIFT (0x18U)
196
197/*!
198 * \brief Macro which defines the invalid value of the interrupt mux number
199 */
200#define INVALID_INTC_MUX_NUM (0xffffU)
201
202/*!
203 * \brief GPMC operation modes
204 */
205typedef enum gpmcOperMode_s {
206 GPMC_OPER_MODE_BLOCKING,
207 GPMC_OPER_MODE_POLLING,
208 GPMC_OPER_MODE_CALLBACK
209} gpmcOperMode;
210
211/*!
212 * \brief Nand ECC alogorithm typedef
213 */
214typedef enum GPMC_v1_nandEccAlgo_s
215{
216 GPMC_NAND_ECC_ALGO_NONE = 0x00U,
217 GPMC_NAND_ECC_ALGO_HAMMING_1BIT,
218 GPMC_NAND_ECC_ALGO_BCH_4BIT,
219 GPMC_NAND_ECC_ALGO_BCH_8BIT,
220 GPMC_NAND_ECC_ALGO_BCH_16BIT
221
222} GPMC_v1_nandEccAlgo;
223
224
225/*!
226 * \brief Structure holding the timing parameters
227 */
228typedef struct GPMC_v1_timingParams
229{
230 uint32_t csOnTime;
231 /**< Chip Select assertion time. */
232 uint32_t csRdOffTime;
233 /**< Chip Select Read de-assertion time. */
234 uint32_t csWrOffTime;
235 /**< Chip Select Write de-assertion time. */
236 uint32_t advOnTime;
237 /**< ADV Assertion time. */
238 uint32_t advRdOffTime;
239 /**< ADV Read de-assertion time. */
240 uint32_t advWrOffTime;
241 /**< ADV Write de-assertion time. */
242 uint32_t advAadMuxOnTime;
243 /**< ADV Assertion time in an AADMultiplexed access. */
244 uint32_t advAadMuxRdOffTime;
245 /**< ADV Read de-assertion time in an AADMultiplexed access. */
246 uint32_t advAadMuxWrOffTime;
247 /**< ADV Write de-assertion time in an AADMultiplexed access. */
248 uint32_t weOnTtime;
249 /**< WE assertion time. */
250 uint32_t weOffTime;
251 /**< WE de-assertion time. */
252 uint32_t oeOnTime;
253 /**< OE assertion time. */
254 uint32_t oeOffTime;
255 /**< OE de-assertion time. */
256 uint32_t oeAadMuxOnTime;
257 /**< OE assertion time in an AADMultiplexed access. */
258 uint32_t oeAadMuxOffTime;
259 /**< OE de-assertion time in an AADMultiplexed access. */
260 uint32_t pageBurstAccess;
261 /**< Multiple access word delay. */
262 uint32_t rdAccessTime;
263 /**< Start-cycle to first valid delay. */
264 uint32_t wrAcessTime;
265 /**< Delay from StartAccessTime to the CLK rising edge. */
266 uint32_t rdCycleTime;
267 /**< Total read cycle time. */
268 uint32_t wrCycleTime;
269 /**< Total write cycle time. */
270 uint32_t wrDataOnMuxBusTime;
271 /**< Write Data on Mux Bus Time. */
272 uint32_t cycle2CycleDelay;
273 /**< Chip Select high pulse delay between two successive accesses. */
274 uint32_t cycleDelaySameChipSel;
275 /**< Value to control adding of cycle2cycle delay between two successive
276 accesses to the same chip select. */
277 uint32_t cycleDelayDiffChipSel;
278 /**< Value to control adding of cycle2cycle delay between two successive
279 accesses to the different chip select. */
280 uint32_t busTurnAroundTime;
281 /**< Bus turn around time between two successive
282 accesses to the same chip-select (read to write)
283 or to a different chip-select(read to read and read to write)
284 in GPMC_FCLK cycles. */
285} GPMC_v1_timingParams_t;
286
287
288/******************************************************************************
289* Structures to be passed to GPMC_soc
290******************************************************************************/
291
292/* GPMC function table pointer */
293extern const GPMC_FxnTable GPMC_FxnTable_v1;
294
295
296/*!
297 * @brief GPMC_v1 Object
298 *
299 * The application must not access any member variables of this structure!
300 */
301typedef struct GPMC_v1_Object_s {
302 /* GPMC OS specific objects */
303 void *mutex; /* instance lock */
304 void *transferComplete; /*! Transfer complete lock */
305 void *hwi; /*! Hwi object */
306 uint32_t waitTimeout; /* Wait time out count */
307 GPMC_Params gpmcParams; /* input parameters */
308 GPMC_TransactionType transType; /* Read or Write Transaction */
309 uint32_t intrPollMode; /* Interrupt or polling mode */
310 uint8_t *writeBufIdx; /* Internal inc. writeBuf index */
311 uint32_t writeCountIdx; /* Internal dec. writeCounter */
312 uint8_t *readBufIdx; /* Internal inc. readBuf index */
313 uint32_t readCountIdx; /* Internal dec. readCounter */
314 bool isOpen; /* flag to indicate module is open */
315
316} GPMC_v1_Object;
317
318/*!
319 * @brief GPMC Hardware attributes
320 */
321typedef struct GPMC_v1_HwAttrs_s {
322 /*! GPMC IP V1 Peripheral base address. */
323 uint32_t gpmcBaseAddr;
324 /*! device type, NAND or NOR like */
325 uint32_t devType;
326 /*! device size, 8-bit, 16-bit or 32-bit bus width */
327 uint32_t devSize;
328 /*! address and data multiplexed protocol */
329 uint32_t addrDataMux;
330 /*! Current Active chip select in use by the memory controller */
331 uint32_t timeLatency;
332 /*! Signals timing latencies scalar factor */
333 uint32_t chipSel;
334 /*! Chip select base address (A29 - A24) */
335 uint32_t chipSelBaseAddr;
336 /*! Chip select address mask size */
337 uint32_t chipSelAddrSize;
338 /*! GPMC IP V1 Peripheral CorePac interrupt vector */
339 uint32_t intrNum;
340 /*! GPMC IP V1 Peripheral CorePac intc event ID */
341 uint32_t eventId;
342 /*! interrupt controller mux number.
343 K2: CIC number
344 AM: Xbar instance number
345 -1: reserved for Resource Manager */
346 int32_t intcMuxNum;
347 /*! interrupt controller mux input event ID.
348 K2: CIC input event;
349 AM: Xbar mux input event;
350 -1: reserved for Resource Manager */
351 int32_t intcMuxInEvent;
352 /*! interrupt controller mux output event ID.
353 K2: host int num, output int from CIC;
354 AM: Xbar input index;
355 -1: reserved for Resource Manager */
356 int32_t intcMuxOutEvent;
357 /*! Enable GPMC interrupt. */
358 bool intrEnable;
359 /*! Wait pin Number to which the Ready/Busy pin is connected. */
360 uint32_t waitPinNum;
361 /*! Wait pin polarity */
362 uint32_t waitPinPol;
363 /*! Structure holding the timing parameters for the device. */
364 GPMC_v1_timingParams_t timingParams;
365 /*! Error Location Module base address for ECC computation. */
366 uint32_t elmBaseAddr;
367 /**< ECC algorithm supported by the controller. */
368 GPMC_v1_nandEccAlgo eccAlgo;
369
370} GPMC_v1_HwAttrs;
371
372#endif // _GPMC_V1_H_
diff --git a/src/device/NAND.c b/src/device/NAND.c
deleted file mode 100644
index b3844b0..0000000
--- a/src/device/NAND.c
+++ /dev/null
@@ -1,1102 +0,0 @@
1/*
2 * Copyright (c) 2016, Texas Instruments Incorporated
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 */
33
34/**
35 *
36 * \file NAND.c
37 *
38 * \brief This file contains nand functions.
39 *
40 *
41 ******************************************************************************/
42
43
44/*****************************************************************************
45 * Include Files
46 *****************************************************************************/
47#include <ti\drv\gpmc\src\device\NAND.h>
48#include <ti\drv\gpmc\src\hw_gpmc.h>
49
50/* UART Header files */
51#include <ti/drv/uart/UART.h>
52#include <ti/drv/uart/src/UART_osal.h>
53#include <ti/drv/uart/UART_stdio.h>
54
55
56
57/*****************************************************************************
58 * Globals
59 *****************************************************************************/
60static uint32_t nandErrNo = 0U;
61
62/*****************************************************************************
63 * Defines and Macros
64 *****************************************************************************/
65
66#ifndef IO_CONSOLE
67#define NAND_log UART_printf
68#else
69#define NAND_log printf
70#endif
71
72
73static uint8_t nandPageBuf[BYTES_PER_PAGE + SPARE_BYTES_PER_PAGE];
74
75#if (NAND_ECC_IN)
76
77// Both RBL and Linux offsets are set for 8-bit BCH ECC
78/*
79 * RBL ECC placement structure for each 512 byte block:
80 *
81 * 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
82 * Unused ECC0 ECC1 ECC2 ECC3 ECC4 ECC5 ECC6 ECC7 ECC8 ECC9 ECC10 ECC11 ECC12 Unused
83 */
84static const uint8_t rbl_eccLoc[4*NAND_MAX_NUM_ECC_BYTES] = {
85 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
86 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
87 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
88 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63
89};
90
91/*
92 * U-Boot ECC placement structure:
93 *
94 * The first 2 bytes are used for Bad block marker - 0xFFFF => Good block
95 * The next 'N' bytes is used for BCH bytes
96 *
97 * N = B * <Number of 512-byte sectors in a page>
98 *
99 * B = 8 bytes per 512 byte sector in BCH4
100 * B = 14 bytes per 512 byte sector in BCH8
101 * B = 26 bytes per 512 byte sector in BCH16
102 *
103 */
104static const uint8_t linux_eccLoc[4*NAND_MAX_NUM_ECC_BYTES] = {
105 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
106 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
107 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43,
108 44, 45, 46, 47, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59,
109};
110
111#endif // #if (NAND_ECC_IN)
112
113nandInfo_t gNandInfo;
114nandCtrlInfo_t gNandCtrlInfo;
115nandEccInfo_t gNandEccInfo;
116nandTimingInfo_t gNandTimingInfo;
117
118/*****************************************************************************
119 * Internal functions
120 *****************************************************************************/
121 void nandDelay(uint32_t );
122 void nandDelay(uint32_t uSeconds)
123 {
124 /* To be replaced with Timers */
125 uint32_t i = 0U;
126 uSeconds *= uSeconds;
127 while (i < uSeconds)
128 {
129 i++;
130 }
131 }
132
133/******************************************************************************
134 *
135 * Function: NAND_CmdSet
136 *
137 * Description: This function is used to indicate command cycle occurring
138 * and to send command to NAND device
139 *
140 * Parameters: uint32_t cmd - Command to NAND
141 *
142 * Return Value: None
143 *
144 *****************************************************************************/
145static void NAND_CmdSet(uint32_t cmd)
146{
147 uint16_t *cle_addr = (uint16_t *) NAND_CMD_ADDR;
148
149 *cle_addr = (uint16_t) cmd;
150}
151
152/******************************************************************************
153 *
154 * Function: NAND_AleSet
155 *
156 * Description: This function is used to indicate Address cycle occurring
157 * and to send address value to NAND device
158 *
159 * Parameters: uint32_t addr - Address to NAND
160 *
161 * Return Value: None
162 *
163 *****************************************************************************/
164static void NAND_AleSet(uint32_t addr)
165{
166 uint16_t *ale_addr = (uint16_t *) NAND_ALE_ADDR;
167
168 *ale_addr = (uint16_t) addr;
169
170 return;
171}
172
173/******************************************************************************
174 *
175 * Function: NAND_ProgAddr
176 *
177 * Description: This function is used to send the column, page and block
178 * address to the NAND device using NAND_AleSet
179 *
180 * Parameters: nandAddr_t addr - Address to NAND
181 *
182 * Return Value: None
183 *
184 *****************************************************************************/
185static void NAND_ProgAddr(nandAddr_t addr)
186{
187 /*
188 * Send address of the block + page to be read
189 * Address cycles = 5
190 */
191 NAND_AleSet((addr.nandColumnAddr >> 0u) & 0xFF); // CA0 -CA7 1st Cycle; Column addr
192 NAND_AleSet((addr.nandColumnAddr >> 8u) & 0x07); // CA8 -CA10 2nd Cycle; Column addr
193 NAND_AleSet(((addr.nandBlockAddr << 6u) & 0xC0) | // BA6 -BA7 3rd Cycle; Block addr
194 ((addr.nandPageAddr >> 0u) & 0x3F)); // PA0 -PA5 3rd Cycle; Page addr
195 NAND_AleSet((addr.nandBlockAddr >> 2u) & 0xFF); // BA8 -BA15 4th Cycle; Block addr
196 NAND_AleSet((addr.nandBlockAddr >> 10u) & 0x01); // BA16 5th Cycle; Block addr
197}
198
199/******************************************************************************
200 *
201 * Function: NAND_WaitRdy
202 *
203 * Description: This function waits for the NAND status to be ready
204 *
205 * Parameters: uint32_t in_timeout - time out value in micro seconds
206 *
207 * Return Value: Failure if Ready Pin is not high for prescribed time
208 *
209 *****************************************************************************/
210 static uint32_t NAND_WaitRdy(uint32_t in_timeout)
211 {
212 uint32_t count = 0;
213
214 do
215 {
216 nandDelay(1);
217
218 if (((nandWaitPinStatusGet(&gNandInfo)) & 1) == 1)
219 {
220 break;
221 }
222
223 count++;
224
225 } while (count < in_timeout);
226
227 if (count >= in_timeout)
228 {
229 return FAIL;
230 }
231 else
232 {
233 return SUCCESS;
234 }
235 }
236
237#if (NAND_READ_IN | NAND_WRITE_IN)
238
239 /******************************************************************************
240 *
241 * Function: NAND_ReadDataByte
242 *
243 * Description: This function is used to read Nand data byte
244 *
245 * Parameters: uint8_t* puchValue - Pointer to data buffer
246 *
247 * Return Value: None
248 *
249 *****************************************************************************/
250static void NAND_ReadDataByte(uint8_t* puchValue)
251 {
252 /*8-bit NAND*/
253 uint8_t *data_addr = (uint8_t *) NAND_DATA_ADDR;
254
255 *puchValue = *data_addr;
256 }
257
258 /******************************************************************************
259 *
260 * Function: NAND_ReadDataBytes
261 *
262 * Description: This function is used to read data bytes from the NAND device
263 *
264 * Parameters: uiNumBytes - Number of bytes to be read
265 * pBuffer - Data buffer
266 *
267 * Return Value: Error/Success codes
268 *
269 *****************************************************************************/
270 static uint32_t NAND_ReadDataBytes(uint32_t uiNumBytes, uint8_t *pBuffer)
271 {
272 uint32_t i;
273
274 /* 8-bit NAND */
275 for (i = 0; i < uiNumBytes; i++)
276 {
277 /* NANDRead done directly without checking for nand width */
278 NAND_ReadDataByte((uint8_t *)pBuffer);
279 pBuffer++;
280 }
281 return SUCCESS;
282 }
283
284 /******************************************************************************
285 *
286 * Function: NAND_ReadDataWord
287 *
288 * Description: This function is used to read Nand data word
289 *
290 * Parameters: uint16_t* pushValue - Pointer to data buffer
291 *
292 * Return Value: None
293 *
294 *****************************************************************************/
295 static void NAND_ReadDataWord(uint16_t* pushValue)
296 {
297 uint16_t *data_addr = (uint16_t *) NAND_DATA_ADDR;
298
299 *pushValue = *data_addr;
300 }
301
302 /******************************************************************************
303 *
304 * Function: NAND_ReadDataWords
305 *
306 * Description: This function is used to read data words from the NAND device
307 *
308 * Parameters: uiNumBytes - Number of bytes to be read
309 * pBuffer - Data buffer
310 *
311 * Return Value: Error/Success codes
312 *
313 *****************************************************************************/
314static uint32_t NAND_ReadDataWords(uint32_t uiNumBytes, uint16_t *pBuffer)
315{
316 uint32_t i;
317
318 for (i = 0; i < uiNumBytes/2; i++)
319 {
320 NAND_ReadDataWord(pBuffer);
321 pBuffer++;
322 }
323
324 return SUCCESS;
325}
326
327static uint32_t NAND_ReadData(PLATFORM_DEVICE_info *p_device, uint32_t uiNumBytes, uint8_t *pBuffer)
328{
329 uint16_t *ptrData;
330 uint32_t retVal;
331
332 if(p_device->width == 8)
333 {
334 /* 8-bit NAND */
335 retVal = NAND_ReadDataBytes(uiNumBytes, pBuffer);
336 }
337 else
338 {
339 /* 16-bit NAND */
340 ptrData = (uint16_t *)pBuffer;
341 retVal = NAND_ReadDataWords(uiNumBytes, ptrData);
342 }
343
344 return (retVal);
345}
346
347/******************************************************************************
348 *
349 * Function: NAND_ReadSpareArea
350 *
351 * Description: Function to read Nand spare area
352 *
353 * Parameters: nandBlkAddr - Block Address
354 * nandPage - Page Number
355 * pBuffer - Data Buffer
356 *
357 * Return Value: Error/Success codes
358 *
359 *****************************************************************************/
360uint32_t NAND_ReadSpareArea(PLATFORM_DEVICE_info *p_device, uint32_t nandBlkAddr, uint32_t nandPage, uint8_t *pBuffer)
361{
362 uint32_t ret_val = SUCCESS;
363 uint8_t status;
364 nandAddr_t address;
365
366
367 /* Read the data to the destination buffer and detect error */
368 address.nandColumnAddr = p_device->column;
369 address.nandPageAddr = nandPage;
370 address.nandBlockAddr = nandBlkAddr;
371
372 /* Send 0x50h command to read the spare area */
373 NAND_CmdSet(NAND_PAGE_READ); // First cycle send 0
374 nandDelay(10);
375
376 /* Send address */
377 NAND_ProgAddr(address);
378
379 NAND_CmdSet(0x30); // Last cycle send 30h command
380 nandDelay(NAND_WAIT_PIN_POLL_ST_DLY);
381
382 // Wait for Ready Busy Pin to go HIGH
383 ret_val = NAND_WaitRdy(NAND_PROG_TIMEOUT);
384
385 if (ret_val != SUCCESS) {
386 nandErrNo = NAND_ERRNO_DEV_BUSY;
387 NAND_log("NAND_ReadSpareArea: Device timeout.\n");
388 return FAIL;
389 }
390
391 /* Read the data to the destination buffer and detect error */
392 NAND_ReadData(p_device, p_device->spare_size, pBuffer);
393
394 NAND_CmdSet(NAND_STATUS);
395 nandDelay(10);
396 NAND_ReadDataByte(&status);
397
398 if ((status & 0x01) == 1) {
399 /* if SR0 bit is set to 1, there is Error - operation failed */
400 nandErrNo = NAND_ERRNO_DEV_FAIL;
401 NAND_log("NAND_ReadSpareArea: Status (0x%x) has error bit set.\n", status);
402 return FAIL;
403 }
404
405 return SUCCESS;
406}
407#endif
408
409
410 /******************************************************************************
411 *
412 * Function: NAND_ReadPage
413 *
414 * Description: This function reads a page from NAND flash and detects and
415 * corrects the bit errors if ECC is enabled
416 *
417 * Parameters: nandAddr_t address - Block Address/Page address of NAND flash
418 * uint8_t* puchBuffer - Pointer to buffer
419 *
420 * Return Value: status
421 *
422 * Assumptions: puchBuffer points to a 2KB buffer
423 *
424 ******************************************************************************/
425#if (NAND_READ_IN)
426uint32_t NAND_ReadPage(PLATFORM_DEVICE_info *p_device, nandAddr_t address, uint8_t* puchBuffer)
427{
428 int32_t i = 0;
429 int32_t index;
430 uint32_t byte_count;
431 uint8_t *puchSpareAreaBuf;
432 uint8_t *pBuffer_loc;
433 uint32_t ret_val = SUCCESS;
434 uint8_t status;
435
436#if (NAND_ECC_IN)
437 /* ECC locations for the micron nand device */
438 const uint8_t *eccLoc = (p_device->flags == NAND_FLAG_RBL) ? rbl_eccLoc : linux_eccLoc;
439 uint8_t eccCode[4*NAND_MAX_NUM_ECC_BYTES];
440#endif
441
442 if(puchBuffer == NULL)
443 return NULL_POINTER_ERROR;
444
445 pBuffer_loc = nandPageBuf;
446 puchSpareAreaBuf = nandPageBuf + BYTES_PER_PAGE;
447 ret_val = NAND_ReadSpareArea(p_device, address.nandBlockAddr, address.nandPageAddr, puchSpareAreaBuf);
448
449 if(ret_val != SUCCESS)
450 return FAIL;
451
452 nandDelay(10);
453
454 NAND_CmdSet(NAND_PAGE_READ);
455 nandDelay(10);
456
457 /* Send address */
458 NAND_ProgAddr(address);
459
460 NAND_CmdSet(0x30); // Last cycle send 30h command
461 nandDelay(NAND_WAIT_PIN_POLL_ST_DLY);
462
463 /* Wait for Ready Busy Pin to go HIGH */
464 ret_val = NAND_WaitRdy(NAND_PROG_TIMEOUT);
465
466 if(ret_val != SUCCESS) {
467 nandErrNo = NAND_ERRNO_DEV_TIMEOUT;
468 return FAIL;
469 }
470
471#if (NAND_ECC_IN)
472 nandECCReadSet(&gNandInfo);
473 nandECCDisable(&gNandInfo);
474#endif
475
476 for(byte_count = 0, index = 0; byte_count < p_device->page_size;
477 pBuffer_loc += ECC_BLOCK_SIZE, index++, byte_count += ECC_BLOCK_SIZE)
478 {
479#if (NAND_ECC_IN)
480 /* Start 4-bit ECC HW calculation for read */
481 nandECCEnable(&gNandInfo);
482#endif
483
484 /* Read the data to the destination buffer and detect error */
485 NAND_ReadData(p_device, ECC_BLOCK_SIZE, pBuffer_loc);
486 nandDelay(10);
487
488#if (NAND_ECC_IN)
489
490 /* Read Parity - read parity stored in spare NAND flash */
491 for(i = 0; i < NAND_MAX_NUM_ECC_BYTES; i++)
492 {
493 eccCode[i + (index * NAND_MAX_NUM_ECC_BYTES)] = puchSpareAreaBuf[eccLoc[i + (index * NAND_MAX_NUM_ECC_BYTES)]];
494 }
495
496 if(nandECCCheckAndCorrect(&gNandInfo, &eccCode[index * NAND_MAX_NUM_ECC_BYTES], pBuffer_loc) != NAND_STATUS_PASSED)
497 {
498 return FAIL;
499 }
500
501 nandECCDisable(&gNandInfo);
502#endif
503 }
504
505 NAND_CmdSet(NAND_STATUS);
506 nandDelay(10);
507
508 NAND_ReadDataByte(&status);
509
510 if ((status & 0x01) == 1) {
511 /* if SR0 bit is set to 1, there is Error - operation failed */
512 nandErrNo = NAND_ERRNO_DEV_FAIL;
513 return FAIL;
514 }
515
516 memcpy(puchBuffer, nandPageBuf, gDeviceNand.page_size);
517
518 return SUCCESS;
519}
520#endif
521
522 /******************************************************************************
523 *
524 * Function: NAND_WriteDataBytes
525 *
526 * Description: This function is used to write data bytes to the NAND device
527 *
528 * Parameters: uiNumBytes - Number of bytes to be written
529 * pBuffer - Data buffer
530 *
531 * Return Value: Error/Success codes
532 *
533 *****************************************************************************/
534
535#if (NAND_WRITE_IN)
536 static void NAND_WriteDataByte(uint8_t uchData)
537 {
538 volatile uint8_t* dest;
539
540 /* Data is written to the data register on the rising edge of WE# when
541 CE#, CLE, and ALE are LOW, and
542 the device is not busy. */
543 dest = (volatile uint8_t *)(NAND_DATA_ADDR);
544 *dest = uchData;
545 }
546
547uint32_t NAND_WriteDataBytes(uint32_t uiNumBytes, uint8_t *pBuffer)
548 {
549 uint32_t i;
550
551 for (i = 0; i < uiNumBytes; i++)
552 {
553 /* NAND Write done directly without checking for nand width */
554 NAND_WriteDataByte( (uint8_t) *pBuffer );
555 pBuffer++;
556 }
557
558 return SUCCESS;
559 }
560
561 static void NAND_WriteDataWord(uint16_t ushData)
562 {
563 volatile uint16_t* dest;
564
565 /* Data is written to the data register on the rising edge of WE# when
566 CE#, CLE, and ALE are LOW, and
567 the device is not busy. */
568 dest = (volatile uint16_t *)(NAND_DATA_ADDR);
569 *dest = ushData;
570 }
571
572 uint32_t NAND_WriteDataWords(uint32_t uiNumBytes, uint16_t *pBuffer)
573 {
574 uint32_t i;
575
576 for (i = 0; i < uiNumBytes/2; i++)
577 {
578 /* NAND Write done directly without checking for nand width */
579 NAND_WriteDataWord(*pBuffer);
580 pBuffer++;
581 }
582
583 return SUCCESS;
584 }
585
586uint32_t NAND_WriteData(PLATFORM_DEVICE_info *p_device, uint32_t uiNumBytes, uint8_t *pBuffer)
587{
588 uint16_t* pshData;
589 uint32_t retVal;
590
591 if (p_device->width == 8)
592 {
593 /* 8-bit NAND */
594 retVal = NAND_WriteDataBytes(uiNumBytes, pBuffer);
595 }
596 else
597 {
598 /* 16-bit NAND */
599 pshData = (uint16_t* )pBuffer;
600 retVal = NAND_WriteDataWords(uiNumBytes, pshData);
601 }
602
603 return (retVal);
604}
605
606#endif
607
608 /******************************************************************************
609 *
610 * Function: NAND_WritePage
611 *
612 * Description: This function a page to NAND flash. It computes ECC and
613 * and writes it to spare area if ECC is enabled
614 *
615 * Parameters: nandAddr_t address - Block Address/Page address of NAND flash
616 * uint8_t* puchBuffer - Pointer to buffer
617 *
618 * Return Value: status
619 *
620 * Assumptions: puchBuffer points to a 2KB buffer
621 *
622 ******************************************************************************/
623#if (NAND_WRITE_IN)
624 uint32_t NAND_WritePage(PLATFORM_DEVICE_info *p_device, nandAddr_t address, uint8_t* puchBuffer)
625 {
626 int32_t iErrors = SUCCESS;
627 int32_t i = 0;
628 uint32_t byte_count, index;
629 uint8_t puchSpareAreaBuf[SPARE_BYTES_PER_PAGE];
630 uint8_t *pBuffer_loc;
631 uint32_t ret_val = SUCCESS;
632 uint8_t status;
633
634#if (NAND_ECC_IN)
635 /* ECC locations for the Numonyx nand device */
636 const uint8_t *eccLoc = (p_device->flags == NAND_FLAG_RBL) ? rbl_eccLoc : linux_eccLoc;
637 uint8_t eccCalc[4*NAND_MAX_NUM_ECC_BYTES];
638#endif
639
640 /* Init the buffer by reading the existing values in the spare area */
641 iErrors = NAND_ReadSpareArea(p_device, address.nandBlockAddr, address.nandPageAddr, puchSpareAreaBuf);
642 if(iErrors != SUCCESS)
643 {
644 return iErrors;
645 }
646
647#if (NAND_ECC_IN)
648 nandECCWriteSet(&gNandInfo);
649 nandECCDisable(&gNandInfo);
650#endif
651
652 pBuffer_loc = puchBuffer;
653 for(byte_count = 0, index = 0; byte_count < p_device->page_size;
654 pBuffer_loc += ECC_BLOCK_SIZE, index++, byte_count += ECC_BLOCK_SIZE)
655 {
656 NAND_CmdSet(NAND_PROG_PAGE);
657 nandDelay(10);
658
659 address.nandColumnAddr = byte_count/2;
660 NAND_ProgAddr(address);
661 nandDelay(NAND_WAIT_PIN_POLL_ST_DLY);
662
663#if (NAND_ECC_IN)
664 /* Start ECC HW calculation for write */
665 nandECCEnable(&gNandInfo);
666 nandDelay (10);
667#endif
668
669 /* Write the data */
670 NAND_WriteData(p_device, ECC_BLOCK_SIZE, pBuffer_loc);
671
672 nandDelay (10);
673
674#if (NAND_ECC_IN)
675
676 /* Calculate the ECC bytes for write */
677 nandECCDisable(&gNandInfo);
678 nandECCCalculate(&gNandInfo, &eccCalc[index * NAND_MAX_NUM_ECC_BYTES]);
679
680 /* Update the calculated ECC bytes to spare area data */
681 for (i = 0; i < NAND_MAX_NUM_ECC_BYTES; i++)
682 {
683 puchSpareAreaBuf[eccLoc[i + (index * NAND_MAX_NUM_ECC_BYTES)]] = eccCalc[i + (index * NAND_MAX_NUM_ECC_BYTES)];
684 }
685
686#endif
687
688 /* Wait for Ready Busy Pin to go HIGH */
689 NAND_CmdSet(NAND_CMD_10H);
690
691 nandDelay(NAND_WAIT_PIN_POLL_ST_DLY);
692
693 ret_val = NAND_WaitRdy(NAND_PROG_TIMEOUT*50);
694
695 if (ret_val != SUCCESS) {
696 nandErrNo = NAND_ERRNO_DEV_TIMEOUT;
697 return FAIL;
698 }
699
700 NAND_CmdSet(NAND_STATUS);
701 nandDelay(10);
702
703 NAND_ReadDataByte(&status);
704
705 if ((status & 0x01) == 1) {
706 /* if SR0 bit is set to 1, there is Error - operation failed */
707 nandErrNo = NAND_ERRNO_DEV_FAIL;
708 return FAIL;
709 }
710 }
711
712 /* Write the spare data */
713 ret_val = NAND_WriteSpareArea(p_device, address.nandBlockAddr, address.nandPageAddr, puchSpareAreaBuf);
714
715 if (ret_val != SUCCESS)
716 return FAIL;
717
718 return SUCCESS;
719 }
720#endif
721
722 /******************************************************************************
723 *
724 * Function: NAND_WriteSpareArea
725 *
726 * Description: Function to write a spare area of the NAND
727 *
728 * Parameters: nandBlkAddr - Block Address
729 * nandPage - Page Number
730 * pBuffer - Data Buffer
731 *
732 * Return Value: Error/Success codes
733 *
734 *****************************************************************************/
735#if (NAND_WRITE_IN)
736uint32_t NAND_WriteSpareArea (PLATFORM_DEVICE_info *p_device, uint32_t nandBlkAddr, uint32_t nandPage, uint8_t *pBuffer)
737{
738 uint32_t ret_val = SUCCESS;
739 uint8_t status;
740 uint8_t *pBuffer_loc;
741 nandAddr_t address;
742
743 /* Read the data to the destination buffer and detect error */
744 address.nandColumnAddr = p_device->column;
745 address.nandPageAddr = nandPage;
746 address.nandBlockAddr = nandBlkAddr;
747
748 /* Spare Area*/
749 /*NAND_CmdSet(NAND_PAGE_READ);
750 nandDelay(20);*/
751 NAND_CmdSet(NAND_PROG_PAGE);
752 nandDelay(10);
753
754 /* Send address */
755 NAND_ProgAddr(address);
756 nandDelay (NAND_WAIT_PIN_POLL_ST_DLY);
757
758 /* Write the data */
759 pBuffer_loc = pBuffer;
760 NAND_WriteData(p_device, p_device->spare_size, (uint8_t *)pBuffer_loc);
761
762 /* Wait for Ready Busy Pin to go HIGH */
763 NAND_CmdSet(NAND_CMD_10H);
764
765 nandDelay(NAND_WAIT_PIN_POLL_ST_DLY);
766
767 ret_val = NAND_WaitRdy(NAND_PROG_TIMEOUT*50);
768
769 if (ret_val != SUCCESS) {
770 nandErrNo = NAND_ERRNO_DEV_TIMEOUT;
771 return FAIL;
772 }
773
774 NAND_CmdSet(NAND_STATUS);
775 nandDelay(10);
776
777 NAND_ReadDataByte(&status);
778
779 if ((status & 0x01) == 1) {
780 /* if SR0 bit is set to 1, there is Error - operation failed */
781 nandErrNo = NAND_ERRNO_DEV_FAIL;
782 return FAIL;
783 }
784
785 return SUCCESS;
786}
787#endif
788
789 /******************************************************************************
790 *
791 * Function: nandFlashBlockErase
792 *
793 * Description: This function erases the specified block of NAND flash
794 *
795 * Parameters: nandAddr_t address - Block Address of NAND flash
796 *
797 * Return Value: status
798 *
799 *****************************************************************************/
800#if (NAND_WRITE_IN)
801 uint32_t NAND_FlashBlockErase(PLATFORM_DEVICE_info *p_device, uint32_t nandBlockNumber)
802 {
803 uint32_t ret_val = SUCCESS;
804 uint8_t status;
805
806 NAND_CmdSet(NAND_BLOCK_ERASE); // Block erase command
807 nandDelay(25);
808
809 /*
810 * Send address of the block + page to be read
811 * Address cycles = 3
812 */
813
814 /* Properly adjust the shifts to match to the data sheet */
815
816 NAND_AleSet((nandBlockNumber << 6u) & 0xC0); // B0 -B1 1st Cycle; Block addr
817 nandDelay(25);
818 NAND_AleSet((nandBlockNumber >> 2u) & 0xFF); // B2 -B9 2nd Cycle; Block addr
819 nandDelay(25);
820 NAND_AleSet((nandBlockNumber >> 10u) & 0x01); // B10-B11 3rd Cycle; Block addr
821 nandDelay(1000);
822
823 NAND_CmdSet(NAND_ERASE_CONFIRM); // Erase confirm
824 nandDelay(NAND_WAIT_PIN_POLL_ST_DLY);
825
826 /* Wait for erase operation to finish: 2msec */
827 ret_val = NAND_WaitRdy(NAND_BLOCK_ERASE_TIMEOUT);
828
829 if (ret_val != SUCCESS) {
830 nandErrNo = NAND_ERRNO_DEV_TIMEOUT;
831 return FAIL;
832 }
833
834 NAND_CmdSet(NAND_STATUS);
835 nandDelay(10);
836
837 NAND_ReadDataByte(&status);
838
839 if ((status & 0x01) == 1) {
840 /* if SR0 bit is set to 1, there is Error - operation failed */
841 nandErrNo = NAND_ERRNO_DEV_FAIL;
842 return FAIL;
843 }
844
845 return SUCCESS;
846
847 }
848#endif
849
850/******************************************************************************
851* *
852* \brief Function to initalize the NAND timing info. *
853* *
854* \param nandTimimgInfo : Pointer to structure containing *
855* NAND timing info. *
856* *
857* \return none. *
858* *
859******************************************************************************/
860static void NAND_TimingInfoInit(nandTimingInfo_t *nandTimingInfo)
861{
862 nandTimingInfo->CSWrOffTime = NAND_CSWROFFTIME;
863 nandTimingInfo->CSRdOffTime = NAND_CSRDOFFTIME;
864 nandTimingInfo->CSExtDelayFlag = GPMC_CS_EXTRA_NODELAY;
865 nandTimingInfo->CSOnTime = NAND_CSONTIME;
866
867 nandTimingInfo->ADVAADMuxWrOffTime = NAND_ADVAADMUXWROFFTIME;
868 nandTimingInfo->ADVAADMuxRdOffTime = NAND_ADVAADMUXRDOFFTIME;
869 nandTimingInfo->ADVWrOffTime = NAND_ADVWROFFTIME;
870 nandTimingInfo->ADVRdOffTime = NAND_ADVRDOFFTIME;
871 nandTimingInfo->ADVExtDelayFlag = GPMC_ADV_EXTRA_NODELAY;
872 nandTimingInfo->ADVAADMuxOnTime = NAND_ADVAADMUXONTIME;
873 nandTimingInfo->ADVOnTime = NAND_ADVONTIME;
874
875 nandTimingInfo->WEOffTime = NAND_WEOFFTIME;
876 nandTimingInfo->WEExtDelayFlag = GPMC_WE_EXTRA_NODELAY;
877 nandTimingInfo->WEOnTime = NAND_WEONTIME;
878 nandTimingInfo->OEAADMuxOffTime = NAND_OEAADMUXOFFTIME;
879 nandTimingInfo->OEOffTime = NAND_OEOFFTIME;
880 nandTimingInfo->OEExtDelayFlag = GPMC_OE_EXTRA_NODELAY;
881 nandTimingInfo->OEAADMuxOnTime = NAND_OEAADMUXONTIME;
882 nandTimingInfo->OEOnTime = NAND_OEONTIME;
883
884 nandTimingInfo->rdCycleTime = NAND_RDCYCLETIME;
885 nandTimingInfo->wrCycleTime = NAND_WRCYCLETIME;
886 nandTimingInfo->rdAccessTime = NAND_RDACCESSTIME;
887 nandTimingInfo->pageBurstAccessTime = NAND_PAGEBURSTACCESSTIME;
888
889 nandTimingInfo->cycle2CycleDelay = NAND_CYCLE2CYCLEDELAY;
890 nandTimingInfo->cycle2CycleDelaySameCSCfg = NAND_CYCLE2CYCLESAMECSEN;
891 nandTimingInfo->cycle2CycleDelayDiffCSCfg = NAND_CYCLE2CYCLEDIFFCSEN;
892 nandTimingInfo->busTAtime = NAND_BUSTURNAROUND;
893
894 nandTimingInfo->wrAccessTime = NAND_WRACCESSTIME;
895 nandTimingInfo->wrDataOnADMux = NAND_WRDATAONADMUXBUS;
896}
897
898/******************************************************************************
899* *
900* \brief Function to initalize the NAND configuration info. *
901* *
902* \param nandTimimgInfo : Pointer to structure containing *
903* NAND timing info. *
904* *
905* \return none. *
906* *
907******************************************************************************/
908static void NAND_InfoInit(nandInfo_t *nandInfo)
909{
910 nandCtrlInfo_t *hNandCtrlInfo = nandInfo->hNandCtrlInfo;
911 nandEccInfo_t *hNandEccInfo = nandInfo->hNandEccInfo;
912
913 /* Init the NAND Device Info */
914 nandInfo->eccType = NAND_ECC_ALGO_BCH_8BIT;
915 nandInfo->chipSelectCnt = 1;
916 nandInfo->dieCnt = 1;
917 nandInfo->chipSelects[0] = NAND_CS;
918 nandInfo->busWidth = NAND_BUSWIDTH_16BIT;
919 nandInfo->pageSize = NAND_PAGESIZE_2048BYTES;
920 nandInfo->blkSize = NAND_BLOCKSIZE_128KB;
921 nandInfo->pagesPerBlk = PAGES_PER_BLOCK;
922
923 /* Init the NAND Controller Info struct */
924 hNandCtrlInfo->hNandTimingInfo = &gNandTimingInfo;
925 hNandCtrlInfo->hGpmc = (gpmcHandle)CSL_GPMC_0_CFG_REGS;
926 hNandCtrlInfo->waitPin = GPMC_WAIT_PIN0;
927 hNandCtrlInfo->waitPinPol = GPMC_WAIT_PIN_POLARITY_LOW;
928 hNandCtrlInfo->wpPinPol = GPMC_WP_PIN_LEVEL_HIGH;
929 hNandCtrlInfo->chipSelectBaseAddr[0] = NAND_CS0_BASEADDR;
930 hNandCtrlInfo->chipSelectRegionSize[0] = NAND_CS0_REGIONSIZE;
931 hNandCtrlInfo->currChipSelect = NAND_CS;
932
933 hNandEccInfo->hElm = (elmHandle)CSL_ELM_0_CFG_REGS;
934}
935
936 /******************************************************************************
937 *
938 * Function: NAND_Config
939 *
940 * Description: This function is used to congigure the NAND Device
941 *
942 * Parameters: None
943 *
944 * Return Value: Err Status
945 *
946 *****************************************************************************/
947static uint32_t NAND_Config ()
948{
949 nandStatus_t status;
950
951 /* Initialize NAND info */
952 NAND_Init(&gNandInfo);
953
954 /* Initialize NAND timing information */
955 NAND_TimingInfoInit(gNandCtrlInfo.hNandTimingInfo);
956
957 /* Initialize the controller */
958 status = nandCtrlInit(&gNandInfo);
959 if (status != NAND_STATUS_PASSED)
960 {
961 nandErrNo = NAND_ERRNO_DEV_FAIL;
962 NAND_log("NAND_Config ... Nand Controller Init Failed \n");
963 return FAIL;
964 }
965
966 return SUCCESS;
967}
968
969 /******************************************************************************
970 *
971 * Function: NAND_OpenDevice
972 *
973 * Description: This function is used to open the NAND device and configure it
974 *
975 * Parameters: None
976 *
977 * Return Value: Error/Success codes
978 *
979 *****************************************************************************/
980uint32_t NAND_Open(void)
981 {
982 uint8_t status;
983
984 /* Initialize NAND interface */
985 if (NAND_Config() != SUCCESS) {
986 NAND_log("NAND_OpenDevice ... could not initialize the Nand Interface. \n");
987 return FAIL;
988 }
989
990#if (NAND_ECC_IN)
991 /* Initialize ECC module */
992 if (nandECCInit(&gNandInfo) != NAND_STATUS_PASSED) {
993 NAND_log("nandECCInit ... could not initialize the Nand ECC Interface. \n");
994 return FAIL;
995 }
996#endif
997
998 /* Send reset command to NAND */
999 NAND_CmdSet(NAND_RST);
1000 nandDelay (NAND_WAIT_PIN_POLL_ST_DLY);
1001
1002 if (NAND_WaitRdy(NAND_RESET_TIMEOUT) != SUCCESS) {
1003 nandErrNo = NAND_ERRNO_DEV_TIMEOUT;
1004 NAND_log("NAND_OpenDevice ... Nand wait ready failed. \n");
1005 return FAIL;
1006 }
1007
1008 NAND_CmdSet(NAND_STATUS);
1009 nandDelay(10);
1010
1011 NAND_ReadDataByte(&status);
1012
1013 if ((status & 0x01) == 1) {
1014 /* if SR0 bit is set to 1, there is Error - operation failed */
1015 nandErrNo = NAND_ERRNO_DEV_FAIL;
1016 NAND_log("NAND_OpenDevice ... Nand status error bit was set. \n");
1017 return FAIL;
1018 }
1019
1020 return SUCCESS;
1021 }
1022
1023 /******************************************************************************
1024 *
1025 * Function: NAND_GetDetails
1026 *
1027 * Description: Get details of the NAND flash used from the id and the
1028 * table of NAND
1029 *
1030 * Parameters: pNandInfo - Pointer to Nand Info structure
1031 *
1032 * Return Value: Error/Success codes
1033 *
1034 *****************************************************************************/
1035 uint32_t NAND_GetDetails(PLATFORM_DEVICE_info *pNandInfo)
1036 {
1037 uint32_t i;
1038 uint32_t uiStatus;
1039 nandAddr_t address;
1040
1041 /* Clear the Information */
1042 pNandInfo->device_id = pNandInfo->manufacturer_id = 0x0;
1043
1044 /* Read manufacturer ID and device ID */
1045 NAND_CmdSet(NAND_RDID);
1046 nandDelay(10);
1047 NAND_AleSet(NAND_ADD_00H);
1048 nandDelay(10);
1049
1050 NAND_ReadDataWord((uint16_t *)&pNandInfo->manufacturer_id);
1051 NAND_ReadDataWord((uint16_t *)&pNandInfo->device_id);
1052
1053 /* Get the bad block table */
1054 address.nandPageAddr = 0;
1055 address.nandColumnAddr = 0;
1056
1057 for (i=0; i < BLOCKS_PER_DEVICE; i++) {
1058 address.nandBlockAddr = i;
1059
1060 /* Clear the Spare Area */
1061 memset(nandPageBuf, 0, SPARE_BYTES_PER_PAGE);
1062
1063 // Read the spare area in to buffer
1064 uiStatus = NAND_ReadSpareArea(pNandInfo, address.nandBlockAddr,
1065 address.nandPageAddr, nandPageBuf);
1066 if(uiStatus != SUCCESS) {
1067 return NAND_ERRNO_NANDBBT;
1068 }
1069 else { // Success in reading the NAND spare area
1070 if (nandPageBuf[pNandInfo->bboffset] == 0xFF) {
1071 pNandInfo->bblist[i] = 0xFF;
1072 } else {
1073 pNandInfo->bblist[i] = 0x00;
1074 }
1075 }
1076 }
1077 return SUCCESS;
1078 }
1079
1080 /******************************************************************************
1081 *
1082 * Function: nandInit
1083 *
1084 * Description: This function initialize the EMIF16 NAND flash controller.
1085 *
1086 * Parameters: None
1087 *
1088 * Return Value: status
1089 *
1090 ******************************************************************************/
1091uint32_t NAND_Init(void)
1092{
1093 uint32_t retVal;
1094
1095 gNandInfo.hNandCtrlInfo = &gNandCtrlInfo;
1096 gNandInfo.hNandEccInfo = &gNandEccInfo;
1097
1098 /* Open the NAND Device */
1099 retVal = NAND_Open();
1100
1101 return (retVal);
1102}
diff --git a/src/device/NAND.h b/src/device/NAND.h
deleted file mode 100644
index b424caa..0000000
--- a/src/device/NAND.h
+++ /dev/null
@@ -1,437 +0,0 @@
1/**
2 * \file NAND.h
3 *
4 * \brief Header file for GPMC NAND Flash driver.
5 *
6 */
7
8/*
9 * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 *
18 * Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the
21 * distribution.
22 *
23 * Neither the name of Texas Instruments Incorporated nor the names of
24 * its contributors may be used to endorse or promote products derived
25 * from this software without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 *
39 */
40
41#ifndef __NAND_H
42#define __NAND_H
43
44#ifdef __cplusplus
45extern "C" {
46#endif
47
48#include <stdint.h>
49#include <stddef.h>
50#include <stdbool.h>
51
52/* TI-RTOS Header files */
53#include <ti/drv/gpmc/GPMC.h>
54#include <ti/drv/gpmc/soc/GPMC_v1.h>
55
56
57/*********************************
58 * Defines and Macros and globals
59 *********************************/
60
61#define SUCCESS (0)
62#define FAIL (1)
63
64#define NAND_ERRNO_UNSUPPORTED 0x00000001 /**< Functionality not supported */
65
66#define NAND_ERRNO_ECC_FAIL 0x00000002 /**< The ECC calculation for the page read doesn't match. The application can try re-reading. */
67#define NAND_ERRNO_BADFLASHDEV 0x00000003 /**< The flash routines did no not recognize the flash manufacturer */
68#define NAND_ERRNO_FLASHADDR 0x00000004 /**< The block or page number specified does not exist for the Flash */
69#define NAND_ERRNO_NANDBBT 0x00000005 /**< Could not update the NAND Bad Block Table */
70#define NAND_ERRNO_NOFREEBLOCKS 0x00000006 /**< There were not enough consecutive free blocks to write the data (based on your starting block number)*/
71
72#define NAND_ERRNO_DEV_TIMEOUT 0x00000007 /**< There was an idle timeout waiting on a device action */
73#define NAND_ERRNO_DEV_FAIL 0x00000008
74
75/* NAND chip select ID */
76#define NAND_CS (0)
77
78/* NAND FLASH ADDRESS */
79#define NAND_CMD_ADDR (GPMC_CMD_REG(NAND_CS))
80#define NAND_ALE_ADDR (GPMC_ADDR_REG(NAND_CS))
81#define NAND_DATA_ADDR (GPMC_DATA_REG(NAND_CS))
82
83#define NAND_TYPE_MASK_0X00000020 (0x00000020)
84
85/* NAND FLASH COMMANDS */
86
87#define NAND_ADD_00H (0x00)
88#define NAND_ADD_08H (0x08)
89#define NAND_CMD_05H (0x05) /* Random Data Read Command */
90#define NAND_CMD_10H (0x10) /* Program Confirm Command */
91#define NAND_CMD_30H (0x30)
92#define NAND_CMD_E0H (0xE0)
93#define NAND_BLOCK_ERASE (0x60) /* Block Erase Command */
94#define NAND_ERASE_CONFIRM (0xD0) /* Erase Confirm Command */
95#define NAND_GET_FEATURES (0xEE)
96#define NAND_OTP_DATA_PROG (0xA0)
97#define NAND_OTP_DATA_PROT (0xA5)
98#define NAND_OTP_DATA_READ (0xAF)
99#define NAND_PAGE_READ (0x00) /* Page Read Command */
100#define NAND_PAGE_READ_LAST (0x3F) /* Page Read Cache Mode Start Last*/
101#define NAND_PAGE_READ_RANDOM (0x00)
102#define NAND_PAGE_READ_SEQUENTIAL (0x31) /* page Read Cache mode start */
103#define NAND_INT_DATA_MOVE_PROG (0x85) /* Program for Internal Data Move */
104#define NAND_PROG_PAGE (0x80) /* Program Page Command */
105#define NAND_PROG_PAGE_CACHE (0x80) /* Program Page command */
106#define NAND_RANDOM_DATA_IN (0x85) /* Program for internal Data Move */
107#define NAND_RANDOM_DATA_READ (0x05)
108#define NAND_INT_DATA_MOVE_READ (0xA5)
109#define NAND_RDID (0x90) /* Read NAND ID Command */
110#define NAND_READ_PARAM_PAGE (0xEC)
111#define NAND_STATUS (0x70) /* Read Status command */
112#define NAND_READ_UNIQUE_ID (0xED)
113#define NAND_RST (0xFF) /* Reset Command */
114#define NAND_RDY (0x40)
115#define NAND_RDIDADD (0x20)
116
117/* Maximum number of ECC bytes per page */
118#define NAND_MAX_NUM_ECC_BYTES (NAND_ECC_BCH_8BIT_BYTECNT)
119
120 /**
121 @}
122 */
123/****************
124 * Defines
125 ****************/
126#define PACK_ADDR(col, page, block) \
127 ((col & 0x00000fff) | ((page & 0x0000003f)<<16) | ((block & 0x000003ff) << 22 ))
128
129// Macros for delay in micro Sec
130#define STD_DELAY (25)
131#define NAND_PROG_TIMEOUT (100000)
132#define NAND_RESET_TIMEOUT (100000)
133#define NAND_BLOCK_ERASE_TIMEOUT (2000000)
134#define NAND_WAIT_PIN_POLL_ST_DLY (10)
135
136
137// Macros for errors
138#define INVALID_NAND_ADDR (8)
139#define NAND_PAGE_WRITE_FAIL (9)
140#define NAND_SPARE_AREA_WRITE_FAIL (10)
141#define NAND_PAGE_READ_FAIL (11)
142#define NAND_SPARE_AREA_READ_FAIL (12)
143#define NAND_BLOCK_ERASE_FAIL (13)
144#define NAND_ID_READ_ERROR (14)
145#define NAND_TWO_BIT_ERROR (15)
146#define INVALID_NAND_DEVICE (16)
147
148#define NAND_MAN_ID_MICRON (0x2C)
149#define NAND_DEVICE_ID (0xCA)
150
151#define BYTES_PER_PAGE (2048)
152#define SPARE_BYTES_PER_PAGE (64)
153#define PAGES_PER_BLOCK (64)
154#define TOTAL_BYTES_PER_PAGE (BYTES_PER_PAGE + SPARE_BYTES_PER_PAGE)
155#define BLOCKS_PER_DEVICE (2048)
156
157// ECC related macros
158#define ECC_BLOCK_SIZE (512) // in Bytes
159#define ECC_SPARE_OFFSET (SPARE_BYTES_PER_PAGE/(BYTES_PER_PAGE/ECC_BLOCK_SIZE))
160
161// NAND flags
162#define NAND_FLAG_LINUX (0x0)
163#define NAND_FLAG_RBL (0x1)
164
165/*
166** Macros which defines the chip select base address and cs region size.
167**
168*/
169#define NAND_CS0_BASEADDR (0x4000000)//(0x10000000)
170#define NAND_CS0_REGIONSIZE (GPMC_CS_SIZE_64MB)//(GPMC_CS_SIZE_256MB)
171
172/*
173** Macros which defines the NAND timing info.
174**
175*/
176#define NAND_CSWROFFTIME (20)
177#define NAND_CSRDOFFTIME (20)
178#define NAND_CSONTIME (0)
179
180#define NAND_ADVONTIME (0)
181#define NAND_ADVAADMUXONTIME (0)
182#define NAND_ADVRDOFFTIME (20)
183#define NAND_ADVWROFFTIME (20)
184#define NAND_ADVAADMUXRDOFFTIME (0)
185#define NAND_ADVAADMUXWROFFTIME (0)
186
187#define NAND_WEOFFTIME (15)
188#define NAND_WEONTIME (1)
189#define NAND_OEAADMUXOFFTIME (0)
190#define NAND_OEOFFTIME (15)
191#define NAND_OEAADMUXONTIME (0)
192#define NAND_OEONTIME (1)
193
194#define NAND_RDCYCLETIME (20)
195#define NAND_WRCYCLETIME (20)
196#define NAND_RDACCESSTIME (12)
197#define NAND_PAGEBURSTACCESSTIME (1)
198
199#define NAND_BUSTURNAROUND (0)
200#define NAND_CYCLE2CYCLEDIFFCSEN (0)
201#define NAND_CYCLE2CYCLESAMECSEN (1)
202#define NAND_CYCLE2CYCLEDELAY (10)
203#define NAND_WRDATAONADMUXBUS (15)
204#define NAND_WRACCESSTIME (31)
205
206
207/*****************************************************************************/
208/*
209** nandStatus typedef - returned from most nandLib APIs
210**
211*/
212typedef enum nandStatus
213{
214 NAND_STATUS_PASSED = (0x001),
215 NAND_STATUS_FAILED = (0x002),
216 NAND_STATUS_NOT_FOUND = (0x004),
217 NAND_STATUS_DEVBUSY = (0x008),
218 NAND_STATUS_DEVWRPROTECT = (0x010),
219 NAND_STATUS_WAITTIMEOUT = (0x020),
220 NAND_STATUS_READWRITE_DMA_FAIL = (0x040),
221 NAND_STATUS_ECC_UNSUPPORTED = (0x080),
222 NAND_STATUS_READ_ECC_ERROR_CORRECTED = (0x100),
223 NAND_STATUS_READ_ECC_UNCORRECTABLE_ERROR = (0x200)
224} nandStatus_t;
225
226/*****************************************************************************/
227/*
228** nand ECC alogorithm typedef
229**
230*/
231typedef enum nandEccAlgo
232{
233 NAND_ECC_ALGO_NONE = (0x00),
234 NAND_ECC_ALGO_HAMMING_1BIT = (0x01),
235 NAND_ECC_ALGO_RS_4BIT = (0x02),
236 NAND_ECC_ALGO_BCH_4BIT = (0x04),
237 NAND_ECC_ALGO_BCH_8BIT = (0x08),
238 NAND_ECC_ALGO_BCH_16BIT = (0x10)
239} nandEccAlgo_t;
240
241/*****************************************************************************/
242/*
243** nandPageSize typedef
244**
245*/
246typedef enum nandPageSize
247{
248 NAND_PAGESIZE_INVALID = ((0)*(512)),
249 NAND_PAGESIZE_512BYTES = ((1)*(512)),
250 NAND_PAGESIZE_2048BYTES = ((4)*(512)),
251 NAND_PAGESIZE_4096BYTES = ((8)*(512)),
252 NAND_PAGESIZE_8192BYTES = ((16)*(512))
253} nandPageSize_t;
254
255/*****************************************************************************/
256/*
257** nandBlockSize typedef
258**
259*/
260typedef enum nandBlockSize
261{
262 NAND_BLOCKSIZE_INVALID = ((0)*(1024)),
263 NAND_BLOCKSIZE_64KB = ((64)*(1024)),
264 NAND_BLOCKSIZE_128KB = ((128)*(1024)),
265 NAND_BLOCKSIZE_256KB = ((256)*(1024)),
266 NAND_BLOCKSIZE_512KB = ((512)*(1024))
267} nandBlockSize_t;
268
269/*
270** Macros which can be used as 'busWidth' in NANDDevInfo structure.
271**
272*/
273typedef enum nandBusWidth
274{
275 NAND_BUSWIDTH_INVALID = (0xFF),
276 NAND_BUSWIDTH_8BIT = (0x00),
277 NAND_BUSWIDTH_16BIT = (0x01)
278
279} nandBusWidth_t;
280
281/*******************************************************************************
282* STRUCTURES DECLARION
283*******************************************************************************/
284
285/*
286** NAND access.
287*/
288typedef struct nandAddr
289{
290 uint32_t nandColumnAddr;
291 uint32_t nandPageAddr;
292 uint32_t nandBlockAddr;
293} nandAddr_t;
294
295/*
296** Contains the timing params and base address info for the GPMC NAND access.
297*/
298typedef struct nandTimingInfo
299{
300 unsigned int CSWrOffTime;
301 unsigned int CSRdOffTime;
302 unsigned int CSExtDelayFlag;
303 unsigned int CSOnTime;
304
305 unsigned int ADVAADMuxWrOffTime;
306 unsigned int ADVAADMuxRdOffTime;
307 unsigned int ADVWrOffTime;
308 unsigned int ADVRdOffTime;
309 unsigned int ADVExtDelayFlag;
310 unsigned int ADVAADMuxOnTime;
311 unsigned int ADVOnTime;
312
313 unsigned int WEOffTime;
314 unsigned int WEExtDelayFlag;
315 unsigned int WEOnTime;
316 unsigned int OEAADMuxOffTime;
317 unsigned int OEOffTime;
318 unsigned int OEExtDelayFlag;
319 unsigned int OEAADMuxOnTime;
320 unsigned int OEOnTime;
321
322 unsigned int rdCycleTime;
323 unsigned int wrCycleTime;
324 unsigned int rdAccessTime;
325 unsigned int pageBurstAccessTime;
326
327 unsigned int cycle2CycleDelay;
328 unsigned int cycle2CycleDelaySameCSCfg;
329 unsigned int cycle2CycleDelayDiffCSCfg;
330 unsigned int busTAtime;
331
332 unsigned int wrAccessTime;
333 unsigned int wrDataOnADMux;
334
335} nandTimingInfo_t;
336
337
338/* Contains the controller information like ---
339** 1) chip select
340** 2) Location for data, command and address registers
341** 3) ECC supported by the controller and the default ecc to use.
342** 4) Wait pin onformation
343** 5) DMA related information and so on
344*/
345typedef struct nandCtrlInfo
346{
347 /* Timing info for the device and the controller */
348 void *hNandTimingInfo;
349 /* Base address of the controller */
350 gpmcHandle hGpmc;
351 /* Wait pin where NAND dev R/B pin is connected */
352 unsigned int waitPin;
353 /* Wait pin polarity */
354 unsigned int waitPinPol;
355 /* Write protect pin polarity */
356 unsigned int wpPinPol;
357 /* Chip select base address */
358 unsigned int chipSelectBaseAddr[NAND_MAX_CHIP_SELECTS];
359 /* Chip select region size */
360 unsigned int chipSelectRegionSize[NAND_MAX_CHIP_SELECTS];
361 /* Curr chip select in use by the memory controller */
362 int currChipSelect;
363
364} nandCtrlInfo_t;
365
366typedef struct nandEccInfo
367{
368 /* Base address of the ECC engine (ELM in GPMC for BCH ECC) */
369 elmHandle hElm;
370 /* Offset of the page from where ECC has to store.*/
371 unsigned int eccOffSet;
372 /* Total number of ecc bytes. */
373 unsigned int eccByteCnt;
374
375} nandEccInfo_t;
376
377/*******************************************************************************
378* STRUCTURES DECLARION
379*******************************************************************************/
380
381/* A consolidated structure which is the main object instantiated by the user.
382** This contains all the other information for a NAND device/controller
383** transaction. It contains the info like --
384** 1)NAND Device information that is connected.
385** 2)NAND Controller information that is being used.
386** 3)Function pointers for control/config/transfer.
387**
388*/
389
390typedef struct NAND_Object {
391 GPMC_Handle gpmcHandle; /* Handle for GPMC object */
392 /* Array of memory controller chip selects in use */
393 int chipSelects[NAND_MAX_CHIP_SELECTS];
394
395 /* ECC algorithm required by the NAND device */
396 nandEccAlgo_t eccType;
397
398 /* Count of chip selects the nand device uses */
399 int chipSelectCnt;
400 /* NAND die cnt - how many die in package */
401 int dieCnt;
402 /* Bus width of the device. i,e 8 bit or 16 bit */
403 nandBusWidth_t busWidth;
404 /* Page size of the device */
405 nandPageSize_t pageSize;
406 /* Blk size (with out spare area) of the device */
407 nandBlockSize_t blkSize;
408 /* Pages per block */
409 unsigned int pagesPerBlk;
410
411 /* Pointer to Memory Controller Structure */
412 nandCtrlInfo_t *hNandCtrlInfo;
413 /* Pointer to ECC Structure */
414 nandEccInfo_t *hNandEccInfo;
415}NAND_Object;
416
417/*!
418 * @brief A handle that is returned from a NAND_open() call.
419 */
420typedef NAND_Object *NAND_Handle;
421
422
423
424/******************************************************************************
425* FUNCTION DECLARATIONS
426******************************************************************************/
427
428uint32_t NAND_Init();
429uint32_t NAND_Open();
430uint32_t NAND_ReadPage(NAND_Handle nandHandle, nandAddr_t address, uint8_t* puchBuffer);
431uint32_t NAND_WritePage(NAND_Handle nandHandle, nandAddr_t address, uint8_t* puchBuffer);
432uint32_t NAND_FlashBlockErase(NAND_Handle nandHandle, uint32_t uiBlockNumber);
433uint32_t NAND_GetDetails(NAND_Handle nandHandle);
434uint32_t NAND_ReadSpareArea(NAND_Handle nandHandle, uint32_t uiBlkAddr, uint32_t uiPage, uint8_t *pBuffer);
435uint32_t NAND_WriteSpareArea (NAND_Handle nandHandle, uint32_t uiBlkAddr, uint32_t uiPage, uint8_t *pBuffer);
436
437#endif /* _NAND_H_ */
diff --git a/src/hw_gpmc.h b/src/hw_gpmc.h
deleted file mode 100644
index 1ca9bcc..0000000
--- a/src/hw_gpmc.h
+++ /dev/null
@@ -1,871 +0,0 @@
1/*
2 * Copyright (c) 2016, Texas Instruments Incorporated
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 */
33
34 /**
35 *
36 * \file evmk2g_gpmc.h
37 *
38 * \brief This file is the header file for GPMC module
39 *
40 ******************************************************************************/
41
42#ifndef _HW_GPMC_H_
43#define _HW_GPMC_H_
44
45#include <ti\csl\src\ip\gpmc\V0\cslr_gpmc.h>
46
47/************************
48 * Defines and Macros
49 ************************/
50#define Uint32 uint32_t
51/**
52 * Handle to access GPMC registers.
53 */
54#define hGpmcCfg ((CSL_GpmcRegs *)CSL_GPMC_0_CFG_REGS)
55typedef CSL_GpmcRegs * gpmcHandle;
56
57#define GPMC_CMD_REG(cs) (&hGpmcCfg->NAND_COMMAND_0 + (cs * (0x30)))
58#define GPMC_ADDR_REG(cs) (&hGpmcCfg->NAND_ADDR_0 + (cs * (0x30)))
59#define GPMC_DATA_REG(cs) (&hGpmcCfg->NAND_DATA_0 + (cs * (0x30)))
60
61#define GPMC_BIT_SET_HIGH (1)
62#define GPMC_BIT_SET_LOW (0)
63
64#define GPMC_BIT_ENABLE (1)
65#define GPMC_BIT_DISABLE (0)
66
67/*****************************************************************************/
68/*
69** Macros which can be used as 'mode' parameter to GPMCIdleModeSelect API.
70**
71*/
72#define GPMC_IDLEMODE_FORCEIDLE (0)
73#define GPMC_IDLEMODE_NOIDLE (1)
74#define GPMC_IDLEMODE_SMARTIDLE (2)
75
76/*****************************************************************************/
77/*
78** Macros which can be used as 'configVal' parameter to GPMCAutoIdleConfig API.
79**
80*/
81#define GPMC_AUTOIDLE_FREERUN (0)
82#define GPMC_AUTOIDLE_AUTORUN (1)
83
84/*****************************************************************************/
85/*
86** Macros which can be used as 'flag' parameter to GPMCIntStatusGet,
87** GPMCIntStatusClear APIs.
88**
89*/
90#define GPMC_FIFOEVENT_STATUS (0)
91#define GPMC_TERMINALCOUNT_STATUS (1)
92#define GPMC_WAIT0EDGEDETECTION_STATUS (2)
93#define GPMC_WAIT1EDGEDETECTION_STATUS (3)
94
95/*****************************************************************************/
96/*
97** Macros which can be used as 'flag' parameter to GPMCIntEnable, GPMCIntDisable
98** APIs.
99**
100*/
101#define GPMC_FIFOEVENT_INT (0)
102#define GPMC_TERMINALCOUNT_INT (1)
103#define GPMC_WAIT0EDGEDETECTION_INT (2)
104#define GPMC_WAIT1EDGEDETECTION_INT (3)
105
106/*****************************************************************************/
107/*
108** Macros which can be used as 'flag' parameter to GPMCTimeOutFeatureConfig API.
109**
110*/
111#define GPMC_TIMEOUTFEATURE_ENABLE (1)
112#define GPMC_TIMEOUTFEATURE_DISABLE (0)
113
114/*****************************************************************************/
115/*
116** Macros which can be used as 'err' parameter to GPMCErrStatusGet API.
117**
118*/
119#define GPMC_TIMEOUT_ERROR (0)
120#define GPMC_NOTSUPPMCMD_ERROR (1)
121#define GPMC_NOTSUPPADD_ERROR (2)
122
123/*****************************************************************************/
124/*
125** Macros which can be used as 'pin' parameter to GPMCWaitPinPolaritySelect,
126** GPMCWaitPinStatusGet APIs.
127**
128*/
129#define GPMC_WAIT_PIN0 (0)
130#define GPMC_WAIT_PIN1 (1)
131
132/*****************************************************************************/
133/*
134** Macros which can be used as 'polarity' parameter to GPMCWaitPinPolaritySelect
135** API.
136**
137*/
138#define GPMC_WAIT_PIN_POLARITY_LOW (0)
139#define GPMC_WAIT_PIN_POLARITY_HIGH (1)
140
141/*****************************************************************************/
142/*
143** Macros which can be used as 'pinLevel' parameter to
144** GPMCWriteProtectPinLevelCntrl API.
145*/
146#define GPMC_WP_PIN_LEVEL_LOW (0)
147#define GPMC_WP_PIN_LEVEL_HIGH (1)
148
149/*****************************************************************************/
150/*
151** Macros which can be used as 'flag' parameter to
152** GPMCNANDForcePostedWriteFeatureConfig API.
153*/
154#define GPMC_FORCEPOSTEDWRITE_ENABLE (1)
155#define GPMC_FORCEPOSTEDWRITE_DISABLE (0)
156
157/*****************************************************************************/
158/*
159** Macros which can be used as 'flag' parameter to
160** GPMCLimitedAddrDevSupportConfig API.
161*/
162#define GPMC_LIMITEDADDRESS_SUPPORT_ENABLE (1)
163#define GPMC_LIMITEDADDRESS_SUPPORT_DISABLE (0)
164
165/*****************************************************************************/
166/*
167** Macros which can be used as 'csNum' parameter to GPMCFclkDividerSelect,
168** GPMCTimeParaGranularitySelect, GPMCAddrDataMuxProtocolSelect,
169** GPMCDevTypeSelect, GPMCDevSizeSelect, GPMCWaitPinSelect,
170** GPMCWaitMonitoringTimeSelect, GPMCWaitPinMonitoringConfig,
171** GPMCClkActivationTimeConfig, GPMCDevPageLenSet, GPMCWriteTypeSelect,
172** GPMCReadTypeSelect, GPMCAccessTypeSelect, GPMCSyncWrapBurstConfig,
173** GPMCCSTimingConfig, GPMCADVTimingConfig, GPMCWEAndOETimingConfig,
174** GPMCRdAccessAndCycleTimeTimingConfig, GPMCCSConfig, GPMCBaseAddrSet,
175** GPMCWrAccessAndWrDataOnADMUXBusTimingConfig, GPMCMaskAddrSet,
176** GPMCycle2CycleAndTurnArndTimeTimingConfig, GPMCSNANDCmdWrite,
177** GPMCNANDAddrWrite, GPMCNANDDataWrite, GPMCNANDDataRead, GPMCPrefetchCSSelect,
178** GPMCECCCSSelect, GPMCECCBCHResultGet APIs.
179**
180*/
181#define GPMC_CHIP_SELECT_0 (0)
182#define GPMC_CHIP_SELECT_1 (1)
183#define GPMC_CHIP_SELECT_2 (2)
184#define GPMC_CHIP_SELECT_3 (3)
185#define GPMC_CHIP_SELECT_4 (4)
186#define GPMC_CHIP_SELECT_5 (5)
187#define GPMC_CHIP_SELECT_6 (6)
188#define GPMC_CHIP_SELECT_7 (7)
189
190/*****************************************************************************/
191/*
192** Macros which can be used as 'divideVal' parameter to GPMCFclkDividerSelect
193** API.
194**
195*/
196#define GPMC_FCLK_DIV_BY_1 (0)
197#define GPMC_FCLK_DIV_BY_2 (1)
198#define GPMC_FCLK_DIV_BY_3 (2)
199#define GPMC_FCLK_DIV_BY_4 (3)
200
201/*****************************************************************************/
202/*
203** Macros which can be used as 'scaleftr' parameter to
204** GPMCTimeparaGranularitySelect API.
205**
206*/
207#define GPMC_TIMEPARAGRANULARITY_X1 (0)
208#define GPMC_TIMEPARAGRANULARITY_X2 (1)
209
210/*****************************************************************************/
211/*
212** Macros which can be used as 'protocol' parameter to
213** GPMCAddrDataMuxProtocolSelect API.
214**
215*/
216#define GPMC_MUXADDDATA_NOMUX (0)
217#define GPMC_MUXADDDATA_AADMUX (1)
218#define GPMC_MUXADDDATA_ADMUX (2)
219
220/*****************************************************************************/
221/*
222** Macros which can be used as 'devType' parameter to GPMCDevTypeSelect API.
223**
224*/
225#define GPMC_DEVICETYPE_NORLIKE (0)
226#define GPMC_DEVICETYPE_NANDLIKE (2)
227
228/*****************************************************************************/
229/*
230** Macros which can be used as 'devSize' parameter to GPMCDevSizeSelect API.
231**
232*/
233#define GPMC_DEVICESIZE_8BITS (0)
234#define GPMC_DEVICESIZE_16BITS (1)
235
236/*****************************************************************************/
237/*
238** Macros which can be used as 'flag' parameter to GPMCWaitMonitoringTimeSelect
239** API.
240**
241*/
242#define GPMC_WAITMONITORINGTIME_WITH_VALIDDATA (0)
243#define GPMC_WAITMONITORINGTIME_ONECLKB4_VALIDDATA (1)
244#define GPMC_WAITMONITORINGTIME_TWOCLKB4_VALIDDATA (2)
245
246/*****************************************************************************/
247/*
248** Macros which can be used as 'mode' parameter to GPMCWaitPinMonitoringConfig
249** API.
250**
251*/
252#define GPMC_MODE_READ (0)
253#define GPMC_MODE_WRITE (1)
254
255/*****************************************************************************/
256/*
257** Macros which can be used as 'flag' parameter to GPMCWaitMonitoringTimeConfig
258** API.
259**
260*/
261#define GPMC_WAITMONITORING_ENABLE (1)
262#define GPMC_WAITMONITORING_DISABLE (0)
263
264/*****************************************************************************/
265/*
266** Macros which can be used as 'flag' parameter to GPMCClkActivationTimeConfig
267** API.
268**
269*/
270#define GPMC_CLKACTIVATIONTIME_ATSTART (0)
271#define GPMC_CLKACTIVATIONTIME_ONECLK_AFTR (1)
272#define GPMC_CLKACTIVATIONTIME_TWOCLK_AFTR (2)
273
274/*****************************************************************************/
275/*
276** Macros which can be used as 'pageLen' parameter to GPMCDevPageLenSet API.
277**
278*/
279#define GPMC_DEV_PAGELENGTH_FOUR (0)
280#define GPMC_DEV_PAGELENGTH_EIGHT (1)
281#define GPMC_DEV_PAGELENGTH_SIXTEEN (2)
282
283/*****************************************************************************/
284/*
285** Macros which can be used as 'writeType' parameter to GPMCWriteTypeSelect API.
286**
287*/
288#define GPMC_WRITETYPE_ASYNC (0)
289#define GPMC_WRITETYPE_SYNC (1)
290
291/*****************************************************************************/
292/*
293** Macros which can be used as 'readType' parameter to GPMCReadTypeSelect API.
294**
295*/
296#define GPMC_READTYPE_ASYNC (0)
297#define GPMC_READTYPE_SYNC (1)
298
299/*****************************************************************************/
300/*
301** Macros which can be used as 'AccessType' parameter to GPMCAccessTypeSelect
302** API.
303**
304*/
305#define GPMC_ACCESSTYPE_SINGLE (0)
306#define GPMC_ACCESSTYPE_MULTIPLE (1)
307
308/*****************************************************************************/
309/*
310** Macros which can be used as 'flag' parameter to GPMCSyncWrapBurstConfig API.
311**
312*/
313#define GPMC_WRAPBURST_ENABLE (1)
314#define GPMC_WRAPBURST_DISABLE (0)
315
316/*****************************************************************************/
317/*
318** Macros which can be used as 'CSExtDelayFlag' parameter to
319** GPMC_CS_TIMING_CONFIG macro
320*/
321#define GPMC_CS_EXTRA_DELAY (1)
322#define GPMC_CS_EXTRA_NODELAY (0)
323
324/*
325* \brief This macro used to make the conf value which is used to configure the
326* CS signal timing configuration.\n
327*
328* \param CSWrOffTime CS# de-assertion time from start cycle time for write
329* accesses in GPMC_FCLK cycles.
330*
331* CSRdOffTime CS# de-assertion time from start cycle time for read
332* accesses in GPMC_FCLK cycles
333*
334* CSExtDelayFlag Flag to indicate whether to add half GPMC_FCLK delay to
335* CS or not.
336* This can take one of the following values :
337* GPMC_CS_EXTRA_DELAY -- CS# Timing control
338* signal is delayed of
339* half GPMC_FCLK cycle.
340* GPMC_CS_EXTRA_NODELAY -- CS# Timing control
341* signal is not delayed
342*
343* CSOnTime CS# assertion time from start cycle time in GPMC_FCLK
344* cycles.
345*/
346
347#define GPMC_CS_TIMING_CONFIG(CSWrOffTime, CSRdOffTime, CSExtDelayFlag, CSOnTime ) ((Uint32) \
348 (CSL_FMK(GPMC_CONFIG2_0_CSWROFFTIME, CSWrOffTime)) | \
349 (CSL_FMK(GPMC_CONFIG2_0_CSRDOFFTIME, CSRdOffTime)) | \
350 (CSL_FMK(GPMC_CONFIG2_0_CSEXTRADELAY, CSExtDelayFlag)) | \
351 (CSL_FMK(GPMC_CONFIG2_0_CSONTIME, CSOnTime)))
352
353/*****************************************************************************/
354/*
355** Macros which can be used as 'ADVExtDelayFlag' parameter to
356** GPMC_ADV_TIMING_CONFIG macro
357*/
358#define GPMC_ADV_EXTRA_DELAY (1)
359#define GPMC_ADV_EXTRA_NODELAY (0)
360
361/*
362* \brief This macro used to make the conf value which is used to configure the
363* ADV# signal timing configuration.\n
364*
365* \param ADVAADMuxWrOffTime ADV# de-assertion time in GPMC_FCLK cycles for
366* first address phase when using the AAD-Mux
367* prorocol.
368*
369* ADVAADMuxRdOffTime ADV# de-assertion time in GPMC_FCLK cycles for
370* first address phase when using the AAD-Mux
371* prorocol.
372*
373* ADVWrOffTime ADV# de-assertion time in GPMC_FCLK cycles from
374* start cycle time for write accesses
375*
376* ADVRdOffTime ADV# de-assertion time in GPMC_FCLK cycles from
377* start cycle time for write accesses
378*
379* ADVExtDelayFlag Flag to indicate whether to add half GPMC_FCLK
380* delay to ADV or not.
381* This can take one of the following values :
382* GPMC_ADV_EXTRA_DELAY -- ADV# Timing control
383* signal is delayed of
384* half GPMC_FCLK cycle.
385* GPMC_ADV_EXTRA_NODELAY -- ADV# Timing control
386* signal is not delayed.
387*
388* ADVAADMuxOnTime ADV# assertion time in GPMC_FCLK cycles for
389* first address phase when using the
390* AAD-Multiplexed protocol.
391*
392* ADVOnTime ADV# assertion time from start cycle time in
393* GPMC_FCLK cycles.
394*/
395
396#define GPMC_ADV_TIMING_CONFIG(ADVAADMuxWrOffTime, ADVAADMuxRdOffTime, ADVWrOffTime, ADVRdOffTime, ADVExtDelayFlag, ADVAADMuxOnTime, ADVOnTime) ((Uint32) \
397 (CSL_FMK(GPMC_CONFIG3_0_ADVAADMUXWROFFTIME, ADVAADMuxWrOffTime)) | \
398 (CSL_FMK(GPMC_CONFIG3_0_ADVAADMUXRDOFFTIME, ADVAADMuxRdOffTime)) | \
399 (CSL_FMK(GPMC_CONFIG3_0_ADVWROFFTIME, ADVWrOffTime)) | \
400 (CSL_FMK(GPMC_CONFIG3_0_ADVRDOFFTIME, ADVRdOffTime)) | \
401 (CSL_FMK(GPMC_CONFIG3_0_ADVEXTRADELAY, ADVExtDelayFlag)) | \
402 (CSL_FMK(GPMC_CONFIG3_0_ADVAADMUXONTIME, ADVAADMuxOnTime)) | \
403 (CSL_FMK(GPMC_CONFIG3_0_ADVONTIME, ADVOnTime)))
404
405/*****************************************************************************/
406/*
407** Macros which can be used as 'OEExtDelayFlag' parameter to
408** GPMC_WE_OE_TIMING_CONFIG macro
409*/
410#define GPMC_OE_EXTRA_DELAY (1)
411#define GPMC_OE_EXTRA_NODELAY (0)
412
413/*****************************************************************************/
414/*
415** Macros which can be used as 'WEExtDelayFlag' parameter to
416** GPMC_WE_OE_TIMING_CONFIG macro
417*/
418#define GPMC_WE_EXTRA_DELAY (1)
419#define GPMC_WE_EXTRA_NODELAY (0)
420
421
422/*
423* \brief This macro used to make the conf value which is used to configure the
424* WE# and OE# signal timing configuration.\n
425*
426* \param WEOffTime WE# de-assertion time in GPMC_FCLK cycles from
427* start cycle time.
428*
429* WEExtDelayFlag Flag to indicate whether to add half GPMC_FCLK
430* delay to WE or not.
431* This can take one of the following values :
432* GPMC_WE_EXTRA_DELAY -- WE# Timing control
433* signal is delayed of
434* half GPMC_FCLK cycle.
435* GPMC_WE_EXTRA_NODELAY -- WE# Timing control
436* signal is not delayed
437* WEOnTime WE# assertion time in GPMC_FCLK cycles from
438* start cycle time.
439*
440* OEAADMuxOffTime OE# de-assertion time in GPMC_FCLK cycles for
441* first address phase when using the AAD-Mux
442* prorocol.
443*
444* OEOffTime OE# de-assertion time in GPMC_FCLK cycles from
445* start cycle time.
446*
447* OEExtDelayFlag Flag to indicate whether to add half GPMC_FCLK
448* delay to OE or not.
449* This can take one of the following values :
450* GPMC_OE_EXTRA_DELAY -- OE# Timing control
451* signal is delayed of
452* half GPMC_FCLK cycle.
453* GPMC_OE_EXTRA_NODELAY -- OE# Timing control
454* signal is not delayed
455*
456* OEAADMuxOnTime OE# assertion time in GPMC_FCLK cycles for
457* first address phase when using the AAD-Mux
458* prorocol.
459*
460* OEOnTime OE# assertion time in GPMC_FCLK cycles from
461* start cycle time.
462*
463*/
464
465#define GPMC_WE_OE_TIMING_CONFIG(WEOffTime, WEExtDelayFlag, WEOnTime, OEAADMuxOffTime, OEOffTime, OEExtDelayFlag, OEAADMuxOnTime,OEOnTime ) ((Uint32) \
466 (CSL_FMK(GPMC_CONFIG4_0_WEOFFTIME, WEOffTime)) | \
467 (CSL_FMK(GPMC_CONFIG4_0_WEEXTRADELAY, WEExtDelayFlag)) | \
468 (CSL_FMK(GPMC_CONFIG4_0_WEONTIME, WEOnTime)) | \
469 (CSL_FMK(GPMC_CONFIG4_0_OEAADMUXOFFTIME, OEAADMuxOffTime)) | \
470 (CSL_FMK(GPMC_CONFIG4_0_OEOFFTIME, OEOffTime)) | \
471 (CSL_FMK(GPMC_CONFIG4_0_OEEXTRADELAY, OEExtDelayFlag)) | \
472 (CSL_FMK(GPMC_CONFIG4_0_OEAADMUXONTIME, OEAADMuxOnTime)) | \
473 (CSL_FMK(GPMC_CONFIG4_0_OEONTIME, OEOnTime)))
474
475/*
476* \brief This macro used to make the conf value which is used to configure the
477* read access and cycle time timing configuration.\n
478*
479* \param rdCycleTime Total read cycle time in GPMC_FCLK cycles.
480*
481* wrCycleTime Total write cycle time in GPMC_FCLK cycles.
482*
483* rdAccessTime Read access time (Delay between start cycle time
484* and first data valid) in GPMC_FCLK cycles.
485*
486* pageBurstAccessTime Page burest access time (Delay between
487* successive words in a multiple access)in
488* GPMC_FCLK cycles.
489*
490*/
491
492#define GPMC_RDACCESS_CYCLETIME_TIMING_CONFIG(rdCycleTime, wrCycleTime, rdAccessTime, pageBurstAccessTime ) ((Uint32) \
493 (CSL_FMK(GPMC_CONFIG5_0_RDCYCLETIME, rdCycleTime)) | \
494 (CSL_FMK(GPMC_CONFIG5_0_WRCYCLETIME, wrCycleTime)) | \
495 (CSL_FMK(GPMC_CONFIG5_0_RDACCESSTIME, rdAccessTime)) | \
496 (CSL_FMK(GPMC_CONFIG5_0_PAGEBURSTACCESSTIME, pageBurstAccessTime)))
497
498/*****************************************************************************/
499/*
500** Macros which can be used as 'cycle2CycleDelaySameCSCfg' parameter to
501** GPMC_CYCLE2CYCLE_BUSTURNAROUND_TIMING_CONFIG macro
502*/
503#define GPMC_CYCLE2CYCLESAMECSEN_C2CDELAY (1)
504#define GPMC_CYCLE2CYCLESAMECSEN_NOC2CDELAY (0)
505
506/*****************************************************************************/
507/*
508** Macros which can be used as 'cycle2CycleDelayDiffCSCfg' parameter to
509** GPMC_CYCLE2CYCLE_BUSTURNAROUND_TIMING_CONFIG macro
510*/
511#define GPMC_CYCLE2CYCLEDIFFCSEN_C2CDELAY (1)
512#define GPMC_CYCLE2CYCLEDIFFCSEN_NOC2CDELAY (0)
513
514/*
515* \brief This macro used to make the conf value which is used to configure the
516* cycle to cycle and bus turn around time timing configuration.\n
517*
518* \param cycle2CycleDelay Cycle to cycle delay (Chip select high pulse
519* delay between two successive accesses)in
520* GPMC_FCLK cycles.
521*
522* cycle2CycleDelaySameCSCfg Specified whether to add the cycle to cycle
523* delay between two successive accesses or not
524* (to the same chip-select).
525* This can take one of the following values :
526* GPMC_CYCLE2CYCLESAMECSEN_C2CDELAY -- To add
527* the delay.
528* GPMC_CYCLE2CYCLESAMECSEN_NOC2CDELAY -- Don't
529* add the delay.
530*
531* cycle2CycleDelayDiffCSCfg Specified whether to add the cycle to cycle
532* delay between two successive accesses or not
533* (to the diffrent chip-select).
534* This can take one of the following values :
535* GPMC_CYCLE2CYCLEDIFFCSEN_C2CDELAY -- To add
536* the delay.
537* GPMC_CYCLE2CYCLEDIFFCSEN_NOC2CDELAY -- Don't
538* add the delay.
539*
540* busTAtime Bus turn aroung time between two successive
541* accesses to the same chip-select (read to write)
542* or to a diff chip-select in GPMC_FCLK cycles.
543*
544*
545*/
546
547#define GPMC_CYCLE2CYCLE_BUSTURNAROUND_TIMING_CONFIG(cycle2CycleDelay, cycle2CycleDelaySameCSCfg, cycle2CycleDelayDiffCSCfg, busTAtime ) ((Uint32) \
548 (CSL_FMK(GPMC_CONFIG6_0_CYCLE2CYCLEDELAY, cycle2CycleDelay)) | \
549 (CSL_FMK(GPMC_CONFIG6_0_CYCLE2CYCLESAMECSEN, cycle2CycleDelaySameCSCfg)) | \
550 (CSL_FMK(GPMC_CONFIG6_0_CYCLE2CYCLEDIFFCSEN, cycle2CycleDelayDiffCSCfg)) | \
551 (CSL_FMK(GPMC_CONFIG6_0_BUSTURNAROUND, busTAtime)))
552
553/*****************************************************************************/
554/*
555** Macros which can be used as 'conf' parameter to GPMCCSConfig API.
556**
557*/
558#define GPMC_CS_ENABLE (1)
559#define GPMC_CS_DISABLE (0)
560
561/*****************************************************************************/
562/*
563** Macros which can be used as 'addrMask' parameter to GPMCSMaskAddrSet API.
564**
565*/
566#define GPMC_CS_SIZE_256MB (0x00)
567#define GPMC_CS_SIZE_128MB (0x08)
568#define GPMC_CS_SIZE_64MB (0x0c)
569#define GPMC_CS_SIZE_32MB (0x0e)
570#define GPMC_CS_SIZE_16MB (0x0f)
571
572/*****************************************************************************/
573/*
574** Macros which can be used as 'accessMode' parameter to
575** GPMCPREFETCHAccessModeSelect API.
576*/
577#define GPMC_PREFETCH_ACCESSMODE_READ (0)
578#define GPMC_PREFETCH_ACCESSMODE_WRITE (1)
579
580/*****************************************************************************/
581/*
582** Macros which can be used as 'syncType' parameter to
583** GPMCPREFETCHSyncTypeSelect API.
584**
585*/
586#define GPMC_PREFETCH_SYNCTYPE_DMA (1)
587#define GPMC_PREFETCH_SYNCTYPE_INT (0)
588
589/*****************************************************************************/
590/*
591** Macros which can be used as 'flag' parameter to GPMCPrefetchSyncModeConfig
592** API.
593**
594*/
595#define GPMC_PREFETCH_ACCESSCS_AT_START (0)
596#define GPMC_PREFETCH_ACCESSCS_AT_STARTANDWAIT (1)
597
598/*****************************************************************************/
599/*
600** Macros which can be used as 'waitPin' parameter to GPMCPrefetchWaitPinSelect
601** API.
602**
603*/
604#define GPMC_PREFETCH_WAITPINSELECTOR_W0 (0)
605#define GPMC_PREFETCH_WAITPINSELECTOR_W1 (1)
606
607/*****************************************************************************/
608/*
609** Macros which can be used as 'configVal' GPMCPrefetchAccessCycleOptConfig API.
610**
611*/
612#define GPMC_PREFETCH_OPTIMIZED_ACCESS_ENABLE (1)
613#define GPMC_PREFETCH_OPTIMIZED_ACCESS_DISABLE (0)
614
615/*****************************************************************************/
616/*
617** Macros which can be used as 'configVal' parameter to
618** GPMCPrefetchRRArbitrationConfig API.
619*/
620#define GPMC_PREFETCH_RR_ARBITRATION_ENABLE (1)
621#define GPMC_PREFETCH_RR_ARBITRATION_DISABLE (0)
622
623/*****************************************************************************/
624/*
625** Macros which can be used as 'algo' parameter to GPMCECCAlgoSelect API.
626**
627*/
628#define GPMC_ECC_ALGORITHM_HAMMINGCODE (0)
629#define GPMC_ECC_ALGORITHM_BCH (1)
630
631/*****************************************************************************/
632/*
633** Macros which can be used as 'errCorrCapVal' parameter to
634** GPMCECCBCHErrCorrectionCapSelect API.
635**
636*/
637#define GPMC_ECC_BCH_ERRCORRCAP_UPTO_4BITS (0)
638#define GPMC_ECC_BCH_ERRCORRCAP_UPTO_8BITS (1)
639#define GPMC_ECC_BCH_ERRCORRCAP_UPTO_16BITS (2)
640
641/*****************************************************************************/
642/*
643** Macros which can be used as 'eccColVal' parameter to GPMCECCColumnSelect API.
644**
645*/
646#define GPMC_ECC_COLUMNS_8 (0)
647#define GPMC_ECC_COLUMNS_16 (1)
648
649/*****************************************************************************/
650/*
651** Macros which can be used as 'numOfSects' parameter to
652** GPMCECCBCHNumOfSectorsSelect API.
653** Here 1 SECTOR = 512 bytes.
654**
655*/
656#define GPMC_ECC_BCH_NUMOFSECTS_1 (0)
657#define GPMC_ECC_BCH_NUMOFSECTS_2 (1)
658#define GPMC_ECC_BCH_NUMOFSECTS_3 (2)
659#define GPMC_ECC_BCH_NUMOFSECTS_4 (3)
660#define GPMC_ECC_BCH_NUMOFSECTS_5 (4)
661#define GPMC_ECC_BCH_NUMOFSECTS_6 (5)
662#define GPMC_ECC_BCH_NUMOFSECTS_7 (6)
663#define GPMC_ECC_BCH_NUMOFSECTS_8 (7)
664
665/*****************************************************************************/
666/*
667** Macros which can be used as 'eccResReg' parameter to GPMCECCResultRegSelect
668** API.
669**
670*/
671#define GPMC_ECCPOINTER_RESULT_1 (1)
672#define GPMC_ECCPOINTER_RESULT_2 (2)
673#define GPMC_ECCPOINTER_RESULT_3 (3)
674#define GPMC_ECCPOINTER_RESULT_4 (4)
675#define GPMC_ECCPOINTER_RESULT_5 (5)
676#define GPMC_ECCPOINTER_RESULT_6 (6)
677#define GPMC_ECCPOINTER_RESULT_7 (7)
678#define GPMC_ECCPOINTER_RESULT_8 (8)
679#define GPMC_ECCPOINTER_RESULT_9 (9)
680
681/*****************************************************************************/
682/*
683** Macros which can be used as 'eccSize' parameter to GPMCECCSizeValSet API.
684**
685*/
686#define GPMC_ECC_SIZE_0 (0)
687#define GPMC_ECC_SIZE_1 (1)
688
689/*****************************************************************************/
690/*
691** Macros which can be used as 'eccResReg' parameter to GPMCECCResultSizeSelect
692** API.
693**
694*/
695#define GPMC_ECC_RESULT_1 (1)
696#define GPMC_ECC_RESULT_2 (2)
697#define GPMC_ECC_RESULT_3 (3)
698#define GPMC_ECC_RESULT_4 (4)
699#define GPMC_ECC_RESULT_5 (5)
700#define GPMC_ECC_RESULT_6 (6)
701#define GPMC_ECC_RESULT_7 (7)
702#define GPMC_ECC_RESULT_8 (8)
703#define GPMC_ECC_RESULT_9 (9)
704
705/*****************************************************************************/
706/*
707** Macros which can be used as 'resIndex' parameter to GPMCECCBCHResultGet API.
708**
709*/
710#define GPMC_BCH_RESULT_0 (0)
711#define GPMC_BCH_RESULT_1 (1)
712#define GPMC_BCH_RESULT_2 (2)
713#define GPMC_BCH_RESULT_3 (3)
714#define GPMC_BCH_RESULT_4 (4)
715#define GPMC_BCH_RESULT_5 (5)
716#define GPMC_BCH_RESULT_6 (6)
717
718/*
719** Macros which defines the ECC size values.
720*/
721#define GPMC_ECC_SIZE0_VAL (0xFF)
722#define GPMC_ECC_SIZE1_VAL (0xFF)
723
724/***************************************************************************/
725/*
726** Function Prototypes
727*/
728extern void GPMCECCEnable(gpmcHandle hGpmc);
729extern void GPMCECCDisable(gpmcHandle hGpmc);
730extern void GPMCModuleSoftReset(gpmcHandle hGpmc);
731extern void GPMCECCResultRegClear(gpmcHandle hGpmc);
732extern void GPMCPrefetchEngineStop(gpmcHandle hGpmc);
733extern void GPMCPrefetchEngineStart(gpmcHandle hGpmc);
734extern Uint32 GPMCErrAddrGet(gpmcHandle hGpmc);
735extern void GPMCPrefetchEngineEnable(gpmcHandle hGpmc);
736extern Uint32 GPMCRevisionGet(gpmcHandle hGpmc);
737extern void GPMCPrefetchEngineDisable(gpmcHandle hGpmc);
738extern Uint32 GPMCErrSysCmdGet(gpmcHandle hGpmc);
739extern Uint32 GPMCECCBCHSWDataRead(gpmcHandle hGpmc);
740extern Uint32 GPMCErrValStatusGet(gpmcHandle hGpmc);
741extern Uint32 GPMCPREFETCHCountValGet(gpmcHandle hGpmc);
742extern void GPMCIntEnable(gpmcHandle hGpmc, Uint32 flag);
743extern Uint32 GPMCModuleResetStatusGet(gpmcHandle hGpmc);
744extern Uint32 GPMCPrefetchFIFOPtrValGet(gpmcHandle hGpmc);
745extern void GPMCIntDisable(gpmcHandle hGpmc, Uint32 flag);
746extern void GPMCECCCSSelect(gpmcHandle hGpmc, Uint32 csNum);
747extern Uint32 GPMCPrefetchEngineStatusGet(gpmcHandle hGpmc);
748extern void GPMCECCAlgoSelect(gpmcHandle hGpmc, Uint32 algo);
749extern void GPMCIntStatusClear(gpmcHandle hGpmc, Uint32 flag);
750extern void GPMCIdleModeSelect(gpmcHandle hGpmc, Uint32 mode);
751extern Uint32 GPMCPrefetchFIFOThrldStatusGet(gpmcHandle hGpmc);
752extern void GPMCPrefetchCSSelect(gpmcHandle hGpmc, Uint32 csNum);
753extern void GPMCECCBCHSWDataWrite(gpmcHandle hGpmc,Uint32 bchData);
754extern Uint32 GPMCErrStatusGet(gpmcHandle hGpmc, Uint32 err);
755extern void GPMCAutoIdleConfig(gpmcHandle hGpmc, Uint32 configVal);
756extern void GPMCECCColumnSelect(gpmcHandle hGpmc, Uint32 eccColVal);
757extern Uint32 GPMCIntStatusGet(gpmcHandle hGpmc, Uint32 flag);
758extern void GPMCTimeOutFeatureConfig(gpmcHandle hGpmc, Uint32 flag);
759extern void GPMCPrefetchSyncModeConfig(gpmcHandle hGpmc,Uint32 flag);
760extern void GPMCECCResultRegSelect(gpmcHandle hGpmc,
761 Uint32 eccResReg);
762extern Uint32 GPMCSNANDDataRead(gpmcHandle hGpmc,
763 Uint32 csNum);
764extern Uint32 GPMCECCResultGet(gpmcHandle hGpmc,
765 Uint32 eccResReg);
766extern void GPMCPrefetchWaitPinSelect(gpmcHandle hGpmc,
767 Uint32 waitPin);
768extern Uint32 GPMCWaitPinStatusGet(gpmcHandle hGpmc,
769 Uint32 pin);
770extern void GPMCPrefetchSyncTypeSelect(gpmcHandle hGpmc,
771 Uint32 syncType);
772extern void GPMCTimeOutStartValSet(gpmcHandle hGpmc,
773 Uint32 timeoutVal);
774extern void GPMCPrefetchCycleOptValSet(gpmcHandle hGpmc,
775 Uint32 cleOptVal);
776extern void GPMCECCBCHWrapModeValSet(gpmcHandle hGpmc,
777 Uint32 wrapModeVal);
778extern void GPMCPrefetchTrnsCntValSet(gpmcHandle hGpmc,
779 Uint32 trnsCntVal);
780extern void GPMCPrefetchWeightedPrioSet(gpmcHandle hGpmc,
781 Uint32 accessVal);
782extern void GPMCLimitedAddrDevSupportConfig(gpmcHandle hGpmc,
783 Uint32 flag);
784extern void GPMCPrefetchAccessCycleOptConfig(gpmcHandle hGpmc,
785 Uint32 configVal);
786extern void GPMCECCBCHNumOfSectorsSelect(gpmcHandle hGpmc,
787 Uint32 numOfSects);
788extern void GPMCPrefetchAccessModeSelect(gpmcHandle hGpmc,
789 Uint32 accessMode);
790extern void GPMCPrefetchFifoThrldValSet(gpmcHandle hGpmc,
791 Uint32 fifoThrsld);
792extern void GPMCECCBCHErrCorrectionCapSelect(gpmcHandle hGpmc,
793 Uint32 errCorrCapVal);
794extern void GPMCWriteProtectPinLevelCtrl(gpmcHandle hGpmc,
795 Uint32 pinLevel);
796extern Uint32 GPMCEmptyWriteBuffStatusGet(gpmcHandle hGpmc);
797extern void GPMCNANDForcePostedWriteFeatureConfig(gpmcHandle hGpmc,
798 Uint32 flag);
799extern void GPMCECCSizeValSet(gpmcHandle hGpmc,Uint32 eccSize,
800 Uint32 eccSizeVal);
801extern void GPMCCSConfig(gpmcHandle hGpmc, Uint32 csNum,
802 Uint32 conf);
803extern void GPMCBaseAddrSet(gpmcHandle hGpmc, Uint32 csNum,
804 Uint32 addr);
805extern void GPMCMaskAddrSet(gpmcHandle hGpmc, Uint32 csNum,
806 Uint32 maskaddr);
807extern void GPMNANDCmdWrite(gpmcHandle hGpmc, Uint32 csNum,
808 Uint32 cmd);
809extern void GPMCDevTypeSelect(gpmcHandle hGpmc, Uint32 csNum,
810 Uint32 devType);
811extern void GPMCDevSizeSelect(gpmcHandle hGpmc, Uint32 csNum,
812 Uint32 devSize);
813extern void GPMCWaitPinSelect(gpmcHandle hGpmc, Uint32 csNum,
814 Uint32 waitPin);
815extern void GPMCCSTimingConfig(gpmcHandle hGpmc, Uint32 csNum,
816 Uint32 conf);
817extern void GPMCNANDAddrWrite(gpmcHandle hGpmc, Uint32 csNum,
818 Uint32 addr);
819extern void GPMCNANDDataWrite(gpmcHandle hGpmc, Uint32 csNum,
820 Uint32 data);
821extern void GPMCReadTypeSelect(gpmcHandle hGpmc, Uint32 csNum,
822 Uint32 readType);
823extern void GPMCADVTimingConfig(gpmcHandle hGpmc, Uint32 csNum,
824 Uint32 conf);
825extern void GPMCWriteTypeSelect(gpmcHandle hGpmc, Uint32 csNum,
826 Uint32 writeType);
827extern void GPMCDevPageLenSet(gpmcHandle hGpmc, Uint32 csNum,
828 Uint32 pageLen);
829extern void GPMCFclkDividerSelect(gpmcHandle hGpmc, Uint32 csNum,
830 Uint32 divideVal);
831extern void GPMCWaitPinPolaritySelect(gpmcHandle hGpmc, Uint32 pin,
832 Uint32 polarity);
833extern void GPMCECCResultSizeSelect(gpmcHandle hGpmc,Uint32 eccResReg,
834 Uint32 eccSize);
835extern void GPMCWEAndOETimingConfig(gpmcHandle hGpmc, Uint32 csNum,
836 Uint32 conf);
837extern void GPMCSyncWrapBurstConfig(gpmcHandle hGpmc, Uint32 csNum,
838 Uint32 flag);
839extern Uint32 GPMCECCBCHResultGet(gpmcHandle hGpmc,
840 Uint32 resIndex,
841 Uint32 csNum);
842extern void GPMCClkActivationTimeConfig(gpmcHandle hGpmc,
843 Uint32 csNum,
844 Uint32 flag);
845extern void GPMCWaitMonitoringTimeSelect(gpmcHandle hGpmc,
846 Uint32 csNum,
847 Uint32 flag);
848extern void GPMCAddrDataMuxProtocolSelect(gpmcHandle hGpmc,
849 Uint32 csNum,
850 Uint32 protocol);
851extern void GPMCTimeParaGranularitySelect(gpmcHandle hGpmc,
852 Uint32 csNum,
853 Uint32 scaleftr);
854extern void GPMCRdAccessAndCycleTimeTimingConfig(gpmcHandle hGpmc,
855 Uint32 csNum,
856 Uint32 conf);
857extern void GPMCycle2CycleAndTurnArndTimeTimingConfig(gpmcHandle hGpmc,
858 Uint32 csNum,
859 Uint32 conf);
860extern void GPMCAccessTypeSelect(gpmcHandle hGpmc, Uint32 csNum,
861 Uint32 mode, Uint32 accessType);
862extern void GPMCWaitPinMonitoringConfig(gpmcHandle hGpmc, Uint32 csNum,
863 Uint32 mode, Uint32 flag);
864extern void GPMCWrAccessAndWrDataOnADMUXBusTimingConfig(gpmcHandle hGpmc,
865 Uint32 csNum,
866 Uint32 wrAccessTime,
867 Uint32 wrDataOnADmuxBus);
868extern Uint32 GPMCPrefetchFifoPtrValGet(gpmcHandle hGpmc);
869
870#endif /* _EVMK2G_GPMC_H_ */
871
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