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authorMing Wei2019-06-13 15:04:56 -0500
committerMing Wei2019-06-13 15:04:56 -0500
commit42c28dd064206261824c1056457ec7ecbb4ba1e4 (patch)
treeed8bd2602892b4b7a0df2beed1c85ecb5a75e95b
parentb0a1d7641d2d189e8afb528820a179c10e71f59b (diff)
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move DMTimer0 settings to application code and bug fixes
Signed-off-by: Ming Wei <mwei@ti.com>
-rw-r--r--soc/j721e/I2C_soc.c78
-rwxr-xr-xtest/eeprom_read/src/main_test.c7
2 files changed, 10 insertions, 75 deletions
diff --git a/soc/j721e/I2C_soc.c b/soc/j721e/I2C_soc.c
index 813ecd4..c3cbe87 100644
--- a/soc/j721e/I2C_soc.c
+++ b/soc/j721e/I2C_soc.c
@@ -60,11 +60,8 @@
60/* DMSC SYSFW C66x destination host int # for I2C0 */ 60/* DMSC SYSFW C66x destination host int # for I2C0 */
61#define I2C_TISCI_C66X_DST_HOST_IRQ0 (60U) 61#define I2C_TISCI_C66X_DST_HOST_IRQ0 (60U)
62 62
63/* C7x INTC int # for DMTimer0 */
64#define DMTimer_C7X_IRQ0 (14U)
65
66/* C7x INTC int # for I2C0 */ 63/* C7x INTC int # for I2C0 */
67#define I2C_C7X_IRQ0 (10U) 64#define I2C_C7X_IRQ0 (30U)
68 65
69#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2) 66#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
70static uint32_t I2C_socGetSciSrcID(uint32_t baseAddr); 67static uint32_t I2C_socGetSciSrcID(uint32_t baseAddr);
@@ -133,7 +130,7 @@ I2C_HwAttrs i2cInitCfg[I2C_HWIP_MAX_CNT] =
133#if defined (BUILD_C7X_1) 130#if defined (BUILD_C7X_1)
134 /* default configuration for I2C instance and DSP core on Main domain*/ 131 /* default configuration for I2C instance and DSP core on Main domain*/
135 CSL_I2C1_CFG_BASE, /* baseAddr */ 132 CSL_I2C1_CFG_BASE, /* baseAddr */
136 I2C_C7X_IRQ0, /* intNum */ 133 I2C_C7X_IRQ0 + 1, /* intNum */
137 CSLR_COMPUTE_CLUSTER0_GIC_SPI_I2C1_POINTRPEND_0 + I2C_CLEC_GIC_SPI_IN_EVT_OFFSET, /* eventId, input event # to CLEC */ 134 CSLR_COMPUTE_CLUSTER0_GIC_SPI_I2C1_POINTRPEND_0 + I2C_CLEC_GIC_SPI_IN_EVT_OFFSET, /* eventId, input event # to CLEC */
138#endif 135#endif
139 I2C_INPUT_CLK, 136 I2C_INPUT_CLK,
@@ -163,7 +160,7 @@ I2C_HwAttrs i2cInitCfg[I2C_HWIP_MAX_CNT] =
163#if defined (BUILD_C7X_1) 160#if defined (BUILD_C7X_1)
164 /* default configuration for I2C instance and DSP core on Main domain*/ 161 /* default configuration for I2C instance and DSP core on Main domain*/
165 CSL_I2C2_CFG_BASE, /* baseAddr */ 162 CSL_I2C2_CFG_BASE, /* baseAddr */
166 I2C_C7X_IRQ0, /* intNum */ 163 I2C_C7X_IRQ0 + 2, /* intNum */
167 CSLR_COMPUTE_CLUSTER0_GIC_SPI_I2C2_POINTRPEND_0 + I2C_CLEC_GIC_SPI_IN_EVT_OFFSET, /* eventId, input event # to CLEC */ 164 CSLR_COMPUTE_CLUSTER0_GIC_SPI_I2C2_POINTRPEND_0 + I2C_CLEC_GIC_SPI_IN_EVT_OFFSET, /* eventId, input event # to CLEC */
168#endif 165#endif
169 I2C_INPUT_CLK, 166 I2C_INPUT_CLK,
@@ -193,7 +190,7 @@ I2C_HwAttrs i2cInitCfg[I2C_HWIP_MAX_CNT] =
193#if defined (BUILD_C7X_1) 190#if defined (BUILD_C7X_1)
194 /* default configuration for I2C instance and DSP core on Main domain*/ 191 /* default configuration for I2C instance and DSP core on Main domain*/
195 CSL_I2C3_CFG_BASE, /* baseAddr */ 192 CSL_I2C3_CFG_BASE, /* baseAddr */
196 I2C_C7X_IRQ0, /* intNum */ 193 I2C_C7X_IRQ0 + 3, /* intNum */
197 CSLR_COMPUTE_CLUSTER0_GIC_SPI_I2C3_POINTRPEND_0 + I2C_CLEC_GIC_SPI_IN_EVT_OFFSET, /* eventId, input event # to CLEC */ 194 CSLR_COMPUTE_CLUSTER0_GIC_SPI_I2C3_POINTRPEND_0 + I2C_CLEC_GIC_SPI_IN_EVT_OFFSET, /* eventId, input event # to CLEC */
198#endif 195#endif
199 I2C_INPUT_CLK, 196 I2C_INPUT_CLK,
@@ -223,7 +220,7 @@ I2C_HwAttrs i2cInitCfg[I2C_HWIP_MAX_CNT] =
223#if defined (BUILD_C7X_1) 220#if defined (BUILD_C7X_1)
224 /* default configuration for I2C instance and DSP core on Main domain*/ 221 /* default configuration for I2C instance and DSP core on Main domain*/
225 CSL_I2C4_CFG_BASE, /* baseAddr */ 222 CSL_I2C4_CFG_BASE, /* baseAddr */
226 I2C_C7X_IRQ0, /* intNum */ 223 I2C_C7X_IRQ0 + 4, /* intNum */
227 CSLR_COMPUTE_CLUSTER0_GIC_SPI_I2C4_POINTRPEND_0 + I2C_CLEC_GIC_SPI_IN_EVT_OFFSET, /* eventId, input event # to CLEC */ 224 CSLR_COMPUTE_CLUSTER0_GIC_SPI_I2C4_POINTRPEND_0 + I2C_CLEC_GIC_SPI_IN_EVT_OFFSET, /* eventId, input event # to CLEC */
228#endif 225#endif
229 I2C_INPUT_CLK, 226 I2C_INPUT_CLK,
@@ -253,7 +250,7 @@ I2C_HwAttrs i2cInitCfg[I2C_HWIP_MAX_CNT] =
253#if defined (BUILD_C7X_1) 250#if defined (BUILD_C7X_1)
254 /* default configuration for I2C instance and DSP core on Main domain*/ 251 /* default configuration for I2C instance and DSP core on Main domain*/
255 CSL_I2C5_CFG_BASE, /* baseAddr */ 252 CSL_I2C5_CFG_BASE, /* baseAddr */
256 I2C_C7X_IRQ0, /* intNum */ 253 I2C_C7X_IRQ0 + 5, /* intNum */
257 CSLR_COMPUTE_CLUSTER0_GIC_SPI_I2C5_POINTRPEND_0 + I2C_CLEC_GIC_SPI_IN_EVT_OFFSET, /* eventId, input event # to CLEC */ 254 CSLR_COMPUTE_CLUSTER0_GIC_SPI_I2C5_POINTRPEND_0 + I2C_CLEC_GIC_SPI_IN_EVT_OFFSET, /* eventId, input event # to CLEC */
258#endif 255#endif
259 I2C_INPUT_CLK, 256 I2C_INPUT_CLK,
@@ -283,7 +280,7 @@ I2C_HwAttrs i2cInitCfg[I2C_HWIP_MAX_CNT] =
283#if defined (BUILD_C7X_1) 280#if defined (BUILD_C7X_1)
284 /* default configuration for I2C instance and DSP core on Main domain*/ 281 /* default configuration for I2C instance and DSP core on Main domain*/
285 CSL_I2C6_CFG_BASE, /* baseAddr */ 282 CSL_I2C6_CFG_BASE, /* baseAddr */
286 I2C_C7X_IRQ0, /* intNum */ 283 I2C_C7X_IRQ0 + 6, /* intNum */
287 CSLR_COMPUTE_CLUSTER0_GIC_SPI_I2C6_POINTRPEND_0 + I2C_CLEC_GIC_SPI_IN_EVT_OFFSET, /* eventId, input event # to CLEC */ 284 CSLR_COMPUTE_CLUSTER0_GIC_SPI_I2C6_POINTRPEND_0 + I2C_CLEC_GIC_SPI_IN_EVT_OFFSET, /* eventId, input event # to CLEC */
288#endif 285#endif
289 I2C_INPUT_CLK, 286 I2C_INPUT_CLK,
@@ -555,6 +552,7 @@ static int32_t I2C_configSocIntrPath(void *pHwAttrs, bool setIntrPath)
555 } 552 }
556 } 553 }
557#endif 554#endif
555
558#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2) 556#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
559 int32_t retVal; 557 int32_t retVal;
560 I2C_HwAttrs *hwAttrs = (I2C_HwAttrs *)(pHwAttrs); 558 I2C_HwAttrs *hwAttrs = (I2C_HwAttrs *)(pHwAttrs);
@@ -619,57 +617,6 @@ static int32_t I2C_configSocIntrPath(void *pHwAttrs, bool setIntrPath)
619 { 617 {
620 ret = I2C_ERROR; 618 ret = I2C_ERROR;
621 } 619 }
622
623 /* Set up C66x interrupt router for DMTimer0 */
624 if(setIntrPath)
625 {
626 memset (&rmIrqReq, 0, sizeof(rmIrqReq));
627 rmIrqReq.secondary_host = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;
628 rmIrqReq.src_id = TISCI_DEV_TIMER0;
629 rmIrqReq.src_index = 0; /* set to 0 for non-event based interrupt */
630
631 /* Set the destination interrupt */
632 rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_ID_VALID;
633 rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID;
634
635 /* Set the destination based on the core */
636 rmIrqReq.dst_id = dst_id;
637 rmIrqReq.dst_host_irq = 40; /* DMSC dest event, input to C66x INTC */
638 }
639 else
640 {
641 memset (&rmIrqRelease,0,sizeof(rmIrqRelease));
642 rmIrqRelease.secondary_host = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;
643 rmIrqRelease.src_id = TISCI_DEV_TIMER0;
644 rmIrqRelease.src_index = 0; /* set to 0 for non-event based interrupt */
645
646 /* Set the destination interrupt */
647 rmIrqRelease.valid_params |= TISCI_MSG_VALUE_RM_DST_ID_VALID;
648 rmIrqRelease.valid_params |= TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID;
649
650 /* Set the destination based on the core */
651 rmIrqRelease.dst_id = dst_id;
652 rmIrqRelease.dst_host_irq = 40;
653 }
654
655 /* Config event */
656 if(setIntrPath)
657 {
658 retVal = Sciclient_rmIrqSet(
659 (const struct tisci_msg_rm_irq_set_req *)&rmIrqReq,
660 &rmIrqResp,
661 SCICLIENT_SERVICE_WAIT_FOREVER);
662 }
663 else
664 {
665 retVal = Sciclient_rmIrqRelease(
666 (const struct tisci_msg_rm_irq_release_req *)&rmIrqRelease,
667 SCICLIENT_SERVICE_WAIT_FOREVER);
668 }
669 if(0U != retVal)
670 {
671 ret = I2C_ERROR;
672 }
673#endif 620#endif
674 621
675#if defined (BUILD_C7X_1) 622#if defined (BUILD_C7X_1)
@@ -677,7 +624,6 @@ static int32_t I2C_configSocIntrPath(void *pHwAttrs, bool setIntrPath)
677 I2C_HwAttrs *hwAttrs = (I2C_HwAttrs *)(pHwAttrs); 624 I2C_HwAttrs *hwAttrs = (I2C_HwAttrs *)(pHwAttrs);
678 CSL_ClecEventConfig cfgClec; 625 CSL_ClecEventConfig cfgClec;
679 CSL_CLEC_EVTRegs *clecBaseAddr = (CSL_CLEC_EVTRegs *)CSL_COMPUTE_CLUSTER0_CLEC_BASE; 626 CSL_CLEC_EVTRegs *clecBaseAddr = (CSL_CLEC_EVTRegs *)CSL_COMPUTE_CLUSTER0_CLEC_BASE;
680 uint32_t input = CSLR_COMPUTE_CLUSTER0_GIC_SPI_TIMER0_INTR_PEND_0 + 992; /* Used for Timer Interrupt */
681 627
682 /* Configure CLEC for I2C0 */ 628 /* Configure CLEC for I2C0 */
683 cfgClec.secureClaimEnable = FALSE; 629 cfgClec.secureClaimEnable = FALSE;
@@ -690,14 +636,6 @@ static int32_t I2C_configSocIntrPath(void *pHwAttrs, bool setIntrPath)
690 { 636 {
691 ret = I2C_ERROR; 637 ret = I2C_ERROR;
692 } 638 }
693
694 /* Configure CLEC for DMTimer0, SYS/BIOS uses interrupt 14 for DMTimer0 by default */
695 cfgClec.secureClaimEnable = FALSE;
696 cfgClec.evtSendEnable = TRUE;
697 cfgClec.rtMap = CSL_CLEC_RTMAP_CPU_ALL;
698 cfgClec.extEvtNum = 0;
699 cfgClec.c7xEvtNum = 14;
700 CSL_clecConfigEvent(clecBaseAddr, input, &cfgClec);
701#endif 639#endif
702 640
703 return(ret); 641 return(ret);
diff --git a/test/eeprom_read/src/main_test.c b/test/eeprom_read/src/main_test.c
index 980f319..795ce53 100755
--- a/test/eeprom_read/src/main_test.c
+++ b/test/eeprom_read/src/main_test.c
@@ -79,6 +79,7 @@
79#include <ti/csl/soc/j721e/src/cslr_intr_c66_corepac0.h> 79#include <ti/csl/soc/j721e/src/cslr_intr_c66_corepac0.h>
80#include <ti/csl/csl_clec.h> 80#include <ti/csl/csl_clec.h>
81#include <ti/drv/sciclient/sciclient.h> 81#include <ti/drv/sciclient/sciclient.h>
82
82/* Define the I2C test interface */ 83/* Define the I2C test interface */
83typedef struct I2C_Tests_s 84typedef struct I2C_Tests_s
84{ 85{
@@ -168,6 +169,7 @@ bool Board_initI2C(void)
168 { 169 {
169 return (false); 170 return (false);
170 } 171 }
172
171 I2C_init(); 173 I2C_init();
172 174
173 /* Get the default I2C init configurations */ 175 /* Get the default I2C init configurations */
@@ -208,12 +210,7 @@ bool Board_initI2C(void)
208 i2c_cfg.intNum = CSLR_MCU_ARMSS0_CPU0_INTR_WKUP_I2C0_POINTRPEND_0; 210 i2c_cfg.intNum = CSLR_MCU_ARMSS0_CPU0_INTR_WKUP_I2C0_POINTRPEND_0;
209 } 211 }
210#endif 212#endif
211#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
212 i2c_cfg.intNum = OSAL_REGINT_INTVEC_EVENT_COMBINER; /* intNum, use event combiner for C66x INTC */
213 i2c_cfg.eventId = 60; /* eventId, DMSC dest event, input to C66x INTC I2C_TISCI_C66X_DST_HOST_IRQ0 */
214#endif
215#if defined (BUILD_C7X_1) 213#if defined (BUILD_C7X_1)
216 i2c_cfg.intNum = 10, /* intNum */
217 i2c_cfg.eventId = CSLR_COMPUTE_CLUSTER0_GIC_SPI_WKUP_I2C0_POINTRPEND_0 + 992U, /* eventId, input event # to CLEC */ 214 i2c_cfg.eventId = CSLR_COMPUTE_CLUSTER0_GIC_SPI_WKUP_I2C0_POINTRPEND_0 + 992U, /* eventId, input event # to CLEC */
218#endif 215#endif
219#endif 216#endif