add support for lte dio mode

4 files changed, 277 insertions, 172 deletions

diff --git a/include/IQN2_defs.h b/include/IQN2_defs.h
index a516f48..4630a8e 100644
--- a/include/IQN2_defs.h
+++ b/include/IQN2_defs.h
@@ -720,6 +720,8 @@ typedef struct IQN2_DioEventObj{
                     uint32_t                   numCtlChannel;
                     /** Holds the AID2 SI delay on this Aid */
                     uint32_t                   siDelay;
+                    /** Setup the LTE traffic to use DIO instead of PKTDMA */
+                    uint32_t                               lteDio;
                     } IQN2_AidConfigObj, *IQN2_AidConfigHandle;
                                         
 /**
@@ -757,6 +759,8 @@ typedef struct IQN2_DioEventObj{
                                         uint32_t                   rsaOn;
                                         /** Set Egress UL traffic  */
                                         uint32_t                   egRsaOn;
+                                        /** Set if dio is used for LTE or WCDMA */
+                                        uint32_t                                   lteMode;
                     } IQN2_DioConfigObj, *IQN2_DioConfigHandle;
 
 /**
diff --git a/src/iqn2lld/IQN2_init.c b/src/iqn2lld/IQN2_init.c
index 207326c..e43cb67 100644
--- a/src/iqn2lld/IQN2_init.c
+++ b/src/iqn2lld/IQN2_init.c
@@ -176,7 +176,7 @@ const char* IQN2_getVersionStr (void)
     return iqn2LldVersionStr;
 }
 
-//Initialize IQN2 DIO buffers
+//Initialize IQN2 DIO buffers                           //FIXME need update for lte dio mode
 void
 IQN2_initDio(
                 IQN2_ConfigHandle  hIqn2
@@ -201,6 +201,16 @@ IQN2_initDio(
                         num_AxC_pe += hIqn2->ailConfig[j].numWcdmaPeAxC;        
                 }
                 num_AxC_pe += hIqn2->aidConfig.numWcdmaEgressAxC;
+                for (i=0;i<=(num_AxC_pe/16);i++)
+                {
+                    hIqn2->dioConfig[i].offsetPeDBCH = i*16;
+                    if(i == num_AxC_pe/16)
+                                hIqn2->dioConfig[i].numPeDBCH = num_AxC_pe%16;
+                        else
+                                hIqn2->dioConfig[i].numPeDBCH = 16;
+                }
+        } else {
+                num_AxC_pe = num_channel_pe;
         }
         
         if( num_channel_pd == 0)
@@ -210,24 +220,16 @@ IQN2_initDio(
                         num_AxC_pd += hIqn2->ailConfig[j].numWcdmaPdAxC;        
                 }
                 num_AxC_pd += hIqn2->aidConfig.numWcdmaIngressAxC;
-        }
-        
-        for (i=0;i<=(num_AxC_pe/16);i++)
-        {
-            hIqn2->dioConfig[i].offsetPeDBCH = i*16;
-            if(i == num_AxC_pe/16)
-                        hIqn2->dioConfig[i].numPeDBCH = num_AxC_pe%16;
-                else
-                        hIqn2->dioConfig[i].numPeDBCH = 16;
-        }
-        
-        for (i=0;i<=(num_AxC_pd/16);i++)
-        {
-                hIqn2->dioConfig[i].offsetPdDBCH = i*16;
-                if(i == num_AxC_pd/16)
-                        hIqn2->dioConfig[i].numPdDBCH = num_AxC_pd%16;
-                else
-                        hIqn2->dioConfig[i].numPdDBCH = 16;
+                for (i=0;i<=(num_AxC_pd/16);i++)
+                {
+                        hIqn2->dioConfig[i].offsetPdDBCH = i*16;
+                        if(i == num_AxC_pd/16)
+                                hIqn2->dioConfig[i].numPdDBCH = num_AxC_pd%16;
+                        else
+                                hIqn2->dioConfig[i].numPdDBCH = 16;
+                }
+        } else {
+                num_AxC_pd = num_channel_pd;
         }
 
     for (i=0; i<IQN2_MAX_NUM_DIO_ENGINE; i++)
@@ -622,18 +624,25 @@ IQN2_initHw(
             Iqn2_osalLog("Fatal Error: addAxCtoEgrGroupTable returned bad ID\n");
         } else {
             if (isNewGroup) {
-                if (lteCpType == IQN2_LTE_CPTYPE_NORMAL) {
-                    egrRadStdInfo[groupId].indexSc     = frameIndexSc;//start index
-                    egrRadStdInfo[groupId].indexTc     = frameIndexSc + ((MBSFN_FACTOR * IQN2_LTE_SYMBOL_NUM) - 1);//terminal index
-                    egrRadStdInfo[groupId].symbolTc    = IQN2_LTE_FRAME_SYMBOL_NUM-1;//140 symbols for LTE
-                    frameIndexSc += (MBSFN_FACTOR * IQN2_LTE_SYMBOL_NUM);
-                }
-                else { // Extended CP
-                    egrRadStdInfo[groupId].indexSc  = frameIndexSc;//start index
-                    egrRadStdInfo[groupId].indexTc  = frameIndexSc + (IQN2_LTE_SYMBOL_NUM_EXT_CP-1);//terminal index
-                    egrRadStdInfo[groupId].symbolTc = IQN2_LTE_FRAME_SYMBOL_NUM_EXT_CP-1;//120 symbols for LTE with extended CP
-                    frameIndexSc += IQN2_LTE_SYMBOL_NUM_EXT_CP;
-                }
+//              if(hIqn2->aidConfig.lteDio == 1)
+//              {
+//                      egrRadStdInfo[groupId].indexSc     = frameIndexSc;//start index
+//                                      egrRadStdInfo[groupId].indexTc     = frameIndexSc;//terminal index
+//                                      frameIndexSc += 1;
+//              } else {
+                                        if (lteCpType == IQN2_LTE_CPTYPE_NORMAL) {
+                                                egrRadStdInfo[groupId].indexSc     = frameIndexSc;//start index
+                                                egrRadStdInfo[groupId].indexTc     = frameIndexSc + ((MBSFN_FACTOR * IQN2_LTE_SYMBOL_NUM) - 1);//terminal index
+                                                egrRadStdInfo[groupId].symbolTc    = IQN2_LTE_FRAME_SYMBOL_NUM-1;//140 symbols for LTE
+                                                frameIndexSc += (MBSFN_FACTOR * IQN2_LTE_SYMBOL_NUM);
+                                        }
+                                        else { // Extended CP
+                                                egrRadStdInfo[groupId].indexSc  = frameIndexSc;//start index
+                                                egrRadStdInfo[groupId].indexTc  = frameIndexSc + (IQN2_LTE_SYMBOL_NUM_EXT_CP-1);//terminal index
+                                                egrRadStdInfo[groupId].symbolTc = IQN2_LTE_FRAME_SYMBOL_NUM_EXT_CP-1;//120 symbols for LTE with extended CP
+                                                frameIndexSc += IQN2_LTE_SYMBOL_NUM_EXT_CP;
+                                        }
+//              }
             }
         }
     }
@@ -716,17 +725,24 @@ IQN2_initHw(
             Iqn2_osalLog("Fatal Error: addAxCtoIngrGroupTable returned bad ID\n");
         } else {
             if (isNewGroup) {
-                if (lteCpType == IQN2_LTE_CPTYPE_NORMAL) {
-                    ingrRadStdInfo[groupId].indexSc     = frameIndexSc;//start index
-                    ingrRadStdInfo[groupId].indexTc     = frameIndexSc + (IQN2_LTE_SYMBOL_NUM-1);//terminal index
-                    ingrRadStdInfo[groupId].symbolTc    = IQN2_LTE_FRAME_SYMBOL_NUM-1;//140 symbols for LTE
-                    frameIndexSc += IQN2_LTE_SYMBOL_NUM;
-                } else { // Extended CP
-                    ingrRadStdInfo[groupId].indexSc  = frameIndexSc;//start index
-                    ingrRadStdInfo[groupId].indexTc  = frameIndexSc + (IQN2_LTE_SYMBOL_NUM_EXT_CP-1);//terminal index
-                    ingrRadStdInfo[groupId].symbolTc = IQN2_LTE_FRAME_SYMBOL_NUM_EXT_CP-1;//120 symbols for LTE with extended CP
-                    frameIndexSc += IQN2_LTE_SYMBOL_NUM_EXT_CP;
-                }
+//              if(hIqn2->aidConfig.lteDio == 1)
+//              {
+//                      ingrRadStdInfo[groupId].indexSc     = frameIndexSc;//start index
+//                      ingrRadStdInfo[groupId].indexTc     = frameIndexSc;//terminal index
+//                                      frameIndexSc += 1;
+//              } else {
+                                        if (lteCpType == IQN2_LTE_CPTYPE_NORMAL) {
+                                                ingrRadStdInfo[groupId].indexSc     = frameIndexSc;//start index
+                                                ingrRadStdInfo[groupId].indexTc     = frameIndexSc + (IQN2_LTE_SYMBOL_NUM-1);//terminal index
+                                                ingrRadStdInfo[groupId].symbolTc    = IQN2_LTE_FRAME_SYMBOL_NUM-1;//140 symbols for LTE
+                                                frameIndexSc += IQN2_LTE_SYMBOL_NUM;
+                                        } else { // Extended CP
+                                                ingrRadStdInfo[groupId].indexSc  = frameIndexSc;//start index
+                                                ingrRadStdInfo[groupId].indexTc  = frameIndexSc + (IQN2_LTE_SYMBOL_NUM_EXT_CP-1);//terminal index
+                                                ingrRadStdInfo[groupId].symbolTc = IQN2_LTE_FRAME_SYMBOL_NUM_EXT_CP-1;//120 symbols for LTE with extended CP
+                                                frameIndexSc += IQN2_LTE_SYMBOL_NUM_EXT_CP;
+                                        }
+//              }
             }
         }
     }
@@ -753,10 +769,16 @@ IQN2_initHw(
     {
         if (ingrGroupInfo[i].g.isLte)
         {
-                        FrameMsg1[i] = ingrGroupInfo[i].g.samplingRate * (IQN2_LTE20_FFT_SIZE + IQN2_LTE20_CYPRENORMAL1_SIZE) / IQN2_LTE20_SAMPLE_RATE;
-                        FrameMsg[i] = ingrGroupInfo[i].g.samplingRate * (IQN2_LTE20_FFT_SIZE + IQN2_LTE20_CYPRENORMAL_SIZE) / IQN2_LTE20_SAMPLE_RATE;
-                        FrameMsg2[i] = ingrGroupInfo[i].g.samplingRate * (IQN2_LTE20_FFT_SIZE + IQN2_LTE20_CYPREEXTENDED_SIZE) / IQN2_LTE20_SAMPLE_RATE;
-            FrameMsgTot[i] = FrameMsg1[i] + (6 * FrameMsg[i]);
+//              if ((ingrRadStdInfo[groupId].indexTc - ingrRadStdInfo[groupId].indexSc == 0))
+//                      {
+//                      FrameMsg[i] = ingrGroupInfo[i].g.samplingRate / 7680 * 2560;
+//                      FrameMsgTot[i] = FrameMsg[i];
+//                      } else {
+                                FrameMsg1[i] = ingrGroupInfo[i].g.samplingRate * (IQN2_LTE20_FFT_SIZE + IQN2_LTE20_CYPRENORMAL1_SIZE) / IQN2_LTE20_SAMPLE_RATE;
+                                FrameMsg[i] = ingrGroupInfo[i].g.samplingRate * (IQN2_LTE20_FFT_SIZE + IQN2_LTE20_CYPRENORMAL_SIZE) / IQN2_LTE20_SAMPLE_RATE;
+                                FrameMsg2[i] = ingrGroupInfo[i].g.samplingRate * (IQN2_LTE20_FFT_SIZE + IQN2_LTE20_CYPREEXTENDED_SIZE) / IQN2_LTE20_SAMPLE_RATE;
+                                FrameMsgTot[i] = FrameMsg1[i] + (6 * FrameMsg[i]);
+//                      }
         } else {
             FrameMsg[i] = 2560;
             FrameMsgTot[i] = FrameMsg[i];
@@ -781,7 +803,8 @@ IQN2_initHw(
         }
     }
 
-    for(i=0;i<hIqn2->aidConfig.numLteEgressAxC;i++){
+
+    for(i=0;i<hIqn2->aidConfig.numLteEgressAxC;i++){ //FIXME lteDIO
         topSetup.top_psr_cfg.drop_pkt[i] = 1;//1;
         topSetup.top_psr_cfg.pack_ps_data[i] = 1;//pack ps data for pktDMA chan
     }
@@ -819,17 +842,25 @@ IQN2_initHw(
     }
         
     for(i=0;i<hIqn2->aidConfig.numWcdmaEgressAxC;i++){
-        iqs2Setup.iqs2_egress_chan_cfg.egr_dio2_cfg[i].chan = hIqn2->aidConfig.firstWcdmaAxC + i;//DIO chan 0 ~ 15 is mapped to AIL0 chan 0 ~ 15
-        iqs2Setup.iqs2_egress_chan_cfg.egr_dio2_cfg[i].dest = IQN2FL_AID2_AXC;    //IQN2FL_AIL0_AXC; //destination is AIL0 AxC
+        iqs2Setup.iqs2_egress_chan_cfg.egr_dio2_cfg[i].chan = hIqn2->aidConfig.firstWcdmaAxC + i;//DIO chan 0 ~ 15 is mapped to AID chan 0 ~ 15
+        iqs2Setup.iqs2_egress_chan_cfg.egr_dio2_cfg[i].dest = IQN2FL_AID2_AXC;    //IQN2FL_AID_AXC; //destination is AID AxC
         iqs2Setup.iqs2_egress_chan_cfg.egr_dio2_cfg[i].psi_pri = 1;
         iqs2Setup.iqs2_egress_chan_cfg.egr_dio2_cfg[i].arb_pri = 1;
     }
 
         for(i=0;i<hIqn2->aidConfig.numLteEgressAxC;i++){
-            iqs2Setup.iqs2_egress_chan_cfg.egr_pktdma_cfg[i].chan = hIqn2->aidConfig.firstLteAxC + i;//pktDMA chan 0 ~ 3 is mapped to AID chan 0 ~ 3
-            iqs2Setup.iqs2_egress_chan_cfg.egr_pktdma_cfg[i].dest = IQN2FL_AID2_AXC; //destination is AID AxC
-        iqs2Setup.iqs2_egress_chan_cfg.egr_pktdma_cfg[i].arb_pri = 0;
-        iqs2Setup.iqs2_egress_chan_cfg.egr_pktdma_cfg[i].psi_pri = 0;
+                if(hIqn2->aidConfig.lteDio==1)
+                {
+                        iqs2Setup.iqs2_egress_chan_cfg.egr_dio2_cfg[i].chan = hIqn2->aidConfig.firstLteAxC + i;//DIO chan 0 ~ 15 is mapped to AID chan 0 ~ 15
+                        iqs2Setup.iqs2_egress_chan_cfg.egr_dio2_cfg[i].dest = IQN2FL_AID2_AXC;    //IQN2FL_AID_AXC; //destination is AID AxC
+                        iqs2Setup.iqs2_egress_chan_cfg.egr_dio2_cfg[i].psi_pri = 1;
+                        iqs2Setup.iqs2_egress_chan_cfg.egr_dio2_cfg[i].arb_pri = 1;
+                } else {
+                        iqs2Setup.iqs2_egress_chan_cfg.egr_pktdma_cfg[i].chan = hIqn2->aidConfig.firstLteAxC + i;//pktDMA chan 0 ~ 3 is mapped to AID chan 0 ~ 3
+                        iqs2Setup.iqs2_egress_chan_cfg.egr_pktdma_cfg[i].dest = IQN2FL_AID2_AXC; //destination is AID AxC
+                        iqs2Setup.iqs2_egress_chan_cfg.egr_pktdma_cfg[i].arb_pri = 0;
+                        iqs2Setup.iqs2_egress_chan_cfg.egr_pktdma_cfg[i].psi_pri = 0;
+                }
         }
 
         for(i=0;i<hIqn2->aidConfig.numCtlChannel;i++){
@@ -882,8 +913,14 @@ IQN2_initHw(
     }
         
         for(i=0;i<hIqn2->aidConfig.numLteIngressAxC;i++){
-                iqs2Setup.iqs2_ingress_chan_cfg.aid2_axc_lut_cfg[i + hIqn2->aidConfig.firstLteAxC].chan = i;//AID chan 0 ~ 3 is mapped to PktDMA chan 0 ~ 3
-                iqs2Setup.iqs2_ingress_chan_cfg.aid2_axc_lut_cfg[i + hIqn2->aidConfig.firstLteAxC].dest = IQN2FL_PKTDMA;//destination is PktDMA
+                if(hIqn2->aidConfig.lteDio==1)
+                {
+                        iqs2Setup.iqs2_ingress_chan_cfg.aid2_axc_lut_cfg[i + hIqn2->aidConfig.firstLteAxC].chan = i;//AID chan 0 ~ 3 is mapped to PktDMA chan 0 ~ 3
+                        iqs2Setup.iqs2_ingress_chan_cfg.aid2_axc_lut_cfg[i + hIqn2->aidConfig.firstLteAxC].dest = IQN2FL_DIO2;//destination is PktDMA
+                } else {
+                        iqs2Setup.iqs2_ingress_chan_cfg.aid2_axc_lut_cfg[i + hIqn2->aidConfig.firstLteAxC].chan = i;//AID chan 0 ~ 3 is mapped to PktDMA chan 0 ~ 3
+                        iqs2Setup.iqs2_ingress_chan_cfg.aid2_axc_lut_cfg[i + hIqn2->aidConfig.firstLteAxC].dest = IQN2FL_PKTDMA;//destination is PktDMA
+                }
         }
         
         for(i=0;i<hIqn2->aidConfig.numCtlChannel;i++){
@@ -914,7 +951,6 @@ IQN2_initHw(
     }
     if (enableDio)
     {
-        uint32_t firstDioAxC = 0;
         /********* DIO Core setup ***************************/
 #ifdef DEVICE_LE
         dio2Setup.dio2_global_cfg_rsa_big_endian  = 0;//little endian order for UL RSA data
@@ -936,6 +972,10 @@ IQN2_initHw(
                     dio2Setup.dio2_core_egress.dma_cfg0[j].dma_num_qwd = IQN2FL_2QW;//2 QWD for UL
                     dio2Setup.dio2_core_egress.dma_cfg0[j].dma_brst_ln = IQN2FL_2QW;//2 QWD per burst
                     dio2Setup.dio2_core_egress.dma_cfg0[j].rsa_cnvrt_en = 1;
+                } else if (hIqn2->dioConfig[j].lteMode == 1){
+                        dio2Setup.dio2_core_egress.dma_cfg0[j].dma_num_qwd = IQN2FL_4QW;//1 QWD for DL
+                                        dio2Setup.dio2_core_egress.dma_cfg0[j].dma_brst_ln = IQN2FL_4QW;//1 QWD per burst
+                                        dio2Setup.dio2_core_egress.dma_cfg0[j].rsa_cnvrt_en = 0;
                 } else {
                     dio2Setup.dio2_core_egress.dma_cfg0[j].dma_num_qwd = IQN2FL_1QW;//1 QWD for DL
                     dio2Setup.dio2_core_egress.dma_cfg0[j].dma_brst_ln = IQN2FL_1QW;//1 QWD per burst
@@ -945,7 +985,11 @@ IQN2_initHw(
                 if (hIqn2->dioConfig[j].usedWithTAC == 0)
                 {
                     dio2Setup.dio2_core_egress.dma_cfg0[j].dma_num_blks = hIqn2->dioConfig[j].outNumBlock - 1;//DIO_NUM_BLOCK -1;//Set N-1
-                    dio2Setup.dio2_core_egress.dma_cfg1_dma_blk_addr_stride[j] = (dio2Setup.dio2_core_egress.dma_cfg0[j].dma_num_qwd)+1;
+                    if (hIqn2->dioConfig[j].lteMode == 1){
+                        dio2Setup.dio2_core_egress.dma_cfg1_dma_blk_addr_stride[j] = 4;
+                    } else {
+                        dio2Setup.dio2_core_egress.dma_cfg1_dma_blk_addr_stride[j] = (dio2Setup.dio2_core_egress.dma_cfg0[j].dma_num_qwd)+1;
+                    }
                 } else {
                     if (hIqn2->dioConfig[j].outNumBlock <= 64)
                         dio2Setup.dio2_core_egress.dma_cfg0[j].dma_num_blks = hIqn2->dioConfig[j].outNumBlock - 1;//DIO_NUM_BLOCK -1;//Set N-1
@@ -981,6 +1025,10 @@ IQN2_initHw(
                     dio2Setup.dio2_core_ingress.dma_cfg0[j].dma_num_qwd = IQN2FL_2QW;//2 QWD for UL
                     dio2Setup.dio2_core_ingress.dma_cfg0[j].dma_brst_ln = IQN2FL_2QW;//2 QWD per burst
                     dio2Setup.dio2_core_ingress.dma_cfg0[j].rsa_cnvrt_en = 1;
+                } else if (hIqn2->dioConfig[j].lteMode == 1){
+                        dio2Setup.dio2_core_ingress.dma_cfg0[j].dma_num_qwd = IQN2FL_4QW;//1 QWD for DL
+                                        dio2Setup.dio2_core_ingress.dma_cfg0[j].dma_brst_ln = IQN2FL_4QW;//1 QWD per burst
+                                        dio2Setup.dio2_core_ingress.dma_cfg0[j].rsa_cnvrt_en = 0;
                 } else {
                     dio2Setup.dio2_core_ingress.dma_cfg0[j].dma_num_qwd = IQN2FL_1QW;//1 QWD for DL
                     dio2Setup.dio2_core_ingress.dma_cfg0[j].dma_brst_ln = IQN2FL_1QW;//1 QWD per burst
@@ -990,7 +1038,11 @@ IQN2_initHw(
 
                 if (hIqn2->dioConfig[j].usedWithRAC == 0){
                     dio2Setup.dio2_core_ingress.dma_cfg0[j].dma_num_blks = hIqn2->dioConfig[j].inNumBlock - 1; //DIO_NUM_BLOCK -1;//Set N-1
-                    dio2Setup.dio2_core_ingress.dma_cfg1_dma_blk_addr_stride[j] = (dio2Setup.dio2_core_ingress.dma_cfg0[j].dma_num_qwd)+1;//1qwd per AxC
+                    if (hIqn2->dioConfig[j].lteMode == 1){
+                        dio2Setup.dio2_core_ingress.dma_cfg1_dma_blk_addr_stride[j] = 4;//1qwd per AxC
+                    } else {
+                        dio2Setup.dio2_core_ingress.dma_cfg1_dma_blk_addr_stride[j] = (dio2Setup.dio2_core_ingress.dma_cfg0[j].dma_num_qwd)+1;//1qwd per AxC
+                    }
                 } else {
                     // The fact that the RAC FE is mapped with a jump of 0x800 every 8 chips with 4 blocks every 32-chip period
                     //  -> Block Stride is 0x80
@@ -1016,35 +1068,37 @@ IQN2_initHw(
 
 
         /** DIO SI setup. Be careful! DIO SI has reversed order of Egress/Ingress when compared to SoC level order ***/
-        if(hIqn2->aidConfig.aidEnable)
-        {
-            firstDioAxC = hIqn2->aidConfig.firstWcdmaAxC;
-        } else {
-            for  (k=0;k<IQN2_MAX_NUM_AIL;k++)
-            {
-                if (hIqn2->ailConfig[k].numWcdmaPeAxC != 0)
-                    firstDioAxC = hIqn2->ailConfig[k].firstWcdmaAxC;
-            }
-        }
 
         //DIO SI ingress for SoC level egress operation (matched with AIL egress)
         for(j=0; j<IQN2_MAX_NUM_DIO_ENGINE;j++)
         {
             for(i = 0; i < hIqn2->dioConfig[j].numPeDBCH; i++){
                 dio2Setup.dio2_ife_chan_cfg_grp[i].chan_en = 1;
-                dio2Setup.dio2_ife_chan_cfg_grp[i].chan_radio_sel = (Iqn2Fl_ChanRadioSel) IQN2_getEgressRadioStandardId(i + firstDioAxC);
+                dio2Setup.dio2_ife_chan_cfg_grp[i].chan_radio_sel = (Iqn2Fl_ChanRadioSel) IQN2_getEgressRadioStandardId(i + hIqn2->dioConfig[j].offsetPeDBCH);
                 dio2Setup.dio2_ife_chan_cfg_grp[i].chan_axc_offset = 0;//fine AxC offset within QWD level. normally set to zero
             }
         }
 
         for (i=0;i<IQN2_MAX_NUM_RADIO_STANDARD;i++)
         {
-            if((egrGroupInfo[i].g.isLte == 0) && (egrGroupInfo[i].g.isPopulated == 1))
+            if((egrGroupInfo[i].g.isPopulated == 1) && ((egrGroupInfo[i].g.isLte == 0) || ((egrGroupInfo[i].g.isLte==1)&&(hIqn2->aidConfig.lteDio==1))))
             {
                 dio2Setup.dio2_ife_radio_std_grp.ife_frm_tc_cfg[i].sym_tc = egrRadStdInfo[i].symbolTc;//15 WCDMA slots. Set N-1
                 dio2Setup.dio2_ife_radio_std_grp.ife_frm_tc_cfg[i].index_sc = egrRadStdInfo[i].indexSc;
                 dio2Setup.dio2_ife_radio_std_grp.ife_frm_tc_cfg[i].index_tc = egrRadStdInfo[i].indexTc;
-                dio2Setup.ife_frm_samp_tc_cfg_samp_tc[egrRadStdInfo[i].indexSc] = FrameMsg[i] - 1;//Set N-1
+                if(egrGroupInfo[i].g.isLte == 0)
+                {
+                        dio2Setup.ife_frm_samp_tc_cfg_samp_tc[egrRadStdInfo[i].indexSc] = FrameMsg[i] - 1;//Set N-1
+                } else {
+                                        dio2Setup.ife_frm_samp_tc_cfg_samp_tc[egrRadStdInfo[i].indexSc] = FrameMsg1[i] - 1;//Set N-1
+                                        for(j=1;j<(IQN2_LTE_SYMBOL_NUM);j++){
+                                                dio2Setup.ife_frm_samp_tc_cfg_samp_tc[egrRadStdInfo[i].indexSc+j] = FrameMsg[i]- 1;//frame message terminal count for other 6 normal cyclic prefix LTE symbols
+                                        }
+                                        for(j = IQN2_LTE_SYMBOL_NUM; j < (MBSFN_FACTOR * IQN2_LTE_SYMBOL_NUM); j++) {
+                                                dio2Setup.ife_frm_samp_tc_cfg_samp_tc[egrRadStdInfo[i].indexSc + j] =
+                                                dio2Setup.ife_frm_samp_tc_cfg_samp_tc[egrRadStdInfo[i].indexSc + (j - IQN2_LTE_SYMBOL_NUM)];
+                                        }
+                }
             }
         }
 
@@ -1055,19 +1109,27 @@ IQN2_initHw(
         {
             for(i = 0; i < hIqn2->dioConfig[j].numPdDBCH; i++){
                 dio2Setup.dio2_efe_cfg_grp.chan_en[i] = 1;
-                dio2Setup.dio2_efe_cfg_grp.chan_radio_sel[i] = (Iqn2Fl_ChanRadioSel) IQN2_getIngressRadioStandardId(i + firstDioAxC);//use radio standard 0 for WCDMA
+                dio2Setup.dio2_efe_cfg_grp.chan_radio_sel[i] = (Iqn2Fl_ChanRadioSel) IQN2_getIngressRadioStandardId(i + hIqn2->dioConfig[j].offsetPdDBCH);//use radio standard 0 for WCDMA
                 dio2Setup.efe_chan_axc_offset_cfg[i] = 0;//for CPRI,this should be matched with AIL PD AxC offset
             }
         }
 
         for (i=0;i<IQN2_MAX_NUM_RADIO_STANDARD;i++)
         {
-            if((ingrGroupInfo[i].g.isLte == 0) && (ingrGroupInfo[i].g.isPopulated == 1))
+                        if((ingrGroupInfo[i].g.isPopulated == 1) && ((ingrGroupInfo[i].g.isLte == 0) || ((ingrGroupInfo[i].g.isLte==1)&&(hIqn2->aidConfig.lteDio==1))))
             {
                 dio2Setup.dio2_efe_radio_std_grp.efe_frm_tc_cfg[i].sym_tc = ingrRadStdInfo[i].symbolTc;//15 WCDMA slots. Set N-1
                 dio2Setup.dio2_efe_radio_std_grp.efe_frm_tc_cfg[i].index_sc = ingrRadStdInfo[i].indexSc;
                 dio2Setup.dio2_efe_radio_std_grp.efe_frm_tc_cfg[i].index_tc = ingrRadStdInfo[i].indexTc;
-                dio2Setup.efe_frm_samp_tc_cfg[ingrRadStdInfo[i].indexSc] = FrameMsg[i] - 1;//Set N-1
+                if(ingrGroupInfo[i].g.isLte == 0)
+                {
+                        dio2Setup.efe_frm_samp_tc_cfg[ingrRadStdInfo[i].indexSc] = FrameMsg[i] - 1;//Set N-1
+                } else {
+                        dio2Setup.efe_frm_samp_tc_cfg[ingrRadStdInfo[i].indexSc] = FrameMsg1[i] - 1;//Set N-1
+                        for(j=1;j<(IQN2_LTE_SYMBOL_NUM);j++){
+                                dio2Setup.efe_frm_samp_tc_cfg[ingrRadStdInfo[i].indexSc+j] = FrameMsg[i] - 1;//Set N-1
+                        }
+                }
             }
         }
 
@@ -1081,9 +1143,9 @@ IQN2_initHw(
 
         for (i=0;i<IQN2_MAX_NUM_RADIO_STANDARD;i++)
         {
-            if((ingrGroupInfo[i].g.isLte == 0) && (ingrGroupInfo[i].g.isPopulated == 1))
+                if((ingrGroupInfo[i].g.isPopulated == 1) && ((ingrGroupInfo[i].g.isLte == 0) || ((ingrGroupInfo[i].g.isLte==1)&&(hIqn2->aidConfig.lteDio==1))))
             {
-                dio2Setup.efe_rad_std_sch_cfg_tdm_start[i] = 0;
+                dio2Setup.efe_rad_std_sch_cfg_tdm_start[i] = i*16;                                              //FIXME lteDio
                 dio2Setup.efe_rad_std_sch_cfg_tdm_len[i] = 16;//ingrGroupInfo[i].endAxC - ingrGroupInfo[i].startAxC;            //FIXME TODO try new settings for this value
                 dio2Setup.efe_rad_std_sch_cfg_tdm_en[i] = 1;
             }
@@ -1098,22 +1160,19 @@ IQN2_initHw(
                 if ((hIqn2->protocol == IQN2FL_PROTOCOL_CPRI) || (hIqn2->protocol == IQN2FL_PROTOCOL_DFE_245_76))
                 {
                     dio2Setup.uat_dio_egr_radt_tc_cfg_val[j] = IQN2_CPRI_CLOCK_COUNT_TC_PHY_TIMER;//CPRI frame length with 245.76 MHz clock
-                    if (hIqn2->dioConfig[j].egRsaOn == 1)
-                        dio2Setup.uat_evt_clk_cnt_tc_cfg_val[16+j] = (64 * 8) - 1;//8 chip event for UL
-                    else
-                        dio2Setup.uat_evt_clk_cnt_tc_cfg_val[16+j] = (64 * 4) - 1;//4 chip event for DL
+                } else if (hIqn2->protocol == IQN2FL_PROTOCOL_DFE_368_64){
+                        dio2Setup.uat_dio_egr_radt_tc_cfg_val[j] = IQN2_DFE_368_64_CLOCK_COUNT_TC_PHY_TIMER;
                 } else if (hIqn2->protocol == IQN2FL_PROTOCOL_OBSAI){  //OBSAI
                     dio2Setup.uat_dio_egr_radt_tc_cfg_val[j] = IQN2_OBSAI_CLOCK_COUNT_TC_PHY_TIMER;//OBSAI frame length with 307.20 MHz clock
-                    if (hIqn2->dioConfig[j].egRsaOn == 1)
-                        dio2Setup.uat_evt_clk_cnt_tc_cfg_val[16+j] = (80 * 8) - 1;//4 chip event for DL
-                    else
-                        dio2Setup.uat_evt_clk_cnt_tc_cfg_val[16+j] = (80 * 4) - 1;//4 chip event for DL
-                } else if (hIqn2->protocol == IQN2FL_PROTOCOL_DFE_368_64){
-                    dio2Setup.uat_dio_egr_radt_tc_cfg_val[j] = IQN2_DFE_368_64_CLOCK_COUNT_TC_PHY_TIMER;//DFE frame length with 368.64 MHz clock
-                    if (hIqn2->dioConfig[j].egRsaOn == 1)
-                        dio2Setup.uat_evt_clk_cnt_tc_cfg_val[16+j] = (96 * 8) - 1;//4 chip event for DL
-                    else
-                        dio2Setup.uat_evt_clk_cnt_tc_cfg_val[16+j] = (96 * 4) - 1;//4 chip event for DL
+                }
+                if(hIqn2->dioConfig[j].lteMode == 1)
+                {
+                        dio2Setup.uat_evt_clk_cnt_tc_cfg_val[16+j] = (((dio2Setup.uat_dio_egr_radt_tc_cfg_val[j]+1)/FrameMsgTot[IQN2_getEgressRadioStandardId(hIqn2->dioConfig[j].offsetPeDBCH)]/20) * 16) - 1;//16 sample event for Lte
+                } else {
+                                        if (hIqn2->dioConfig[j].egRsaOn == 1)
+                                                dio2Setup.uat_evt_clk_cnt_tc_cfg_val[16+j] = (((dio2Setup.uat_dio_egr_radt_tc_cfg_val[j]+1)/FrameMsgTot[IQN2_getEgressRadioStandardId(hIqn2->dioConfig[j].offsetPeDBCH)]/15) * 8) - 1;//8 sample event for UL
+                                        else
+                                                dio2Setup.uat_evt_clk_cnt_tc_cfg_val[16+j] = (((dio2Setup.uat_dio_egr_radt_tc_cfg_val[j]+1)/FrameMsgTot[IQN2_getEgressRadioStandardId(hIqn2->dioConfig[j].offsetPeDBCH)]/15) * 4) - 1;//4 sample event for DL
                 }
                 dio2Setup.uat_dio_egr_radt_offset_cfg_val[j] = 0;//not used for DIAG_SYNC test mode
                 dio2Setup.uat_evt_radt_cmp_cfg_val[16+j] = 0;//No initial delay
@@ -1124,25 +1183,30 @@ IQN2_initHw(
         //DIO SI Ingress RADT is not used (SoC level DIO egress doesn't require event)
 
         //DIO SI Egress RADT0 with event0 (Used for SoC level Ingress operation)
-        if ((hIqn2->protocol == IQN2FL_PROTOCOL_CPRI) || (hIqn2->protocol == IQN2FL_PROTOCOL_DFE_245_76))
+        for (j=0;j<IQN2_MAX_NUM_DIO_ENGINE;j++)
         {
-            dio2Setup.uat_egr_radt_tc_cfg_val[IQN2_getIngressRadioStandardId(firstDioAxC)] = IQN2_CPRI_CLOCK_COUNT_TC_PHY_TIMER;//CPRI frame length with 245.76 MHz clock
-            dio2Setup.uat_egr_radt_offset_cfg_val[IQN2_getIngressRadioStandardId(firstDioAxC)] = 0;//not used for DIAG_SYNC test mode
-            if (hIqn2->aidConfig.aidEnable)
-                dio2Setup.uat_evt_radt_cmp_cfg_val[IQN2_getIngressRadioStandardId(firstDioAxC)] = hIqn2->aidConfig.siDelay + 500;//(AID2 SI offset) + 500 (ingress pipe delay)
-            else
-                dio2Setup.uat_evt_radt_cmp_cfg_val[IQN2_getIngressRadioStandardId(firstDioAxC)] = hIqn2->ailConfig[0].pe2Offset + 500;//pi + 500 (ingress pipe delay)
-            dio2Setup.uat_evt_clk_cnt_tc_cfg_val[IQN2_getIngressRadioStandardId(firstDioAxC)] = (64 * 4) - 1;//4 sample event
-        } else if(hIqn2->protocol == IQN2FL_PROTOCOL_OBSAI){            //OBSAI
-            dio2Setup.uat_egr_radt_tc_cfg_val[IQN2_getIngressRadioStandardId(firstDioAxC)] = IQN2_OBSAI_CLOCK_COUNT_TC_PHY_TIMER;//OBSAI frame length with 307.20 MHz clock
-            dio2Setup.uat_egr_radt_offset_cfg_val[IQN2_getIngressRadioStandardId(firstDioAxC)] = 0;//not used for DIAG_SYNC test mode
-            dio2Setup.uat_evt_radt_cmp_cfg_val[IQN2_getIngressRadioStandardId(firstDioAxC)] = dio2Setup.uat_evt_radt_cmp_cfg_val[IQN2_getIngressRadioStandardId(firstDioAxC)] + 500;//(DIO SI delay) + (ingress pipe delay)
-            dio2Setup.uat_evt_clk_cnt_tc_cfg_val[IQN2_getIngressRadioStandardId(firstDioAxC)] = (80 * 4) - 1;//4 sample event
-        } else if (hIqn2->protocol == IQN2FL_PROTOCOL_DFE_368_64){
-            dio2Setup.uat_egr_radt_tc_cfg_val[IQN2_getIngressRadioStandardId(firstDioAxC)] = IQN2_DFE_368_64_CLOCK_COUNT_TC_PHY_TIMER;//DFE frame length with 368.64 MHz clock
-            dio2Setup.uat_egr_radt_offset_cfg_val[IQN2_getIngressRadioStandardId(firstDioAxC)] = 0;//not used for DIAG_SYNC test mode
-            dio2Setup.uat_evt_radt_cmp_cfg_val[IQN2_getIngressRadioStandardId(firstDioAxC)] = hIqn2->aidConfig.siDelay + 500;//(DIO SI delay) + (ingress pipe delay)
-            dio2Setup.uat_evt_clk_cnt_tc_cfg_val[IQN2_getIngressRadioStandardId(firstDioAxC)] = (96 * 4) - 1;//4 sample event
+            if(hIqn2->dioConfig[j].numPdDBCH != 0)
+            {
+                                if ((hIqn2->protocol == IQN2FL_PROTOCOL_CPRI) || (hIqn2->protocol == IQN2FL_PROTOCOL_DFE_245_76))
+                                {
+                                        dio2Setup.uat_egr_radt_tc_cfg_val[IQN2_getIngressRadioStandardId(hIqn2->dioConfig[j].offsetPdDBCH)] = IQN2_CPRI_CLOCK_COUNT_TC_PHY_TIMER;//CPRI frame length with 245.76 MHz clock
+                                } else if (hIqn2->protocol == IQN2FL_PROTOCOL_DFE_368_64){
+                                        dio2Setup.uat_egr_radt_tc_cfg_val[IQN2_getIngressRadioStandardId(hIqn2->dioConfig[j].offsetPdDBCH)] = IQN2_DFE_368_64_CLOCK_COUNT_TC_PHY_TIMER;//DFE frame length with 368.64 MHz clock
+                                } else if(hIqn2->protocol == IQN2FL_PROTOCOL_OBSAI){            //OBSAI
+                                        dio2Setup.uat_egr_radt_tc_cfg_val[IQN2_getIngressRadioStandardId(hIqn2->dioConfig[j].offsetPdDBCH)] = IQN2_OBSAI_CLOCK_COUNT_TC_PHY_TIMER;//OBSAI frame length with 307.20 MHz clock
+                                }
+                                dio2Setup.uat_egr_radt_offset_cfg_val[IQN2_getIngressRadioStandardId(hIqn2->dioConfig[j].offsetPdDBCH)] = 0;//not used for DIAG_SYNC test mode
+                                if (hIqn2->aidConfig.aidEnable)
+                                        dio2Setup.uat_evt_radt_cmp_cfg_val[IQN2_getIngressRadioStandardId(hIqn2->dioConfig[j].offsetPdDBCH)] = hIqn2->aidConfig.siDelay + hIqn2->AxCconfig[hIqn2->dioConfig[j].offsetPdDBCH].ingressAxCOffset + 500;//(AID2 SI offset) + 500 (ingress pipe delay)
+                                else
+                                        dio2Setup.uat_evt_radt_cmp_cfg_val[IQN2_getIngressRadioStandardId(hIqn2->dioConfig[j].offsetPdDBCH)] = hIqn2->ailConfig[0].pe2Offset + 500;//pi + 500 (ingress pipe delay)
+
+                                if(hIqn2->dioConfig[j].lteMode == 1){
+                                        dio2Setup.uat_evt_clk_cnt_tc_cfg_val[IQN2_getIngressRadioStandardId(hIqn2->dioConfig[j].offsetPdDBCH)] = ((dio2Setup.uat_egr_radt_tc_cfg_val[IQN2_getIngressRadioStandardId(hIqn2->dioConfig[j].offsetPdDBCH)]+1) / FrameMsgTot[IQN2_getIngressRadioStandardId(hIqn2->dioConfig[j].offsetPdDBCH)] / 20 * 4) - 1;//4 sample event
+                                } else {
+                                        dio2Setup.uat_evt_clk_cnt_tc_cfg_val[IQN2_getIngressRadioStandardId(hIqn2->dioConfig[j].offsetPdDBCH)] = ((dio2Setup.uat_egr_radt_tc_cfg_val[IQN2_getIngressRadioStandardId(hIqn2->dioConfig[j].offsetPdDBCH)]+1) / FrameMsgTot[IQN2_getIngressRadioStandardId(hIqn2->dioConfig[j].offsetPdDBCH)] / 15 * 4) - 1;//4 sample event
+                                }
+            }
         }
 
         for (j=0;j<IQN2_MAX_NUM_DIO_ENGINE;j++)
@@ -1150,38 +1214,28 @@ IQN2_initHw(
             if(hIqn2->dioConfig[j].numPdDBCH != 0)
             {
                 //DIO Core Ingress RADT0 with event19 (Used for Soc level Ingress operation)
-                if ((hIqn2->protocol == IQN2FL_PROTOCOL_CPRI) || (hIqn2->protocol == IQN2FL_PROTOCOL_DFE_245_76))
-                {
+                if ((hIqn2->protocol == IQN2FL_PROTOCOL_CPRI) || (hIqn2->protocol == IQN2FL_PROTOCOL_DFE_245_76)) {
                     dio2Setup.uat_dio_ing_radt_tc_cfg_val[j] = IQN2_CPRI_CLOCK_COUNT_TC_PHY_TIMER;//CPRI frame length with 245.76 MHz clock
-                    if (hIqn2->dioConfig[j].rsaOn == 1)
-                    {
-                        dio2Setup.uat_evt_clk_cnt_tc_cfg_val[19+j] = (64 * 8) - 1;//8 chip event for UL
-                        dio2Setup.uat_evt_radt_cmp_cfg_val[19+j] = 1230;//DIO SI delay + 480 = 1230 clock delay for 8 chip DMA
-                    } else {
-                        dio2Setup.uat_evt_clk_cnt_tc_cfg_val[19+j] = (64 * 4) - 1;//4 chip event for DL
-                        dio2Setup.uat_evt_radt_cmp_cfg_val[19+j] = 990;//DIO SI delay + 240 = 1400 clock delay for 4 chip DMA
-                    }
-                } else if(hIqn2->protocol == IQN2FL_PROTOCOL_OBSAI){            //OBSAI
-                    dio2Setup.uat_dio_ing_radt_tc_cfg_val[j] = IQN2_OBSAI_CLOCK_COUNT_TC_PHY_TIMER;//OBSAI frame length with 307.20 MHz clock
-                    if (hIqn2->dioConfig[j].rsaOn == 1)
-                    {
-                        dio2Setup.uat_evt_clk_cnt_tc_cfg_val[19+j] = (80 * 8) - 1;//8 chip event for UL
-                        dio2Setup.uat_evt_radt_cmp_cfg_val[19+j] = 1230;//DIO SI delay + 480 = 1230 clock delay for 8 chip DMA
-                    } else {
-                        dio2Setup.uat_evt_clk_cnt_tc_cfg_val[19+j] = (80 * 4) - 1;//4 chip event for DL
-                            dio2Setup.uat_evt_radt_cmp_cfg_val[19+j] = 1090;//DIO SI delay + 240 = 1400 clock delay for 4 chip DMA
-                        }
-                } else if(hIqn2->protocol == IQN2FL_PROTOCOL_DFE_368_64){
-                    dio2Setup.uat_dio_ing_radt_tc_cfg_val[j] = IQN2_DFE_368_64_CLOCK_COUNT_TC_PHY_TIMER;//DFE frame length with 368.64 MHz clock
-                    if (hIqn2->dioConfig[j].rsaOn == 1)
-                    {
-                        dio2Setup.uat_evt_clk_cnt_tc_cfg_val[19+j] = (96 * 8) - 1;//8 chip event for UL
-                        dio2Setup.uat_evt_radt_cmp_cfg_val[19+j] = 1230;//DIO SI delay + 480 = 1230 clock delay for 8 chip DMA
-                    } else {
-                        dio2Setup.uat_evt_clk_cnt_tc_cfg_val[19+j] = (96 * 4) - 1;//4 chip event for DL
-                        dio2Setup.uat_evt_radt_cmp_cfg_val[19+j] = 990;//DIO SI delay + 240 = 1400 clock delay for 4 chip DMA
-                    }
+                } else if (hIqn2->protocol == IQN2FL_PROTOCOL_OBSAI) {
+                        dio2Setup.uat_dio_ing_radt_tc_cfg_val[j] = IQN2_OBSAI_CLOCK_COUNT_TC_PHY_TIMER;//OBSAI frame length with 307.20 MHz clock
+                } else if (hIqn2->protocol == IQN2FL_PROTOCOL_DFE_368_64) {
+                        dio2Setup.uat_dio_ing_radt_tc_cfg_val[j] = IQN2_DFE_368_64_CLOCK_COUNT_TC_PHY_TIMER;//DFE frame length with 368.64 MHz clock
+                }
+
+                if (hIqn2->dioConfig[j].lteMode == 1) {
+                        dio2Setup.uat_evt_clk_cnt_tc_cfg_val[19+j] = (((dio2Setup.uat_dio_ing_radt_tc_cfg_val[j]+1)/FrameMsgTot[IQN2_getIngressRadioStandardId(hIqn2->dioConfig[j].offsetPdDBCH)]/20) * 16) - 1;
+                        dio2Setup.uat_evt_radt_cmp_cfg_val[19+j] = dio2Setup.uat_evt_radt_cmp_cfg_val[IQN2_getIngressRadioStandardId(hIqn2->dioConfig[j].offsetPdDBCH)] + (dio2Setup.uat_evt_clk_cnt_tc_cfg_val[19+j]);//DIO SI delay + n chip delay
+                } else {
+                                        if (hIqn2->dioConfig[j].rsaOn == 1)
+                                        {
+                                                dio2Setup.uat_evt_clk_cnt_tc_cfg_val[19+j] = (((dio2Setup.uat_dio_ing_radt_tc_cfg_val[j]+1)/FrameMsgTot[IQN2_getIngressRadioStandardId(hIqn2->dioConfig[j].offsetPdDBCH)]/15) * 8) - 1;
+                                                dio2Setup.uat_evt_radt_cmp_cfg_val[19+j] = dio2Setup.uat_evt_radt_cmp_cfg_val[IQN2_getIngressRadioStandardId(hIqn2->dioConfig[j].offsetPdDBCH)] + 480;//DIO SI delay + 480 = 1230 clock delay for 8 chip DMA
+                                        } else {
+                                                dio2Setup.uat_evt_clk_cnt_tc_cfg_val[19+j] = (((dio2Setup.uat_dio_ing_radt_tc_cfg_val[j]+1)/FrameMsgTot[IQN2_getIngressRadioStandardId(hIqn2->dioConfig[j].offsetPdDBCH)]/15) * 4) - 1;
+                                                dio2Setup.uat_evt_radt_cmp_cfg_val[19+j] = dio2Setup.uat_evt_radt_cmp_cfg_val[IQN2_getIngressRadioStandardId(hIqn2->dioConfig[j].offsetPdDBCH)] + 240;//DIO SI delay + 240 = 1400 clock delay for 4 chip DMA
+                                        }
                 }
+
                 dio2Setup.uat_dio_ing_radt_offset_cfg_val[j] = 0;//not used for DIAG_SYNC test mode
             }
         }
@@ -1989,23 +2043,28 @@ IQN2_initHw(
 
                 if(egrGroupInfo[i].g.isLte)
                 {
-                    if(egrGroupInfo[i].g.cpType == IQN2_LTE_CPTYPE_NORMAL)
-                    {
-                        aid2Setup.efe_samp_tc[egrRadStdInfo[i].indexSc] = FrameMsg1[i] - 1;//2208 samples for first 20MHz symbol
-                        for(j=1;j<(IQN2_LTE_SYMBOL_NUM);j++){
-                            aid2Setup.efe_samp_tc[egrRadStdInfo[i].indexSc + j] = FrameMsg[i]- 1;//frame message terminal count for other 6 normal cyclic prefix LTE symbols
-                        }
-
-                        for(j = IQN2_LTE_SYMBOL_NUM; j < (MBSFN_FACTOR * IQN2_LTE_SYMBOL_NUM); j++) {
-                            aid2Setup.efe_samp_tc[egrRadStdInfo[i].indexSc + j] =
-                            aid2Setup.efe_samp_tc[egrRadStdInfo[i].indexSc + (j - IQN2_LTE_SYMBOL_NUM)];
-                        }
-
-                    } else {
-                        for(j=0 ;j<(IQN2_LTE_SYMBOL_NUM_EXT_CP);j++){
-                            aid2Setup.efe_samp_tc[egrRadStdInfo[i].indexSc + j] = FrameMsg2[i]- 1;
-                        }
-                    }
+//                      if(hIqn2->aidConfig.lteDio == 1)
+//                      {
+//                              aid2Setup.efe_samp_tc[egrRadStdInfo[i].indexSc] = FrameMsg[i]- 1;
+//                      } else {
+                                                if(egrGroupInfo[i].g.cpType == IQN2_LTE_CPTYPE_NORMAL)
+                                                {
+                                                        aid2Setup.efe_samp_tc[egrRadStdInfo[i].indexSc] = FrameMsg1[i] - 1;//2208 samples for first 20MHz symbol
+                                                        for(j=1;j<(IQN2_LTE_SYMBOL_NUM);j++){
+                                                                aid2Setup.efe_samp_tc[egrRadStdInfo[i].indexSc + j] = FrameMsg[i]- 1;//frame message terminal count for other 6 normal cyclic prefix LTE symbols
+                                                        }
+
+                                                        for(j = IQN2_LTE_SYMBOL_NUM; j < (MBSFN_FACTOR * IQN2_LTE_SYMBOL_NUM); j++) {
+                                                                aid2Setup.efe_samp_tc[egrRadStdInfo[i].indexSc + j] =
+                                                                aid2Setup.efe_samp_tc[egrRadStdInfo[i].indexSc + (j - IQN2_LTE_SYMBOL_NUM)];
+                                                        }
+
+                                                } else {
+                                                        for(j=0 ;j<(IQN2_LTE_SYMBOL_NUM_EXT_CP);j++){
+                                                                aid2Setup.efe_samp_tc[egrRadStdInfo[i].indexSc + j] = FrameMsg2[i]- 1;
+                                                        }
+                                                }
+//                      }
                 } else {
                     aid2Setup.efe_samp_tc[egrRadStdInfo[i].indexSc] = FrameMsg[i]- 1;
                 }
@@ -2015,7 +2074,7 @@ IQN2_initHw(
         for(i=hIqn2->aidConfig.firstWcdmaAxC;i<hIqn2->aidConfig.numWcdmaEgressAxC + hIqn2->aidConfig.firstWcdmaAxC;i++){//EFE TDM look up table setup
             aid2Setup.efe_chan_index_cfg[i] = i;
             aid2Setup.efe_chan_index_en_cfg[i] = 1;
-#ifdef DEVICE_LE
+#ifdef DEVICE_LE                                                                                                //FIXME lteDio maybe needed for lte too
             if (hIqn2->dioConfig[i/16].egRsaOn == 1)
             {
                 aid2Setup.edc_ch_cfg_dat_swap[i] = 0;//no swap
@@ -2100,16 +2159,21 @@ IQN2_initHw(
 
                 if (ingrGroupInfo[i].g.isLte)
                 {
-                    if (ingrRadStdInfo[i].symbolTc == (IQN2_LTE_FRAME_SYMBOL_NUM-1)) {
-                        aid2Setup.ife_samp_tc[ingrRadStdInfo[i].indexSc] = FrameMsg1[i] - 1;//2208 samples for first 20MHz symbol
-                        for(j=1;j<(IQN2_LTE_SYMBOL_NUM);j++){
-                            aid2Setup.ife_samp_tc[ingrRadStdInfo[i].indexSc + j] = FrameMsg[i]- 1;//frame message terminal count for other 6 normal cyclic prefix LTE symbols
-                        }
-                    } else {
-                        for(j=0 ;j<(IQN2_LTE_SYMBOL_NUM_EXT_CP);j++){
-                            aid2Setup.ife_samp_tc[ingrRadStdInfo[i].indexSc + j] = FrameMsg2[i]- 1;
-                        }
-                    }
+//                      if(hIqn2->aidConfig.lteDio == 1)
+//                      {
+//                              aid2Setup.ife_samp_tc[ingrRadStdInfo[i].indexSc] = FrameMsg[i]- 1;
+//                      } else {
+                                                if (ingrRadStdInfo[i].symbolTc == (IQN2_LTE_FRAME_SYMBOL_NUM-1)) {
+                                                        aid2Setup.ife_samp_tc[ingrRadStdInfo[i].indexSc] = FrameMsg1[i] - 1;//2208 samples for first 20MHz symbol
+                                                        for(j=1;j<(IQN2_LTE_SYMBOL_NUM);j++){
+                                                                aid2Setup.ife_samp_tc[ingrRadStdInfo[i].indexSc + j] = FrameMsg[i]- 1;//frame message terminal count for other 6 normal cyclic prefix LTE symbols
+                                                        }
+                                                } else {
+                                                        for(j=0 ;j<(IQN2_LTE_SYMBOL_NUM_EXT_CP);j++){
+                                                                aid2Setup.ife_samp_tc[ingrRadStdInfo[i].indexSc + j] = FrameMsg2[i]- 1;
+                                                        }
+                                                }
+//                      }
                 } else {
                     aid2Setup.ife_samp_tc[ingrRadStdInfo[i].indexSc] = FrameMsg[i]- 1;
                 }
@@ -2154,9 +2218,14 @@ IQN2_initHw(
                 aid2Setup.uat_evt_radt_cmp_cfg_val[i] = hIqn2->aidConfig.siDelay + hIqn2->AxCconfig[egrGroupInfo[i].g.startAxC].egressAxCOffset;//200 clock delay for AID SI event start
 
                 if (egrGroupInfo[i].g.isLte)
-                    aid2Setup.uat_evt_clk_cnt_tc_cfg_val[i] = ((frameLength+1) / FrameMsgTot[i] / 20 * 4) - 1;//4 sample event (LTE20MHz)
-                else
+                {
+//                      if(hIqn2->aidConfig.lteDio == 1)
+//                              aid2Setup.uat_evt_clk_cnt_tc_cfg_val[i] = ((frameLength+1) / FrameMsgTot[i] / 15 * 4) - 1;//
+//                      else
+                                aid2Setup.uat_evt_clk_cnt_tc_cfg_val[i] = ((frameLength+1) / FrameMsgTot[i] / 20 * 4) - 1;//4 sample event (LTE20MHz)
+                } else {
                     aid2Setup.uat_evt_clk_cnt_tc_cfg_val[i] = ((frameLength+1) / FrameMsgTot[i] / 15 * 4) - 1;//
+                }
             }
             if (ingrGroupInfo[i].g.isPopulated)
             {
@@ -2165,9 +2234,14 @@ IQN2_initHw(
                 aid2Setup.uat_ing_radt_offset_cfg_val[i] = 0;//not used for DIAG_SYNC test mode
                 aid2Setup.uat_evt_radt_cmp_cfg_val[8 + i] = hIqn2->aidConfig.siDelay + 8 + hIqn2->AxCconfig[ingrGroupInfo[i].g.startAxC].ingressAxCOffset;// radio delay for AID SI event start (+8 is a temporaly fix for dfe exception in LTE)
                 if (ingrGroupInfo[i].g.isLte)
-                        aid2Setup.uat_evt_clk_cnt_tc_cfg_val[8 + i] = ((frameLength+1) / FrameMsgTot[i] / 20 * 4) - 1;//4 sample event (LTE20MHz)
-                else
+                {
+//                      if(hIqn2->aidConfig.lteDio == 1)
+                                aid2Setup.uat_evt_clk_cnt_tc_cfg_val[8 + i] = ((frameLength+1) / FrameMsgTot[i] / 20 * 4) - 1;//4 sample event (LTE20MHz)
+//                      else
+//                              aid2Setup.uat_evt_clk_cnt_tc_cfg_val[8 + i] = ((frameLength+1) / FrameMsgTot[i] / 15 * 4) - 1;//4 sample event (LTE20MHz)
+                } else {
                     aid2Setup.uat_evt_clk_cnt_tc_cfg_val[8 + i] = ((frameLength+1) / FrameMsgTot[i] / 15 * 4) - 1;//4 sample event (LTE20MHz)
+                }
             }
 
         }
@@ -2322,7 +2396,7 @@ IQN2_initRadioTimer(
               at2Setup.at2_radt_0_cfg_lutindex_tc[i]                  = lut_index;
               at2Setup.at2_radt_sym_lut_ram_cfg_symbcnt_tc[lut_index] = FrameMsg[grpId] - 1;;//2560 chips in slot
               lut_index++;
-              at2Setup.at2_radt_0_cfg_symb_tc[i]                      = 14; //15 slots in frame
+              at2Setup.at2_radt_0_cfg_symb_tc[i]                      = 14; //15 slots in frame  //FIXME add user specified for WCDMA radio timer
           }
       }
   }
@@ -2536,7 +2610,7 @@ void IQN2_startHw(
                         Iqn2Fl_hwControl(hIqn2->hFl, IQN2FL_CMD_AID2_ICTL_GLOBAL_ENABLE_SET, (void *)&ctrlArg);
                 }
 
-                if (hIqn2->aidConfig.numWcdmaEgressAxC != 0)
+                if ((hIqn2->aidConfig.numWcdmaEgressAxC != 0) || ((hIqn2->aidConfig.numLteEgressAxC != 0) && (hIqn2->aidConfig.lteDio)))
                 {
                     //global enable of DIO SI (Egress, Ingress)
                     Iqn2Fl_hwControl(hIqn2->hFl, IQN2FL_CMD_DIO2_EFE_GLOBAL_ENABLE_SET, (void *)&ctrlArg);
diff --git a/test/utils/wcdmaUtils.c b/test/utils/wcdmaUtils.c
index 82bda4b..5941c2f 100644
--- a/test/utils/wcdmaUtils.c
+++ b/test/utils/wcdmaUtils.c
@@ -84,6 +84,32 @@ void load_dioData(IQN2_DioConfigHandle hDioConfig)
         }
 }
 
+void load_dioData_lte(IQN2_DioConfigHandle hDioConfig)
+{
+        uint32_t idx, idx2, numChip;
+        uint32_t *ptr;
+
+        numChip = 4;
+        if (hDioConfig->out[0]) {
+            UTILS_cacheInvalidate((void *)hDioConfig->out[0], (hDioConfig->numPdDBCH*numChip*hDioConfig->inNumBlock)); // writeback in MSM
+        }
+        for (idx2 = 0; idx2 < hDioConfig->numPdDBCH; idx2 ++)
+        {
+            ptr = hDioConfig->out[idx2];
+            if (ptr)
+            {
+            for(idx =0; idx < numChip*hDioConfig->inNumBlock; idx++)
+            {
+                *ptr = (idx2 << 24) + idx;///numChip;
+                ptr++;
+            }
+            }
+        }
+        if (hDioConfig->out[0]) {
+            UTILS_cacheWriteBack((void *)hDioConfig->out[0], (hDioConfig->numPdDBCH*numChip*hDioConfig->inNumBlock)); // writeback in MSM
+        }
+}
+
 void wcdmaFinalCheck(IQN2_DioConfigHandle hDioConfig)
 {
         uint32_t testpass = 0;
diff --git a/test/utils/wcdmaUtils.h b/test/utils/wcdmaUtils.h
index 8137ef2..f55c031 100644
--- a/test/utils/wcdmaUtils.h
+++ b/test/utils/wcdmaUtils.h
@@ -56,6 +56,7 @@ extern volatile unsigned int testcheck;
 
 
 extern void load_dioData(IQN2_DioConfigHandle hDioConfig);
+extern void load_dioData_lte(IQN2_DioConfigHandle hDioConfig);
 extern void wcdmaFinalCheck(IQN2_DioConfigHandle hDioConfig);