diff options
author | Casey Smith | 2012-10-05 10:09:53 -0500 |
---|---|---|
committer | Casey Smith | 2012-10-05 10:09:53 -0500 |
commit | 2be4abf3dbf8244dc342e6c91e74abf338ad1178 (patch) | |
tree | ba4fed4eafdbafd33200d558128771d6d24841cb | |
parent | 5ee82674f1201b693c12bf97503a4c946c6d84c5 (diff) | |
download | mcsdk-platform-2be4abf3dbf8244dc342e6c91e74abf338ad1178.tar.gz mcsdk-platform-2be4abf3dbf8244dc342e6c91e74abf338ad1178.tar.xz mcsdk-platform-2be4abf3dbf8244dc342e6c91e74abf338ad1178.zip |
Updated PLL sequence for 6657, 6670 and 6678
-rw-r--r-- | evmc6657l/platform_lib/src/evmc6657.c | 126 | ||||
-rwxr-xr-x | evmc6670l/platform_lib/include/platform_internal.h | 2 | ||||
-rwxr-xr-x | evmc6670l/platform_lib/src/evmc6670.c | 218 | ||||
-rwxr-xr-x | evmc6678l/platform_lib/src/evmc6678.c | 221 |
4 files changed, 310 insertions, 257 deletions
diff --git a/evmc6657l/platform_lib/src/evmc6657.c b/evmc6657l/platform_lib/src/evmc6657.c index 0f1e255..e17fb8b 100644 --- a/evmc6657l/platform_lib/src/evmc6657.c +++ b/evmc6657l/platform_lib/src/evmc6657.c | |||
@@ -119,7 +119,7 @@ CSL_Status CorePllcHwSetup ( | |||
119 | CSL_BootCfgUnlockKicker(); | 119 | CSL_BootCfgUnlockKicker(); |
120 | 120 | ||
121 | 121 | ||
122 | /* Wait for Stabilization time (min 100 us) * | 122 | /* 1. Wait for Stabilization time (min 100 us) * |
123 | * The below loop is good enough for the Gel file to get minimum of * | 123 | * The below loop is good enough for the Gel file to get minimum of * |
124 | * 100 micro seconds, this should be appropriately modified for port * | 124 | * 100 micro seconds, this should be appropriately modified for port * |
125 | * to a C function * | 125 | * to a C function * |
@@ -127,36 +127,35 @@ CSL_Status CorePllcHwSetup ( | |||
127 | * more than required, but should be Okay */ | 127 | * more than required, but should be Okay */ |
128 | pll_delay(140056); | 128 | pll_delay(140056); |
129 | 129 | ||
130 | /* If PLL previously configured in RBL, avoid di/dt supply excursion by * | 130 | /* 2. If PLL previously configured in RBL, avoid di/dt supply excursion by * |
131 | * matching PLL output to RefClk rate * | 131 | * matching PLL output to RefClk rate * |
132 | * if RBL configures the PLL, the BYPASS bit would be set to '0' */ | 132 | * if RBL configures the PLL, the BYPASS bit would be set to '0' */ |
133 | temp = hPllcRegs->SECCTL & 0x00800000; /* Check the Bit 23 value */ | 133 | temp = hPllcRegs->SECCTL & 0x00800000; /* Check the Bit 23 value */ |
134 | 134 | ||
135 | if (temp != 0) { | 135 | if (temp != 0) /* PLL BYPASS is enabled, we assume if not in Bypass ENSAT = 1 */ |
136 | /* PLL BYPASS is enabled, we assume if not in Bypass ENSAT = 1 */ | 136 | { |
137 | 137 | /* 2a. Usage Note 9: For optimal PLL operation, the ENSAT bit in the PLL control * | |
138 | /* Usage Note 9: For optimal PLL operation, the ENSAT bit in the PLL control * | 138 | * registers for the Main PLL, DDR3 PLL, and PA PLL should be set to 1. * |
139 | * registers for the Main PLL, DDR3 PLL, and PA PLL should be set to 1. * | 139 | * The PLL initialization sequence in the boot ROM sets this bit to 0 and * |
140 | * The PLL initialization sequence in the boot ROM sets this bit to 0 and * | 140 | * could lead to non-optimal PLL operation. Software can set the bit to the * |
141 | * could lead to non-optimal PLL operation. Software can set the bit to the * | 141 | * optimal value of 1 after boot * |
142 | * optimal value of 1 after boot * | 142 | * Ref: http://www.ti.com/lit/er/sprz334b/sprz334b.pdf * |
143 | * Ref: http://www.ti.com/lit/er/sprz334b/sprz334b.pdf * | 143 | * |31...7 |6 |5 4 |3...0 | * |
144 | * |31...7 |6 |5 4 |3...0 | * | 144 | * |Reserved |ENSAT |Reserved |BWADJ[11:8]| */ |
145 | * |Reserved |ENSAT |Reserved |BWADJ[11:8]| */ | ||
146 | 145 | ||
147 | hBootCfg->CORE_PLL_CTL1 = hBootCfg->CORE_PLL_CTL1 | 0x00000040; | 146 | hBootCfg->CORE_PLL_CTL1 = hBootCfg->CORE_PLL_CTL1 | 0x00000040; |
148 | 147 | ||
149 | /* Clear PLLENSRC bit */ | 148 | /* 2b. Clear PLLEN bit */ |
150 | hPllcRegs-> PLLCTL &= ~(1 << 5); | ||
151 | |||
152 | /* Clear PLLEN bit */ | ||
153 | hPllcRegs-> PLLCTL &= ~(1 << 0); | 149 | hPllcRegs-> PLLCTL &= ~(1 << 0); |
150 | |||
151 | /* 2c. Clear PLLENSRC bit */ | ||
152 | hPllcRegs-> PLLCTL &= ~(1 << 5); | ||
154 | 153 | ||
155 | /* Wait for 4 RefClks * | 154 | /* 2d. Wait for 4 RefClks * |
156 | * Assuming slowest Ref clock of 25MHz, min: 160 ns delay */ | 155 | * Assuming slowest Ref clock of 25MHz, min: 160 ns delay */ |
157 | pll_delay(225); | 156 | pll_delay(225); |
158 | 157 | ||
159 | /* Bypass needed to perform PWRDN cycle for C6657 * | 158 | /* 2e. Bypass needed to perform PWRDN cycle for C6657 * |
160 | * Needed on all devices when in NOBOOT, I2C or SPI boot modes * | 159 | * Needed on all devices when in NOBOOT, I2C or SPI boot modes * |
161 | * Ref: Figure 4-2 of http://www.ti.com/lit/ug/sprugv2a/sprugv2a.pdf * | 160 | * Ref: Figure 4-2 of http://www.ti.com/lit/ug/sprugv2a/sprugv2a.pdf * |
162 | * PLL Secondary Control Register (SECCTL) Layout * | 161 | * PLL Secondary Control Register (SECCTL) Layout * |
@@ -165,7 +164,7 @@ CSL_Status CorePllcHwSetup ( | |||
165 | 164 | ||
166 | hPllcRegs->SECCTL |= 0x00800000; /* Set the Bit 23 */ | 165 | hPllcRegs->SECCTL |= 0x00800000; /* Set the Bit 23 */ |
167 | 166 | ||
168 | /* Advisory 8: Multiple PLLs May Not Lock After Power-on Reset Issue * | 167 | /* 2f. Advisory 8: Multiple PLLs May Not Lock After Power-on Reset Issue * |
169 | * In order to ensure proper PLL startup, the PLL power_down pin needs to be * | 168 | * In order to ensure proper PLL startup, the PLL power_down pin needs to be * |
170 | * toggled. This is accomplished by toggling the PLLPWRDN bit in the PLLCTL * | 169 | * toggled. This is accomplished by toggling the PLLPWRDN bit in the PLLCTL * |
171 | * register. This needs to be done before the main PLL initialization * | 170 | * register. This needs to be done before the main PLL initialization * |
@@ -177,35 +176,41 @@ CSL_Status CorePllcHwSetup ( | |||
177 | 176 | ||
178 | hPllcRegs-> PLLCTL |= 0x00000002; /*Power Down the PLL */ | 177 | hPllcRegs-> PLLCTL |= 0x00000002; /*Power Down the PLL */ |
179 | 178 | ||
180 | /* Stay in a loop such that the bit is set for 5 µs (minimum) and * | 179 | /* 2g. Stay in a loop such that the bit is set for 5 µs (minimum) and * |
181 | * then clear the bit. */ | 180 | * then clear the bit. */ |
182 | 181 | ||
183 | pll_delay(14005); | 182 | pll_delay(14005); |
184 | 183 | ||
185 | /* Power up the PLL */ | 184 | /* 2h. Power up the PLL */ |
186 | hPllcRegs-> PLLCTL &= ~(0x00000002); | 185 | hPllcRegs-> PLLCTL &= ~(0x00000002); |
187 | 186 | ||
188 | } | 187 | } |
188 | else | ||
189 | { | ||
190 | /* 3. Enable BYPASS in the PLL contoller */ | ||
191 | |||
192 | /* 3a. Clear PLLEN bit (bypass enabled in PLL controller mux) */ | ||
193 | hPllcRegs->PLLCTL &= ~(1 << 0); | ||
194 | |||
195 | /* 3b. Clear PLLENSRC bit (enable PLLEN to control PLL controller mux) */ | ||
196 | hPllcRegs->PLLCTL &= ~(1 << 5); | ||
197 | |||
198 | /* 3c. Wait for 4 RefClks (to make sure the PLL controller * | ||
199 | * mux switches properly to bypass) * | ||
200 | * Assuming slowest Ref clock of 25MHz, min: 160 ns delay */ | ||
201 | pll_delay(225); | ||
202 | } | ||
189 | 203 | ||
190 | /* Place PLL in Reset, In PLLCTL, write PLLRST = 1 (PLL is reset) */ | 204 | /* 4, 5, 6 and 7 are done here: * |
191 | hPllcRegs-> PLLCTL |= 0x00000008; | 205 | * Program the necessary multipliers/dividers and BW adjustments */ |
192 | |||
193 | /* Wait for PLL Reset assertion Time (min: 50 us) * | ||
194 | * Minimum delay in GEL can be 1 milli seconds, so program to 1ms=1000us, * | ||
195 | * more than required, but should be Okay */ | ||
196 | /*pll_delay(140050);*/ | ||
197 | |||
198 | /* Program the necessary multipliers/dividers and BW adjustments */ | ||
199 | prog_pll1_values(hwSetup); | 206 | prog_pll1_values(hwSetup); |
207 | |||
208 | /* 8. Set PLL dividers if needed */ | ||
200 | 209 | ||
201 | /* go stat bit needs to be zero here */ | 210 | /* part of 8, go stat bit needs to be zero here * |
202 | /* Read the GOSTAT bit in PLLSTAT to make sure the bit returns to 0 to * | 211 | * Read the GOSTAT bit in PLLSTAT to make sure the bit returns to 0 to * |
203 | * indicate that the GO operation has completed */ | 212 | * indicate that the GO operation has completed * |
204 | /* wait for the GOSTAT, but don't trap if lock is never read */ | 213 | * wait for the GOSTAT, but don't trap if lock is never read */ |
205 | |||
206 | /*while ((PLL1_STAT & 0x00000001) != 0) { | ||
207 | gostat_counter++; | ||
208 | }*/ | ||
209 | for (i = 0; i < 100; i++) { | 214 | for (i = 0; i < 100; i++) { |
210 | pll_delay(300); | 215 | pll_delay(300); |
211 | if ( (hPllcRegs->PLLSTAT & 0x00000001) == 0 ) { | 216 | if ( (hPllcRegs->PLLSTAT & 0x00000001) == 0 ) { |
@@ -216,26 +221,22 @@ CSL_Status CorePllcHwSetup ( | |||
216 | return CSL_ESYS_FAIL; | 221 | return CSL_ESYS_FAIL; |
217 | } | 222 | } |
218 | 223 | ||
219 | /* Set PLL dividers if needed */ | 224 | /* part of 8, Set PLL dividers if needed */ |
220 | hPllcRegs->PLLDIV1_3[1] = (0x8000) | (hwSetup->pllDiv2); | 225 | hPllcRegs->PLLDIV1_3[1] = (0x8000) | (hwSetup->pllDiv2); |
221 | hPllcRegs->PLLDIV4_16[1] = (0x8000) | (hwSetup->pllDiv5); | 226 | hPllcRegs->PLLDIV4_16[1] = (0x8000) | (hwSetup->pllDiv5); |
222 | hPllcRegs->PLLDIV4_16[4] = (0x8000) | (hwSetup->pllDiv8); | 227 | hPllcRegs->PLLDIV4_16[4] = (0x8000) | (hwSetup->pllDiv8); |
223 | 228 | ||
224 | /* Program ALNCTLn */ | 229 | /* part of 8, Program ALNCTLn * |
225 | /* Set bit 1, 4 and 7 */ | 230 | * Set bit 1, 4 and 7 */ |
226 | hPllcRegs->ALNCTL |= ( (1 << 1) | (1 << 4) | (1 << 7)); | 231 | hPllcRegs->ALNCTL |= ( (1 << 1) | (1 << 4) | (1 << 7)); |
227 | 232 | ||
228 | /* Set GOSET bit in PLLCMD to initiate the GO operation to change the divide * | 233 | /* part of 8, Set GOSET bit in PLLCMD to initiate the GO operation to change the divide * |
229 | * values and align the SYSCLKs as programmed */ | 234 | * values and align the SYSCLKs as programmed */ |
230 | hPllcRegs->PLLCMD |= 0x00000001; | 235 | hPllcRegs->PLLCMD |= 0x00000001; |
231 | 236 | ||
232 | /* wait for the phase adj */ | 237 | /* part of 8, Read the GOSTAT bit in PLLSTAT to make sure the bit returns to 0 to * |
233 | pll_delay(1000); | 238 | * indicate that the GO operation has completed * |
234 | 239 | * wait for the GOSTAT, but don't trap if lock is never read */ | |
235 | /* Read the GOSTAT bit in PLLSTAT to make sure the bit returns to 0 to * | ||
236 | * indicate that the GO operation has completed */ | ||
237 | |||
238 | /* wait for the GOSTAT, but don't trap if lock is never read */ | ||
239 | for (i = 0; i < 100; i++) { | 240 | for (i = 0; i < 100; i++) { |
240 | pll_delay(300); | 241 | pll_delay(300); |
241 | if ( (hPllcRegs->PLLSTAT & 0x00000001) == 0 ) { | 242 | if ( (hPllcRegs->PLLSTAT & 0x00000001) == 0 ) { |
@@ -245,18 +246,29 @@ CSL_Status CorePllcHwSetup ( | |||
245 | if (i == 100) { | 246 | if (i == 100) { |
246 | return CSL_ESYS_FAIL; | 247 | return CSL_ESYS_FAIL; |
247 | } | 248 | } |
248 | /* Wait for a minimum of 7 us*/ | 249 | |
250 | /* 9. Place PLL in Reset, In PLLCTL, write PLLRST = 1 (PLL is reset) */ | ||
251 | hPllcRegs-> PLLCTL |= 0x00000008; | ||
252 | |||
253 | /* 10. Wait for PLL Reset assertion Time (min: 7 us) */ | ||
249 | pll_delay (14006); | 254 | pll_delay (14006); |
250 | 255 | ||
251 | /*In PLLCTL, write PLLRST = 0 to bring PLL out of reset */ | 256 | /* 11. In PLLCTL, write PLLRST = 0 to bring PLL out of reset */ |
252 | hPllcRegs->PLLCTL &= ~(0x00000008); | 257 | hPllcRegs->PLLCTL &= ~(0x00000008); |
253 | 258 | ||
254 | /* Wait for PLL Lock time (min 50 us) */ | 259 | /* 12. PLL Lock Delay needs to be 500 RefClk periods * (PLLD + 1) * |
260 | * i.e., Wait for at least 500 * CLKIN cycles * (PLLD + 1) (PLL lock timer) * | ||
261 | * Using 2000 25ns RefClk periods per DM * | ||
262 | * Wait for PLL to lock min 50 us */ | ||
255 | pll_delay (140056 >> 1); | 263 | pll_delay (140056 >> 1); |
264 | |||
265 | /* 13. In SECCTL, write BYPASS = 0 (enable PLL mux to switch to PLL mode) */ | ||
256 | hPllcRegs->SECCTL &= ~(0x00800000); /* Release Bypass */ | 266 | hPllcRegs->SECCTL &= ~(0x00800000); /* Release Bypass */ |
257 | 267 | ||
258 | /* Set the PLLEN */ | 268 | /* 14. In PLLCTL, write PLLEN = 1 (enable PLL contoller mux to switch to PLL mode) */ |
259 | hPllcRegs->PLLCTL |= (1 << 0); | 269 | hPllcRegs->PLLCTL |= (1 << 0); |
270 | |||
271 | /* 15. The PLL and PLL Controller are now initialized in PLL mode - Completed. */ | ||
260 | 272 | ||
261 | return status; | 273 | return status; |
262 | } | 274 | } |
@@ -356,9 +368,6 @@ CSL_Status SetDDR3PllConfig(void) | |||
356 | /*Wait 4 cycles for the slowest of PLLOUT or reference clock source (CLKIN)*/ | 368 | /*Wait 4 cycles for the slowest of PLLOUT or reference clock source (CLKIN)*/ |
357 | /*pll_delay(4);*/ | 369 | /*pll_delay(4);*/ |
358 | 370 | ||
359 | /* In PLL Controller, reset the PLL (bit 13) in DDR3PLLCTL1_REG register */ | ||
360 | hBootCfg->DDR3_PLL_CTL1 |= 0x00002000; | ||
361 | |||
362 | /* Wait for the PLL Reset time (min: 1000 ns) */ | 371 | /* Wait for the PLL Reset time (min: 1000 ns) */ |
363 | /*pll_delay(1400);*/ | 372 | /*pll_delay(1400);*/ |
364 | 373 | ||
@@ -377,6 +386,9 @@ CSL_Status SetDDR3PllConfig(void) | |||
377 | hBootCfg->DDR3_PLL_CTL0 |= ((temp << 24) & 0xFF000000); | 386 | hBootCfg->DDR3_PLL_CTL0 |= ((temp << 24) & 0xFF000000); |
378 | hBootCfg->DDR3_PLL_CTL1 &= ~(0x0000000F); | 387 | hBootCfg->DDR3_PLL_CTL1 &= ~(0x0000000F); |
379 | hBootCfg->DDR3_PLL_CTL1 |= ((temp >> 8) & 0x0000000F); | 388 | hBootCfg->DDR3_PLL_CTL1 |= ((temp >> 8) & 0x0000000F); |
389 | |||
390 | /* In PLL Controller, reset the PLL (bit 13) in DDR3PLLCTL1_REG register */ | ||
391 | hBootCfg->DDR3_PLL_CTL1 |= 0x00002000; | ||
380 | 392 | ||
381 | /*Wait for PLL to lock min 5 micro seconds*/ | 393 | /*Wait for PLL to lock min 5 micro seconds*/ |
382 | pll_delay(7000); | 394 | pll_delay(7000); |
diff --git a/evmc6670l/platform_lib/include/platform_internal.h b/evmc6670l/platform_lib/include/platform_internal.h index 4e7415a..73a6798 100755 --- a/evmc6670l/platform_lib/include/platform_internal.h +++ b/evmc6670l/platform_lib/include/platform_internal.h | |||
@@ -379,7 +379,7 @@ extern void xmc_setup(); | |||
379 | #define PLLSEL_BIT_SHIFT 13 | 379 | #define PLLSEL_BIT_SHIFT 13 |
380 | #define PA_PLL_ENSAT_MASK (1 << ENSAT_BIT_SHIFT) /* Tells the configuration of the ENSAT bit */ | 380 | #define PA_PLL_ENSAT_MASK (1 << ENSAT_BIT_SHIFT) /* Tells the configuration of the ENSAT bit */ |
381 | #define PA_PLL_RESET_MASK (1 << RESET_BIT_SHIFT) /* Tells the configuration of the RESET bit */ | 381 | #define PA_PLL_RESET_MASK (1 << RESET_BIT_SHIFT) /* Tells the configuration of the RESET bit */ |
382 | #define PA_PLL_RESET_MASK (1 << PLLSEL_BIT_SHIFT) /* Tells the configuration of the PLLSEL bit */ | 382 | #define PA_PLL_PLLSEL_MASK (1 << PLLSEL_BIT_SHIFT) /* Tells the configuration of the PLLSEL bit */ |
383 | 383 | ||
384 | /* PASS PLL settings for 1044 MHz */ | 384 | /* PASS PLL settings for 1044 MHz */ |
385 | #define PLLM_PASS 31 | 385 | #define PLLM_PASS 31 |
diff --git a/evmc6670l/platform_lib/src/evmc6670.c b/evmc6670l/platform_lib/src/evmc6670.c index a37b89b..9907f16 100755 --- a/evmc6670l/platform_lib/src/evmc6670.c +++ b/evmc6670l/platform_lib/src/evmc6670.c | |||
@@ -119,7 +119,7 @@ CSL_Status CorePllcHwSetup ( | |||
119 | CSL_BootCfgUnlockKicker(); | 119 | CSL_BootCfgUnlockKicker(); |
120 | 120 | ||
121 | 121 | ||
122 | /* Wait for Stabilization time (min 100 us) * | 122 | /* 1. Wait for Stabilization time (min 100 us) * |
123 | * The below loop is good enough for the Gel file to get minimum of * | 123 | * The below loop is good enough for the Gel file to get minimum of * |
124 | * 100 micro seconds, this should be appropriately modified for port * | 124 | * 100 micro seconds, this should be appropriately modified for port * |
125 | * to a C function * | 125 | * to a C function * |
@@ -127,44 +127,44 @@ CSL_Status CorePllcHwSetup ( | |||
127 | * more than required, but should be Okay */ | 127 | * more than required, but should be Okay */ |
128 | pll_delay(140056); | 128 | pll_delay(140056); |
129 | 129 | ||
130 | /* If PLL previously configured in RBL, avoid di/dt supply excursion by * | 130 | /* 2. Check the status of BYPASS bit in SECCTL register, * |
131 | * matching PLL output to RefClk rate * | 131 | * execute the following steps if * |
132 | * if RBL configures the PLL, the BYPASS bit would be set to '0' */ | 132 | * BYPASS == 1 (if bypass enabled), if BYPASS==0 then Jump to Step 3 */ |
133 | temp = SECCTL_REG & 0x00800000; /* Check the Bit 23 value */ | 133 | temp = SECCTL_REG & 0x00800000; /* Check the Bit 23 value */ |
134 | 134 | ||
135 | if (temp != 0) { | 135 | if (temp != 0) /* PLL BYPASS is enabled, we assume if not in Bypass ENSAT = 1 */ |
136 | /* PLL BYPASS is enabled, we assume if not in Bypass ENSAT = 1 */ | 136 | { |
137 | 137 | /* 2a. Usage Note 9: For optimal PLL operation, the ENSAT bit in the PLL control * | |
138 | /* Usage Note 9: For optimal PLL operation, the ENSAT bit in the PLL control * | 138 | * registers for the Main PLL, DDR3 PLL, and PA PLL should be set to 1. * |
139 | * registers for the Main PLL, DDR3 PLL, and PA PLL should be set to 1. * | 139 | * The PLL initialization sequence in the boot ROM sets this bit to 0 and * |
140 | * The PLL initialization sequence in the boot ROM sets this bit to 0 and * | 140 | * could lead to non-optimal PLL operation. Software can set the bit to the * |
141 | * could lead to non-optimal PLL operation. Software can set the bit to the * | 141 | * optimal value of 1 after boot * |
142 | * optimal value of 1 after boot * | 142 | * Ref: http://www.ti.com/lit/er/sprz334b/sprz334b.pdf * |
143 | * Ref: http://www.ti.com/lit/er/sprz334b/sprz334b.pdf * | 143 | * |31...7 |6 |5 4 |3...0 | * |
144 | * |31...7 |6 |5 4 |3...0 | * | 144 | * |Reserved |ENSAT |Reserved |BWADJ[11:8]| */ |
145 | * |Reserved |ENSAT |Reserved |BWADJ[11:8]| */ | 145 | |
146 | |||
147 | MAINPLLCTL1_REG = MAINPLLCTL1_REG | 0x00000040; | 146 | MAINPLLCTL1_REG = MAINPLLCTL1_REG | 0x00000040; |
148 | 147 | ||
149 | /* Clear PLLENSRC bit */ | 148 | /* 2b. Clear PLLEN bit (bypass enabled in PLL controller mux) */ |
150 | PLLCTL_REG &= ~(1 << 5); | ||
151 | |||
152 | /* Clear PLLEN bit */ | ||
153 | PLLCTL_REG &= ~(1 << 0); | 149 | PLLCTL_REG &= ~(1 << 0); |
154 | 150 | ||
155 | /* Wait for 4 RefClks * | 151 | /* 2c. Clear PLLENSRC bit (enable PLLEN to control PLL controller mux) */ |
152 | PLLCTL_REG &= ~(1 << 5); | ||
153 | |||
154 | /* 2d. Wait for 4 RefClks(to make sure the PLL controller * | ||
155 | * mux switches properly to the bypass) * | ||
156 | * Assuming slowest Ref clock of 25MHz, min: 160 ns delay */ | 156 | * Assuming slowest Ref clock of 25MHz, min: 160 ns delay */ |
157 | pll_delay(225); | 157 | pll_delay(225); |
158 | 158 | ||
159 | /* Bypass needed to perform PWRDN cycle for C6670 and C6678 * | 159 | /* 2e. Bypass needed to perform PWRDN cycle for C6670 and C6657 * |
160 | * Needed on all devices when in NOBOOT, I2C or SPI boot modes * | 160 | * Needed on all devices when in NOBOOT, I2C or SPI boot modes * |
161 | * Ref: Figure 4-2 of http://www.ti.com/lit/ug/sprugv2a/sprugv2a.pdf * | 161 | * Ref: Figure 4-2 of http://www.ti.com/lit/ug/sprugv2a/sprugv2a.pdf * |
162 | * PLL Secondary Control Register (SECCTL) Layout * | 162 | * PLL Secondary Control Register (SECCTL) Layout * |
163 | * |31...24 |23 |22...19 |18...0 | * | 163 | * |31...24 |23 |22...19 |18...0 | * |
164 | * |Reserved |BYPASS |OUTPUT DIVIDE |Reserved | */ | 164 | * |Reserved |BYPASS |OUTPUT DIVIDE |Reserved | */ |
165 | PLLCTL_REG |= 0x00800000; /* Set the Bit 23 */ | 165 | SECCTL_REG |= 0x00800000; /* Set the Bit 23 */ |
166 | 166 | ||
167 | /* Advisory 8: Multiple PLLs May Not Lock After Power-on Reset Issue * | 167 | /* 2f. Advisory 8: Multiple PLLs May Not Lock After Power-on Reset Issue * |
168 | * In order to ensure proper PLL startup, the PLL power_down pin needs to be * | 168 | * In order to ensure proper PLL startup, the PLL power_down pin needs to be * |
169 | * toggled. This is accomplished by toggling the PLLPWRDN bit in the PLLCTL * | 169 | * toggled. This is accomplished by toggling the PLLPWRDN bit in the PLLCTL * |
170 | * register. This needs to be done before the main PLL initialization * | 170 | * register. This needs to be done before the main PLL initialization * |
@@ -173,86 +173,105 @@ CSL_Status CorePllcHwSetup ( | |||
173 | * PLL Control Register (PLLCTL) Layout * | 173 | * PLL Control Register (PLLCTL) Layout * |
174 | * |31...4 |3 |2 |1 |0 | * | 174 | * |31...4 |3 |2 |1 |0 | * |
175 | * |Reserved |PLLRST |Reserved |PLLPWRDN |Reserved | */ | 175 | * |Reserved |PLLRST |Reserved |PLLPWRDN |Reserved | */ |
176 | 176 | ||
177 | PLLCTL_REG |= 0x00000002; /*Power Down the PLL */ | 177 | PLLCTL_REG |= 0x00000002; /* Power Down the PLL */ |
178 | 178 | ||
179 | /* Stay in a loop such that the bit is set for 5 µs (minimum) and * | 179 | /* 2g. Stay in a loop such that the bit is set for 5 µs (minimum) and * |
180 | * then clear the bit. */ | 180 | * then clear the bit. */ |
181 | 181 | ||
182 | pll_delay(14005); | 182 | pll_delay(14005); |
183 | 183 | ||
184 | /* Power up the PLL */ | 184 | /* 2h. Power up the PLL */ |
185 | PLLCTL_REG &= ~(0x00000002); | 185 | PLLCTL_REG &= ~(0x00000002); |
186 | |||
187 | } | 186 | } |
188 | 187 | else | |
189 | /* Place PLL in Reset, In PLLCTL, write PLLRST = 1 (PLL is reset) */ | 188 | { |
190 | PLLCTL_REG |= 0x00000008; | 189 | /* 3. Enable BYPASS in the PLL contoller */ |
191 | 190 | ||
192 | /* Wait for PLL Reset assertion Time (min: 50 us) * | 191 | /* 3a. Clear PLLEN bit (bypass enabled in PLL controller mux) */ |
193 | * Minimum delay in GEL can be 1 milli seconds, so program to 1ms=1000us, * | 192 | PLLCTL_REG &= ~(1 << 0); |
194 | * more than required, but should be Okay */ | 193 | |
195 | /*pll_delay(140050);*/ | 194 | /* 3b. Clear PLLENSRC bit (enable PLLEN to control PLL controller mux) */ |
196 | 195 | PLLCTL_REG &= ~(1 << 5); | |
197 | /* Program the necessary multipliers/dividers and BW adjustments */ | 196 | |
197 | /* 3c. Wait for 4 RefClks (to make sure the PLL controller * | ||
198 | * mux switches properly to bypass) * | ||
199 | * Assuming slowest Ref clock of 25MHz, min: 160 ns delay */ | ||
200 | pll_delay(225); | ||
201 | } | ||
202 | |||
203 | /* 4, 5, 6 and 7 are done here: * | ||
204 | * Program the necessary multipliers/dividers and BW adjustments */ | ||
198 | prog_pll1_values(hwSetup); | 205 | prog_pll1_values(hwSetup); |
199 | 206 | ||
200 | /* go stat bit needs to be zero here */ | 207 | /* 8. Set PLL dividers if needed */ |
201 | /* Read the GOSTAT bit in PLLSTAT to make sure the bit returns to 0 to * | 208 | |
202 | * indicate that the GO operation has completed */ | 209 | /* part of 8, go stat bit needs to be zero here * |
203 | /* wait for the GOSTAT, but don't trap if lock is never read */ | 210 | * Read the GOSTAT bit in PLLSTAT to make sure the bit reurns to 0 to * |
204 | for (i = 0; i < 100; i++) { | 211 | * indicate that the GO operation has completed * |
212 | * wait for the GOSTAT, but don't trap if lock is never read */ | ||
213 | for (i = 0; i < 100; i++) | ||
214 | { | ||
205 | pll_delay(300); | 215 | pll_delay(300); |
206 | if ( (PLL1_STAT & 0x00000001) == 0 ) { | 216 | if ( (PLL1_STAT & 0x00000001) == 0 ) { |
207 | break; | 217 | break; |
208 | } | 218 | } |
209 | } | 219 | } |
210 | if (i == 100) { | 220 | if ( i == 100 ) { |
211 | return CSL_ESYS_FAIL; | 221 | return CSL_ESYS_FAIL; |
212 | } | 222 | } |
213 | 223 | ||
214 | /* Set PLL dividers if needed */ | 224 | /* part of 8, Set PLL dividers if needed */ |
215 | PLL1_DIV2 = (0x8000) | (hwSetup->pllDiv2); | 225 | PLL1_DIV2 = (0x8000) | (hwSetup->pllDiv2); |
216 | PLL1_DIV5 = (0x8000) | (hwSetup->pllDiv5); | 226 | PLL1_DIV5 = (0x8000) | (hwSetup->pllDiv5); |
217 | PLL1_DIV8 = (0x8000) | (hwSetup->pllDiv8); | 227 | PLL1_DIV8 = (0x8000) | (hwSetup->pllDiv8); |
218 | 228 | ||
219 | /* Program ALNCTLn */ | 229 | /* part of 8, Program ALNCTLn * |
220 | /* Set bit 1, 4 and 7 */ | 230 | * Set bit 1, 4 and 7 */ |
221 | PLLALNCTL_REG |= ( (1 << 1) | (1 << 4) | (1 << 7)); | 231 | PLLALNCTL_REG |= ((1 << 1) | (1 << 4) | (1 << 7)); |
222 | 232 | ||
223 | /* Set GOSET bit in PLLCMD to initiate the GO operation to change the divide * | 233 | /* part of 8, Set GOSET bit in PLLCMD to initiate the GO operation to change the divide * |
224 | * values and align the SYSCLKs as programmed */ | 234 | * values and align the SYSCLKSs as programmed */ |
225 | PLLCMD_REG |= 0x00000001; | 235 | PLLCMD_REG |= 0x00000001; |
226 | 236 | ||
227 | /* wait for the phase adj */ | 237 | /* part of 8, go stat bit needs to be zero here * |
228 | pll_delay(1000); | 238 | * Read the GOSTAT bit in PLLSTAT to make sure the bit reurns to 0 to * |
229 | 239 | * indicate that the GO operation has completed * | |
230 | /* Read the GOSTAT bit in PLLSTAT to make sure the bit returns to 0 to * | 240 | * wait for the GOSTAT, but don't trap if lock is never read */ |
231 | * indicate that the GO operation has completed */ | 241 | for (i = 0; i < 100; i++) |
232 | 242 | { | |
233 | /* wait for the GOSTAT, but don't trap if lock is never read */ | ||
234 | for (i = 0; i < 100; i++) { | ||
235 | pll_delay(300); | 243 | pll_delay(300); |
236 | if ( (PLL1_STAT & 0x00000001) == 0 ) { | 244 | if ( (PLL1_STAT & 0x00000001) == 0 ) { |
237 | break; | 245 | break; |
238 | } | 246 | } |
239 | } | 247 | } |
240 | if (i == 100) { | 248 | if ( i == 100 ) { |
241 | return CSL_ESYS_FAIL; | 249 | return CSL_ESYS_FAIL; |
242 | } | 250 | } |
243 | /* Wait for a minimum of 7 us*/ | 251 | |
244 | pll_delay (14006); | 252 | /* 9. Place PLL in Reset, In PLLCTL, write PLLRST = 1 (PLL is reset) */ |
245 | 253 | PLLCTL_REG |= 0x00000008; | |
246 | /*In PLLCTL, write PLLRST = 0 to bring PLL out of reset */ | 254 | |
255 | /* 10. Wait for PLL Reset assertion Time (min: 7 us) */ | ||
256 | pll_delay(14006); | ||
257 | |||
258 | /* 11. In PLLCTL, write PLLRST = 0 (PLL reset is de-asserted) */ | ||
247 | PLLCTL_REG &= ~(0x00000008); | 259 | PLLCTL_REG &= ~(0x00000008); |
248 | 260 | ||
249 | /* Wait for PLL Lock time (min 50 us) */ | 261 | /* 12. PLL Lock Delay needs to be 500 RefClk periods * (PLLD + 1) * |
250 | pll_delay (140056 >> 1); | 262 | * i.e., Wait for at least 500 * CLKIN cycles * (PLLD + 1) (PLL lock timer) * |
251 | PLL1_SECCTL &= ~(0x00800000); /* Release Bypass */ | 263 | * Using 2000 25ns RefClk periods per DM * |
252 | 264 | * Wait for PLL to lock min 50 us */ | |
253 | /* Set the PLLEN */ | 265 | pll_delay(140056 >> 1); |
266 | |||
267 | /* 13. In SECCTL, write BYPASS = 0 (enable PLL mux to switch to PLL mode) */ | ||
268 | SECCTL_REG &= ~(0x00800000); /* Release Bypass */ | ||
269 | |||
270 | /* 14. In PLLCTL, write PLLEN = 1 (enable PLL controller mux to switch to PLL mode) */ | ||
254 | PLLCTL_REG |= (1 << 0); | 271 | PLLCTL_REG |= (1 << 0); |
255 | 272 | ||
273 | /* 15. The PLL and PLL Controller are now initialized in PLL mode - Completed. */ | ||
274 | |||
256 | return status; | 275 | return status; |
257 | } | 276 | } |
258 | 277 | ||
@@ -337,9 +356,6 @@ SetPaPllConfig | |||
337 | /*Wait 4 cycles for the slowest of PLLOUT or reference clock source (CLKIN)*/ | 356 | /*Wait 4 cycles for the slowest of PLLOUT or reference clock source (CLKIN)*/ |
338 | /*pll_delay(4);*/ | 357 | /*pll_delay(4);*/ |
339 | 358 | ||
340 | /* In PLL Controller, reset the PLL (bit 14), set PLLSEL bit (bit 13) in PAPLLCTL1_REG register */ | ||
341 | PAPLLCTL1_REG |= 0x00006000; | ||
342 | |||
343 | /* Wait for the PLL Reset time (min: 1000 ns) */ | 359 | /* Wait for the PLL Reset time (min: 1000 ns) */ |
344 | /*pll_delay(1400);*/ | 360 | /*pll_delay(1400);*/ |
345 | 361 | ||
@@ -353,15 +369,21 @@ SetPaPllConfig | |||
353 | PAPLLCTL0_REG |= ((pa_pllm << 6) & 0x0007FFC0 ); | 369 | PAPLLCTL0_REG |= ((pa_pllm << 6) & 0x0007FFC0 ); |
354 | 370 | ||
355 | /* Set the BWADJ */ | 371 | /* Set the BWADJ */ |
356 | temp = (pa_pllm >> 1); | 372 | temp = ((pa_pllm + 1) >> 1) - 1; |
357 | PAPLLCTL0_REG &= ~(0xFF000000); | 373 | PAPLLCTL0_REG &= ~(0xFF000000); |
358 | PAPLLCTL0_REG |= ((temp << 24) & 0xFF000000); | 374 | PAPLLCTL0_REG |= ((temp << 24) & 0xFF000000); |
359 | PAPLLCTL1_REG &= ~(0x0000000F); | 375 | PAPLLCTL1_REG &= ~(0x0000000F); |
360 | PAPLLCTL1_REG |= ((temp >> 8) & 0x0000000F); | 376 | PAPLLCTL1_REG |= ((temp >> 8) & 0x0000000F); |
377 | |||
378 | /* In PLL Controller, reset the PLL (bit 14) in PAPLLCTL1_REG register */ | ||
379 | PAPLLCTL1_REG |= 0x00004000; | ||
361 | 380 | ||
362 | /*Wait for PLL to lock min 5 micro seconds*/ | 381 | /*Wait for PLL to lock min 5 micro seconds*/ |
363 | pll_delay(7000); | 382 | pll_delay(7000); |
364 | 383 | ||
384 | /*In PAPLLCTL1_REG, write PLLSELECT = 1 (for selecting the output of PASS PLL as the input to PASS) */ | ||
385 | PAPLLCTL1_REG |= 0x00002000; | ||
386 | |||
365 | /*In PAPLLCTL1_REG, write PLLRST = 0 to bring PLL out of reset */ | 387 | /*In PAPLLCTL1_REG, write PLLRST = 0 to bring PLL out of reset */ |
366 | PAPLLCTL1_REG &= ~(0x00004000); | 388 | PAPLLCTL1_REG &= ~(0x00004000); |
367 | 389 | ||
@@ -493,9 +515,6 @@ CSL_Status SetDDR3PllConfig(void) | |||
493 | /*Wait 4 cycles for the slowest of PLLOUT or reference clock source (CLKIN)*/ | 515 | /*Wait 4 cycles for the slowest of PLLOUT or reference clock source (CLKIN)*/ |
494 | /*pll_delay(4);*/ | 516 | /*pll_delay(4);*/ |
495 | 517 | ||
496 | /* In PLL Controller, reset the PLL (bit 13) in DDR3PLLCTL1_REG register */ | ||
497 | DDR3PLLCTL1_REG |= 0x00002000; | ||
498 | |||
499 | /* Wait for the PLL Reset time (min: 1000 ns) */ | 518 | /* Wait for the PLL Reset time (min: 1000 ns) */ |
500 | /*pll_delay(1400);*/ | 519 | /*pll_delay(1400);*/ |
501 | 520 | ||
@@ -509,11 +528,14 @@ CSL_Status SetDDR3PllConfig(void) | |||
509 | DDR3PLLCTL0_REG |= ((ddr3_pllm << 6) & 0x0007FFC0 ); | 528 | DDR3PLLCTL0_REG |= ((ddr3_pllm << 6) & 0x0007FFC0 ); |
510 | 529 | ||
511 | /* Set the BWADJ */ | 530 | /* Set the BWADJ */ |
512 | temp = (ddr3_pllm >> 1); | 531 | temp = ((ddr3_pllm + 1) >> 1) - 1; |
513 | DDR3PLLCTL0_REG &= ~(0xFF000000); | 532 | DDR3PLLCTL0_REG &= ~(0xFF000000); |
514 | DDR3PLLCTL0_REG |= ((temp << 24) & 0xFF000000); | 533 | DDR3PLLCTL0_REG |= ((temp << 24) & 0xFF000000); |
515 | DDR3PLLCTL1_REG &= ~(0x0000000F); | 534 | DDR3PLLCTL1_REG &= ~(0x0000000F); |
516 | DDR3PLLCTL1_REG |= ((temp >> 8) & 0x0000000F); | 535 | DDR3PLLCTL1_REG |= ((temp >> 8) & 0x0000000F); |
536 | |||
537 | /* In PLL Controller, reset the PLL (bit 13) in DDR3PLLCTL1_REG register */ | ||
538 | DDR3PLLCTL1_REG |= 0x00002000; | ||
517 | 539 | ||
518 | /*Wait for PLL to lock min 5 micro seconds*/ | 540 | /*Wait for PLL to lock min 5 micro seconds*/ |
519 | pll_delay(7000); | 541 | pll_delay(7000); |
@@ -534,11 +556,11 @@ CSL_Status SetDDR3PllConfig(void) | |||
534 | 556 | ||
535 | /* Tells the multiplier value for the DDR3 PLL */ | 557 | /* Tells the multiplier value for the DDR3 PLL */ |
536 | ddr3_pllm = (((ddr3pllctl0val & 0x0007FFC0) >> 6) + 1); | 558 | ddr3_pllm = (((ddr3pllctl0val & 0x0007FFC0) >> 6) + 1); |
537 | IFPRINT(platform_write("PA PLL programmable multiplier = %d\n", ddr3_pllm)); | 559 | IFPRINT(platform_write("DDR3 PLL programmable multiplier = %d\n", ddr3_pllm)); |
538 | 560 | ||
539 | /* Tells the divider value for the DDR3 PLL */ | 561 | /* Tells the divider value for the DDR3 PLL */ |
540 | ddr3_plld = (((ddr3pllctl0val & 0x0000003F) >> 0) +1); | 562 | ddr3_plld = (((ddr3pllctl0val & 0x0000003F) >> 0) +1); |
541 | IFPRINT(platform_write("PA PLL programmable divider = %d\n", ddr3_plld)); | 563 | IFPRINT(platform_write("DDR3 PLL programmable divider = %d\n", ddr3_plld)); |
542 | 564 | ||
543 | IFPRINT(platform_write("PLL2 Setup... Done.\n" )); | 565 | IFPRINT(platform_write("PLL2 Setup... Done.\n" )); |
544 | 566 | ||
diff --git a/evmc6678l/platform_lib/src/evmc6678.c b/evmc6678l/platform_lib/src/evmc6678.c index daa8cce..8cbd450 100755 --- a/evmc6678l/platform_lib/src/evmc6678.c +++ b/evmc6678l/platform_lib/src/evmc6678.c | |||
@@ -119,7 +119,7 @@ CSL_Status CorePllcHwSetup ( | |||
119 | CSL_BootCfgUnlockKicker(); | 119 | CSL_BootCfgUnlockKicker(); |
120 | 120 | ||
121 | 121 | ||
122 | /* Wait for Stabilization time (min 100 us) * | 122 | /* 1. Wait for Stabilization time (min 100 us) * |
123 | * The below loop is good enough for the Gel file to get minimum of * | 123 | * The below loop is good enough for the Gel file to get minimum of * |
124 | * 100 micro seconds, this should be appropriately modified for port * | 124 | * 100 micro seconds, this should be appropriately modified for port * |
125 | * to a C function * | 125 | * to a C function * |
@@ -127,44 +127,44 @@ CSL_Status CorePllcHwSetup ( | |||
127 | * more than required, but should be Okay */ | 127 | * more than required, but should be Okay */ |
128 | pll_delay(140056); | 128 | pll_delay(140056); |
129 | 129 | ||
130 | /* If PLL previously configured in RBL, avoid di/dt supply excursion by * | 130 | /* 2. Check the status of BYPASS bit in SECCTL register, * |
131 | * matching PLL output to RefClk rate * | 131 | * execute the following steps if * |
132 | * if RBL configures the PLL, the BYPASS bit would be set to '0' */ | 132 | * BYPASS == 1 (if bypass enabled), if BYPASS==0 then Jump to Step 3 */ |
133 | temp = SECCTL_REG & 0x00800000; /* Check the Bit 23 value */ | 133 | temp = SECCTL_REG & 0x00800000; /* Check the Bit 23 value */ |
134 | 134 | ||
135 | if (temp != 0) { | 135 | if (temp != 0) /* PLL BYPASS is enabled, we assume if not in Bypass ENSAT = 1 */ |
136 | /* PLL BYPASS is enabled, we assume if not in Bypass ENSAT = 1 */ | 136 | { |
137 | 137 | /* 2a. Usage Note 9: For optimal PLL operation, the ENSAT bit in the PLL control * | |
138 | /* Usage Note 9: For optimal PLL operation, the ENSAT bit in the PLL control * | 138 | * registers for the Main PLL, DDR3 PLL, and PA PLL should be set to 1. * |
139 | * registers for the Main PLL, DDR3 PLL, and PA PLL should be set to 1. * | 139 | * The PLL initialization sequence in the boot ROM sets this bit to 0 and * |
140 | * The PLL initialization sequence in the boot ROM sets this bit to 0 and * | 140 | * could lead to non-optimal PLL operation. Software can set the bit to the * |
141 | * could lead to non-optimal PLL operation. Software can set the bit to the * | 141 | * optimal value of 1 after boot * |
142 | * optimal value of 1 after boot * | 142 | * Ref: http://www.ti.com/lit/er/sprz334b/sprz334b.pdf * |
143 | * Ref: http://www.ti.com/lit/er/sprz334b/sprz334b.pdf * | 143 | * |31...7 |6 |5 4 |3...0 | * |
144 | * |31...7 |6 |5 4 |3...0 | * | 144 | * |Reserved |ENSAT |Reserved |BWADJ[11:8]| */ |
145 | * |Reserved |ENSAT |Reserved |BWADJ[11:8]| */ | 145 | |
146 | |||
147 | MAINPLLCTL1_REG = MAINPLLCTL1_REG | 0x00000040; | 146 | MAINPLLCTL1_REG = MAINPLLCTL1_REG | 0x00000040; |
148 | 147 | ||
149 | /* Clear PLLENSRC bit */ | 148 | /* 2b. Clear PLLEN bit (bypass enabled in PLL controller mux) */ |
150 | PLLCTL_REG &= ~(1 << 5); | ||
151 | |||
152 | /* Clear PLLEN bit */ | ||
153 | PLLCTL_REG &= ~(1 << 0); | 149 | PLLCTL_REG &= ~(1 << 0); |
154 | 150 | ||
155 | /* Wait for 4 RefClks * | 151 | /* 2c. Clear PLLENSRC bit (enable PLLEN to control PLL controller mux) */ |
152 | PLLCTL_REG &= ~(1 << 5); | ||
153 | |||
154 | /* 2d. Wait for 4 RefClks(to make sure the PLL controller * | ||
155 | * mux switches properly to the bypass) * | ||
156 | * Assuming slowest Ref clock of 25MHz, min: 160 ns delay */ | 156 | * Assuming slowest Ref clock of 25MHz, min: 160 ns delay */ |
157 | pll_delay(225); | 157 | pll_delay(225); |
158 | 158 | ||
159 | /* Bypass needed to perform PWRDN cycle for C6670 and C6678 * | 159 | /* 2e. Bypass needed to perform PWRDN cycle for C6670 and C6657 * |
160 | * Needed on all devices when in NOBOOT, I2C or SPI boot modes * | 160 | * Needed on all devices when in NOBOOT, I2C or SPI boot modes * |
161 | * Ref: Figure 4-2 of http://www.ti.com/lit/ug/sprugv2a/sprugv2a.pdf * | 161 | * Ref: Figure 4-2 of http://www.ti.com/lit/ug/sprugv2a/sprugv2a.pdf * |
162 | * PLL Secondary Control Register (SECCTL) Layout * | 162 | * PLL Secondary Control Register (SECCTL) Layout * |
163 | * |31...24 |23 |22...19 |18...0 | * | 163 | * |31...24 |23 |22...19 |18...0 | * |
164 | * |Reserved |BYPASS |OUTPUT DIVIDE |Reserved | */ | 164 | * |Reserved |BYPASS |OUTPUT DIVIDE |Reserved | */ |
165 | PLLCTL_REG |= 0x00800000; /* Set the Bit 23 */ | 165 | SECCTL_REG |= 0x00800000; /* Set the Bit 23 */ |
166 | 166 | ||
167 | /* Advisory 8: Multiple PLLs May Not Lock After Power-on Reset Issue * | 167 | /* 2f. Advisory 8: Multiple PLLs May Not Lock After Power-on Reset Issue * |
168 | * In order to ensure proper PLL startup, the PLL power_down pin needs to be * | 168 | * In order to ensure proper PLL startup, the PLL power_down pin needs to be * |
169 | * toggled. This is accomplished by toggling the PLLPWRDN bit in the PLLCTL * | 169 | * toggled. This is accomplished by toggling the PLLPWRDN bit in the PLLCTL * |
170 | * register. This needs to be done before the main PLL initialization * | 170 | * register. This needs to be done before the main PLL initialization * |
@@ -173,89 +173,105 @@ CSL_Status CorePllcHwSetup ( | |||
173 | * PLL Control Register (PLLCTL) Layout * | 173 | * PLL Control Register (PLLCTL) Layout * |
174 | * |31...4 |3 |2 |1 |0 | * | 174 | * |31...4 |3 |2 |1 |0 | * |
175 | * |Reserved |PLLRST |Reserved |PLLPWRDN |Reserved | */ | 175 | * |Reserved |PLLRST |Reserved |PLLPWRDN |Reserved | */ |
176 | 176 | ||
177 | PLLCTL_REG |= 0x00000002; /*Power Down the PLL */ | 177 | PLLCTL_REG |= 0x00000002; /* Power Down the PLL */ |
178 | 178 | ||
179 | /* Stay in a loop such that the bit is set for 5 µs (minimum) and * | 179 | /* 2g. Stay in a loop such that the bit is set for 5 µs (minimum) and * |
180 | * then clear the bit. */ | 180 | * then clear the bit. */ |
181 | 181 | ||
182 | pll_delay(14005); | 182 | pll_delay(14005); |
183 | 183 | ||
184 | /* Power up the PLL */ | 184 | /* 2h. Power up the PLL */ |
185 | PLLCTL_REG &= ~(0x00000002); | 185 | PLLCTL_REG &= ~(0x00000002); |
186 | |||
187 | } | 186 | } |
188 | /*while ((PLL1_STAT & 0x00000001) != 0) { | 187 | else |
189 | gostat_counter++; | 188 | { |
190 | }*/ | 189 | /* 3. Enable BYPASS in the PLL contoller */ |
191 | 190 | ||
192 | /* Place PLL in Reset, In PLLCTL, write PLLRST = 1 (PLL is reset) */ | 191 | /* 3a. Clear PLLEN bit (bypass enabled in PLL controller mux) */ |
193 | PLLCTL_REG |= 0x00000008; | 192 | PLLCTL_REG &= ~(1 << 0); |
194 | 193 | ||
195 | /* Wait for PLL Reset assertion Time (min: 50 us) * | 194 | /* 3b. Clear PLLENSRC bit (enable PLLEN to control PLL controller mux) */ |
196 | * Minimum delay in GEL can be 1 milli seconds, so program to 1ms=1000us, * | 195 | PLLCTL_REG &= ~(1 << 5); |
197 | * more than required, but should be Okay */ | 196 | |
198 | /*pll_delay(140050);*/ | 197 | /* 3c. Wait for 4 RefClks (to make sure the PLL controller * |
199 | 198 | * mux switches properly to bypass) * | |
200 | /* Program the necessary multipliers/dividers and BW adjustments */ | 199 | * Assuming slowest Ref clock of 25MHz, min: 160 ns delay */ |
200 | pll_delay(225); | ||
201 | } | ||
202 | |||
203 | /* 4, 5, 6 and 7 are done here: * | ||
204 | * Program the necessary multipliers/dividers and BW adjustments */ | ||
201 | prog_pll1_values(hwSetup); | 205 | prog_pll1_values(hwSetup); |
202 | 206 | ||
203 | /* go stat bit needs to be zero here */ | 207 | /* 8. Set PLL dividers if needed */ |
204 | /* Read the GOSTAT bit in PLLSTAT to make sure the bit returns to 0 to * | 208 | |
205 | * indicate that the GO operation has completed */ | 209 | /* part of 8, go stat bit needs to be zero here * |
206 | /* wait for the GOSTAT, but don't trap if lock is never read */ | 210 | * Read the GOSTAT bit in PLLSTAT to make sure the bit reurns to 0 to * |
207 | for (i = 0; i < 100; i++) { | 211 | * indicate that the GO operation has completed * |
212 | * wait for the GOSTAT, but don't trap if lock is never read */ | ||
213 | for (i = 0; i < 100; i++) | ||
214 | { | ||
208 | pll_delay(300); | 215 | pll_delay(300); |
209 | if ( (PLL1_STAT & 0x00000001) == 0 ) { | 216 | if ( (PLL1_STAT & 0x00000001) == 0 ) { |
210 | break; | 217 | break; |
211 | } | 218 | } |
212 | } | 219 | } |
213 | if (i == 100) { | 220 | if ( i == 100 ) { |
214 | return CSL_ESYS_FAIL; | 221 | return CSL_ESYS_FAIL; |
215 | } | 222 | } |
216 | 223 | ||
217 | /* Set PLL dividers if needed */ | 224 | /* part of 8, Set PLL dividers if needed */ |
218 | PLL1_DIV2 = (0x8000) | (hwSetup->pllDiv2); | 225 | PLL1_DIV2 = (0x8000) | (hwSetup->pllDiv2); |
219 | PLL1_DIV5 = (0x8000) | (hwSetup->pllDiv5); | 226 | PLL1_DIV5 = (0x8000) | (hwSetup->pllDiv5); |
220 | PLL1_DIV8 = (0x8000) | (hwSetup->pllDiv8); | 227 | PLL1_DIV8 = (0x8000) | (hwSetup->pllDiv8); |
221 | 228 | ||
222 | /* Program ALNCTLn */ | 229 | /* part of 8, Program ALNCTLn * |
223 | /* Set bit 1, 4 and 7 */ | 230 | * Set bit 1, 4 and 7 */ |
224 | PLLALNCTL_REG |= ( (1 << 1) | (1 << 4) | (1 << 7)); | 231 | PLLALNCTL_REG |= ((1 << 1) | (1 << 4) | (1 << 7)); |
225 | 232 | ||
226 | /* Set GOSET bit in PLLCMD to initiate the GO operation to change the divide * | 233 | /* part of 8, Set GOSET bit in PLLCMD to initiate the GO operation to change the divide * |
227 | * values and align the SYSCLKs as programmed */ | 234 | * values and align the SYSCLKSs as programmed */ |
228 | PLLCMD_REG |= 0x00000001; | 235 | PLLCMD_REG |= 0x00000001; |
229 | 236 | ||
230 | /* wait for the phase adj */ | 237 | /* part of 8, go stat bit needs to be zero here * |
231 | pll_delay(1000); | 238 | * Read the GOSTAT bit in PLLSTAT to make sure the bit reurns to 0 to * |
232 | 239 | * indicate that the GO operation has completed * | |
233 | /* Read the GOSTAT bit in PLLSTAT to make sure the bit returns to 0 to * | 240 | * wait for the GOSTAT, but don't trap if lock is never read */ |
234 | * indicate that the GO operation has completed */ | 241 | for (i = 0; i < 100; i++) |
235 | 242 | { | |
236 | /* wait for the GOSTAT, but don't trap if lock is never read */ | ||
237 | for (i = 0; i < 100; i++) { | ||
238 | pll_delay(300); | 243 | pll_delay(300); |
239 | if ( (PLL1_STAT & 0x00000001) == 0 ) { | 244 | if ( (PLL1_STAT & 0x00000001) == 0 ) { |
240 | break; | 245 | break; |
241 | } | 246 | } |
242 | } | 247 | } |
243 | if (i == 100) { | 248 | if ( i == 100 ) { |
244 | return CSL_ESYS_FAIL; | 249 | return CSL_ESYS_FAIL; |
245 | } | 250 | } |
246 | /* Wait for a minimum of 7 us*/ | 251 | |
247 | pll_delay (14006); | 252 | /* 9. Place PLL in Reset, In PLLCTL, write PLLRST = 1 (PLL is reset) */ |
248 | 253 | PLLCTL_REG |= 0x00000008; | |
249 | /*In PLLCTL, write PLLRST = 0 to bring PLL out of reset */ | 254 | |
255 | /* 10. Wait for PLL Reset assertion Time (min: 7 us) */ | ||
256 | pll_delay(14006); | ||
257 | |||
258 | /* 11. In PLLCTL, write PLLRST = 0 (PLL reset is de-asserted) */ | ||
250 | PLLCTL_REG &= ~(0x00000008); | 259 | PLLCTL_REG &= ~(0x00000008); |
251 | 260 | ||
252 | /* Wait for PLL Lock time (min 50 us) */ | 261 | /* 12. PLL Lock Delay needs to be 500 RefClk periods * (PLLD + 1) * |
253 | pll_delay (140056 >> 1); | 262 | * i.e., Wait for at least 500 * CLKIN cycles * (PLLD + 1) (PLL lock timer) * |
254 | PLL1_SECCTL &= ~(0x00800000); /* Release Bypass */ | 263 | * Using 2000 25ns RefClk periods per DM * |
255 | 264 | * Wait for PLL to lock min 50 us */ | |
256 | /* Set the PLLEN */ | 265 | pll_delay(140056 >> 1); |
266 | |||
267 | /* 13. In SECCTL, write BYPASS = 0 (enable PLL mux to switch to PLL mode) */ | ||
268 | SECCTL_REG &= ~(0x00800000); /* Release Bypass */ | ||
269 | |||
270 | /* 14. In PLLCTL, write PLLEN = 1 (enable PLL controller mux to switch to PLL mode) */ | ||
257 | PLLCTL_REG |= (1 << 0); | 271 | PLLCTL_REG |= (1 << 0); |
258 | 272 | ||
273 | /* 15. The PLL and PLL Controller are now initialized in PLL mode - Completed. */ | ||
274 | |||
259 | return status; | 275 | return status; |
260 | } | 276 | } |
261 | 277 | ||
@@ -340,9 +356,6 @@ SetPaPllConfig | |||
340 | /*Wait 4 cycles for the slowest of PLLOUT or reference clock source (CLKIN)*/ | 356 | /*Wait 4 cycles for the slowest of PLLOUT or reference clock source (CLKIN)*/ |
341 | /*pll_delay(4);*/ | 357 | /*pll_delay(4);*/ |
342 | 358 | ||
343 | /* In PLL Controller, reset the PLL (bit 14), set (PLLSEL bit 13) in PAPLLCTL1_REG register */ | ||
344 | PAPLLCTL1_REG |= 0x00006000; | ||
345 | |||
346 | /* Wait for the PLL Reset time (min: 1000 ns) */ | 359 | /* Wait for the PLL Reset time (min: 1000 ns) */ |
347 | /*pll_delay(1400);*/ | 360 | /*pll_delay(1400);*/ |
348 | 361 | ||
@@ -356,15 +369,21 @@ SetPaPllConfig | |||
356 | PAPLLCTL0_REG |= ((pa_pllm << 6) & 0x0007FFC0 ); | 369 | PAPLLCTL0_REG |= ((pa_pllm << 6) & 0x0007FFC0 ); |
357 | 370 | ||
358 | /* Set the BWADJ */ | 371 | /* Set the BWADJ */ |
359 | temp = (pa_pllm >> 1); | 372 | temp = ((pa_pllm + 1) >> 1) - 1; |
360 | PAPLLCTL0_REG &= ~(0xFF000000); | 373 | PAPLLCTL0_REG &= ~(0xFF000000); |
361 | PAPLLCTL0_REG |= ((temp << 24) & 0xFF000000); | 374 | PAPLLCTL0_REG |= ((temp << 24) & 0xFF000000); |
362 | PAPLLCTL1_REG &= ~(0x0000000F); | 375 | PAPLLCTL1_REG &= ~(0x0000000F); |
363 | PAPLLCTL1_REG |= ((temp >> 8) & 0x0000000F); | 376 | PAPLLCTL1_REG |= ((temp >> 8) & 0x0000000F); |
377 | |||
378 | /* In PLL Controller, reset the PLL (bit 14) in PAPLLCTL1_REG register */ | ||
379 | PAPLLCTL1_REG |= 0x00004000; | ||
364 | 380 | ||
365 | /*Wait for PLL to lock min 5 micro seconds*/ | 381 | /*Wait for PLL to lock min 5 micro seconds*/ |
366 | pll_delay(7000); | 382 | pll_delay(7000); |
367 | 383 | ||
384 | /*In PAPLLCTL1_REG, write PLLSELECT = 1 (for selecting the output of PASS PLL as the input to PASS) */ | ||
385 | PAPLLCTL1_REG |= 0x00002000; | ||
386 | |||
368 | /*In PAPLLCTL1_REG, write PLLRST = 0 to bring PLL out of reset */ | 387 | /*In PAPLLCTL1_REG, write PLLRST = 0 to bring PLL out of reset */ |
369 | PAPLLCTL1_REG &= ~(0x00004000); | 388 | PAPLLCTL1_REG &= ~(0x00004000); |
370 | 389 | ||
@@ -497,9 +516,6 @@ CSL_Status SetDDR3PllConfig(void) | |||
497 | /*Wait 4 cycles for the slowest of PLLOUT or reference clock source (CLKIN)*/ | 516 | /*Wait 4 cycles for the slowest of PLLOUT or reference clock source (CLKIN)*/ |
498 | /*pll_delay(4);*/ | 517 | /*pll_delay(4);*/ |
499 | 518 | ||
500 | /* In PLL Controller, reset the PLL (bit 13) in DDR3PLLCTL1_REG register */ | ||
501 | DDR3PLLCTL1_REG |= 0x00002000; | ||
502 | |||
503 | /* Wait for the PLL Reset time (min: 1000 ns) */ | 519 | /* Wait for the PLL Reset time (min: 1000 ns) */ |
504 | /*pll_delay(1400);*/ | 520 | /*pll_delay(1400);*/ |
505 | 521 | ||
@@ -513,11 +529,14 @@ CSL_Status SetDDR3PllConfig(void) | |||
513 | DDR3PLLCTL0_REG |= ((ddr3_pllm << 6) & 0x0007FFC0 ); | 529 | DDR3PLLCTL0_REG |= ((ddr3_pllm << 6) & 0x0007FFC0 ); |
514 | 530 | ||
515 | /* Set the BWADJ */ | 531 | /* Set the BWADJ */ |
516 | temp = (ddr3_pllm >> 1); | 532 | temp = ((ddr3_pllm + 1) >> 1) - 1; |
517 | DDR3PLLCTL0_REG &= ~(0xFF000000); | 533 | DDR3PLLCTL0_REG &= ~(0xFF000000); |
518 | DDR3PLLCTL0_REG |= ((temp << 24) & 0xFF000000); | 534 | DDR3PLLCTL0_REG |= ((temp << 24) & 0xFF000000); |
519 | DDR3PLLCTL1_REG &= ~(0x0000000F); | 535 | DDR3PLLCTL1_REG &= ~(0x0000000F); |
520 | DDR3PLLCTL1_REG |= ((temp >> 8) & 0x0000000F); | 536 | DDR3PLLCTL1_REG |= ((temp >> 8) & 0x0000000F); |
537 | |||
538 | /* In PLL Controller, reset the PLL (bit 13) in DDR3PLLCTL1_REG register */ | ||
539 | DDR3PLLCTL1_REG |= 0x00002000; | ||
521 | 540 | ||
522 | /*Wait for PLL to lock min 5 micro seconds*/ | 541 | /*Wait for PLL to lock min 5 micro seconds*/ |
523 | pll_delay(7000); | 542 | pll_delay(7000); |
@@ -538,11 +557,11 @@ CSL_Status SetDDR3PllConfig(void) | |||
538 | 557 | ||
539 | /* Tells the multiplier value for the DDR3 PLL */ | 558 | /* Tells the multiplier value for the DDR3 PLL */ |
540 | ddr3_pllm = (((ddr3pllctl0val & 0x0007FFC0) >> 6) + 1); | 559 | ddr3_pllm = (((ddr3pllctl0val & 0x0007FFC0) >> 6) + 1); |
541 | IFPRINT(platform_write("PA PLL programmable multiplier = %d\n", ddr3_pllm)); | 560 | IFPRINT(platform_write("DDR3 PLL programmable multiplier = %d\n", ddr3_pllm)); |
542 | 561 | ||
543 | /* Tells the divider value for the DDR3 PLL */ | 562 | /* Tells the divider value for the DDR3 PLL */ |
544 | ddr3_plld = (((ddr3pllctl0val & 0x0000003F) >> 0) +1); | 563 | ddr3_plld = (((ddr3pllctl0val & 0x0000003F) >> 0) +1); |
545 | IFPRINT(platform_write("PA PLL programmable divider = %d\n", ddr3_plld)); | 564 | IFPRINT(platform_write("DDR3 PLL programmable divider = %d\n", ddr3_plld)); |
546 | 565 | ||
547 | IFPRINT(platform_write("PLL2 Setup... Done.\n" )); | 566 | IFPRINT(platform_write("PLL2 Setup... Done.\n" )); |
548 | 567 | ||