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authorHao Zhang2013-03-18 13:31:26 -0500
committerHao Zhang2013-03-18 13:31:26 -0500
commit7a7c1fd3027ce1b37b73848bc28c243539fcf3ff (patch)
treed97f34fdbde7faad68f467112e8308681dec8847
parentcd8df024db3ba3099e51770efe41ca8b171dd547 (diff)
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MCSDK 3.0: update platform lib to support DDR3A 1333M and DDR3B 1600M rate
-rwxr-xr-xevmk2h/platform_lib/include/evmc66x_pllc.h1
-rwxr-xr-xevmk2h/platform_lib/include/platform_internal.h140
-rwxr-xr-xevmk2h/platform_lib/src/evmc66x.c936
-rwxr-xr-xevmk2h/platform_lib/src/platform.c24
4 files changed, 349 insertions, 752 deletions
diff --git a/evmk2h/platform_lib/include/evmc66x_pllc.h b/evmk2h/platform_lib/include/evmc66x_pllc.h
index 0b4dd1a..1fa54b2 100755
--- a/evmk2h/platform_lib/include/evmc66x_pllc.h
+++ b/evmk2h/platform_lib/include/evmc66x_pllc.h
@@ -87,7 +87,6 @@ CSL_Status CorePllcGetHwSetup(PllcHwSetup*);
87CSL_Status CorePllcHwSetup (PllcHwSetup*); 87CSL_Status CorePllcHwSetup (PllcHwSetup*);
88CSL_Status corePllcInit(void *); 88CSL_Status corePllcInit(void *);
89CSL_Status SetPaPllConfig(void); 89CSL_Status SetPaPllConfig(void);
90CSL_Status SetDDR3PllConfig();
91CSL_Status DDR3Init(void); 90CSL_Status DDR3Init(void);
92void evmI2CInit(void); 91void evmI2CInit(void);
93 92
diff --git a/evmk2h/platform_lib/include/platform_internal.h b/evmk2h/platform_lib/include/platform_internal.h
index f593770..3b6c0ff 100755
--- a/evmk2h/platform_lib/include/platform_internal.h
+++ b/evmk2h/platform_lib/include/platform_internal.h
@@ -307,8 +307,10 @@ extern void xmc_setup();
307#define DEVSTAT_REG (*((volatile uint32_t *) 0x02620020)) 307#define DEVSTAT_REG (*((volatile uint32_t *) 0x02620020))
308#define MAINPLLCTL0_REG (*((volatile uint32_t *) 0x02620328)) 308#define MAINPLLCTL0_REG (*((volatile uint32_t *) 0x02620328))
309#define MAINPLLCTL1_REG (*((volatile uint32_t *) 0x0262032C)) 309#define MAINPLLCTL1_REG (*((volatile uint32_t *) 0x0262032C))
310#define DDR3PLLCTL0_REG (*((volatile uint32_t *) 0x02620330)) 310
311#define DDR3PLLCTL1_REG (*((volatile uint32_t *) 0x02620334)) 311/* DDR3A and DDR3B PLL control registers */
312#define DDR3PLLCTL0_REG(x) (*((volatile uint32_t *) (0x02620360+(8*x))))
313#define DDR3PLLCTL1_REG(x) (*((volatile uint32_t *) (0x02620364+(8*x))))
312 314
313/* PA PLL Registers */ 315/* PA PLL Registers */
314#define PAPLLCTL0_REG (*((volatile uint32_t *) 0x02620338)) 316#define PAPLLCTL0_REG (*((volatile uint32_t *) 0x02620338))
@@ -387,8 +389,136 @@ extern void xmc_setup();
387#define PLLM_PASS 31 389#define PLLM_PASS 31
388#define PLLD_PASS 1 390#define PLLD_PASS 1
389 391
390/* DDR3 PLL settings for 1333 MHz */ 392/* DDR3A PLL settings for 1333 MHz */
391#define PLLM_DDR3 19 393#define PLLM_DDR3A 20
392#define PLLD_DDR3 0 394#define PLLD_DDR3A 1
395#define PLLOD_DDR3A 6
396
397/* DDR3B PLL settings for 1600 MHz */
398#define PLLM_DDR3B 16
399#define PLLD_DDR3B 1
400#define PLLOD_DDR3B 4
401
402/* DDR3 configuration definitions */
403
404/* PLL identifiers */
405enum pll_type_e {
406 DDR3A_PLL,
407 DDR3B_PLL
408};
409
410/* PLL configuration data */
411typedef struct pll_init_data {
412 uint32_t pll;
413 uint32_t pll_m; /* PLL Multiplier */
414 uint32_t pll_d; /* PLL divider */
415 uint32_t pll_od; /* PLL output divider */
416} pll_init_data;
417
418#define DDR_CFG_DELAY 200
419
420/* DDR3A definitions */
421#define TCI6638_DDR3A_EMIF_CTRL_BASE 0x21010000
422#define TCI6638_DDR3A_EMIF_DATA_BASE 0x80000000
423#define TCI6638_DDR3A_DDRPHYC 0x02329000
424/* DDR3B definitions */
425#define TCI6638_DDR3B_EMIF_CTRL_BASE 0x21020000
426#define TCI6638_DDR3B_EMIF_DATA_BASE 0x60000000
427#define TCI6638_DDR3B_DDRPHYC 0x02328000
428
429#define TCI6638_DDRPHY_PIR_OFFSET 0x04
430#define TCI6638_DDRPHY_PGCR0_OFFSET 0x08
431#define TCI6638_DDRPHY_PGCR1_OFFSET 0x0C
432#define TCI6638_DDRPHY_PGSR0_OFFSET 0x10
433#define TCI6638_DDRPHY_PGSR1_OFFSET 0x14
434#define TCI6638_DDRPHY_PLLCR_OFFSET 0x18
435#define TCI6638_DDRPHY_PTR0_OFFSET 0x1C
436#define TCI6638_DDRPHY_PTR1_OFFSET 0x20
437#define TCI6638_DDRPHY_PTR2_OFFSET 0x24
438#define TCI6638_DDRPHY_PTR3_OFFSET 0x28
439#define TCI6638_DDRPHY_PTR4_OFFSET 0x2C
440#define TCI6638_DDRPHY_DCR_OFFSET 0x44
441
442#define TCI6638_DDRPHY_DTPR0_OFFSET 0x48
443#define TCI6638_DDRPHY_DTPR1_OFFSET 0x4C
444#define TCI6638_DDRPHY_DTPR2_OFFSET 0x50
445
446#define TCI6638_DDRPHY_MR0_OFFSET 0x54
447#define TCI6638_DDRPHY_MR1_OFFSET 0x58
448#define TCI6638_DDRPHY_MR2_OFFSET 0x5C
449#define TCI6638_DDRPHY_DTCR_OFFSET 0x68
450#define TCI6638_DDRPHY_PGCR2_OFFSET 0x8C
451
452#define TCI6638_DDRPHY_ZQ0CR1_OFFSET 0x184
453#define TCI6638_DDRPHY_ZQ1CR1_OFFSET 0x194
454#define TCI6638_DDRPHY_ZQ2CR1_OFFSET 0x1A4
455#define TCI6638_DDRPHY_ZQ3CR1_OFFSET 0x1B4
456
457#define TCI6638_DDRPHY_DATX8_8_OFFSET 0x3C0
458
459#define TCI6638_DDR3_MIDR_OFFSET 0x00
460#define TCI6638_DDR3_STATUS_OFFSET 0x04
461#define TCI6638_DDR3_SDCFG_OFFSET 0x08
462#define TCI6638_DDR3_SDRFC_OFFSET 0x10
463#define TCI6638_DDR3_SDTIM1_OFFSET 0x18
464#define TCI6638_DDR3_SDTIM2_OFFSET 0x1C
465#define TCI6638_DDR3_SDTIM3_OFFSET 0x20
466#define TCI6638_DDR3_SDTIM4_OFFSET 0x28
467#define TCI6638_DDR3_PMCTL_OFFSET 0x38
468#define TCI6638_DDR3_ZQCFG_OFFSET 0xC8
469
470#define IODDRM_MASK 0x00000180
471#define ZCKSEL_MASK 0x01800000
472#define CL_MASK 0x00000072
473#define WR_MASK 0x00000E00
474#define BL_MASK 0x00000003
475#define RRMODE_MASK 0x00040000
476#define UDIMM_MASK 0x20000000
477#define BYTEMASK_MASK 0x0000FC00
478#define MPRDQ_MASK 0x00000080
479#define PDQ_MASK 0x00000070
480#define NOSRA_MASK 0x08000000
481#define ECC_MASK 0x00000001
482
483typedef struct ddr3_phy_config {
484 uint32_t pllcr;
485 uint32_t pgcr1_mask;
486 uint32_t pgcr1_val;
487 uint32_t ptr0;
488 uint32_t ptr1;
489 uint32_t ptr2;
490 uint32_t ptr3;
491 uint32_t ptr4;
492 uint32_t dcr_mask;
493 uint32_t dcr_val;
494 uint32_t dtpr0;
495 uint32_t dtpr1;
496 uint32_t dtpr2;
497 uint32_t mr0;
498 uint32_t mr1;
499 uint32_t mr2;
500 uint32_t dtcr;
501 uint32_t pgcr2;
502 uint32_t zq0cr1;
503 uint32_t zq1cr1;
504 uint32_t zq2cr1;
505 uint32_t pir_v1;
506 uint32_t pir_v2;
507} ddr3_phy_config;
508
509typedef struct ddr3_emif_config {
510 uint32_t sdcfg;
511 uint32_t sdtim1;
512 uint32_t sdtim2;
513 uint32_t sdtim3;
514 uint32_t sdtim4;
515 uint32_t zqcfg;
516 uint32_t sdrfc;
517} ddr3_emif_config;
518
519#define read_reg(a) (*(volatile uint32_t *)(a))
520#define write_reg(v,a) (*(volatile uint32_t *)(a) = (v))
521
522CSL_Status SetDDR3PllConfig(pll_init_data *data);
393 523
394#endif 524#endif
diff --git a/evmk2h/platform_lib/src/evmc66x.c b/evmk2h/platform_lib/src/evmc66x.c
index de9c26c..32fe706 100755
--- a/evmk2h/platform_lib/src/evmc66x.c
+++ b/evmk2h/platform_lib/src/evmc66x.c
@@ -1,34 +1,34 @@
1/****************************************************************************** 1/******************************************************************************
2 * Copyright (c) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 2 * Copyright (c) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
3 * 3 *
4 * Redistribution and use in source and binary forms, with or without 4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions 5 * modification, are permitted provided that the following conditions
6 * are met: 6 * are met:
7 * 7 *
8 * Redistributions of source code must retain the above copyright 8 * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer. 9 * notice, this list of conditions and the following disclaimer.
10 * 10 *
11 * Redistributions in binary form must reproduce the above copyright 11 * Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the 12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the 13 * documentation and/or other materials provided with the
14 * distribution. 14 * distribution.
15 * 15 *
16 * Neither the name of Texas Instruments Incorporated nor the names of 16 * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived 17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission. 18 * from this software without specific prior written permission.
19 * 19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 * 31 *
32 *****************************************************************************/ 32 *****************************************************************************/
33 33
34/****************************************************************************** 34/******************************************************************************
@@ -36,7 +36,7 @@
36 * File Name: evmc6670.c 36 * File Name: evmc6670.c
37 * 37 *
38 * Description: This contains TMS320C6670 specific functions. 38 * Description: This contains TMS320C6670 specific functions.
39 * 39 *
40 ******************************************************************************/ 40 ******************************************************************************/
41 41
42/************************ 42/************************
@@ -181,8 +181,8 @@ CSL_Status CorePllcHwSetup (
181 181
182 pll_delay(14005); 182 pll_delay(14005);
183 183
184 /* Power up the PLL */ 184 /* Power up the PLL */
185 PLLCTL_REG &= ~(0x00000002); 185 PLLCTL_REG &= ~(0x00000002);
186 186
187 } 187 }
188 188
@@ -198,7 +198,7 @@ CSL_Status CorePllcHwSetup (
198 prog_pll1_values(hwSetup); 198 prog_pll1_values(hwSetup);
199 199
200 /* go stat bit needs to be zero here */ 200 /* go stat bit needs to be zero here */
201 /* Read the GOSTAT bit in PLLSTAT to make sure the bit returns to 0 to * 201 /* Read the GOSTAT bit in PLLSTAT to make sure the bit returns to 0 to *
202 * indicate that the GO operation has completed */ 202 * indicate that the GO operation has completed */
203 /* wait for the GOSTAT, but don't trap if lock is never read */ 203 /* wait for the GOSTAT, but don't trap if lock is never read */
204 for (i = 0; i < 100; i++) { 204 for (i = 0; i < 100; i++) {
@@ -227,7 +227,7 @@ CSL_Status CorePllcHwSetup (
227 /* wait for the phase adj */ 227 /* wait for the phase adj */
228 pll_delay(1000); 228 pll_delay(1000);
229 229
230 /* Read the GOSTAT bit in PLLSTAT to make sure the bit returns to 0 to * 230 /* Read the GOSTAT bit in PLLSTAT to make sure the bit returns to 0 to *
231 * indicate that the GO operation has completed */ 231 * indicate that the GO operation has completed */
232 232
233 /* wait for the GOSTAT, but don't trap if lock is never read */ 233 /* wait for the GOSTAT, but don't trap if lock is never read */
@@ -288,11 +288,11 @@ CSL_Status CorePllcGetHwSetup (
288 return status; 288 return status;
289} 289}
290 290
291CSL_Status 291CSL_Status
292SetPaPllConfig 292SetPaPllConfig
293( 293(
294 void 294 void
295 ) 295 )
296{ 296{
297 uint32_t passclksel = (DEVSTAT_REG & PASSCLKSEL_MASK); 297 uint32_t passclksel = (DEVSTAT_REG & PASSCLKSEL_MASK);
298 uint32_t papllctl0val = PAPLLCTL0_REG; 298 uint32_t papllctl0val = PAPLLCTL0_REG;
@@ -303,7 +303,7 @@ SetPaPllConfig
303 int pass_freq; 303 int pass_freq;
304 int pass_freM,pass_freD; 304 int pass_freM,pass_freD;
305 305
306 if (passclksel == 0) 306 if (passclksel == 0)
307 { 307 {
308 IFPRINT(platform_write("SYSCLK/ALTCORECLK is the input to the PA PLL...\n")); 308 IFPRINT(platform_write("SYSCLK/ALTCORECLK is the input to the PA PLL...\n"));
309 } 309 }
@@ -311,7 +311,7 @@ SetPaPllConfig
311 /* Unlock the Boot Config */ 311 /* Unlock the Boot Config */
312 CSL_BootCfgUnlockKicker(); 312 CSL_BootCfgUnlockKicker();
313 313
314 if (DNUM == 0) 314 if (DNUM == 0)
315 { 315 {
316 /* Usage Note 9: For optimal PLL operation, the ENSAT bit in the PLL control * 316 /* Usage Note 9: For optimal PLL operation, the ENSAT bit in the PLL control *
317 * registers for the Main PLL, DDR3 PLL, and PA PLL should be set to 1. * 317 * registers for the Main PLL, DDR3 PLL, and PA PLL should be set to 1. *
@@ -354,7 +354,7 @@ SetPaPllConfig
354 354
355 /* Set the BWADJ */ 355 /* Set the BWADJ */
356 temp = ((pa_pllm + 1) >> 1) - 1; 356 temp = ((pa_pllm + 1) >> 1) - 1;
357 PAPLLCTL0_REG &= ~(0xFF000000); 357 PAPLLCTL0_REG &= ~(0xFF000000);
358 PAPLLCTL0_REG |= ((temp << 24) & 0xFF000000); 358 PAPLLCTL0_REG |= ((temp << 24) & 0xFF000000);
359 PAPLLCTL1_REG &= ~(0x0000000F); 359 PAPLLCTL1_REG &= ~(0x0000000F);
360 PAPLLCTL1_REG |= ((temp >> 8) & 0x0000000F); 360 PAPLLCTL1_REG |= ((temp >> 8) & 0x0000000F);
@@ -421,10 +421,10 @@ SetPaPllConfig
421 ***************************************************************************************/ 421 ***************************************************************************************/
422void PowerUpDomains (void) 422void PowerUpDomains (void)
423{ 423{
424 /* PASS power domain is turned OFF by default. It needs to be turned on before doing any 424 /* PASS power domain is turned OFF by default. It needs to be turned on before doing any
425 * PASS device register access. This not required for the simulator. */ 425 * PASS device register access. This not required for the simulator. */
426 426
427 /* Set PASS Power domain to ON */ 427 /* Set PASS Power domain to ON */
428 CSL_PSC_enablePowerDomain (CSL_PSC_PD_ALWAYSON); 428 CSL_PSC_enablePowerDomain (CSL_PSC_PD_ALWAYSON);
429 429
430 /* Enable the clocks for PASS modules */ 430 /* Enable the clocks for PASS modules */
@@ -437,10 +437,10 @@ void PowerUpDomains (void)
437 while (!CSL_PSC_isStateTransitionDone (CSL_PSC_PD_ALWAYSON)); 437 while (!CSL_PSC_isStateTransitionDone (CSL_PSC_PD_ALWAYSON));
438 438
439 439
440 /* PASS power domain is turned OFF by default. It needs to be turned on before doing any 440 /* PASS power domain is turned OFF by default. It needs to be turned on before doing any
441 * PASS device register access. This not required for the simulator. */ 441 * PASS device register access. This not required for the simulator. */
442 442
443 /* Set PASS Power domain to ON */ 443 /* Set PASS Power domain to ON */
444 CSL_PSC_enablePowerDomain (CSL_PSC_PD_NETCP); 444 CSL_PSC_enablePowerDomain (CSL_PSC_PD_NETCP);
445 445
446 /* Enable the clocks for PASS modules */ 446 /* Enable the clocks for PASS modules */
@@ -455,21 +455,21 @@ void PowerUpDomains (void)
455 while (!CSL_PSC_isStateTransitionDone (CSL_PSC_PD_NETCP)); 455 while (!CSL_PSC_isStateTransitionDone (CSL_PSC_PD_NETCP));
456} 456}
457 457
458CSL_Status SetDDR3PllConfig(void) 458CSL_Status SetDDR3PllConfig(pll_init_data *data)
459{ 459{
460 460
461 uint32_t ddr3pllctl0val = DDR3PLLCTL0_REG; 461 uint32_t ddr3pllctl0val = DDR3PLLCTL0_REG(data->pll);
462 uint32_t obsclkval = OBSCLCTL_REG; 462 uint32_t ddr3_pllm = data->pll_m - 1;
463 uint32_t ddr3_pllm = PLLM_DDR3; 463 uint32_t ddr3_plld = (data->pll_d - 1) & 0x3f;
464 uint32_t ddr3_plld = PLLD_DDR3; 464 uint32_t ddr3_pllod = (data->pll_od - 1) & 0xf;
465 uint32_t temp; 465 uint32_t bwadj, temp;
466 466
467 /* Unlock the Boot Config */ 467 /* Unlock the Boot Config */
468 CSL_BootCfgUnlockKicker(); 468 CSL_BootCfgUnlockKicker();
469 469
470 if (DNUM == 0) 470 if (DNUM == 0)
471 { 471 {
472 /* Usage Note 9: For optimal PLL operation, the ENSAT bit in the PLL control * 472 /* Usage Note 9: For optimal PLL operation, the ENSAT bit in the PLL control *
473 * registers for the Main PLL, DDR3 PLL, and PA PLL should be set to 1. * 473 * registers for the Main PLL, DDR3 PLL, and PA PLL should be set to 1. *
474 * The PLL initialization sequence in the boot ROM sets this bit to 0 and * 474 * The PLL initialization sequence in the boot ROM sets this bit to 0 and *
475 * could lead to non-optimal PLL operation. Software can set the bit to the * 475 * could lead to non-optimal PLL operation. Software can set the bit to the *
@@ -478,7 +478,7 @@ CSL_Status SetDDR3PllConfig(void)
478 * |31...7 |6 |5 4 |3...0 | * 478 * |31...7 |6 |5 4 |3...0 | *
479 * |Reserved |ENSAT |Reserved |BWADJ[11:8]| */ 479 * |Reserved |ENSAT |Reserved |BWADJ[11:8]| */
480 480
481 DDR3PLLCTL0_REG |= 0x00000040; 481 DDR3PLLCTL1_REG(data->pll) |= 0x00000040;
482 482
483 /* Wait for the PLL Reset time (min: 1000 ns) */ 483 /* Wait for the PLL Reset time (min: 1000 ns) */
484 /*pll_delay(1400);*/ 484 /*pll_delay(1400);*/
@@ -487,39 +487,31 @@ CSL_Status SetDDR3PllConfig(void)
487 * DDR3PLLCTL0_REG Bit map * 487 * DDR3PLLCTL0_REG Bit map *
488 * |31...24 |23 |22...19 |18...6 |5...0 | * 488 * |31...24 |23 |22...19 |18...6 |5...0 | *
489 * |BWADJ[7:0] |BYPASS |Reserved |PLLM |PLLD | */ 489 * |BWADJ[7:0] |BYPASS |Reserved |PLLM |PLLD | */
490 temp = DDR3PLLCTL0_REG(data->pll);
491 temp &= 0x00800000; /* clear everything except Bypass */
490 492
491 DDR3PLLCTL0_REG |= 0x00800000; /* Set the Bit 23 */ 493 /* Program the necessary multipliers/dividers and BW adjustments */
494 bwadj = ddr3_pllm >> 1;
495 temp |= ((bwadj & 0xff) << 24) | (ddr3_pllm << 6) | (ddr3_plld & 0x3f) | (ddr3_pllod<<19);
496 DDR3PLLCTL0_REG(data->pll) = temp;
492 497
493 /*Wait 4 cycles for the slowest of PLLOUT or reference clock source (CLKIN)*/ 498 /*Wait 4 cycles for the slowest of PLLOUT or reference clock source (CLKIN)*/
494 /*pll_delay(4);*/ 499 /*pll_delay(4);*/
495 500
501 /* Set BWADJ[11:8] bits */
502 temp = DDR3PLLCTL1_REG(data->pll);
503 temp &= ~(0xf);
504 temp |= ((bwadj>>8) & 0xf);
505 DDR3PLLCTL1_REG(data->pll) = temp;
506
496 /* In PLL Controller, reset the PLL (bit 13) in DDR3PLLCTL1_REG register */ 507 /* In PLL Controller, reset the PLL (bit 13) in DDR3PLLCTL1_REG register */
497 DDR3PLLCTL1_REG |= 0x00002000; 508 DDR3PLLCTL1_REG(data->pll) |= 0x00002000;
498 509
499 /* Wait for the PLL Reset time (min: 1000 ns) */ 510 /* Wait for the PLL Reset time (min: 1000 ns) */
500 /*pll_delay(1400);*/
501
502 /* Program the necessary multipliers/dividers and BW adjustments */
503 /* Set the divider values */
504 DDR3PLLCTL0_REG &= ~(0x0000003F);
505 DDR3PLLCTL0_REG |= (ddr3_plld & 0x0000003F);
506
507 /* Set the Multipler values */
508 DDR3PLLCTL0_REG &= ~(0x0007FFC0);
509 DDR3PLLCTL0_REG |= ((ddr3_pllm << 6) & 0x0007FFC0 );
510
511 /* Set the BWADJ */
512 temp = ((ddr3_pllm + 1) >> 1) - 1;
513 DDR3PLLCTL0_REG &= ~(0xFF000000);
514 DDR3PLLCTL0_REG |= ((temp << 24) & 0xFF000000);
515 DDR3PLLCTL1_REG &= ~(0x0000000F);
516 DDR3PLLCTL1_REG |= ((temp >> 8) & 0x0000000F);
517
518 /*Wait for PLL to lock min 5 micro seconds*/
519 pll_delay(7000); 511 pll_delay(7000);
520 512
521 /*In DDR3PLLCTL1_REG, write PLLRST = 0 to bring PLL out of reset */ 513 /*In DDR3PLLCTL1_REG, write PLLRST = 0 to bring PLL out of reset */
522 DDR3PLLCTL1_REG &= ~(0x00002000); 514 DDR3PLLCTL1_REG(data->pll) &= ~(0x00002000);
523 515
524 /*Wait for PLL to lock min 50 micro seconds*/ 516 /*Wait for PLL to lock min 50 micro seconds*/
525 pll_delay(70000); 517 pll_delay(70000);
@@ -528,9 +520,11 @@ CSL_Status SetDDR3PllConfig(void)
528 * DDR3PLLCTL0_REG Bit map * 520 * DDR3PLLCTL0_REG Bit map *
529 * |31...24 |23 |22...19 |18...6 |5...0 | * 521 * |31...24 |23 |22...19 |18...6 |5...0 | *
530 * |BWADJ[7:0] |BYPASS |Reserved |PLLM |PLLD | */ 522 * |BWADJ[7:0] |BYPASS |Reserved |PLLM |PLLD | */
531 DDR3PLLCTL0_REG &= ~(0x00800000); /* ReSet the Bit 23 */ 523 DDR3PLLCTL0_REG(data->pll) &= ~(0x00800000); /* clear bypass, enable pll */
524
525 pll_delay (0x20000);
532 526
533 ddr3pllctl0val = DDR3PLLCTL0_REG; 527 ddr3pllctl0val = DDR3PLLCTL0_REG(data->pll);
534 528
535 /* Tells the multiplier value for the DDR3 PLL */ 529 /* Tells the multiplier value for the DDR3 PLL */
536 ddr3_pllm = (((ddr3pllctl0val & 0x0007FFC0) >> 6) + 1); 530 ddr3_pllm = (((ddr3pllctl0val & 0x0007FFC0) >> 6) + 1);
@@ -560,7 +554,7 @@ CSL_Status SetDDR3PllConfig(void)
560/* XMC MPAX register setting to access DDR3 config space */ 554/* XMC MPAX register setting to access DDR3 config space */
561/*--------------------------------------------------------------*/ 555/*--------------------------------------------------------------*/
562void xmc_setup() 556void xmc_setup()
563{ 557{
564 /* mapping for ddr emif registers XMPAX*2 */ 558 /* mapping for ddr emif registers XMPAX*2 */
565 559
566 XMPAX2_L = 0x121010FF; /* replacement addr + perm */ 560 XMPAX2_L = 0x121010FF; /* replacement addr + perm */
@@ -585,698 +579,160 @@ void xmc_setup()
585 579
586 /* set the xmpax for index2 */ 580 /* set the xmpax for index2 */
587 CSL_XMC_setXMPAXH(2, &mpaxh); 581 CSL_XMC_setXMPAXH(2, &mpaxh);
588 CSL_XMC_setXMPAXL(2, &mpaxl); 582 CSL_XMC_setXMPAXL(2, &mpaxl);
589#endif 583#endif
590} 584}
591 585
592#define OUTPUT_DIVIDE_OFFSET 19
593#define OUTPUT_DIVIDE_MASK 0xFF87FFFF
594
595#define IODDRM_MASK 0x00000180
596#define ZCKSEL_MASK 0x01800000
597#define CL_MASK 0x00000072
598#define WR_MASK 0x00000E00
599#define BL_MASK 0x00000003
600#define RRMODE_MASK 0x00040000
601#define UDIMM_MASK 0x20000000
602#define BYTEMASK_MASK 0x0000FC00
603#define MPRDQ_MASK 0x00000080
604#define PDQ_MASK 0x00000070
605#define NOSRA_MASK 0x08000000
606#define ECC_MASK 0x00000001
607#define RRMODE_MASK 0x00040000
608
609#define CHIP_LEVEL_REG 0x02620000
610#define DDR3APLLCTL0 *(volatile unsigned int*)(CHIP_LEVEL_REG + 0x0360)
611#define DDR3APLLCTL1 *(volatile unsigned int*)(CHIP_LEVEL_REG + 0x0364)
612#define DDR3BPLLCTL0 *(volatile unsigned int*)(CHIP_LEVEL_REG + 0x0368)
613#define DDR3BPLLCTL1 *(volatile unsigned int*)(CHIP_LEVEL_REG + 0x036C)
614
615#define DDR3A_BASE_ADDR (0x21010000)
616#define DDR3A_STATUS (*(volatile unsigned int *)(DDR3A_BASE_ADDR + 0x00000004))
617#define DDR3A_SDCFG (*(volatile unsigned int *)(DDR3A_BASE_ADDR + 0x00000008))
618#define DDR3A_SDRFC (*(volatile unsigned int*)(DDR3A_BASE_ADDR + 0x00000010))
619#define DDR3A_SDTIM1 (*(volatile unsigned int*)(DDR3A_BASE_ADDR + 0x00000018))
620#define DDR3A_SDTIM2 (*(volatile unsigned int*)(DDR3A_BASE_ADDR + 0x0000001C))
621#define DDR3A_SDTIM3 (*(volatile unsigned int*)(DDR3A_BASE_ADDR + 0x00000020))
622#define DDR3A_SDTIM4 (*(volatile unsigned int*)(DDR3A_BASE_ADDR + 0x00000028))
623#define DDR3A_ZQCFG (*(volatile unsigned int*)(DDR3A_BASE_ADDR + 0x000000C8))
624#define DDR3A_TMPALRT (*(volatile unsigned int*)(DDR3A_BASE_ADDR + 0x000000CC))
625#define DDR3A_DDRPHYC (*(volatile unsigned int*)(DDR3A_BASE_ADDR + 0x000000E4))
626
627#define DDR3A_PHY_CFG_BASE (0x02329000)
628#define DDR3A_PIR (*(volatile unsigned int*)(DDR3A_PHY_CFG_BASE + 0x00000004))
629#define DDR3A_PGCR0 (*(volatile unsigned int*)(DDR3A_PHY_CFG_BASE + 0x00000008))
630#define DDR3A_PGCR1 (*(volatile unsigned int*)(DDR3A_PHY_CFG_BASE + 0x0000000C))
631#define DDR3A_PGCR2 (*(volatile unsigned int*)(DDR3A_PHY_CFG_BASE + 0x0000008C))
632#define DDR3A_PGSR0 (*(volatile unsigned int*)(DDR3A_PHY_CFG_BASE + 0x00000010))
633#define DDR3A_PGSR1 (*(volatile unsigned int*)(DDR3A_PHY_CFG_BASE + 0x00000014))
634#define DDR3A_PLLCR (*(volatile unsigned int*)(DDR3A_PHY_CFG_BASE + 0x00000018))
635#define DDR3A_PTR0 (*(volatile unsigned int*)(DDR3A_PHY_CFG_BASE + 0x0000001C))
636#define DDR3A_PTR1 (*(volatile unsigned int*)(DDR3A_PHY_CFG_BASE + 0x00000020))
637#define DDR3A_PTR2 (*(volatile unsigned int*)(DDR3A_PHY_CFG_BASE + 0x00000024))
638#define DDR3A_PTR3 (*(volatile unsigned int*)(DDR3A_PHY_CFG_BASE + 0x00000028))
639#define DDR3A_PTR4 (*(volatile unsigned int*)(DDR3A_PHY_CFG_BASE + 0x0000002C))
640#define DDR3A_DSGCR (*(volatile unsigned int*)(DDR3A_PHY_CFG_BASE + 0x00000040))
641#define DDR3A_DCR (*(volatile unsigned int*)(DDR3A_PHY_CFG_BASE + 0x00000044))
642#define DDR3A_MR0 (*(volatile unsigned int*)(DDR3A_PHY_CFG_BASE + 0x00000054))
643#define DDR3A_MR1 (*(volatile unsigned int*)(DDR3A_PHY_CFG_BASE + 0x00000058))
644#define DDR3A_MR2 (*(volatile unsigned int*)(DDR3A_PHY_CFG_BASE + 0x0000005C))
645#define DDR3A_DTCR (*(volatile unsigned int*)(DDR3A_PHY_CFG_BASE + 0x00000068))
646#define DDR3A_DTPR0 (*(volatile unsigned int*)(DDR3A_PHY_CFG_BASE + 0x00000048))
647#define DDR3A_DTPR1 (*(volatile unsigned int*)(DDR3A_PHY_CFG_BASE + 0x0000004C))
648#define DDR3A_DTPR2 (*(volatile unsigned int*)(DDR3A_PHY_CFG_BASE + 0x00000050))
649
650#define DDR3A_ZQ0CR1 (*(volatile unsigned int*)(DDR3A_PHY_CFG_BASE + 0x00000184))
651#define DDR3A_ZQ1CR1 (*(volatile unsigned int*)(DDR3A_PHY_CFG_BASE + 0x00000194))
652#define DDR3A_ZQ2CR1 (*(volatile unsigned int*)(DDR3A_PHY_CFG_BASE + 0x000001A4))
653#define DDR3A_ZQ3CR1 (*(volatile unsigned int*)(DDR3A_PHY_CFG_BASE + 0x000001B4))
654
655#define DDR3A_DATX8_8 (*(volatile unsigned int*)(DDR3A_PHY_CFG_BASE + 0x000003C0))
656
657#define DDR3B_BASE_ADDR (0x21020000)
658#define DDR3B_STATUS (*(int*)(DDR3B_BASE_ADDR + 0x00000004))
659#define DDR3B_SDCFG (*(int*)(DDR3B_BASE_ADDR + 0x00000008))
660#define DDR3B_SDRFC (*(int*)(DDR3B_BASE_ADDR + 0x00000010))
661#define DDR3B_SDTIM1 (*(int*)(DDR3B_BASE_ADDR + 0x00000018))
662#define DDR3B_SDTIM2 (*(int*)(DDR3B_BASE_ADDR + 0x0000001C))
663#define DDR3B_SDTIM3 (*(int*)(DDR3B_BASE_ADDR + 0x00000020))
664#define DDR3B_SDTIM4 (*(int*)(DDR3B_BASE_ADDR + 0x00000028))
665#define DDR3B_ZQCFG (*(int*)(DDR3B_BASE_ADDR + 0x000000C8))
666#define DDR3B_TMPALRT (*(int*)(DDR3B_BASE_ADDR + 0x000000CC))
667#define DDR3B_DDRPHYC (*(int*)(DDR3B_BASE_ADDR + 0x000000E4))
668
669
670#define DDR3B_PHY_CFG_BASE (0x02328000)
671#define DDR3B_PIR (*(int*)(DDR3B_PHY_CFG_BASE + 0x00000004))
672#define DDR3B_PGCR0 (*(int*)(DDR3B_PHY_CFG_BASE + 0x00000008))
673#define DDR3B_PGCR1 (*(int*)(DDR3B_PHY_CFG_BASE + 0x0000000C))
674#define DDR3B_PGCR2 (*(int*)(DDR3B_PHY_CFG_BASE + 0x0000008C))
675#define DDR3B_PGSR0 (*(int*)(DDR3B_PHY_CFG_BASE + 0x00000010))
676#define DDR3B_PGSR1 (*(int*)(DDR3B_PHY_CFG_BASE + 0x00000014))
677#define DDR3B_PTR0 (*(int*)(DDR3B_PHY_CFG_BASE + 0x0000001C))
678#define DDR3B_PTR1 (*(int*)(DDR3B_PHY_CFG_BASE + 0x00000020))
679#define DDR3B_PTR2 (*(int*)(DDR3B_PHY_CFG_BASE + 0x00000024))
680#define DDR3B_PTR3 (*(int*)(DDR3B_PHY_CFG_BASE + 0x00000028))
681#define DDR3B_PTR4 (*(int*)(DDR3B_PHY_CFG_BASE + 0x0000002C))
682#define DDR3B_DSGCR (*(int*)(DDR3B_PHY_CFG_BASE + 0x00000040))
683#define DDR3B_DCR (*(int*)(DDR3B_PHY_CFG_BASE + 0x00000044))
684#define DDR3B_MR0 (*(int*)(DDR3B_PHY_CFG_BASE + 0x00000054))
685#define DDR3B_MR1 (*(int*)(DDR3B_PHY_CFG_BASE + 0x00000058))
686#define DDR3B_MR2 (*(int*)(DDR3B_PHY_CFG_BASE + 0x0000005C))
687#define DDR3B_DTCR (*(int*)(DDR3B_PHY_CFG_BASE + 0x00000068))
688#define DDR3B_DTPR0 (*(int*)(DDR3B_PHY_CFG_BASE + 0x00000048))
689#define DDR3B_DTPR1 (*(int*)(DDR3B_PHY_CFG_BASE + 0x0000004C))
690#define DDR3B_DTPR2 (*(int*)(DDR3B_PHY_CFG_BASE + 0x00000050))
691#define DDR3B_PLLCR (*(int*)(DDR3B_PHY_CFG_BASE + 0x00000018))
692
693#define DDR3B_ZQ0CR1 (*(int*)(DDR3B_PHY_CFG_BASE + 0x00000184))
694#define DDR3B_ZQ1CR1 (*(int*)(DDR3B_PHY_CFG_BASE + 0x00000194))
695#define DDR3B_ZQ2CR1 (*(int*)(DDR3B_PHY_CFG_BASE + 0x000001A4))
696#define DDR3B_ZQ3CR1 (*(int*)(DDR3B_PHY_CFG_BASE + 0x000001B4))
697
698void ddr3A_32bit_DDR800_setup()
699{
700 unsigned int multiplier = 15;
701 unsigned int divider = 0;
702 int temp;
703 unsigned int OD_val = 8;
704 unsigned int read_val;
705
706 CSL_BootCfgUnlockKicker();
707
708//1. Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010).
709 do {
710 read_val = DDR3A_PGSR0;
711 } while ((read_val&0x00000001) != 0x00000001);
712
713//4. Clocks are enabled and frequency is stable---------------------------------------
714//DDR3A PLL setup
715 //DDR3APLLCTL0 = DDR3APLLCTL0 & 0xFF7FFFFF;
716 // Set ENSAT = 1
717 DDR3APLLCTL1 |= 0x00000040;
718 // Put the PLL in PLL Mode
719 DDR3APLLCTL0 |= 0x00800000;
720 // In PLL Controller, reset the PLL (bit 13 in DDR3APLLCTL1 register)
721 DDR3APLLCTL1 |= 0x00002000;
722 // Program the necessary multipliers/dividers and BW adjustments
723 // Set the divider values
724 DDR3APLLCTL0 &= ~(0x0000003F);
725 DDR3APLLCTL0 |= (divider & 0x0000003F);
726 /* Step 7: Programming OD[3:0] in the SECCTL register */
727 DDR3APLLCTL0 &= OUTPUT_DIVIDE_MASK; // clear the OD bit field
728 DDR3APLLCTL0 |= ~OUTPUT_DIVIDE_MASK & (OD_val - 1) << OUTPUT_DIVIDE_OFFSET; // set the OD[3:0] bit field of PLLD to OD_val
729
730 /* Set the Multipler values */
731 DDR3APLLCTL0 &= ~(0x0007FFC0);
732 DDR3APLLCTL0 |= ((multiplier << 6) & 0x0007FFC0 );
733 temp = ((multiplier + 1) >> 1) - 1;
734 DDR3APLLCTL0 &= ~(0xFF000000);
735 DDR3APLLCTL0 |= ((temp << 24) & 0xFF000000);
736 DDR3APLLCTL1 &= ~(0x0000000F);
737 DDR3APLLCTL1 |= ((temp >> 8) & 0x0000000F);
738 //In DDR3PLLCTL1, write PLLRST = 0 to bring PLL out of reset
739 DDR3APLLCTL1 &= ~(0x00002000);
740 // Put the PLL in PLL Mode
741 DDR3APLLCTL0 &= ~(0x00800000); // ReSet the Bit 23
742//DDR3A PLL setup complete ---------------------------------------
743
744/*------------------------- Start PHY Configuration -------------------------------*/
745
746 //DDR3A_PGCR1 = 0x0280C487;
747
748 //5.a Program FRQSEL in the PLL Control Register (address offset 0x018).
749 DDR3A_PLLCR = 0xDC000; //Set FRQSEL=11, for ctl_clk between 166-275MHz
750
751 //5.b. Program WLSTEP=1, IODDRM=1, and ZCKSEL in the PHY General Configuration Register 1 (address offset 0x00C).
752 DDR3A_PGCR1 |= (1 << 2); //WLSTEP = 1
753
754 DDR3A_PGCR1 &= ~(IODDRM_MASK);
755 DDR3A_PGCR1 |= (( 1 << 7) & IODDRM_MASK);
756
757
758 DDR3A_PGCR1 &= ~(ZCKSEL_MASK);
759 DDR3A_PGCR1 |= (( 1 << 23) & ZCKSEL_MASK);
760
761
762 //5.c. Program PHY Timing Parameters Register 0-4 (address offset 0x01C - 0x02C).
763
764 DDR3A_PTR0 = 0x42C21590;
765
766 DDR3A_PTR1 = 0xD05612C0;
767
768// Maintaining default values of Phy Timing Parameters Register 2 in PUB
769
770 DDR3A_PTR3 = 0x06C30D40;//0x18061A80;
771
772 DDR3A_PTR4 = 0x06413880;//0x0AAE7100;
773
774//5.d. Program PDQ, MPRDQ, and BYTEMASK in the DRAM Configuration Register (address offset 0x044).
775// All other fields must be left at their default values.
776
777 DDR3A_DCR &= ~(PDQ_MASK); //PDQ = 0
778 DDR3A_DCR &= ~(MPRDQ_MASK); //MPRDQ = 0
779
780 DDR3A_DCR &= ~(BYTEMASK_MASK);
781 DDR3A_DCR |= (( 1 << 10) & BYTEMASK_MASK);
782
783
784DDR3A_DCR &= ~(NOSRA_MASK);
785DDR3A_DCR |= (( 1 << 27) & NOSRA_MASK);
786
787
788 DDR3A_DCR &= ~(UDIMM_MASK);
789 DDR3A_DCR |= (( 1 << 29) & UDIMM_MASK);
790
791
792//5.e. Program DRAM Timing Parameters Register 0-2 (address offset 0x048 - 0x050).
793
794 DDR3A_DTPR0 = 0x50CF6644; //0x50CE6644;
795 DDR3A_DTPR1 = 0x12834180;
796 DDR3A_DTPR2 = 0x50022A00;
797
798//5.f. Program BL=0, CL, WR, and PD=1 in the Mode Register 0 (address offset 0x054).
799 //All other fields must be left at their default values.
800
801DDR3A_MR0 = 0x00001420;
802
803
804//5.g. Program DIC, RTT, and TDQS in the Mode Register 1 (address offset 0x058).
805 //All other fields must be left at their default values.
806
807DDR3A_MR1 = 0x00000006;
808
809
810//---------------------------------------------------------------------------------------------------------
811
812//5.h. Program Mode Register 2 (address offset 0x05C).
813 // Maintaining default values of Program Mode Register 2
814 // DDR3A_MR2 = 0x00000018;
815
816//5.i. Program DTMPR=1, DTEXD, DTEXG, RANKEN=1 or 3, and RFSHDT=7 in the Data Training Configuration Register (address offset 0x068).
817 //All other fields must be left at their default values.
818 DDR3A_DTCR = 0x710035C7; //0x710035C7;
819
820//5.j. Program tREFPRD=(5*tREFI/ddr_clk_period) in the PHY General Configuration Register 2 (address offset 0x08C).
821 //All other fields must be left at their default values.
822
823 DDR3A_PGCR2 = 0x00F03D09; //NOBUB = 0, FXDLAT = 0
824//DDR3A_PGCR2 = 0x00F83D09; //NOBUB = 0, FXDLAT = 1
825
826//Set Impedence Register
827DDR3A_ZQ0CR1 = 0x0000005D;
828DDR3A_ZQ1CR1 = 0x0000005B;
829DDR3A_ZQ2CR1 = 0x0000005B;
830
831
832//6. Re-trigger PHY initialization in DDR PHY through the VBUSP interface.
833//6.a. Program 0x00000033 to the PHY Initialization Register (address offset 0x004) to re-trigger PLL, ZCAL, and DCAL initialization.
834
835 DDR3A_PIR = 0x00000033;
836
837//6.b. Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010).
838 do {
839 read_val = DDR3A_PGSR0;
840 } while ((read_val&0x00000001) != 0x00000001);
841
842//---------------------------------------------------------------------------------------------------------
843
844
845
846// 7. Trigger DDR3 initialization and leveling/training in DDR PHY through the VBUSP interface.
847// a. If using a 16-bit wide DDR interface, program DXEN=0 in the DATX8 2-7 General Configuration Registers (address offsets 0x240, 0x280, 0x2C0, 0x300, 0x340, and 0x380) to disable the leveling/training for the upper byte lanes.
848// b. If using a 32-bit wide DDR interface, program DXEN=0 in the DATX8 4-7 General Configuration Registers (address offsets 0x2C0, 0x300, 0x340, and 0x380) to disable the leveling/training for the upper byte lanes.
849// c. If ECC is not required, program DXEN=0 in the DATX8 8 General Configuration Register (address offset 0x3C0) to disable the leveling/training for the ECC byte lane.
850// NOTE: Setup supports 64-bit by default, ECC enable by default.
851
852//7.d. Program 0x0000XF81 to the PHY Initialization Register (address offset 0x004) to trigger DDR3 initialization and leveling/training sequences
853
854 DDR3A_PIR = 0x00000F81; //WLADJ - ON
855 //DDR3A_PIR = 0x00000781; //WLADJ - OFF
856
857//---------------------------------------------------------------------------------------------------------
858
859//7.e. Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010).
860 do {
861 read_val = DDR3A_PGSR0;
862 } while ((read_val&0x00000001) != 0x00000001);
863
864
865 /* End PHY Configuration */
866//---------------------------------------------------------------------------------------------------------
867/* START EMIF INITIALIZATION
868 ++++++++++++++++++SDCFG Register Calculation+++++++++++++++++++
869 | 31 - 29 | 28 |27 - 25 | 24 | 23 - 22| 21 - 17 |
870 |SDRAM_TYPE|Rsvd|DDR_TERM| DDQS | DYN_ODT| Rsvd |
871 | 0x011 | 0 | 0x011 | 0x1 | 0x00 | 0x0 |
872 586
873 | 16-14 |13 - 12 | 11 - 8 | 7 |6 - 5 | 4 | 3 | 2 | 1 - 0 | 587static ddr3_emif_config ddr3_1333_32 = {
874 | CWL | NM | CL | Rsvd |IBANK | Rsvd|EBANK| Rsvd|PAGE_SIZE| 588 0x62009C62,
875 | 0x11 | 0x00 | 0x1110 | 0x0 | 0x11 | 0x0 | 0 | 0 | 0x10 | 589 0x125C8044,
876 SDCFG = 0x0110 0011 0010 0010 0011 0011 1011 0010 590 0x00001D29,
877 SDCFG = 0x6700486A;//0x63223332 591 0x32CDFF43,
878 592 0x543F0ADF,
879 SDRAM_TYPE = 3 593 0x70073200,
880 DDR_TERM = 3 (RZQ/4 = 1; RZQ/6=3) 594 0x00001457,
881 DDQS = 1 595};
882 DYN_ODT = 0 596
883 597static ddr3_phy_config ddr3phy_1333_32 = {
884 CWL = 3 (CWL5=0; CWL6=1; CWL7=2; CWL8=3) 598 0x0005C000,
885 NM = 0 (64-bit=0, 32-bit=1, 16-bit=2) 599 (IODDRM_MASK | ZCKSEL_MASK | ZCKSEL_MASK),
886 CL = 14 (CL5=2; CL6=4; CL7=6; CL8=8; CL9=10; CL10=12; CL11=14) 600 ((1 << 2) | (1 << 7) | (1 << 23)),
887 IBANK = 3 (8bank) 601 0x42C21590,
888 EBANK = 0 (0 - pad_cs_o_n[0] , 1 - pad_cs_o_n[1:0]) 602 0xD05612C0,
889 PAGE_SIZE = 2 (1024page-size=2; 2048page-size=3) 603 0, /* not set in gel */
890*/ 604 0x0B4515C2,
891/* Start DDR3A EMIF Configuration */ 605 0x0A6E08B4,
892//8. Configure the EMIF through the VBUSM interface. 606 (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | NOSRA_MASK | UDIMM_MASK),
893//8.a. Program all EMIF MMR’s. 607 ((1 << 10) | (1 << 27) | (1 << 29)),
894 DDR3A_SDCFG = 0x62001462 ; //0x6200046A 608 0x8558AA55,
895 609 0x12857280,
896 DDR3A_SDTIM1 = 0x0A384C23; 610 0x5002C200,
897 DDR3A_SDTIM2 = 0x00001CA5; 611 0x00001A60,
898 DDR3A_SDTIM3 = 0x21ADFF32; 612 0x00000006,
899 DDR3A_SDTIM4 = 0x533F067F; 613 0x00000010,
900 614 0x710035C7,
901 DDR3A_ZQCFG = 0xF0073200; 615 0x00F065B8,
902//8.b. Program reg_initref_dis=0 in the SDRAM Refresh Control Register (address offset 0x10). 616 0x0000005D,
903 DDR3A_SDRFC = 0x00000C34; 617 0x0000005B,
904 618 0x0000005B,
905 /* End DDR3A EMIF Configuration */ 619 0x00000033,
620 0x0000FF81,
621};
622
623static ddr3_emif_config ddr3_1600_64 = {
624 0x6200CE62,
625 0x16709C55,
626 0x00001D4A,
627 0x435DFF54,
628 0x553F0CFF,
629 0xF0073200,
630 0x00001869,
631};
632
633static ddr3_phy_config ddr3phy_1600_64 = {
634 0x1C000,
635 (IODDRM_MASK | ZCKSEL_MASK | ZCKSEL_MASK),
636 ((1 << 2) | (1 << 7) | (1 << 23)),
637 0x42C21590,
638 0xD05612C0,
639 0, /* not set in gel */
640 0x0D861A80,
641 0x0C827100,
642 (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | NOSRA_MASK),
643 ((1 << 10) | (1 << 27)),
644 0xA19DBB66,
645 0x12868300,
646 0x50035200,
647 0x00001C70,
648 0x00000006,
649 0x00000018,
650 0x710035C7,
651 0x00F07A12,
652 0x0000005D,
653 0x0000005B,
654 0x0000005B,
655 0x00000033,
656 0x0000FF81,
657};
658
659void init_ddrphy(uint32_t base, ddr3_phy_config *phy_cfg)
660{
661 uint32_t tmp;
662
663 while((read_reg(base + TCI6638_DDRPHY_PGSR0_OFFSET)
664 & 0x00000001) != 0x00000001);
665
666 write_reg(phy_cfg->pllcr, base + TCI6638_DDRPHY_PLLCR_OFFSET);
667 platform_delay (DDR_CFG_DELAY);
668
669 tmp = read_reg(base + TCI6638_DDRPHY_PGCR1_OFFSET);
670 tmp &= ~(phy_cfg->pgcr1_mask);
671 tmp |= phy_cfg->pgcr1_val;
672 write_reg(tmp, TCI6638_DDRPHY_PGCR1_OFFSET);
673 platform_delay (DDR_CFG_DELAY);
674
675 write_reg(phy_cfg->ptr0, base + TCI6638_DDRPHY_PTR0_OFFSET);
676 write_reg(phy_cfg->ptr1, base + TCI6638_DDRPHY_PTR1_OFFSET);
677 write_reg(phy_cfg->ptr3, base + TCI6638_DDRPHY_PTR3_OFFSET);
678 write_reg(phy_cfg->ptr4, base + TCI6638_DDRPHY_PTR4_OFFSET);
679
680 tmp = read_reg(base + TCI6638_DDRPHY_DCR_OFFSET);
681 tmp &= ~(phy_cfg->dcr_mask);
682 tmp |= phy_cfg->dcr_val;
683 write_reg(tmp, base + TCI6638_DDRPHY_DCR_OFFSET);
684 platform_delay (DDR_CFG_DELAY);
685
686 write_reg(phy_cfg->dtpr0, base + TCI6638_DDRPHY_DTPR0_OFFSET);
687 write_reg(phy_cfg->dtpr1, base + TCI6638_DDRPHY_DTPR1_OFFSET);
688 write_reg(phy_cfg->dtpr2, base + TCI6638_DDRPHY_DTPR2_OFFSET);
689
690 write_reg(phy_cfg->mr0, base + TCI6638_DDRPHY_MR0_OFFSET);
691 write_reg(phy_cfg->mr1, base + TCI6638_DDRPHY_MR1_OFFSET);
692 write_reg(phy_cfg->mr2, base + TCI6638_DDRPHY_MR2_OFFSET);
693
694 write_reg(phy_cfg->dtcr, base + TCI6638_DDRPHY_DTCR_OFFSET);
695 platform_delay (DDR_CFG_DELAY);
696 write_reg(phy_cfg->pgcr2, base + TCI6638_DDRPHY_PGCR2_OFFSET);
697 platform_delay (DDR_CFG_DELAY);
698
699 write_reg(phy_cfg->zq0cr1, base + TCI6638_DDRPHY_ZQ0CR1_OFFSET);
700 write_reg(phy_cfg->zq1cr1, base + TCI6638_DDRPHY_ZQ1CR1_OFFSET);
701 write_reg(phy_cfg->zq2cr1, base + TCI6638_DDRPHY_ZQ2CR1_OFFSET);
702
703 write_reg(phy_cfg->pir_v1, base + TCI6638_DDRPHY_PIR_OFFSET);
704 platform_delay (DDR_CFG_DELAY);
705 while((read_reg(base + TCI6638_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1);
706
707 write_reg(phy_cfg->pir_v2, base + TCI6638_DDRPHY_PIR_OFFSET);
708 platform_delay (DDR_CFG_DELAY);
709 while((read_reg(base + TCI6638_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1);
906} 710}
907 711
908void ddr3B_64bit_DDR800_setup() 712void init_ddremif(uint32_t base, ddr3_emif_config *emif_cfg)
909{ 713{
910unsigned int multiplier = 15; 714 write_reg(emif_cfg->sdcfg, base + TCI6638_DDR3_SDCFG_OFFSET );
911 unsigned int divider = 0; 715 write_reg(emif_cfg->sdtim1, base + TCI6638_DDR3_SDTIM1_OFFSET);
912 int temp; 716 write_reg(emif_cfg->sdtim2, base + TCI6638_DDR3_SDTIM2_OFFSET);
913 unsigned int OD_val = 8; 717 write_reg(emif_cfg->sdtim3, base + TCI6638_DDR3_SDTIM3_OFFSET);
914 unsigned int read_val; 718 write_reg(emif_cfg->sdtim4, base + TCI6638_DDR3_SDTIM4_OFFSET);
915 719 write_reg(emif_cfg->zqcfg, base + TCI6638_DDR3_ZQCFG_OFFSET );
916 CSL_BootCfgUnlockKicker(); 720 write_reg(emif_cfg->sdrfc, base + TCI6638_DDR3_SDRFC_OFFSET );
917
918
919//1. Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010).
920 do {
921 read_val = DDR3B_PGSR0;
922 } while ((read_val&0x00000001) != 0x00000001);
923
924//4. Clocks are enabled and frequency is stable---------------------------------------
925//DDR3B PLL setup
926 //DDR3BPLLCTL0 = DDR3BPLLCTL0 & 0xFF7FFFFF;
927 // Set ENSAT = 1
928 DDR3BPLLCTL1 |= 0x00000040;
929 // Put the PLL in PLL Mode
930 DDR3BPLLCTL0 |= 0x00800000;
931 // In PLL Controller, reset the PLL (bit 13 in DDR3BPLLCTL1 register)
932 DDR3BPLLCTL1 |= 0x00002000;
933 // Program the necessary multipliers/dividers and BW adjustments
934 // Set the divider values
935 DDR3BPLLCTL0 &= ~(0x0000003F);
936 DDR3BPLLCTL0 |= (divider & 0x0000003F);
937 /* Step 7: Programming OD[3:0] in the SECCTL register */
938 DDR3BPLLCTL0 &= OUTPUT_DIVIDE_MASK; // clear the OD bit field
939 DDR3BPLLCTL0 |= ~OUTPUT_DIVIDE_MASK & (OD_val - 1) << OUTPUT_DIVIDE_OFFSET; // set the OD[3:0] bit field of PLLD to OD_val
940
941 /* Set the Multipler values */
942 DDR3BPLLCTL0 &= ~(0x0007FFC0);
943 DDR3BPLLCTL0 |= ((multiplier << 6) & 0x0007FFC0 );
944 temp = ((multiplier + 1) >> 1) - 1;
945 DDR3BPLLCTL0 &= ~(0xFF000000);
946 DDR3BPLLCTL0 |= ((temp << 24) & 0xFF000000);
947 DDR3BPLLCTL1 &= ~(0x0000000F);
948 DDR3BPLLCTL1 |= ((temp >> 8) & 0x0000000F);
949 //In DDR3PLLCTL1, write PLLRST = 0 to bring PLL out of reset
950 DDR3BPLLCTL1 &= ~(0x00002000);
951 // Put the PLL in PLL Mode
952 DDR3BPLLCTL0 &= ~(0x00800000); // ReSet the Bit 23
953//DDR3B PLL setup complete ---------------------------------------
954
955/*------------------------- Start PHY Configuration -------------------------------*/
956
957 //DDR3B_PGCR1 = 0x0280C487;
958
959 //5.a Program FRQSEL in the PLL Control Register (address offset 0x018).
960 DDR3B_PLLCR = 0xDC000; //Set FRQSEL=11, for ctl_clk between 166-275MHz
961
962 //5.b. Program WLSTEP=1, IODDRM=1, and ZCKSEL in the PHY General Configuration Register 1 (address offset 0x00C).
963 DDR3B_PGCR1 |= (1 << 2); //WLSTEP = 1
964
965 DDR3B_PGCR1 &= ~(IODDRM_MASK);
966 DDR3B_PGCR1 |= (( 1 << 7) & IODDRM_MASK);
967
968
969 DDR3B_PGCR1 &= ~(ZCKSEL_MASK);
970 DDR3B_PGCR1 |= (( 1 << 23) & ZCKSEL_MASK);
971
972 //RRMODE
973 //DDR3B_DSGCR &= ~(RRMODE_MASK); //RR_MODE = 0
974
975//DDR3B_DSGCR &= ~(RRMODE_MASK); //RR_MODE = 1
976 //DDR3B_DSGCR |= (( 1 << 18) & RRMODE_MASK);
977
978
979 //5.c. Program PHY Timing Parameters Register 0-4 (address offset 0x01C - 0x02C).
980
981 DDR3B_PTR0 = 0x42C21590;
982
983 DDR3B_PTR1 = 0xD05612C0;
984
985// Maintaining default values of Phy Timing Parameters Register 2 in PUB
986
987 DDR3B_PTR3 = 0x06C30D40;//0x18061A80;
988
989 DDR3B_PTR4 = 0x6413880;//0x0AAE7100;
990
991//5.d. Program PDQ, MPRDQ, and BYTEMASK in the DRAM Configuration Register (address offset 0x044).
992// All other fields must be left at their default values.
993
994 DDR3B_DCR &= ~(PDQ_MASK); //PDQ = 0
995 DDR3B_DCR &= ~(MPRDQ_MASK); //MPRDQ = 0
996
997 DDR3B_DCR &= ~(BYTEMASK_MASK);
998 DDR3B_DCR |= (( 1 << 10) & BYTEMASK_MASK);
999
1000
1001DDR3B_DCR &= ~(NOSRA_MASK);
1002DDR3B_DCR |= (( 1 << 27) & NOSRA_MASK);
1003
1004
1005 //DDR3B_DCR &= ~(UDIMM_MASK);
1006 //DDR3B_DCR |= (( 1 << 29) & UDIMM_MASK);
1007
1008
1009//5.e. Program DRAM Timing Parameters Register 0-2 (address offset 0x048 - 0x050).
1010
1011 DDR3B_DTPR0 = 0x50CE6644;
1012 DDR3B_DTPR1 = 0x12834180;
1013 DDR3B_DTPR2 = 0x50022A00;
1014
1015//5.f. Program BL=0, CL, WR, and PD=1 in the Mode Register 0 (address offset 0x054).
1016 //All other fields must be left at their default values.
1017
1018DDR3B_MR0 = 0x00001420;
1019
1020
1021//5.g. Program DIC, RTT, and TDQS in the Mode Register 1 (address offset 0x058).
1022 //All other fields must be left at their default values.
1023
1024DDR3B_MR1 = 0x00000006;
1025
1026
1027//---------------------------------------------------------------------------------------------------------
1028
1029//5.h. Program Mode Register 2 (address offset 0x05C).
1030 // Maintaining default values of Program Mode Register 2
1031 // DDR3B_MR2 = 0x00000018;
1032
1033//5.i. Program DTMPR=1, DTEXD, DTEXG, RANKEN=1 or 3, and RFSHDT=7 in the Data Training Configuration Register (address offset 0x068).
1034 //All other fields must be left at their default values.
1035 DDR3B_DTCR = 0x710035C7; //0x710035C7;
1036
1037//5.j. Program tREFPRD=(5*tREFI/ddr_clk_period) in the PHY General Configuration Register 2 (address offset 0x08C).
1038 //All other fields must be left at their default values.
1039
1040 DDR3B_PGCR2 = 0x00F03D09; //NOBUB = 0, FXDLAT = 0
1041//DDR3B_PGCR2 = 0x00F83D09; //NOBUB = 0, FXDLAT = 1
1042
1043//Set Impedence Register
1044DDR3B_ZQ0CR1 = 0x0000005D;
1045DDR3B_ZQ1CR1 = 0x0000005B;
1046DDR3B_ZQ2CR1 = 0x0000005B;
1047
1048
1049//6. Re-trigger PHY initialization in DDR PHY through the VBUSP interface.
1050//6.a. Program 0x00000033 to the PHY Initialization Register (address offset 0x004) to re-trigger PLL, ZCAL, and DCAL initialization.
1051
1052 DDR3B_PIR = 0x00000033;
1053
1054//6.b. Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010).
1055 do {
1056 read_val = DDR3B_PGSR0;
1057 } while ((read_val&0x00000001) != 0x00000001);
1058
1059//---------------------------------------------------------------------------------------------------------
1060
1061
1062
1063// 7. Trigger DDR3 initialization and leveling/training in DDR PHY through the VBUSP interface.
1064// a. If using a 16-bit wide DDR interface, program DXEN=0 in the DATX8 2-7 General Configuration Registers (address offsets 0x240, 0x280, 0x2C0, 0x300, 0x340, and 0x380) to disable the leveling/training for the upper byte lanes.
1065// b. If using a 32-bit wide DDR interface, program DXEN=0 in the DATX8 4-7 General Configuration Registers (address offsets 0x2C0, 0x300, 0x340, and 0x380) to disable the leveling/training for the upper byte lanes.
1066// c. If ECC is not required, program DXEN=0 in the DATX8 8 General Configuration Register (address offset 0x3C0) to disable the leveling/training for the ECC byte lane.
1067// NOTE: Setup supports 64-bit by default, ECC enable by default.
1068
1069//7.d. Program 0x0000XF81 to the PHY Initialization Register (address offset 0x004) to trigger DDR3 initialization and leveling/training sequences
1070
1071 DDR3B_PIR = 0x00000F81; //WLADJ - ON
1072 //DDR3B_PIR = 0x00000781; //WLADJ - OFF
1073
1074//---------------------------------------------------------------------------------------------------------
1075
1076//7.e. Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010).
1077 do {
1078 read_val = DDR3B_PGSR0;
1079 } while ((read_val&0x00000001) != 0x00000001);
1080
1081
1082 /* End PHY Configuration */
1083//---------------------------------------------------------------------------------------------------------
1084/* START EMIF INITIALIZATION
1085 ++++++++++++++++++SDCFG Register Calculation+++++++++++++++++++
1086 | 31 - 29 | 28 |27 - 25 | 24 | 23 - 22| 21 - 17 |
1087 |SDRAM_TYPE|Rsvd|DDR_TERM| DDQS | DYN_ODT| Rsvd |
1088 | 0x011 | 0 | 0x011 | 0x1 | 0x00 | 0x0 |
1089
1090 | 16-14 |13 - 12 | 11 - 8 | 7 |6 - 5 | 4 | 3 | 2 | 1 - 0 |
1091 | CWL | NM | CL | Rsvd |IBANK | Rsvd|EBANK| Rsvd|PAGE_SIZE|
1092 | 0x11 | 0x00 | 0x1110 | 0x0 | 0x11 | 0x0 | 0 | 0 | 0x10 |
1093 SDCFG = 0x0110 0011 0010 0010 0011 0011 1011 0010
1094 SDCFG = 0x6700486A;//0x63223332
1095
1096 SDRAM_TYPE = 3
1097 DDR_TERM = 3 (RZQ/4 = 1; RZQ/6=3)
1098 DDQS = 1
1099 DYN_ODT = 0
1100
1101 CWL = 3 (CWL5=0; CWL6=1; CWL7=2; CWL8=3)
1102 NM = 0 (64-bit=0, 32-bit=1, 16-bit=2)
1103 CL = 14 (CL5=2; CL6=4; CL7=6; CL8=8; CL9=10; CL10=12; CL11=14)
1104 IBANK = 3 (8bank)
1105 EBANK = 0 (0 - pad_cs_o_n[0] , 1 - pad_cs_o_n[1:0])
1106 PAGE_SIZE = 2 (1024page-size=2; 2048page-size=3)
1107*/
1108/* Start DDR3B EMIF Configuration */
1109//8. Configure the EMIF through the VBUSM interface.
1110//8.a. Program all EMIF MMR’s.
1111 DDR3B_SDCFG = 0x62000462 ;
1112
1113 DDR3B_SDTIM1 = 0x0A384C23;
1114 DDR3B_SDTIM2 = 0x00001CA5;
1115 DDR3B_SDTIM3 = 0x21ADFF32;
1116 DDR3B_SDTIM4 = 0x533F067F;
1117
1118 DDR3B_ZQCFG = 0xF0073200;
1119//8.b. Program reg_initref_dis=0 in the SDRAM Refresh Control Register (address offset 0x10).
1120 DDR3B_SDRFC = 0x00000C34;
1121
1122 /* End DDR3B EMIF Configuration */
1123
1124} 721}
1125 722
1126 723
1127/* Set the desired DDR3 configuration -- assumes 66.67 MHz DDR3 clock input */ 724/* Set the desired DDR3 configuration -- assumes 66.67 MHz DDR3 clock input */
1128CSL_Status DDR3Init() 725CSL_Status DDR3Init()
1129{ 726{
1130 CSL_Status status = CSL_SOK; 727 CSL_Status status = CSL_SOK;
1131 728
1132 ddr3A_32bit_DDR800_setup(); 729 CSL_BootCfgUnlockKicker();
1133 ddr3B_64bit_DDR800_setup(); 730 init_ddrphy(TCI6638_DDR3A_DDRPHYC, &ddr3phy_1333_32);
731 init_ddremif(TCI6638_DDR3A_EMIF_CTRL_BASE, &ddr3_1333_32);
1134 732
1135#if 0 733 init_ddrphy(TCI6638_DDR3B_DDRPHYC, &ddr3phy_1600_64);
1136 volatile unsigned int loopCount; 734 init_ddremif(TCI6638_DDR3B_EMIF_CTRL_BASE, &ddr3_1600_64);
1137 uint32_t ddr3config, ddrPhyCtrl;
1138 uint8_t ddrPHYReadLatency;
1139 EMIF4F_TIMING1_CONFIG sdram_tim1;
1140 EMIF4F_OUTPUT_IMP_CONFIG zqcfg;
1141 EMIF4F_PWR_MGMT_CONFIG pwrmgmtcfg;
1142 EMIF4F_SDRAM_CONFIG sdramcfg;
1143
1144 CSL_BootCfgUnlockKicker();
1145
1146 /* Wait for PLL to lock = min 500 ref clock cycles.
1147 With refclk = 100MHz, = 5000 ns = 5us */
1148 platform_delaycycles(50000);
1149
1150 /**************** 3.3 Leveling Register Configuration ********************/
1151 CSL_BootCfgGetDDRConfig(0, &ddr3config);
1152 ddr3config &= ~(0x007FE000); // clear ctrl_slave_ratio field
1153 CSL_BootCfgSetDDRConfig(0, ddr3config);
1154
1155 CSL_BootCfgGetDDRConfig(0, &ddr3config);
1156 ddr3config |= 0x00200000; // set ctrl_slave_ratio to 0x100
1157 CSL_BootCfgSetDDRConfig(0, ddr3config);
1158
1159 CSL_BootCfgGetDDRConfig(12, &ddr3config);
1160 ddr3config |= 0x08000000; // Set invert_clkout = 1
1161 CSL_BootCfgSetDDRConfig(12, ddr3config);
1162
1163 CSL_BootCfgGetDDRConfig(0, &ddr3config);
1164 ddr3config |= 0xF; // set dll_lock_diff to 15
1165 CSL_BootCfgSetDDRConfig(0, ddr3config);
1166
1167 CSL_BootCfgGetDDRConfig(23, &ddr3config);
1168 ddr3config |= 0x00000200; // See section 4.2.1, set for partial automatic levelling
1169 CSL_BootCfgSetDDRConfig(23, ddr3config);
1170
1171 /**************** 3.3 Partial Automatic Leveling ********************/
1172 ddr3config = 0x0000005E ; CSL_BootCfgSetDDRConfig(2, ddr3config);
1173 ddr3config = 0x0000005E; CSL_BootCfgSetDDRConfig(3, ddr3config);
1174 ddr3config = 0x0000005E; CSL_BootCfgSetDDRConfig(4, ddr3config);
1175 ddr3config = 0x00000051; CSL_BootCfgSetDDRConfig(5, ddr3config);
1176 ddr3config = 0x00000038; CSL_BootCfgSetDDRConfig(6, ddr3config);
1177 ddr3config = 0x0000003A; CSL_BootCfgSetDDRConfig(7, ddr3config);
1178 ddr3config = 0x00000024; CSL_BootCfgSetDDRConfig(8, ddr3config);
1179 ddr3config = 0x00000020; CSL_BootCfgSetDDRConfig(9, ddr3config);
1180 ddr3config = 0x00000044; CSL_BootCfgSetDDRConfig(10, ddr3config);
1181
1182 ddr3config = 0x000000DD; CSL_BootCfgSetDDRConfig(14, ddr3config);
1183 ddr3config = 0x000000DD; CSL_BootCfgSetDDRConfig(15, ddr3config);
1184 ddr3config = 0x000000BE; CSL_BootCfgSetDDRConfig(16, ddr3config);
1185 ddr3config = 0x000000CA; CSL_BootCfgSetDDRConfig(17, ddr3config);
1186 ddr3config = 0x000000A9; CSL_BootCfgSetDDRConfig(18, ddr3config);
1187 ddr3config = 0x000000A7; CSL_BootCfgSetDDRConfig(19, ddr3config);
1188 ddr3config = 0x0000009E; CSL_BootCfgSetDDRConfig(20, ddr3config);
1189 ddr3config = 0x000000A1; CSL_BootCfgSetDDRConfig(21, ddr3config);
1190 ddr3config = 0x000000BA; CSL_BootCfgSetDDRConfig(22, ddr3config);
1191
1192 /*Do a PHY reset. Toggle DDR_PHY_CTRL_1 bit 15 0->1->0 */
1193 CSL_EMIF4F_GetPhyControl(&ddrPhyCtrl, &ddrPHYReadLatency);
1194 ddrPhyCtrl &= ~(0x00008000);
1195 CSL_EMIF4F_SetPhyControl(ddrPhyCtrl, ddrPHYReadLatency);
1196
1197 CSL_EMIF4F_GetPhyControl(&ddrPhyCtrl, &ddrPHYReadLatency);
1198 ddrPhyCtrl |= (0x00008000);
1199 CSL_EMIF4F_SetPhyControl(ddrPhyCtrl, ddrPHYReadLatency);
1200
1201 CSL_EMIF4F_GetPhyControl(&ddrPhyCtrl, &ddrPHYReadLatency);
1202 ddrPhyCtrl &= ~(0x00008000);
1203 CSL_EMIF4F_SetPhyControl(ddrPhyCtrl, ddrPHYReadLatency);
1204
1205 /***************** 3.4 Basic Controller and DRAM configuration ************/
1206 /* enable configuration */
1207 /* hEmif->SDRAM_REF_CTRL = 0x00005162; */
1208 CSL_EMIF4F_EnableInitRefresh();
1209 CSL_EMIF4F_SetRefreshRate(0x5162);
1210
1211 /* hEmif->SDRAM_TIM_1 = 0x1113783C; */
1212
1213 sdram_tim1.t_wtr = 4;
1214 sdram_tim1.t_rrd = 7;
1215 sdram_tim1.t_rc = 0x20;
1216 sdram_tim1.t_ras = 0x17;
1217 sdram_tim1.t_wr = 9;
1218 CSL_EMIF4F_SetTiming1Config(&sdram_tim1);
1219
1220
1221 /* hEmif->DDR_PHY_CTRL_1 = 0x0010010F; */
1222 ddrPHYReadLatency = 0x0F;
1223 ddrPhyCtrl = (0x08008);
1224 CSL_EMIF4F_SetPhyControl(ddrPhyCtrl, ddrPHYReadLatency);
1225
1226 /* hEmif->ZQ_CONFIG = 0x70073214; */
1227 zqcfg.zqRefInterval = 0x3214;
1228 zqcfg.zqZQCLMult = 3;
1229 zqcfg.zqSFEXITEn = 1;
1230 zqcfg.zqDualCSEn = 1;
1231 zqcfg.zqCS0En = 1;
1232 zqcfg.zqCS1En = 0;
1233 CSL_EMIF4F_SetOutputImpedanceConfig(&zqcfg);
1234
1235 /* hEmif->PWR_MGMT_CTRL = 0x0; */
1236 pwrmgmtcfg.csTime = 0;
1237 pwrmgmtcfg.srTime = 0;
1238 pwrmgmtcfg.lpMode = 0;
1239 pwrmgmtcfg.dpdEnable = 0;
1240 pwrmgmtcfg.pdTime = 0;
1241 CSL_EMIF4F_SetPowerMgmtConfig (&pwrmgmtcfg);
1242
1243 /* New value with DYN_ODT disabled and SDRAM_DRIVE = RZQ/7 */
1244 /* hEmif->SDRAM_CONFIG = 0x63062A32; */
1245 CSL_EMIF4F_GetSDRAMConfig (&sdramcfg);
1246 sdramcfg.pageSize = 2;
1247 sdramcfg.eBank = 0;
1248 sdramcfg.iBank = 3;
1249 sdramcfg.CASLatency = 10;
1250 sdramcfg.narrowMode = 0;
1251 sdramcfg.CASWriteLat = 2;
1252 sdramcfg.dynODT = 0;
1253 sdramcfg.ddrDDQS = 0;
1254 sdramcfg.ddrTerm = 3;
1255 sdramcfg.type = 3;
1256 CSL_EMIF4F_SetSDRAMConfig (&sdramcfg);
1257
1258 pll_delay(840336); /*Wait 600us for HW init to complete*/
1259
1260 /* Refresh rate = (7.8*666MHz] */
1261 /* hEmif->SDRAM_REF_CTRL = 0x00001450; */
1262 CSL_EMIF4F_SetRefreshRate(0x00001450);
1263
1264 /***************** 4.2.1 Partial automatic leveling ************/
1265 /* hEmif->RDWR_LVL_RMP_CTRL = 0x80000000; */
1266 CSL_EMIF4F_SetLevelingRampControlInfo(1, 0, 0, 0, 0);
1267
1268 /* Trigger full leveling - This ignores read DQS leveling result and uses ratio forced value */
1269 /* hEmif->RDWR_LVL_CTRL = 0x80000000; */
1270 CSL_EMIF4F_SetLevelingControlInfo(1, 0, 0, 0, 0);
1271
1272 /************************************************************
1273 Wait for min 1048576 DDR clock cycles for leveling to complete
1274 = 1048576 * 1.5ns = 1572864ns = 1.57ms.
1275 Actual time = ~10-15 ms
1276 **************************************************************/
1277 pll_delay(4201680); //Wait 3ms for leveling to complete
1278#endif
1279 return (status);
1280 735
736 return (status);
1281} 737}
1282 738
diff --git a/evmk2h/platform_lib/src/platform.c b/evmk2h/platform_lib/src/platform.c
index 740a4fc..e80f9f5 100755
--- a/evmk2h/platform_lib/src/platform.c
+++ b/evmk2h/platform_lib/src/platform.c
@@ -345,6 +345,11 @@ Platform_STATUS platform_init(platform_init_flags * p_flags,
345 PllcHwSetup pllc_hwSetup; 345 PllcHwSetup pllc_hwSetup;
346 PllcHwSetup pllc_hwSetupRead; 346 PllcHwSetup pllc_hwSetupRead;
347 347
348 struct pll_init_data ddr_pll_data[2] = {
349 {DDR3A_PLL, PLLM_DDR3A, PLLD_DDR3A, PLLOD_DDR3A},
350 {DDR3B_PLL, PLLM_DDR3B, PLLD_DDR3B, PLLOD_DDR3B}
351 };
352
348#ifdef PLATFORM_PLL_REINIT 353#ifdef PLATFORM_PLL_REINIT
349 int loop_count; 354 int loop_count;
350#endif 355#endif
@@ -411,12 +416,19 @@ Platform_STATUS platform_init(platform_init_flags * p_flags,
411 return ( (Platform_STATUS) Platform_EFAIL); 416 return ( (Platform_STATUS) Platform_EFAIL);
412 } 417 }
413 418
414 /* Set the DDR3 PLL */ 419 /* Set the DDR3A PLL */
415 /* status = SetDDR3PllConfig(); 420 status = SetDDR3PllConfig(&ddr_pll_data[0]);
416 if (status != CSL_SOK) { 421 if (status != CSL_SOK) {
417 platform_errno = PLATFORM_ERRNO_PLL_SETUP; 422 platform_errno = PLATFORM_ERRNO_PLL_SETUP;
418 return ( (Platform_STATUS) Platform_EFAIL); 423 return ( (Platform_STATUS) Platform_EFAIL);
419 }*/ 424 }
425
426 /* Set the DDR3B PLL */
427 status = SetDDR3PllConfig(&ddr_pll_data[1]);
428 if (status != CSL_SOK) {
429 platform_errno = PLATFORM_ERRNO_PLL_SETUP;
430 return ( (Platform_STATUS) Platform_EFAIL);
431 }
420 } 432 }
421 433
422 /* Initialize DDR */ 434 /* Initialize DDR */