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authorSam Nelson2014-07-30 15:01:00 -0500
committerSam Nelson2014-07-30 15:01:00 -0500
commit293a75ac855688af5ef1a6a3a5c833d760c2df1e (patch)
tree49c53055f8c4709591fcb6730dbdb5cfde37d444 /program_evm/gel/xtcievmk2x.gel
parent474522233cf339815794294347ba6d4c568621b4 (diff)
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program_evm: Add gel files copied from emupackDEV.MCSDK-03.01.00.03
- Unwanted power up of modules removed Signed-off-by: Sam Nelson <sam.nelson@ti.com>
Diffstat (limited to 'program_evm/gel/xtcievmk2x.gel')
-rw-r--r--program_evm/gel/xtcievmk2x.gel3454
1 files changed, 3454 insertions, 0 deletions
diff --git a/program_evm/gel/xtcievmk2x.gel b/program_evm/gel/xtcievmk2x.gel
new file mode 100644
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--- /dev/null
+++ b/program_evm/gel/xtcievmk2x.gel
@@ -0,0 +1,3454 @@
1/******************************************************************************
2* Copyright (c) 2012 Texas Instruments Incorporated - http://www.ti.com
3*
4* Redistribution and use in source and binary forms, with or without
5* modification, are permitted provided that the following conditions
6*
7* are met:
8*
9* Redistributions of source code must retain the above copyright
10* notice, this list of conditions and the following disclaimer.
11*
12*
13* Redistributions in binary form must reproduce the above copyright
14* notice, this list of conditions and the following disclaimer in the
15* documentation and/or other materials provided with the
16*
17* distribution.
18*
19*
20* Neither the name of Texas Instruments Incorporated nor the names of
21* its contributors may be used to endorse or promote products derived
22* from this software without specific prior written permission.
23*
24*
25* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36*
37*****************************************************************************
38*
39 ---------------------------------------------------------------------------*/
40
41#define GEL_VERSION 1.3
42
43// Timeout definitions
44int _GEL_Global_Timeout1 = 0;
45
46#define TIMEOUT_ID 10
47// Global timeout value
48#define GTIMEOUT 2000
49//*****************************************************
50// Power definitions
51#define PSC_BASE 0x02350000
52#define PSC_PTCMD *( unsigned int* )( PSC_BASE+0x120 )
53#define PSC_PTSTAT *( unsigned int* )( PSC_BASE+0x128 )
54#define PSC_PDCTL_BASE ( PSC_BASE+0x300 )
55#define PSC_MDSTAT_BASE ( PSC_BASE+0x800 )
56#define PSC_MDCTL_BASE ( PSC_BASE+0xA00 )
57
58// Modules on power domain 0
59// Always on
60
61// Modules on power domain 1
62#define LPSC_DEBUG (5)
63#define LPSC_TETB (6)
64
65// Modules on power domain 2
66#define LPSC_PA (7)
67#define LPSC_SGMII (8)
68#define LPSC_SA (9)
69
70// Modules on power domain 3
71#define LPSC_PCIE (10)
72
73// Modules on power domain 4
74#define LPSC_SRIO (11)
75
76// Modules on power domain 5
77#define LPSC_HYPERLINK_0 (12)
78
79// Modules on power domain 6
80#define LPSC_SR (13)
81
82// Modules on power domain 7
83#define LPSC_MSMCRAM (14)
84
85// Modules on power domain 8
86#define LPSC_GEM_0 (15)
87
88// Modules on power domain 9
89#define LPSC_GEM_1 (16)
90
91// Modules on power domain 10
92#define LPSC_GEM_2 (17)
93
94// Modules on power domain 11
95#define LPSC_GEM_3 (18)
96
97// Modules on power domain 12
98#define LPSC_GEM_4 (19)
99
100// Modules on power domain 13
101#define LPSC_GEM_5 (20)
102
103// Modules on power domain 14
104#define LPSC_GEM_6 (21)
105
106// Modules on power domain 15
107#define LPSC_GEM_7 (22)
108
109// Modules on power domain 16
110#define LPSC_DDR3_0 (23)
111#define LPSC_DDR3_1 (24)
112
113// Modules on power domain 17
114#define LPSC_TAC (25)
115#define LPSC_RAC_01 (26)
116
117// Modules on power domain 18
118#define LPSC_RAC_23 (27)
119
120// Modules on power domain 19
121#define LPSC_FFTCA_FFTC_0 (28)
122#define LPSC_FFTCA_FFTC_1 (29)
123
124// Modules on power domain 20
125#define LPSC_FFTCA_FFTC_2 (30)
126#define LPSC_FFTCA_FFTC_3 (31)
127#define LPSC_FFTCA_FFTC_4 (32)
128#define LPSC_FFTCA_FFTC_5 (33)
129
130// Modules on power domain 21
131#define LPSC_AIF (34)
132
133// Modules on power domain 22
134#define LPSC_TCP3D_0 (35)
135#define LPSC_TCP3D_1 (36)
136
137// Modules on power domain 23
138#define LPSC_TCP3D_2 (37)
139#define LPSC_TCP3D_3 (38)
140
141// Modules on power domain 24
142#define LPSC_VCP_0 (39)
143#define LPSC_VCP_1 (40)
144#define LPSC_VCP_2 (41)
145#define LPSC_VCP_3 (42)
146
147// Modules on power domain 25
148#define LPSC_VCP_4 (43)
149#define LPSC_VCP_5 (44)
150#define LPSC_VCP_6 (45)
151#define LPSC_VCP_7 (46)
152
153// Modules on power domain 26
154#define LPSC_BCP (47)
155
156// Modules on power domain 27
157#define LPSC_DXB (48)
158
159// Modules on power domain 28
160#define LPSC_HYPERLINK_1 (49)
161
162// Modules on power domain 29
163#define LPSC_XGE (50)
164
165// Modules on power domain 31
166#define LPSC_ARM (52)
167
168
169// Power domains definitions
170#define PD0 (0) // Power Domain-0
171#define PD1 (1) // Power Domain-1
172#define PD2 (2) // Power Domain-2
173#define PD3 (3) // Power Domain-3
174#define PD4 (4) // Power Domain-4
175#define PD5 (5) // Power Domain-5
176#define PD6 (6) // Power Domain-6
177#define PD7 (7) // Power Domain-7
178#define PD8 (8) // Power Domain-8
179#define PD9 (9) // Power Domain-9
180#define PD10 (10) // Power Domain-10
181#define PD11 (11) // Power Domain-11
182#define PD12 (12) // Power Domain-12
183#define PD13 (13) // Power Domain-13
184#define PD14 (14) // Power Domain-14
185#define PD15 (15) // Power Domain-15
186#define PD16 (16) // Power Domain-16
187#define PD17 (17) // Power Domain-17
188#define PD18 (18) // Power Domain-18
189#define PD19 (19) // Power Domain-19
190#define PD20 (20) // Power Domain-20
191#define PD21 (21) // Power Domain-21
192#define PD22 (22) // Power Domain-22
193#define PD23 (23) // Power Domain-23
194#define PD24 (24) // Power Domain-24
195#define PD25 (25) // Power Domain-25
196#define PD26 (26) // Power Domain-26
197#define PD27 (27) // Power Domain-27
198#define PD28 (28) // Power Domain-28
199#define PD29 (29) // Power Domain-29
200#define PD30 (30) // Power Domain-30
201#define PD31 (31) // Power Domain-31
202
203#define PSC_SYNCRESET (0x1)
204#define PSC_DISABLE (0x2)
205#define PSC_ENABLE (0x3)
206
207#define CHIP_LEVEL_REG 0x02620000
208
209/******************* PLL registers **********************************/
210/*Boot cfg registers*/
211#define KICK0 *(unsigned int*)(CHIP_LEVEL_REG + 0x0038)
212#define KICK1 *(unsigned int*)(CHIP_LEVEL_REG + 0x003C)
213#define KICK0_UNLOCK (0x83E70B13)
214#define KICK1_UNLOCK (0x95A4F1E0)
215#define KICK_LOCK 0
216#define TINPSEL *(unsigned int*)(CHIP_LEVEL_REG + 0x0300)
217#define TOUTPSEL *(unsigned int*)(CHIP_LEVEL_REG + 0x0304)
218#define MAINPLLCTL0 *(unsigned int*)(CHIP_LEVEL_REG + 0x0350) //0x0328)
219#define MAINPLLCTL1 *(unsigned int*)(CHIP_LEVEL_REG + 0x0354) //0x032C)
220#define MAIN_PLLD_OFFSET 0
221#define MAIN_PLLD_MASK 0xFFFFFFC0
222#define MAIN_PLLM_OFFSET 12
223#define MAIN_PLLM_MASK 0xFFF80FFF
224#define MAIN_BWADJ0_OFFSET 24
225#define MAIN_BWADJ0_MASK 0x00FFFFFF
226#define MAIN_ENSAT_OFFSET 6
227#define MAIN_ENSAT_MASK 0xFFFFFFBF
228#define MAIN_BWADJ1_OFFSET 0
229#define MAIN_BWADJ1_MASK 0xFFFFFFF0
230
231#define OBSCLKCTL *(unsigned int*)(CHIP_LEVEL_REG + 0x0C80)
232
233/* PA PLL Registers */
234#define BYPASS_BIT_SHIFT 23
235#define CLKF_BIT_SHIFT 6
236#define CLKD_BIT_SHIFT 0
237#define DEVSTAT (*((unsigned int *) 0x02620020))
238#define PAPLLCTL0 *(unsigned int*)(CHIP_LEVEL_REG + 0x0358)
239#define PAPLLCTL1 *(unsigned int*)(CHIP_LEVEL_REG + 0x035C)
240#define PASSCLKSEL_MASK (1 << 17) /* Tells the configuration of the PASSCLKSEL pin */
241#define PA_PLL_BYPASS_MASK (1 << BYPASS_BIT_SHIFT) /* Tells whether the PA PLL is in BYPASS mode or not */
242#define PA_PLL_CLKOD_MASK (0x00780000) /* Tells the output divider value for the PA PLL */
243#define PA_PLL_CLKF_MASK (0x0007FFC0) /* Tells the multiplier value for the PA PLL */
244#define PA_PLL_CLKR_MASK (0x0000003F) /* Tells the divider value for the PA PLL */
245#define PA_PLL_RESET_MASK (0x00004000)
246
247
248#define CHIP_MISC1 *(unsigned int*)(CHIP_LEVEL_REG + 0x0C7C)
249#define ARMPLL_ENABLE_OFFSET 13
250
251
252#define DDR3APLLCTL0 *(unsigned int*)(CHIP_LEVEL_REG + 0x0360)
253#define DDR3APLLCTL1 *(unsigned int*)(CHIP_LEVEL_REG + 0x0364)
254#define DDR3BPLLCTL0 *(unsigned int*)(CHIP_LEVEL_REG + 0x0368)
255#define DDR3BPLLCTL1 *(unsigned int*)(CHIP_LEVEL_REG + 0x036C)
256
257//******************************************************
258// PLL 1 definitions (DSP and ARM clock and subsystems)
259#define PLL1_BASE 0x02310000
260#define PLL1_PLLCTL (*(unsigned int*)(PLL1_BASE + 0x100)) // PLL1 Control
261#define PLL1_SECCTL (*(unsigned int*)(PLL1_BASE + 0x108)) // PLL1 Secondary Control
262#define PLL1_PLLM (*(unsigned int*)(PLL1_BASE + 0x110)) // PLL1 Multiplier
263#define PLL1_DIV1 (*(unsigned int*)(PLL1_BASE + 0x118)) // DIV1 divider
264#define PLL1_DIV2 (*(unsigned int*)(PLL1_BASE + 0x11C)) // DIV2 divider
265#define PLL1_DIV3 (*(unsigned int*)(PLL1_BASE + 0x120)) // DIV3 divider
266#define PLL1_CMD (*(unsigned int*)(PLL1_BASE + 0x138)) // CMD control
267#define PLL1_STAT (*(unsigned int*)(PLL1_BASE + 0x13C)) // STAT control
268#define PLL1_ALNCTL (*(unsigned int*)(PLL1_BASE + 0x140)) // ALNCTL control
269#define PLL1_DCHANGE (*(unsigned int*)(PLL1_BASE + 0x144)) // DCHANGE status
270#define PLL1_CKEN (*(unsigned int*)(PLL1_BASE + 0x148)) // CKEN control
271#define PLL1_CKSTAT (*(unsigned int*)(PLL1_BASE + 0x14C)) // CKSTAT status
272#define PLL1_SYSTAT (*(unsigned int*)(PLL1_BASE + 0x150)) // SYSTAT status
273#define PLL1_DIV4 (*(unsigned int*)(PLL1_BASE + 0x160)) // DIV4 divider
274#define PLL1_DIV5 (*(unsigned int*)(PLL1_BASE + 0x164)) // DIV5 divider
275#define PLL1_DIV6 (*(unsigned int*)(PLL1_BASE + 0x168)) // DIV6 divider
276#define PLL1_DIV7 (*(unsigned int*)(PLL1_BASE + 0x16C)) // DIV7 divider
277#define PLL1_DIV8 (*(unsigned int*)(PLL1_BASE + 0x170)) // DIV8 divider
278#define PLL1_DIV9 (*(unsigned int*)(PLL1_BASE + 0x174)) // DIV9 divider
279#define PLL1_DIV10 (*(unsigned int*)(PLL1_BASE + 0x178)) // DIV10 divider
280#define PLL1_DIV11 (*(unsigned int*)(PLL1_BASE + 0x17C)) // DIV11 divider
281#define PLL1_DIV12 (*(unsigned int*)(PLL1_BASE + 0x180)) // DIV12 divider
282#define PLL1_DIV13 (*(unsigned int*)(PLL1_BASE + 0x184)) // DIV13 divider
283#define PLL1_DIV14 (*(unsigned int*)(PLL1_BASE + 0x188)) // DIV14 divider
284#define PLL1_DIV15 (*(unsigned int*)(PLL1_BASE + 0x18C)) // DIV15 divider
285#define PLL1_DIV16 (*(unsigned int*)(PLL1_BASE + 0x190)) // DIV16 divider
286#define PLLPWRDN_OFFSET 1
287#define PLLPWRDN_MASK 0xFFFFFFFD
288#define PLLRST_OFFSET 3
289#define PLLRST_MASK 0xFFFFFFF7
290#define PLLENSRC_OFFSET 5
291#define PLLENSRC_MASK 0xFFFFFFDF
292#define PLLEN_OFFSET 0
293#define PLLEN_MASK 0xFFFFFFFE
294#define OUTPUT_DIVIDE_OFFSET 19
295#define OUTPUT_DIVIDE_MASK 0xFF87FFFF
296#define BYPASS_OFFSET 23
297#define BYPASS_MASK 0xFF7FFFFF
298#define PLLM_OFFSET 0
299#define PLLM_MASK 0xFFFFFFC0
300#define GOSET_OFFSET 0
301#define GOSET_MASK 0xFFFFFFFE
302#define GOSTAT_OFFSET 0
303#define GOSTAT_MASK 0xFFFFFFFE
304
305#define OUTPUT_DIVIDE_OFFSET 19
306#define OUTPUT_DIVIDE_MASK 0xFF87FFFF
307
308// ARMPLL definitions
309#define SEC_PLLCTL0_PLLM_OFFSET 6
310#define SEC_PLLCTL0_PLLM_MASK 0xFFFF003F
311#define SEC_PLLCTL0_BWADJ_OFFSET 24
312#define SEC_PLLCTL0_BWADJ_MASK 0x00FFFFFF
313#define SEC_PLLCTL0_OD_OFFSET 19
314#define SEC_PLLCTL0_OD_MASK 0xFF87FFFF
315#define SEC_PLLCTL0_BYPASS_OFFSET 23
316#define SEC_PLLCTL0_BYPASS_MASK 0xFF7FFFFF
317#define SEC_PLLCTL1_RESET_OFFSET 14
318#define SEC_PLLCTL1_RESET_MASK 0xFFFFBFFF
319#define SEC_PLLCTL1_PWRDWN_OFFSET 15
320#define SEC_PLLCTL1_PWRDWN_MASK 0xFFFF7FFF
321#define SEC_PLLCTL1_ENSTAT_OFFSET 6
322#define SEC_PLLCTL1_ENSTAT_MASK 0xFFFFFFBF
323
324/*----------------DDR3A Register definition---------------------*/
325
326#define DDR3A_BASE_ADDR (0x21010000)
327#define DDR3A_STATUS (*(int*)(DDR3A_BASE_ADDR + 0x00000004))
328#define DDR3A_SDCFG (*(int*)(DDR3A_BASE_ADDR + 0x00000008))
329#define DDR3A_SDRFC (*(int*)(DDR3A_BASE_ADDR + 0x00000010))
330#define DDR3A_SDTIM1 (*(int*)(DDR3A_BASE_ADDR + 0x00000018))
331#define DDR3A_SDTIM2 (*(int*)(DDR3A_BASE_ADDR + 0x0000001C))
332#define DDR3A_SDTIM3 (*(int*)(DDR3A_BASE_ADDR + 0x00000020))
333#define DDR3A_SDTIM4 (*(int*)(DDR3A_BASE_ADDR + 0x00000028))
334#define DDR3A_ZQCFG (*(int*)(DDR3A_BASE_ADDR + 0x000000C8))
335#define DDR3A_TMPALRT (*(int*)(DDR3A_BASE_ADDR + 0x000000CC))
336#define DDR3A_DDRPHYC (*(int*)(DDR3A_BASE_ADDR + 0x000000E4))
337
338#define DDR3A_PHY_CFG_BASE (0x02329000)
339#define DDR3A_PIR (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000004))
340#define DDR3A_PGCR0 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000008))
341#define DDR3A_PGCR1 (*(int*)(DDR3A_PHY_CFG_BASE + 0x0000000C))
342#define DDR3A_PGCR2 (*(int*)(DDR3A_PHY_CFG_BASE + 0x0000008C))
343#define DDR3A_PGSR0 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000010))
344#define DDR3A_PGSR1 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000014))
345#define DDR3A_PLLCR (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000018))
346#define DDR3A_PTR0 (*(int*)(DDR3A_PHY_CFG_BASE + 0x0000001C))
347#define DDR3A_PTR1 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000020))
348#define DDR3A_PTR2 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000024))
349#define DDR3A_PTR3 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000028))
350#define DDR3A_PTR4 (*(int*)(DDR3A_PHY_CFG_BASE + 0x0000002C))
351#define DDR3A_DSGCR (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000040))
352#define DDR3A_DCR (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000044))
353#define DDR3A_MR0 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000054))
354#define DDR3A_MR1 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000058))
355#define DDR3A_MR2 (*(int*)(DDR3A_PHY_CFG_BASE + 0x0000005C))
356#define DDR3A_DTCR (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000068))
357#define DDR3A_DTPR0 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000048))
358#define DDR3A_DTPR1 (*(int*)(DDR3A_PHY_CFG_BASE + 0x0000004C))
359#define DDR3A_DTPR2 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000050))
360
361#define DDR3A_ZQ0CR1 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000184))
362#define DDR3A_ZQ1CR1 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000194))
363#define DDR3A_ZQ2CR1 (*(int*)(DDR3A_PHY_CFG_BASE + 0x000001A4))
364#define DDR3A_ZQ3CR1 (*(int*)(DDR3A_PHY_CFG_BASE + 0x000001B4))
365
366#define DDR3A_DATX8_8 (*(int*)(DDR3A_PHY_CFG_BASE + 0x000003C0))
367
368
369#define DDR3_TEST_START_ADDRESS (*(int*)(0x80000000))
370
371#define IODDRM_MASK 0x00000180
372#define ZCKSEL_MASK 0x01800000
373#define CL_MASK 0x00000072
374#define WR_MASK 0x00000E00
375#define BL_MASK 0x00000003
376#define RRMODE_MASK 0x00040000
377#define UDIMM_MASK 0x20000000
378#define BYTEMASK_MASK 0x0000FC00
379#define MPRDQ_MASK 0x00000080
380#define PDQ_MASK 0x00000070
381#define NOSRA_MASK 0x08000000
382#define ECC_MASK 0x00000001
383#define RRMODE_MASK 0x00040000
384
385#define DDR3A_DX0GSR0 (*(int*)(DDR3A_PHY_CFG_BASE + 0x000001C4)) //0x71
386#define DDR3A_DX1GSR0 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000204)) //0x81
387#define DDR3A_DX2GSR0 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000244)) //0x91
388#define DDR3A_DX3GSR0 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000284)) //0xA1
389#define DDR3A_DX4GSR0 (*(int*)(DDR3A_PHY_CFG_BASE + 0x000002C4)) //0xB1
390#define DDR3A_DX5GSR0 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000304)) //0xC1
391#define DDR3A_DX6GSR0 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000344)) //0xD1
392#define DDR3A_DX7GSR0 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000384)) //0xE1
393#define DDR3A_DX8GSR0 (*(int*)(DDR3A_PHY_CFG_BASE + 0x000003C4)) //0xF1
394
395#define DDR3A_TEST_START_ADDRESS (0x80000000)
396
397#define DDR3A_TEST_END_ADDRESS (DDR3A_TEST_START_ADDRESS + (4 * 100))
398#define DDR3A_BASE_ADDRESS 0x80000000
399
400
401#define DDR3B_BASE_ADDR (0x21020000)
402#define DDR3B_STATUS (*(int*)(DDR3B_BASE_ADDR + 0x00000004))
403#define DDR3B_SDCFG (*(int*)(DDR3B_BASE_ADDR + 0x00000008))
404#define DDR3B_SDRFC (*(int*)(DDR3B_BASE_ADDR + 0x00000010))
405#define DDR3B_SDTIM1 (*(int*)(DDR3B_BASE_ADDR + 0x00000018))
406#define DDR3B_SDTIM2 (*(int*)(DDR3B_BASE_ADDR + 0x0000001C))
407#define DDR3B_SDTIM3 (*(int*)(DDR3B_BASE_ADDR + 0x00000020))
408#define DDR3B_SDTIM4 (*(int*)(DDR3B_BASE_ADDR + 0x00000028))
409#define DDR3B_ZQCFG (*(int*)(DDR3B_BASE_ADDR + 0x000000C8))
410#define DDR3B_TMPALRT (*(int*)(DDR3B_BASE_ADDR + 0x000000CC))
411#define DDR3B_DDRPHYC (*(int*)(DDR3B_BASE_ADDR + 0x000000E4))
412
413
414#define DDR3B_PHY_CFG_BASE (0x02328000)
415#define DDR3B_PIR (*(int*)(DDR3B_PHY_CFG_BASE + 0x00000004))
416#define DDR3B_PGCR0 (*(int*)(DDR3B_PHY_CFG_BASE + 0x00000008))
417#define DDR3B_PGCR1 (*(int*)(DDR3B_PHY_CFG_BASE + 0x0000000C))
418#define DDR3B_PGCR2 (*(int*)(DDR3B_PHY_CFG_BASE + 0x0000008C))
419#define DDR3B_PGSR0 (*(int*)(DDR3B_PHY_CFG_BASE + 0x00000010))
420#define DDR3B_PGSR1 (*(int*)(DDR3B_PHY_CFG_BASE + 0x00000014))
421#define DDR3B_PTR0 (*(int*)(DDR3B_PHY_CFG_BASE + 0x0000001C))
422#define DDR3B_PTR1 (*(int*)(DDR3B_PHY_CFG_BASE + 0x00000020))
423#define DDR3B_PTR2 (*(int*)(DDR3B_PHY_CFG_BASE + 0x00000024))
424#define DDR3B_PTR3 (*(int*)(DDR3B_PHY_CFG_BASE + 0x00000028))
425#define DDR3B_PTR4 (*(int*)(DDR3B_PHY_CFG_BASE + 0x0000002C))
426#define DDR3B_DSGCR (*(int*)(DDR3B_PHY_CFG_BASE + 0x00000040))
427#define DDR3B_DCR (*(int*)(DDR3B_PHY_CFG_BASE + 0x00000044))
428#define DDR3B_MR0 (*(int*)(DDR3B_PHY_CFG_BASE + 0x00000054))
429#define DDR3B_MR1 (*(int*)(DDR3B_PHY_CFG_BASE + 0x00000058))
430#define DDR3B_MR2 (*(int*)(DDR3B_PHY_CFG_BASE + 0x0000005C))
431#define DDR3B_DTCR (*(int*)(DDR3B_PHY_CFG_BASE + 0x00000068))
432#define DDR3B_DTPR0 (*(int*)(DDR3B_PHY_CFG_BASE + 0x00000048))
433#define DDR3B_DTPR1 (*(int*)(DDR3B_PHY_CFG_BASE + 0x0000004C))
434#define DDR3B_DTPR2 (*(int*)(DDR3B_PHY_CFG_BASE + 0x00000050))
435#define DDR3B_PLLCR (*(int*)(DDR3B_PHY_CFG_BASE + 0x00000018))
436
437#define DDR3B_ZQ0CR1 (*(int*)(DDR3B_PHY_CFG_BASE + 0x00000184))
438#define DDR3B_ZQ1CR1 (*(int*)(DDR3B_PHY_CFG_BASE + 0x00000194))
439#define DDR3B_ZQ2CR1 (*(int*)(DDR3B_PHY_CFG_BASE + 0x000001A4))
440#define DDR3B_ZQ3CR1 (*(int*)(DDR3B_PHY_CFG_BASE + 0x000001B4))
441
442#define DDR3B_TEST_START_ADDRESS (0x60000000)
443
444#define DDR3B_TEST_END_ADDRESS (DDR3B_TEST_START_ADDRESS + (4 * 100))
445
446#define DDR3B_BASE_ADDRESS 0x60000000
447
448
449
450#define TETRIS_BASE 0x01E80000
451
452#define TETRIS_CPU0_PTCMD *(unsigned int*)(TETRIS_BASE + 0x0400)
453#define TETRIS_CPU0_PDSTAT *(unsigned int*)(TETRIS_BASE + 0x0404)
454#define TETRIS_CPU0_PDCTL *(unsigned int*)(TETRIS_BASE + 0x0408)
455
456#define TETRIS_CPU1_PTCMD *(unsigned int*)(TETRIS_BASE + 0x040C)
457#define TETRIS_CPU1_PDSTAT *(unsigned int*)(TETRIS_BASE + 0x0410)
458#define TETRIS_CPU1_PDCTL *(unsigned int*)(TETRIS_BASE + 0x0414)
459
460#define TETRIS_CPU2_PTCMD *(unsigned int*)(TETRIS_BASE + 0x0418)
461#define TETRIS_CPU2_PDSTAT *(unsigned int*)(TETRIS_BASE + 0x041C)
462#define TETRIS_CPU2_PDCTL *(unsigned int*)(TETRIS_BASE + 0x0420)
463
464#define TETRIS_CPU3_PTCMD *(unsigned int*)(TETRIS_BASE + 0x0424)
465#define TETRIS_CPU3_PDSTAT *(unsigned int*)(TETRIS_BASE + 0x0428)
466#define TETRIS_CPU3_PDCTL *(unsigned int*)(TETRIS_BASE + 0x042C)
467
468#define SECPLLCTL0 *(unsigned int*)(CHIP_LEVEL_REG + 0x0370)
469#define SECPLLCTL1 *(unsigned int*)(CHIP_LEVEL_REG + 0x0374)
470unsigned int read_val;
471
472/****************************************************************************
473 *
474 * NAME
475 * OnTargetConnect
476 *
477 * PURPOSE:
478 * Setup almost everything ready for a new debug session:
479 * DSP modules and EVM board modules, at target connection.
480 * Do nothing if target is in realtime mode.
481 * This routine is called when you connect to the target board.
482 *
483 * IMPORTANT: this routine won't attempt to connect to the target
484 * if the target is not in real-time mode and that the dsp boot
485 * mode switches are not set in emulation boot mode.
486 *
487 * USAGE
488 * This routine is a callback routine and called by CCS only.
489 *
490 * RETURN VALUE
491 * NONE
492 *
493 * REFERENCE
494 *
495 ****************************************************************************/
496OnTargetConnect()
497{
498 /*------------------------------------------------------*/
499 /* GEL_Reset() is used to deal with the worst case */
500 /* senario of unknown target state. If for some reason */
501 /* a reset is not desired upon target connection, */
502 /* GEL_Reset() may be removed and replaced with */
503 /* something "less brutal" like a cache initialization */
504 /* function. */
505 /*------------------------------------------------------*/
506 //GEL_Reset();
507 //xmc_setup();
508 //ddr3_setup();
509
510 GEL_TextOut("\nConnecting Target...\n");
511
512 // Check if target is not in real-time mode. If it is in stop mode,
513 // initialize everything. In real-time mode, do nothing to connect
514 // unobtrusively...
515 if (!GEL_IsInRealtimeMode())
516 {
517 // Validates if emulation boot mode
518 if (DEVSTAT & 0x0000000E)
519 {
520 GEL_TextOut("No initialization performed since bootmode = %x \n",,,,,(DEVSTAT >> 1 ) & 0xF);
521 GEL_TextOut("You can manually initialize with GlobalDefaultSetup\n");
522 }
523 else
524 {
525 // Comment the following line at production application test
526 // when the application need to initialize everything, but not the
527 // GEL file.
528 Global_Default_Setup_Silent();
529 }
530 } else {
531 GEL_TextOut("No initialization performed in real time mode\n");
532 }
533}
534
535/*--------------------------------------------------------------*/
536/* OnReset() */
537/* This function is called by CCS when you do Debug->Resest. */
538/* The goal is to put the C6x into a known good state with */
539/* respect to cache, edma and interrupts. */
540/*--------------------------------------------------------------*/
541OnReset( int nErrorCode )
542{
543}
544
545/*--------------------------------------------------------------*/
546/* xmc_setup() */
547/* XMC MPAX register setting to access DDR3 config space */
548/*--------------------------------------------------------------*/
549
550#define XMC_BASE_ADDR (0x08000000)
551#define XMPAX2_L (*(int*)(XMC_BASE_ADDR + 0x00000010))
552#define XMPAX2_H (*(int*)(XMC_BASE_ADDR + 0x00000014))
553
554xmc_setup()
555{
556 /* mapping for ddr emif registers XMPAX*2 */
557
558 XMPAX2_L = 0x121010FF; /* replacement addr + perm */
559 XMPAX2_H = 0x2101000B; /* base addr + seg size (64KB)*/ //"1B"-->"B" by xj
560 GEL_TextOut("XMC setup complete.\n");
561}
562
563/****************************************************************************
564 *
565 * NAME
566 * Global_Default_Setup_Silent
567 *
568 * PURPOSE:
569 * Setup almost everything ready for a new debug session:
570 * DSP modules and EVM board modules.
571 *
572 * USAGE
573 * This routine can be called as:
574 *
575 * Global_Default_Setup_Silent()
576 *
577 * RETURN VALUE
578 * NONE
579 *
580 * REFERENCE
581 *
582 ****************************************************************************/
583Global_Default_Setup_Silent()
584{
585 float gel_ver = GEL_VERSION;
586
587 // Set DSP cache to pre defined values...
588 GEL_TextOut( "TCI6638K2K GEL file Ver is %f \n",,,,, (float) (gel_ver/1.0));
589
590 //Set_DSP_Cache();
591
592 // Only core 0 can set these
593 if (DNUM == 0)
594 {
595 // Setup main PLL DSP @ 983 MHz
596 Set_Pll1(3); // call Set_Pll1 with index = 3 -> 122.88 MHz to 983.04 MHz operation
597
598 // Setup all Power Domains on
599 Set_Psc_All_On();
600
601 // Setup PA PLL
602 PaPllConfig();
603
604 GEL_TextOut("DDR begin\n");
605 xmc_setup();
606 ddr3A_32bit_DDR1333_setup();
607 ddr3B_64bit_DDR1600_setup();
608 GEL_TextOut("DDR done\n");
609 }
610}
611
612/****************************************************************************
613 *
614 * NAME
615 * Set_PSC_State
616 *
617 * PURPOSE:
618 * Set a new power state for the specified domain id in a power controler
619 * domain. Wait for the power transition to complete.
620 *
621 * USAGE
622 * This routine can be called as:
623 *
624 * Set_PSC_State(unsigned int pd,unsigned int id,unsigned int state)
625 *
626 * pd - (i) power domain.
627 *
628 * id - (i) module id to use for module in the specified power domain
629 *
630 * state - (i) new state value to set
631 * 0 = RESET
632 * 1 = SYNC RESET
633 * 2 = DISABLE
634 * 3 = ENABLE
635 *
636 * RETURN VALUE
637 * 0 if ok, !=0 for error
638 *
639 * REFERENCE
640 *
641 ****************************************************************************/
642Set_PSC_State(unsigned int pd,unsigned int id,unsigned int state)
643{
644 unsigned int* mdctl;
645 unsigned int* mdstat;
646 unsigned int* pdctl;
647 int ret=0;
648
649 // Only core0 can set PSC
650 if (DNUM == 0)
651 {
652 mdctl = ( unsigned int* )(PSC_MDCTL_BASE + ( 4 * id ));
653 mdstat = ( unsigned int* )( PSC_MDSTAT_BASE + ( 4 * id ));
654 pdctl = ( unsigned int* )(PSC_PDCTL_BASE + ( 4 * pd ));
655
656 // If state is already set, do nothing
657 if ( ( *mdstat & 0x1f ) == state )
658 {
659 return(0);
660 }
661
662 // Wait for GOSTAT to clear
663 Set_Timeout(GTIMEOUT);
664 while( Get_Timeout() && (PSC_PTSTAT & (0x1 << pd)) != 0 );
665
666 // Check if we got timeout error while waiting
667 if (!Get_Timeout())
668 {
669 GEL_TextOut( "Set_PSC_State... Timeout Error #01 pd=%d, md=%d!\n",,2,,,pd,id);
670 ret=1;
671 }
672 else
673 {
674 // Set power domain control
675 *pdctl = (*pdctl) | 0x00000001;
676
677 // Set MDCTL NEXT to new state
678 *mdctl = ((*mdctl) & ~(0x1f)) | state;
679
680 // Start power transition by setting PTCMD GO to 1
681 PSC_PTCMD = (PSC_PTCMD) | (0x1<<pd);
682
683 // Wait for PTSTAT GOSTAT to clear
684 Set_Timeout(GTIMEOUT);
685 while( Get_Timeout() && (PSC_PTSTAT & (0x1 << pd)) != 0 );
686
687 // Check if we got timeout error while waiting
688 if (!Get_Timeout())
689 {
690 GEL_TextOut( "Set_PSC_State... Timeout Error #02 pd=%d, md=%d!\n",,2,,,pd,id);
691 ret=2;
692 }
693 else
694 {
695 // Verify state changed
696 Set_Timeout(GTIMEOUT);
697 while(Get_Timeout() && ( *mdstat & 0x1f ) != state );
698
699 // Check if we got timeout error while waiting
700 if (!Get_Timeout())
701 {
702 GEL_TextOut( "Set_PSC_State... Timeout Error #03 pd=%d, md=%d!\n",,2,,,pd,id);
703 ret=3;
704 }
705 }
706 }
707
708 // Kill the currently running timeout
709 Kill_Timeout();
710 }
711 else
712 {
713 GEL_TextOut("DSP core #%d cannot set PSC.\n",,2,,,DNUM);
714 }
715
716 return(ret);
717}
718
719/****************************************************************************
720 *
721 * NAME
722 * Set_Timeout
723 *
724 * PURPOSE:
725 * Starts a timeout period of msec. The running timeout period can be
726 * query with Get_Timeout. To kill a running timeout before the end,
727 * call Kill_Timeout. Only one timeout period can be used at any time.
728 * A timeout period can be used to measure a period of time while doing
729 * anything else. Not accurate, sets timer at least as big as desired.
730 *
731 * USAGE
732 * This routine can be called as:
733 *
734 * Set_Timeout(msec)
735 *
736 * msec - (i) timeout period in msec (not very precise < sec range)
737 *
738 * RETURN VALUE
739 * NONE
740 *
741 * REFERENCE
742 *
743 ****************************************************************************/
744Set_Timeout(msec)
745{
746 // Cancel the current timer if not already expired
747 GEL_CancelTimer(TIMEOUT_ID);
748
749 // Starts the timeout period
750 _GEL_Global_Timeout1=1;
751
752 // Setup a callback routine with specified timeout
753 GEL_SetTimer(msec, TIMEOUT_ID, "_Timeout_Callback()");
754}
755
756/****************************************************************************
757 *
758 * NAME
759 * Get_Timeout
760 *
761 * PURPOSE:
762 * Query the running state of a timeout period started by Set_Timeout.
763 * (see Set_Timeout for more info).
764 *
765 * USAGE
766 * This routine can be called as:
767 *
768 * Get_Timeout()
769 *
770 * RETURN VALUE
771 * 0:expired, 1:running
772 *
773 * REFERENCE
774 *
775 ****************************************************************************/
776Get_Timeout()
777{
778 if (!_GEL_Global_Timeout1)
779 {
780 // Cancel the current timer
781 GEL_CancelTimer(TIMEOUT_ID);
782 }
783
784 // Return the global timeout status 1=running, 0=expired
785 return _GEL_Global_Timeout1;
786}
787
788/****************************************************************************
789 *
790 * NAME
791 * Kill_Timeout
792 *
793 * PURPOSE:
794 * Cancel a running timeout period before it expires
795 * (see Set_Timeout for more info).
796 *
797 * USAGE
798 * This routine can be called as:
799 *
800 * Kill_Timeout()
801 *
802 * RETURN VALUE
803 * NONE
804 *
805 * REFERENCE
806 *
807 ****************************************************************************/
808Kill_Timeout()
809{
810 // Cancel the current timer
811 GEL_CancelTimer(TIMEOUT_ID);
812
813 // The timeout period is expired
814 _GEL_Global_Timeout1=0;
815}
816
817/****************************************************************************
818 *
819 * NAME
820 * _Timeout_Callback
821 *
822 * PURPOSE:
823 * Internal Callback function used by Set_timeout
824 * (see Set_Timeout for more info).
825 *
826 * USAGE
827 * This routine must not be called by itself.
828 *
829 * RETURN VALUE
830 * NONE
831 *
832 * REFERENCE
833 *
834 ****************************************************************************/
835_Timeout_Callback()
836{
837 // The timeout period is expired
838 _GEL_Global_Timeout1=0;
839}
840
841
842/****************************************************************************
843 *
844 * NAME
845 * Set_Psc_All_On
846 *
847 * PURPOSE:
848 * Enable all PSC modules and DSP power domains on ALWAYSON, and wait
849 * for these power transitions to complete.
850 *
851 * USAGE
852 * This routine can be called as:
853 *
854 * Set_Psc_All_On()
855 *
856 * RETURN VALUE
857 * NONE
858 *
859 * REFERENCE
860 *
861 ****************************************************************************/
862hotmenu Set_Psc_All_On( )
863{
864 unsigned int i=0;
865
866 // Only core0 can set PSC
867 if (DNUM == 0)
868 {
869 GEL_TextOut( "Power on all PSC modules and DSP domains... \n");
870
871 Set_PSC_State(PD1, LPSC_DEBUG, PSC_ENABLE);
872 Set_PSC_State(PD1, LPSC_TETB, PSC_ENABLE);
873 Set_PSC_State(PD2, LPSC_PA, PSC_ENABLE);
874 Set_PSC_State(PD2, LPSC_SGMII, PSC_ENABLE);
875// Removed unwanted power up of modules
876// Set_PSC_State(PD2, LPSC_SA, PSC_ENABLE);
877// Set_PSC_State(PD3, LPSC_PCIE, PSC_ENABLE);
878// Set_PSC_State(PD4, LPSC_SRIO, PSC_ENABLE);
879// Set_PSC_State(PD5, LPSC_HYPERLINK_0, PSC_ENABLE);
880 Set_PSC_State(PD6, LPSC_SR, PSC_ENABLE);
881 Set_PSC_State(PD7, LPSC_MSMCRAM, PSC_ENABLE);
882 Set_PSC_State(PD8, LPSC_GEM_0, PSC_ENABLE);
883 Set_PSC_State(PD9, LPSC_GEM_1, PSC_ENABLE);
884 Set_PSC_State(PD10, LPSC_GEM_2, PSC_ENABLE);
885 Set_PSC_State(PD11, LPSC_GEM_3, PSC_ENABLE);
886 Set_PSC_State(PD12, LPSC_GEM_4, PSC_ENABLE);
887 Set_PSC_State(PD13, LPSC_GEM_5, PSC_ENABLE);
888 Set_PSC_State(PD14, LPSC_GEM_6, PSC_ENABLE);
889 Set_PSC_State(PD15, LPSC_GEM_7, PSC_ENABLE);
890 Set_PSC_State(PD16, LPSC_DDR3_0, PSC_ENABLE);
891 Set_PSC_State(PD16, LPSC_DDR3_1, PSC_ENABLE);
892// Set_PSC_State(PD17, LPSC_TAC, PSC_ENABLE);
893// Set_PSC_State(PD17, LPSC_RAC_01, PSC_ENABLE);
894// Set_PSC_State(PD18, LPSC_RAC_23, PSC_ENABLE);
895// Set_PSC_State(PD19, LPSC_FFTCA_FFTC_0, PSC_ENABLE);
896// Set_PSC_State(PD19, LPSC_FFTCA_FFTC_1, PSC_ENABLE);
897// Set_PSC_State(PD20, LPSC_FFTCA_FFTC_2, PSC_ENABLE);
898// Set_PSC_State(PD20, LPSC_FFTCA_FFTC_3, PSC_ENABLE);
899// Set_PSC_State(PD20, LPSC_FFTCA_FFTC_4, PSC_ENABLE);
900// Set_PSC_State(PD20, LPSC_FFTCA_FFTC_5, PSC_ENABLE);
901// Set_PSC_State(PD21, LPSC_AIF, PSC_ENABLE);
902// Set_PSC_State(PD22, LPSC_TCP3D_0, PSC_ENABLE);
903// Set_PSC_State(PD22, LPSC_TCP3D_1, PSC_ENABLE);
904// Set_PSC_State(PD23, LPSC_TCP3D_2, PSC_ENABLE);
905// Set_PSC_State(PD23, LPSC_TCP3D_3, PSC_ENABLE);
906// Set_PSC_State(PD24, LPSC_VCP_0, PSC_ENABLE);
907// Set_PSC_State(PD24, LPSC_VCP_1, PSC_ENABLE);
908// Set_PSC_State(PD24, LPSC_VCP_2, PSC_ENABLE);
909// Set_PSC_State(PD24, LPSC_VCP_3, PSC_ENABLE);
910// Set_PSC_State(PD25, LPSC_VCP_4, PSC_ENABLE);
911// Set_PSC_State(PD25, LPSC_VCP_5, PSC_ENABLE);
912// Set_PSC_State(PD25, LPSC_VCP_6, PSC_ENABLE);
913// Set_PSC_State(PD25, LPSC_VCP_7, PSC_ENABLE);
914// Set_PSC_State(PD26, LPSC_BCP, PSC_ENABLE);
915// Set_PSC_State(PD27, LPSC_DXB, PSC_ENABLE);
916// Set_PSC_State(PD28, LPSC_HYPERLINK_1, PSC_ENABLE);
917 Set_PSC_State(PD29, LPSC_XGE, PSC_ENABLE);
918 Set_PSC_State(PD31, LPSC_ARM, PSC_ENABLE);
919
920 GEL_TextOut( "Power on all PSC modules and DSP domains... Done.\n" );
921 }
922 else
923 {
924 GEL_TextOut("DSP core #%d cannot set PSC.\n",,2,,,DNUM);
925 }
926}
927
928
929//********************************************************************************************************************************
930//********************************************************************************************************************************
931/*
932 Set_Pll1() - This function executes the main PLL initialization
933 sequence needed to get the main PLL up after coming out of an initial power up
934 before it is locked or after it is already locked.
935
936 Index value determines multiplier, divier used and clock reference assumed for
937 output display.
938 */
939Set_Pll1(int index)
940{
941 int i, TEMP;
942 unsigned int BYPASS_val;
943 unsigned int BWADJ_val;
944 unsigned int OD_val;
945
946 float CLKIN_val;
947 unsigned int PLLM_val;
948 unsigned int PLLD_val;
949 unsigned int PLLDIV3_val; //example value for SYSCLK2 (from 6614 spec) Default /2 - Fast Peripherals, (L2, MSMC, DDR3 EMIF, EDMA0...)
950 unsigned int PLLDIV4_val; //example value for SYSCLK3 (from 6614 spec) Default /3 - Switch Fabric
951 unsigned int PLLDIV7_val; //example value for SYSCLK6 (from 6614 spec) Defualt /6 - Slow Peripherals (UART, SPI, I2C, GPIO...)
952
953 unsigned int debug_info_on;
954 unsigned int delay;
955
956 if(index == 1){ // 122.88 MHz -> 614.4 MHz
957 CLKIN_val = 122.88; // setup CLKIN to 122.88 MHz
958 PLLM_val = 10; // setup PLLM (PLL multiplier) to x10
959 PLLD_val = 1; // setup PLLD (reference divider) to /1
960 OD_val = 2; // setup OD to a fixed /2
961 }
962 else if(index == 2){ // 122.88MHz -> 737.28 MHz
963 CLKIN_val = 122.88; // setup CLKIN to 122.88 MHz
964 PLLM_val = 12; // setup PLLM (PLL multiplier) to x12
965 PLLD_val = 1; // setup PLLD (reference divider) to /1
966 OD_val = 2; // setup OD to a fixed /2
967 }
968
969 else if(index == 3){ // 122.88MHz -> 983.04 MHz
970 CLKIN_val = 122.88; // setup CLKIN to 122.88 MHz
971 PLLM_val = 16; // setup PLLM (PLL multiplier) to x12
972 PLLD_val = 1; // setup PLLD (reference divider) to /1
973 OD_val = 2; // setup OD to a fixed /2
974 }
975
976 else if(index == 4){ // 122.88 MHz -> 1.2 GHz
977 CLKIN_val = 122.88; // setup CLKIN to 122.88 MHz
978 PLLM_val = 20; // setup PLLM (PLL multiplier) to x20
979 PLLD_val = 1; // setup PLLD (reference divider) to /1
980 OD_val = 2; // setup OD to a fixed /2
981 }
982 else if(index == 5){ // 122.88 MHz -> 1.35 GHz
983 CLKIN_val = 122.88; // setup CLKIN to 122.88 MHz
984 PLLM_val = 22; // setup PLLM (PLL multiplier) to x22
985 PLLD_val = 1; // setup PLLD (reference divider) to /1
986 OD_val = 2; // setup OD to a fixed /2
987 }
988
989
990
991
992 PLLDIV3_val = 3; // setup PLL output divider 3 to /3
993 PLLDIV4_val = 5; // setup PLL output divider 4 to /3
994 PLLDIV7_val = 6; // setup PLL output divider 7 to /6
995
996 BYPASS_val = PLL1_SECCTL & ~BYPASS_MASK; // get value of the BYPASS field
997 BWADJ_val = (PLLM_val) >> 1; // setup BWADJ to be 1/2 the value of PLLM
998 OD_val = 2; // setup OD to a fixed /2
999
1000 debug_info_on = 1;
1001 delay = 1000; // fix this!
1002
1003 /* Step 1: Unlock Boot Config Registers */
1004 KICK0 = KICK0_UNLOCK;
1005 KICK1 = KICK1_UNLOCK;
1006
1007 /* Step 2: Check if SECCTL bypass is low or high indicating what state the Main PLL is currently in. if
1008 the Main PLL is in bypass still (not yet setup) execute the following steps. */
1009
1010 if(BYPASS_val != 0x00000000){ // PLL bypass enabled - Execute PLL setup for PLL fresh out of power on reset
1011 if(debug_info_on){
1012 GEL_TextOut("Detected PLL bypass enabled: SECCTL[BYPASS] = %x\n",,,,, BYPASS_val);
1013 }
1014 /* Step 2a: Set MAINPLLCTL1[ENSAT] = 1 - This enables proper biasing of PLL analog circuitry */
1015 MAINPLLCTL1 |= (1 << MAIN_ENSAT_OFFSET);
1016 if(debug_info_on){
1017 GEL_TextOut("(2a) MAINPLLCTL1 = %x\n",,,,, MAINPLLCTL1);
1018 }
1019
1020 /* Step 2b: Set PLLCTL[PLLEN] = 0 This enables bypass in PLL controller MUX */
1021 PLL1_PLLCTL &= ~(1 << PLLEN_OFFSET);
1022 if(debug_info_on){
1023 GEL_TextOut("(2b) PLLCTL = %x\n",,,,, PLL1_PLLCTL);
1024 }
1025
1026 /* Step 2c: Set PLLCTL[PLLENSRC] = 0 - This enables PLLEN to control PLL controller MUX */
1027 PLL1_PLLCTL &= ~(1 << PLLENSRC_OFFSET);
1028 if(debug_info_on){
1029 GEL_TextOut("(2c) PLLCTL = %x\n",,,,, PLL1_PLLCTL);
1030 }
1031
1032 /* Step 2d: Wait 4 reference clock cycles (slowest of ALTCORE or SYSCLK) to make sure
1033 that the PLL controller MUX switches properly to bypass. */
1034 if(debug_info_on){
1035 GEL_TextOut("(2d) Delay...\n",,,,,);
1036 }
1037 for(i = 0; i < delay; i++); // this delay is much more than required
1038
1039 /* Step 2e: Set SECCTL[BYPASS] = 1 - enables bypass in PLL MUX */
1040 PLL1_SECCTL |= (1 << BYPASS_OFFSET);
1041 if(debug_info_on){
1042 GEL_TextOut("(2e) SECCTL = %x\n",,,,, PLL1_SECCTL);
1043 }
1044
1045 /* Step 2f: Set PLLCTL[PLLPWRDN] = 1 - power down the PLL */
1046 PLL1_PLLCTL |= (1 << PLLPWRDN_OFFSET);
1047 if(debug_info_on){
1048 GEL_TextOut("(2f) PLLCTL = %x\n",,,,, PLL1_PLLCTL);
1049 }
1050
1051 /* Step 2g: Wait for at least 5us for the PLL to power down */
1052 if(debug_info_on){
1053 GEL_TextOut("(2g) Delay...\n",,,,,);
1054 }
1055 for(i = 0; i < delay; i++); // this delay is much more than required
1056
1057 /* Step 2h: Set PLLCTL[PLLPWRDN] = 0 - Power the PLL back up */
1058 PLL1_PLLCTL &= ~(1 << PLLPWRDN_OFFSET);
1059 if(debug_info_on){
1060 GEL_TextOut("(2h) PLLCTL = %x\n",,,,, PLL1_PLLCTL);
1061 }
1062
1063 }
1064 else{ // PLL bypass disabled - Execute PLL setup for PLL that has previously been locked (skip to Step 3)
1065 if(debug_info_on){
1066 GEL_TextOut("Detected PLL bypass disabled: SECCTL[BYPASS] = %x\n",,,,, BYPASS_val);
1067 }
1068
1069 /* Step 3a: Set PLLCTL[PLLEN] = 0 This enables bypass in PLL controller MUX */
1070 PLL1_PLLCTL &= ~(1 << PLLEN_OFFSET);
1071 if(debug_info_on){
1072 GEL_TextOut("(3a) PLLCTL = %x\n",,,,, PLL1_PLLCTL);
1073 }
1074
1075 /* Step 3b: Set PLLCTL[PLLENSRC] = 0 - This enables PLLEN to control PLL controller MUX */
1076 PLL1_PLLCTL &= ~(1 << PLLENSRC_OFFSET);
1077 if(debug_info_on){
1078 GEL_TextOut("(3b) PLLCTL = %x\n",,,,, PLL1_PLLCTL);
1079 }
1080
1081 /* Step 3c: Wait 4 reference clock cycles (slowest of ALTCORE or SYSCLK) to make sure
1082 that the PLL controller MUX switches properly to bypass. */
1083 if(debug_info_on){
1084 GEL_TextOut("(3c) Delay...\n",,,,,);
1085 }
1086 for(i = 0; i < delay; i++); // this delay is much more than required
1087
1088 }
1089
1090
1091 /* Step 4: Programming PLLM[5:0] in the PLLM register of the PLL controller and
1092 programming PLLM[12:6] in the MAINPLLCTL0 register */
1093 PLL1_PLLM &= PLLM_MASK; // clear the PLLM[5:0] bit field
1094 PLL1_PLLM |= ~PLLM_MASK & (PLLM_val - 1); // set the PLLM[5:0] bit field to the 6 LSB of PLLM_val
1095
1096 if(debug_info_on){
1097 GEL_TextOut("(4)PLLM[PLLM] = %x\n",,,,, PLL1_PLLM);
1098 }
1099
1100 MAINPLLCTL0 &= MAIN_PLLM_MASK; // clear the PLLM[12:6] bit field
1101 MAINPLLCTL0 |= ~MAIN_PLLM_MASK & (( (PLLM_val - 1) >> 6) << MAIN_PLLM_OFFSET); // set the PLLM[12:6] bit field to the 7 MSB of PLL_val
1102
1103 if(debug_info_on){
1104 GEL_TextOut("MAINPLLCTL0 = %x\n",,,,, MAINPLLCTL0);
1105 }
1106
1107 /* Step 5: Programming BWADJ[7:0] in the MAINPLLCTL0 register and BWADJ[11:8] in MAINPLLCTL1 register */
1108 MAINPLLCTL0 &= MAIN_BWADJ0_MASK; // clear the MAIN_BWADJ0 bit field
1109 MAINPLLCTL0 |= ~MAIN_BWADJ0_MASK & ((BWADJ_val - 1) << MAIN_BWADJ0_OFFSET); // set the MAIN_BWADJ[7:0] bit field to the 8 LSB of BWADJ_val
1110
1111 if(debug_info_on){
1112 GEL_TextOut("(5) MAINPLLCTL0 = %x\n",,,,, MAINPLLCTL0);
1113 }
1114
1115 MAINPLLCTL1 &= MAIN_BWADJ1_MASK; // clear the MAIN_BWADJ1 bit field
1116 MAINPLLCTL1 |= ~MAIN_BWADJ1_MASK & (( (BWADJ_val - 1) >> 8) << MAIN_BWADJ1_OFFSET); // set the MAIN_BWADJ[11:8] bit field to the 4 MSB of BWADJ_val
1117
1118 if(debug_info_on){
1119 GEL_TextOut("(5) MAINPLLCTL1 = %x\n",,,,, MAINPLLCTL1);
1120 }
1121
1122 /* Step 6: Programming PLLD[5:0] in the MAINPLLCTL0 register */
1123 MAINPLLCTL0 &= MAIN_PLLD_MASK; // clear the PLLD bit field
1124 MAINPLLCTL0 |= ~MAIN_PLLD_MASK & (PLLD_val - 1); // set the PLLD[5:0] bit field of PLLD to PLLD_val
1125
1126 if(debug_info_on){
1127 GEL_TextOut("(6) MAINPLLCTL0 = %x\n",,,,, MAINPLLCTL0);
1128 }
1129
1130 /* Step 7: Programming OD[3:0] in the SECCTL register */
1131 PLL1_SECCTL &= OUTPUT_DIVIDE_MASK; // clear the OD bit field
1132 PLL1_SECCTL |= ~OUTPUT_DIVIDE_MASK & (OD_val - 1) << OUTPUT_DIVIDE_OFFSET; // set the OD[3:0] bit field of PLLD to OD_val
1133
1134 if(debug_info_on){
1135 GEL_TextOut("(7) SECCTL = %x\n",,,,, PLL1_SECCTL);
1136 }
1137
1138 /* Step 8: Following steps are needed to change the default output dividers */
1139
1140 /* Step 8a: Check that the GOSTAT bit in PLLSTAT is cleared to show that no GO
1141 operation is currently in progress*/
1142 if(debug_info_on){
1143 GEL_TextOut("(8a) Delay...\n",,,,,);
1144 }
1145 while((PLL1_STAT) & 0x00000001);
1146
1147 /* Step 8b: Program the RATIO field in PLLDIVn to the desired new divide-down rate.
1148 If RATIO field is changed, the PLL controller will flag the change in the
1149 corresponding bit of DCHANGE*/
1150 PLL1_DIV3 = (PLLDIV3_val-1) | 0x8000; //Set PLLDIV3
1151 PLL1_DIV4 = (PLLDIV4_val-1) | 0x8000; //Set PLLDIV4
1152 PLL1_DIV7 = (PLLDIV7_val-1) | 0x8000; //Set PLLDIV7
1153
1154 if(debug_info_on){
1155 GEL_TextOut("PLL1_DIV3 = %x\n",,,,, PLL1_DIV3);
1156 GEL_TextOut("PLL1_DIV4 = %x\n",,,,, PLL1_DIV4);
1157 GEL_TextOut("PLL1_DIV7 = %x\n",,,,, PLL1_DIV7);
1158 }
1159
1160 /* Step 8c: Set GOSET bit in PLLCMD to initiate the GO operation to change the divide
1161 values and align the SYSCLKs as programmed */
1162 PLL1_CMD |= 0x00000001;
1163
1164 /*Step 8d/e: Read the GOSTAT bit in PLLSTAT to make sure the bit returns to 0 to
1165 indicate that the GO operation has completed */
1166 if(debug_info_on){
1167 GEL_TextOut("(8d/e) Delay...\n",,,,,);
1168 }
1169 while((PLL1_STAT) & 0x00000001);
1170
1171 /* Step 9: Set PLLCTL[PLLRST] = 1 - Assert PLL reset (Previously Step 3)*/
1172 PLL1_PLLCTL |= (1 << PLLRST_OFFSET);
1173
1174 /* Step 10: Wait for the at least 7us for the PLL reset properly (128 CLKIN1 cycles) */
1175 if(debug_info_on){
1176 GEL_TextOut("(10) Delay...\n",,,,,);
1177 }
1178 for(i=0;i<delay;i++);
1179
1180 /* Step 11: Set PLLCTL[PLLRST] = 0 - De-Assert PLL reset */
1181 PLL1_PLLCTL &= ~(1 << PLLRST_OFFSET);
1182
1183 /* Step 12: Wait for PLL to lock (2000 CLKIN1 cycles) */
1184 if(debug_info_on){
1185 GEL_TextOut("(12) Delay...\n",,,,,);
1186 }
1187 for(i=0;i<delay;i++);
1188
1189 /* Step 13: In SECCTL, write BYPASS = 0 (enable PLL mux to switch to PLL mode) */
1190 PLL1_SECCTL &= ~(1 << BYPASS_OFFSET);
1191 if(debug_info_on){
1192 GEL_TextOut("(13) SECCTL = %x\n",,,,, PLL1_SECCTL);
1193 }
1194 if(debug_info_on){
1195 GEL_TextOut("(Delay...\n",,,,,);
1196 }
1197 for(i=0;i<delay;i++);
1198 if(debug_info_on){
1199 GEL_TextOut("(Delay...\n",,,,,);
1200 }
1201 for(i=0;i<delay;i++);
1202
1203 /* Step 14: In PLLCTL, write PLLEN = 1 to enable PLL mode */
1204 PLL1_PLLCTL |= (1 << PLLEN_OFFSET);
1205 if(debug_info_on){
1206 GEL_TextOut("(14) PLLCTL = %x\n",,,,, PLL1_PLLCTL);
1207 }
1208
1209 /* Step 15: Lock Boot Config Registers */
1210 KICK0 = 0x00000000;
1211 KICK1 = 0x00000000;
1212
1213 GEL_TextOut("PLL has been configured (CLKIN * PLLM / PLLD / PLLOD = PLLOUT):\n",,,,,);
1214 GEL_TextOut("PLL has been configured (%f MHz * %d / %d / 2 = %f MHz)\n",,,,, CLKIN_val, PLLM_val, PLLD_val, (CLKIN_val * PLLM_val / PLLD_val / 2) );
1215
1216}
1217
1218
1219
1220Set_Tetris_Pll(int index)
1221{
1222
1223 unsigned int BWADJ_val;
1224 unsigned int OD_val;
1225 unsigned int PLLM_val;
1226 float CLKIN_val;
1227 int i;
1228
1229 GEL_TextOut("Switching on ARM Core 0\n",,,,,);
1230 TETRIS_CPU0_PDCTL = 0x00000000;
1231 TETRIS_CPU0_PTCMD = 0x00000001;
1232
1233 GEL_TextOut("Switching on ARM Core 1\n",,,,,);
1234 TETRIS_CPU1_PDCTL = 0x00000000;
1235 TETRIS_CPU1_PTCMD = 0x00000001;
1236
1237 GEL_TextOut("Switching on ARM Core 2\n",,,,,);
1238 TETRIS_CPU2_PDCTL = 0x00000000;
1239 TETRIS_CPU2_PTCMD = 0x00000001;
1240
1241 GEL_TextOut("Switching on ARM Core 3\n",,,,,);
1242 TETRIS_CPU3_PDCTL = 0x00000000;
1243 TETRIS_CPU3_PTCMD = 0x00000001;
1244
1245 if(index == 1){ // 100 MHz -> 1.0 GHz
1246 CLKIN_val = 125; // setup CLKIN to 125 MHz
1247 PLLM_val = 16; // setup PLLM (PLL multiplier) to x20
1248 OD_val = 2; // setup OD to a fixed /2
1249 }
1250 else if(index == 2){ // 100 MHz -> 1.4 GHz
1251 CLKIN_val = 125; // setup CLKIN to 125 MHz
1252 PLLM_val = 22; // setup PLLM (PLL multiplier) to x28
1253 OD_val = 2; // setup OD to a fixed /2
1254 }
1255 else if(index == 3){ // 174.825MHz -> 1.4 GHz
1256
1257 CLKIN_val = 174.825; // setup CLKIN to 174.825 MHz
1258 PLLM_val = 16; // setup PLLM (PLL multiplier) to x16
1259 OD_val = 2; // setup OD to a fixed /2
1260 }
1261
1262 BWADJ_val = (PLLM_val-1) >> 1; // setup BWADJ to be 1/2 the value of PLLM
1263 OD_val = 2; // setup OD to a fixed /2
1264
1265 /* Step 1: Unlock Boot Config Registers */
1266 KICK0 = KICK0_UNLOCK;
1267 KICK1 = KICK1_UNLOCK;
1268
1269 //Step 1 : Assert SEC PLL Reset
1270 SECPLLCTL1 = ((1 << SEC_PLLCTL1_RESET_OFFSET) | (1 << SEC_PLLCTL1_ENSTAT_OFFSET));
1271
1272 //Step 2 : Change CLKF/OD/BWADJ etc. for SEC PLL
1273 SECPLLCTL0 = ((BWADJ_val << SEC_PLLCTL0_BWADJ_OFFSET) |
1274 ((OD_val-1) << SEC_PLLCTL0_OD_OFFSET)|
1275 ((PLLM_val-1) << SEC_PLLCTL0_PLLM_OFFSET));
1276
1277 //Step 3 : Make sure the resets are held for 5us
1278 for(i = 0; i < 200000; i++);
1279
1280 //Step 4 : Remove SEC PLL reset
1281 SECPLLCTL1 = (1 << SEC_PLLCTL1_ENSTAT_OFFSET);
1282
1283 //Step 5 : Wait for PLL to lock (4000 CLKIN1 cycles)
1284 for(i = 0; i < 4000; i++);
1285
1286 //Step 6 : Get the PLL out of Bypass
1287 //SECPLLCTL0 &= ~(1 << SEC_PLLCTL0_BYPASS_OFFSET);
1288 CHIP_MISC1 |= (1 << ARMPLL_ENABLE_OFFSET);
1289
1290
1291 //Step 6 : Lock Boot Config Registers
1292 KICK0 = 0x00000000;
1293 KICK1 = 0x00000000;
1294
1295 GEL_TextOut("ARM PLL has been configured (%f MHz * %d / %d = %f MHz)\n",,,,, CLKIN_val, PLLM_val, OD_val, (CLKIN_val * PLLM_val)/OD_val);
1296
1297}
1298
1299
1300/* Set the desired PA PLL configuration */
1301PaPllConfig()
1302{
1303 unsigned int passclksel = (DEVSTAT & PASSCLKSEL_MASK);
1304 unsigned int papllctl0val_orig = PAPLLCTL0;
1305 unsigned int papllctl1val_orig = PAPLLCTL1;
1306 unsigned int papllctl0val_final;
1307 unsigned int papllctl1val_final;
1308 unsigned int papllclkf = 16; //204; // 204; 20 (if PASSREFCLK == 100mhz) Multiply by clkf + 1
1309 unsigned int papllclkd = 0; //11; // 11; 1 (if PASSREFCLK == 100mhz) Divide by clkd + 1
1310 unsigned int i = 0;
1311
1312 if (passclksel != PASSCLKSEL_MASK) GEL_TextOut("WARNING: SYSCLK is the input to the PA PLL.\n");
1313
1314 /* Unlock Chip Level Registers */
1315 KICK0 = KICK0_UNLOCK;
1316 KICK1 = KICK1_UNLOCK;
1317
1318 // PAPLLCTL1 = PAPLLCTL1 | 0x00000040; //Set ENSAT = 1; Set PLL Select to 0 (for SYCLK0 as input of PASS)
1319 PAPLLCTL1 = PAPLLCTL1 | 0x00002040; //Set ENSAT = 1; Set PLL Select to 1 (for PA PLL as input of PASS)
1320
1321 /*in PAPLLCTL0, clear bypass bit to set the PA PLL in Bypass Mode*/
1322 //PAPLLCTL0 &= ~(1<<BYPASS_BIT_SHIFT); // Not setting Bypass bit
1323 PAPLLCTL0 |= (1<<BYPASS_BIT_SHIFT); // Actually setting bypass bit
1324
1325 /*Wait 4 cycles for the slowest of PLLOUT or reference clock source (CLKIN)*/
1326 for(i=0;i<100;i++);
1327
1328 /*In PAPLLCTL1, write PLL reset bit to put the PLL in reset*/
1329 PAPLLCTL1 |= PA_PLL_RESET_MASK;
1330
1331 /* Program the multiplier value */
1332 PAPLLCTL0 &= (~PA_PLL_CLKF_MASK); //clear multiplier value
1333 PAPLLCTL0 &= (~PA_PLL_CLKR_MASK); //clear divider value
1334 PAPLLCTL0 |= (papllclkf<<CLKF_BIT_SHIFT); // set PLLM
1335 PAPLLCTL0 |= (papllclkd<<CLKD_BIT_SHIFT); // set PLLD
1336
1337
1338 PAPLLCTL0 &= 0x00FFFFFF;
1339 PAPLLCTL0 |= ((((papllclkf + 1)>>1)-1)<<24);
1340
1341 //PAPLLCTL1 = PAPLLCTL1 | 0x00002000;
1342
1343 /*Wait for PLL to properly reset (128 CLKIN1 cycles) */
1344 for(i=0;i<1000;i++);
1345
1346 /* take the PA PLL out of reset */
1347 PAPLLCTL1 &= (~PA_PLL_RESET_MASK);
1348
1349 /*Wait for PLL to lock (2000 CLKIN1 cycles) */
1350 for(i=0;i<5000;i++);
1351
1352 /* enable PLL mode */
1353 PAPLLCTL0 &= ~(1<<BYPASS_BIT_SHIFT); // actually setting PLL MODE
1354
1355 for(i=0;i<4000;i++);
1356
1357 /* Lock Chip Level Registers */
1358 KICK0 = KICK_LOCK;
1359 KICK1 = KICK_LOCK;
1360
1361 papllctl0val_final = PAPLLCTL0;
1362 papllctl1val_final = PAPLLCTL1;
1363
1364 GEL_TextOut("Completed PA PLL Setup\n");
1365 GEL_TextOut("PAPLLCTL0 - before: 0x%x\t after: 0x%x\n",,,,, papllctl0val_orig, papllctl0val_final);
1366 GEL_TextOut("PAPLLCTL1 - before: 0x%x\t after: 0x%x\n",,,,, papllctl1val_orig, papllctl1val_final);
1367
1368 if ((papllctl0val_final != 0x09080500) || (papllctl1val_final != 0x00002040))
1369 {
1370 return 1;
1371 }
1372
1373 return 0;
1374
1375}
1376
1377//*************************************************************************************************
1378//*************************************************************************************************
1379//*************************************************************************************************
1380//*************************************************************************************************
1381//*************************************************************************************************
1382//*************************************************************************************************
1383
1384//--------DDR3A Memory test----------------------
1385
1386ddr3A_memory_test ()
1387{
1388 unsigned int index, value;
1389
1390 GEL_TextOut( "DDR3A memory test... Started\n" );
1391
1392 /* Write a pattern */
1393 for (index = DDR3A_TEST_START_ADDRESS; index < DDR3A_TEST_END_ADDRESS; index += 4) {
1394 *index = index;
1395 }
1396
1397 /* Read and check the pattern */
1398 for (index = DDR3A_TEST_START_ADDRESS; index < DDR3A_TEST_END_ADDRESS; index += 4) {
1399
1400 value = *index;
1401
1402 if (value != index) {
1403 GEL_TextOut( "DDR3A memory test... Failed\n" );
1404 return -1;
1405 }
1406 }
1407
1408 /* Write a pattern for complementary values */
1409 for (index = DDR3A_TEST_START_ADDRESS; index < DDR3A_TEST_END_ADDRESS; index += 4) {
1410 *index = ~index;
1411 }
1412
1413 /* Read and check the pattern */
1414 for (index = DDR3A_TEST_START_ADDRESS; index < DDR3A_TEST_END_ADDRESS; index += 4) {
1415
1416 value = *index;
1417
1418 if (value != ~index) {
1419 GEL_TextOut( "DDR3A memory test... Failed\n" );
1420 return -1;
1421 }
1422 }
1423
1424 GEL_TextOut( "DDR3A memory test... Passed\n" );
1425 return 0;
1426
1427}
1428
1429//---------------------------------------------------
1430
1431//--------DDR3B Memory test----------------------
1432
1433ddr3B_memory_test ()
1434{
1435 unsigned int index, value;
1436
1437 GEL_TextOut( "DDR3B memory test... Started\n" );
1438
1439 /* Write a pattern */
1440 for (index = DDR3B_TEST_START_ADDRESS; index < DDR3B_TEST_END_ADDRESS; index += 4) {
1441 *index = index;
1442 }
1443
1444 /* Read and check the pattern */
1445 for (index = DDR3B_TEST_START_ADDRESS; index < DDR3B_TEST_END_ADDRESS; index += 4) {
1446
1447 value = *index;
1448
1449 if (value != index) {
1450 GEL_TextOut( "DDR3B memory test... Failed\n" );
1451 return -1;
1452 }
1453 }
1454
1455 /* Write a pattern for complementary values */
1456 for (index = DDR3B_TEST_START_ADDRESS; index < DDR3B_TEST_END_ADDRESS; index += 4) {
1457 *index = ~index;
1458 }
1459
1460 /* Read and check the pattern */
1461 for (index = DDR3B_TEST_START_ADDRESS; index < DDR3B_TEST_END_ADDRESS; index += 4) {
1462
1463 value = *index;
1464
1465 if (value != ~index) {
1466 GEL_TextOut( "DDR3B memory test... Failed\n" );
1467 return -1;
1468 }
1469 }
1470
1471 GEL_TextOut( "DDR3B memory test... Passed\n" );
1472 return 0;
1473
1474}
1475
1476//-------------------------------------------------------------------------
1477
1478
1479/****************************************************************************
1480 *
1481 * NAME
1482 * Setup_Memory_Map
1483 *
1484 * PURPOSE:
1485 * Setup the Memory Map for EVMC6678L.
1486 * Defined memory location avoid debugger access outside these locations.
1487 *
1488 * USAGE
1489 * This routine can be called as:
1490 *
1491 * Setup_Memory_Map()
1492 *
1493 * RETURN VALUE
1494 * NONE
1495 *
1496 * REFERENCE
1497 * Based on TMS320C6678 datasheet.
1498 *
1499 ****************************************************************************/
1500hotmenu Setup_Memory_Map( )
1501{
1502 GEL_TextOut("Setup_Memory_Map...\n",,);
1503
1504 GEL_MapOn( );
1505 GEL_MapReset( );
1506
1507 GEL_MapAddStr( 0x00000000, 0, 0x21400000, "R|W|AS4", 0 ); //
1508 GEL_MapAddStr( 0x21400000,0, 0x00000080, "R|W|AS4", 0 ); // Hyperlink Config (remote)
1509 //GEL_MapAddStr( 0x21400080,0, 0x00000080, "R|W|AS4", 0 ); // Hyperlink Config (remote)
1510 GEL_MapAddStr( 0x21400200, 0, 0xdebffe00, "R|W|AS4", 0 ); //
1511 GEL_TextOut( "Setup_Memory_Map... Done.\n" );
1512}
1513
1514/*----------------------------------------------------- DDR3A : DDR800, 32bit--------------------------------------------------------------------------*/
1515ddr3A_32bit_DDR800_setup()
1516{
1517unsigned int multiplier = 15;
1518 unsigned int divider = 0;
1519 int temp;
1520 unsigned int OD_val = 8;
1521 KICK0 = 0x83E70B13;
1522 KICK1 = 0x95A4F1E0;
1523
1524
1525//1. Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010).
1526 do {
1527 read_val = DDR3A_PGSR0;
1528 } while ((read_val&0x00000001) != 0x00000001);
1529
1530//4. Clocks are enabled and frequency is stable---------------------------------------
1531//DDR3A PLL setup
1532 GEL_TextOut ( "DDR3 PLL (PLL2) Setup ... \n");
1533 //DDR3APLLCTL0 = DDR3APLLCTL0 & 0xFF7FFFFF;
1534 // Set ENSAT = 1
1535 DDR3APLLCTL1 |= 0x00000040;
1536 // Put the PLL in PLL Mode
1537 DDR3APLLCTL0 |= 0x00800000;
1538 // In PLL Controller, reset the PLL (bit 13 in DDR3APLLCTL1 register)
1539 DDR3APLLCTL1 |= 0x00002000;
1540 // Program the necessary multipliers/dividers and BW adjustments
1541 // Set the divider values
1542 DDR3APLLCTL0 &= ~(0x0000003F);
1543 DDR3APLLCTL0 |= (divider & 0x0000003F);
1544 /* Step 7: Programming OD[3:0] in the SECCTL register */
1545 DDR3APLLCTL0 &= OUTPUT_DIVIDE_MASK; // clear the OD bit field
1546 DDR3APLLCTL0 |= ~OUTPUT_DIVIDE_MASK & (OD_val - 1) << OUTPUT_DIVIDE_OFFSET; // set the OD[3:0] bit field of PLLD to OD_val
1547
1548 /* Set the Multipler values */
1549 DDR3APLLCTL0 &= ~(0x0007FFC0);
1550 DDR3APLLCTL0 |= ((multiplier << 6) & 0x0007FFC0 );
1551 temp = ((multiplier + 1) >> 1) - 1;
1552 DDR3APLLCTL0 &= ~(0xFF000000);
1553 DDR3APLLCTL0 |= ((temp << 24) & 0xFF000000);
1554 DDR3APLLCTL1 &= ~(0x0000000F);
1555 DDR3APLLCTL1 |= ((temp >> 8) & 0x0000000F);
1556 //In DDR3PLLCTL1, write PLLRST = 0 to bring PLL out of reset
1557 DDR3APLLCTL1 &= ~(0x00002000);
1558 // Put the PLL in PLL Mode
1559 DDR3APLLCTL0 &= ~(0x00800000); // ReSet the Bit 23
1560 GEL_TextOut( "DDR3 PLL Setup complete, DDR3A clock now running at 400MHz.\n" );
1561//DDR3A PLL setup complete ---------------------------------------
1562
1563/*------------------------- Start PHY Configuration -------------------------------*/
1564
1565 //DDR3A_PGCR1 = 0x0280C487;
1566
1567 //5.a Program FRQSEL in the PLL Control Register (address offset 0x018).
1568 DDR3A_PLLCR = 0xDC000; //Set FRQSEL=11, for ctl_clk between 166-275MHz
1569
1570 //5.b. Program WLSTEP=1, IODDRM=1, and ZCKSEL in the PHY General Configuration Register 1 (address offset 0x00C).
1571 DDR3A_PGCR1 |= (1 << 2); //WLSTEP = 1
1572
1573 DDR3A_PGCR1 &= ~(IODDRM_MASK);
1574 DDR3A_PGCR1 |= (( 1 << 7) & IODDRM_MASK);
1575
1576
1577 DDR3A_PGCR1 &= ~(ZCKSEL_MASK);
1578 DDR3A_PGCR1 |= (( 1 << 23) & ZCKSEL_MASK);
1579
1580
1581 //5.c. Program PHY Timing Parameters Register 0-4 (address offset 0x01C - 0x02C).
1582
1583 DDR3A_PTR0 = 0x42C21590;
1584
1585 DDR3A_PTR1 = 0xD05612C0;
1586
1587// Maintaining default values of Phy Timing Parameters Register 2 in PUB
1588
1589 DDR3A_PTR3 = 0x06C30D40;//0x18061A80;
1590
1591 DDR3A_PTR4 = 0x06413880;//0x0AAE7100;
1592
1593//5.d. Program PDQ, MPRDQ, and BYTEMASK in the DRAM Configuration Register (address offset 0x044).
1594// All other fields must be left at their default values.
1595
1596 DDR3A_DCR &= ~(PDQ_MASK); //PDQ = 0
1597 DDR3A_DCR &= ~(MPRDQ_MASK); //MPRDQ = 0
1598
1599 DDR3A_DCR &= ~(BYTEMASK_MASK);
1600 DDR3A_DCR |= (( 1 << 10) & BYTEMASK_MASK);
1601
1602
1603DDR3A_DCR &= ~(NOSRA_MASK);
1604DDR3A_DCR |= (( 1 << 27) & NOSRA_MASK);
1605
1606
1607 DDR3A_DCR &= ~(UDIMM_MASK);
1608 DDR3A_DCR |= (( 1 << 29) & UDIMM_MASK);
1609
1610
1611//5.e. Program DRAM Timing Parameters Register 0-2 (address offset 0x048 - 0x050).
1612
1613 DDR3A_DTPR0 = 0x50CF6644; //0x50CE6644;
1614 DDR3A_DTPR1 = 0x12834180;
1615 DDR3A_DTPR2 = 0x50022A00;
1616
1617//5.f. Program BL=0, CL, WR, and PD=1 in the Mode Register 0 (address offset 0x054).
1618 //All other fields must be left at their default values.
1619
1620DDR3A_MR0 = 0x00001420;
1621
1622
1623//5.g. Program DIC, RTT, and TDQS in the Mode Register 1 (address offset 0x058).
1624 //All other fields must be left at their default values.
1625
1626DDR3A_MR1 = 0x00000006;
1627
1628
1629//---------------------------------------------------------------------------------------------------------
1630
1631//5.h. Program Mode Register 2 (address offset 0x05C).
1632 // Maintaining default values of Program Mode Register 2
1633 // DDR3A_MR2 = 0x00000018;
1634
1635//5.i. Program DTMPR=1, DTEXD, DTEXG, RANKEN=1 or 3, and RFSHDT=7 in the Data Training Configuration Register (address offset 0x068).
1636 //All other fields must be left at their default values.
1637 DDR3A_DTCR = 0x710035C7; //0x710035C7;
1638
1639//5.j. Program tREFPRD=(5*tREFI/ddr_clk_period) in the PHY General Configuration Register 2 (address offset 0x08C).
1640 //All other fields must be left at their default values.
1641
1642 DDR3A_PGCR2 = 0x00F03D09; //NOBUB = 0, FXDLAT = 0
1643//DDR3A_PGCR2 = 0x00F83D09; //NOBUB = 0, FXDLAT = 1
1644
1645//Set Impedence Register
1646DDR3A_ZQ0CR1 = 0x0000005D;
1647DDR3A_ZQ1CR1 = 0x0000005B;
1648DDR3A_ZQ2CR1 = 0x0000005B;
1649
1650
1651//6. Re-trigger PHY initialization in DDR PHY through the VBUSP interface.
1652//6.a. Program 0x00000033 to the PHY Initialization Register (address offset 0x004) to re-trigger PLL, ZCAL, and DCAL initialization.
1653
1654 DDR3A_PIR = 0x00000033;
1655
1656//6.b. Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010).
1657 do {
1658 read_val = DDR3A_PGSR0;
1659 } while ((read_val&0x00000001) != 0x00000001);
1660
1661//---------------------------------------------------------------------------------------------------------
1662
1663
1664
1665// 7. Trigger DDR3 initialization and leveling/training in DDR PHY through the VBUSP interface.
1666// a. If using a 16-bit wide DDR interface, program DXEN=0 in the DATX8 2-7 General Configuration Registers (address offsets 0x240, 0x280, 0x2C0, 0x300, 0x340, and 0x380) to disable the leveling/training for the upper byte lanes.
1667// b. If using a 32-bit wide DDR interface, program DXEN=0 in the DATX8 4-7 General Configuration Registers (address offsets 0x2C0, 0x300, 0x340, and 0x380) to disable the leveling/training for the upper byte lanes.
1668// c. If ECC is not required, program DXEN=0 in the DATX8 8 General Configuration Register (address offset 0x3C0) to disable the leveling/training for the ECC byte lane.
1669// NOTE: Setup supports 64-bit by default, ECC enable by default.
1670
1671//7.d. Program 0x0000XF81 to the PHY Initialization Register (address offset 0x004) to trigger DDR3 initialization and leveling/training sequences
1672
1673 DDR3A_PIR = 0x00000F81; //WLADJ - ON
1674 //DDR3A_PIR = 0x00000781; //WLADJ - OFF
1675
1676//---------------------------------------------------------------------------------------------------------
1677
1678//7.e. Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010).
1679 do {
1680 read_val = DDR3A_PGSR0;
1681 } while ((read_val&0x00000001) != 0x00000001);
1682
1683
1684 /* End PHY Configuration */
1685//---------------------------------------------------------------------------------------------------------
1686/* START EMIF INITIALIZATION
1687 ++++++++++++++++++SDCFG Register Calculation+++++++++++++++++++
1688 | 31 - 29 | 28 |27 - 25 | 24 | 23 - 22| 21 - 17 |
1689 |SDRAM_TYPE|Rsvd|DDR_TERM| DDQS | DYN_ODT| Rsvd |
1690 | 0x011 | 0 | 0x011 | 0x1 | 0x00 | 0x0 |
1691
1692 | 16-14 |13 - 12 | 11 - 8 | 7 |6 - 5 | 4 | 3 | 2 | 1 - 0 |
1693 | CWL | NM | CL | Rsvd |IBANK | Rsvd|EBANK| Rsvd|PAGE_SIZE|
1694 | 0x11 | 0x00 | 0x1110 | 0x0 | 0x11 | 0x0 | 0 | 0 | 0x10 |
1695 SDCFG = 0x0110 0011 0010 0010 0011 0011 1011 0010
1696 SDCFG = 0x6700486A;//0x63223332
1697
1698 SDRAM_TYPE = 3
1699 DDR_TERM = 3 (RZQ/4 = 1; RZQ/6=3)
1700 DDQS = 1
1701 DYN_ODT = 0
1702
1703 CWL = 3 (CWL5=0; CWL6=1; CWL7=2; CWL8=3)
1704 NM = 0 (64-bit=0, 32-bit=1, 16-bit=2)
1705 CL = 14 (CL5=2; CL6=4; CL7=6; CL8=8; CL9=10; CL10=12; CL11=14)
1706 IBANK = 3 (8bank)
1707 EBANK = 0 (0 - pad_cs_o_n[0] , 1 - pad_cs_o_n[1:0])
1708 PAGE_SIZE = 2 (1024page-size=2; 2048page-size=3)
1709*/
1710/* Start DDR3A EMIF Configuration */
1711//8. Configure the EMIF through the VBUSM interface.
1712//8.a. Program all EMIF MMRís.
1713 DDR3A_SDCFG = 0x62001462 ; //0x6200046A
1714
1715 DDR3A_SDTIM1 = 0x0A384C23;
1716 DDR3A_SDTIM2 = 0x00001CA5;
1717 DDR3A_SDTIM3 = 0x21ADFF32;
1718 DDR3A_SDTIM4 = 0x533F067F;
1719
1720 DDR3A_ZQCFG = 0xF0073200;
1721//8.b. Program reg_initref_dis=0 in the SDRAM Refresh Control Register (address offset 0x10).
1722 DDR3A_SDRFC = 0x00000C34;
1723
1724 GEL_TextOut("DDR3A initialization complete \n");
1725 /* End DDR3A EMIF Configuration */
1726
1727 }
1728
1729
1730/*----------------------------------------------------- DDR3A : DDR1066, 32bit--------------------------------------------------------------------------*/
1731ddr3A_32bit_DDR1066_setup()
1732{
1733
1734unsigned int multiplier = 15;
1735 unsigned int divider = 0;
1736 int temp;
1737 unsigned int OD_val = 6;
1738 KICK0 = 0x83E70B13;
1739 KICK1 = 0x95A4F1E0;
1740
1741
1742//1. Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010).
1743 do {
1744 read_val = DDR3A_PGSR0;
1745 } while ((read_val&0x00000001) != 0x00000001);
1746
1747//4. Clocks are enabled and frequency is stable---------------------------------------
1748//DDR3A PLL setup
1749 GEL_TextOut ( "DDR3 PLL (PLL2) Setup ... \n");
1750 //DDR3APLLCTL0 = DDR3APLLCTL0 & 0xFF7FFFFF;
1751 // Set ENSAT = 1
1752 DDR3APLLCTL1 |= 0x00000040;
1753 // Put the PLL in PLL Mode
1754 DDR3APLLCTL0 |= 0x00800000;
1755 // In PLL Controller, reset the PLL (bit 13 in DDR3APLLCTL1 register)
1756 DDR3APLLCTL1 |= 0x00002000;
1757 // Program the necessary multipliers/dividers and BW adjustments
1758 // Set the divider values
1759 DDR3APLLCTL0 &= ~(0x0000003F);
1760 DDR3APLLCTL0 |= (divider & 0x0000003F);
1761 /* Step 7: Programming OD[3:0] in the SECCTL register */
1762 DDR3APLLCTL0 &= OUTPUT_DIVIDE_MASK; // clear the OD bit field
1763 DDR3APLLCTL0 |= ~OUTPUT_DIVIDE_MASK & (OD_val - 1) << OUTPUT_DIVIDE_OFFSET; // set the OD[3:0] bit field of PLLD to OD_val
1764
1765 /* Set the Multipler values */
1766 DDR3APLLCTL0 &= ~(0x0007FFC0);
1767 DDR3APLLCTL0 |= ((multiplier << 6) & 0x0007FFC0 );
1768 temp = ((multiplier + 1) >> 1) - 1;
1769 DDR3APLLCTL0 &= ~(0xFF000000);
1770 DDR3APLLCTL0 |= ((temp << 24) & 0xFF000000);
1771 DDR3APLLCTL1 &= ~(0x0000000F);
1772 DDR3APLLCTL1 |= ((temp >> 8) & 0x0000000F);
1773 //In DDR3PLLCTL1, write PLLRST = 0 to bring PLL out of reset
1774 DDR3APLLCTL1 &= ~(0x00002000);
1775 // Put the PLL in PLL Mode
1776 DDR3APLLCTL0 &= ~(0x00800000); // ReSet the Bit 23
1777 GEL_TextOut( "DDR3 PLL Setup complete, DDR3A clock now running at 533MHz.\n" );
1778//DDR3A PLL setup complete ---------------------------------------
1779
1780/*------------------------- Start PHY Configuration -------------------------------*/
1781
1782 //DDR3A_PGCR1 = 0x0280C487;
1783
1784 //5.a Program FRQSEL in the PLL Control Register (address offset 0x018).
1785 DDR3A_PLLCR = 0xDC000; //Set FRQSEL=11, for ctl_clk between 166-275MHz
1786
1787 //5.b. Program WLSTEP=1, IODDRM=1, and ZCKSEL in the PHY General Configuration Register 1 (address offset 0x00C).
1788 DDR3A_PGCR1 |= (1 << 2); //WLSTEP = 1
1789
1790 DDR3A_PGCR1 &= ~(IODDRM_MASK);
1791 DDR3A_PGCR1 |= (( 1 << 7) & IODDRM_MASK);
1792
1793
1794 DDR3A_PGCR1 &= ~(ZCKSEL_MASK);
1795 DDR3A_PGCR1 |= (( 1 << 23) & ZCKSEL_MASK);
1796
1797
1798 //5.c. Program PHY Timing Parameters Register 0-4 (address offset 0x01C - 0x02C).
1799
1800 DDR3A_PTR0 = 0x42C21590;
1801
1802 DDR3A_PTR1 = 0xD05612C0;
1803
1804// Maintaining default values of Phy Timing Parameters Register 2 in PUB
1805
1806 DDR3A_PTR3 = 0x05B41104;//0x09041104;//0x18061A80;
1807
1808 DDR3A_PTR4 = 0x0855A068;//0x0AAE7100;
1809
1810//5.d. Program PDQ, MPRDQ, and BYTEMASK in the DRAM Configuration Register (address offset 0x044).
1811// All other fields must be left at their default values.
1812
1813 DDR3A_DCR &= ~(PDQ_MASK); //PDQ = 0
1814
1815 DDR3A_DCR &= ~(MPRDQ_MASK); //MPRDQ = 0
1816
1817 DDR3A_DCR &= ~(BYTEMASK_MASK);
1818 DDR3A_DCR |= (( 1 << 10) & BYTEMASK_MASK);
1819
1820
1821DDR3A_DCR &= ~(NOSRA_MASK);
1822DDR3A_DCR |= (( 1 << 27) & NOSRA_MASK);
1823
1824//DDR3A_DCR &= ~(UDIMM_MASK);
1825//DDR3A_DCR |= (( 1 << 29) & UDIMM_MASK);
1826
1827//RRMODE
1828 //DDR3A_DSGCR &= ~(RRMODE_MASK); //RR_MODE = 0
1829
1830//DDR3A_DSGCR &= ~(RRMODE_MASK); //RR_MODE = 1
1831 //DDR3A_DSGCR |= (( 1 << 18) & RRMODE_MASK);
1832
1833
1834//5.e. Program DRAM Timing Parameters Register 0-2 (address offset 0x048 - 0x050).
1835
1836 DDR3A_DTPR0 = 0x6D147764;//0x6D148844; //0x6D148844; 0x69137764 ---changed in rev 1.3
1837
1838 DDR3A_DTPR1 = 0x1282B200;//0x12845A00;
1839 DDR3A_DTPR2 = 0x50023600;
1840
1841//5.f. Program BL=0, CL, WR, and PD=1 in the Mode Register 0 (address offset 0x054).
1842 //All other fields must be left at their default values.
1843
1844DDR3A_MR0 = 0x00001830; //0x00001870;
1845
1846
1847//5.g. Program DIC, RTT, and TDQS in the Mode Register 1 (address offset 0x058).
1848 //All other fields must be left at their default values.
1849
1850DDR3A_MR1 = 0x00000006; //0x00000044; ---changed in rev 1.3
1851
1852
1853//---------------------------------------------------------------------------------------------------------
1854
1855//5.h. Program Mode Register 2 (address offset 0x05C).
1856 // Maintaining default values of Program Mode Register 2
1857 DDR3A_MR2 = 0x00000008; //18 ---changed in rev 1.3
1858
1859
1860//5.i. Program DTMPR=1, DTEXD, DTEXG, RANKEN=1 or 3, and RFSHDT=7 in the Data Training Configuration Register (address offset 0x068).
1861 //All other fields must be left at their default values.
1862 DDR3A_DTCR = 0x710035C7; //0x730035C7;
1863
1864//5.j. Program tREFPRD=(5*tREFI/ddr_clk_period) in the PHY General Configuration Register 2 (address offset 0x08C).
1865 //All other fields must be left at their default values.
1866
1867 DDR3A_PGCR2 = 0x00F05159; //NOBUB = 0, FXDLAT = 0
1868//DDR3A_PGCR2 = 0x00F83D09; //NOBUB = 0, FXDLAT = 1
1869
1870
1871//Set Impedence Register
1872DDR3A_ZQ0CR1 = 0x0000005D;
1873DDR3A_ZQ1CR1 = 0x0000005B;
1874DDR3A_ZQ2CR1 = 0x0000005B;
1875
1876
1877
1878//6. Re-trigger PHY initialization in DDR PHY through the VBUSP interface.
1879//6.a. Program 0x00000033 to the PHY Initialization Register (address offset 0x004) to re-trigger PLL, ZCAL, and DCAL initialization.
1880
1881 DDR3A_PIR = 0x00000033;
1882
1883//6.b. Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010).
1884 do {
1885 read_val = DDR3A_PGSR0;
1886 } while ((read_val&0x00000001) != 0x00000001);
1887
1888//---------------------------------------------------------------------------------------------------------
1889
1890
1891
1892// 7. Trigger DDR3 initialization and leveling/training in DDR PHY through the VBUSP interface.
1893// a. If using a 16-bit wide DDR interface, program DXEN=0 in the DATX8 2-7 General Configuration Registers (address offsets 0x240, 0x280, 0x2C0, 0x300, 0x340, and 0x380) to disable the leveling/training for the upper byte lanes.
1894// b. If using a 32-bit wide DDR interface, program DXEN=0 in the DATX8 4-7 General Configuration Registers (address offsets 0x2C0, 0x300, 0x340, and 0x380) to disable the leveling/training for the upper byte lanes.
1895// c. If ECC is not required, program DXEN=0 in the DATX8 8 General Configuration Register (address offset 0x3C0) to disable the leveling/training for the ECC byte lane.
1896// NOTE: Setup supports 64-bit by default, ECC enable by default.
1897
1898//7.d. Program 0x0000XF81 to the PHY Initialization Register (address offset 0x004) to trigger DDR3 initialization and leveling/training sequences
1899
1900 DDR3A_PIR = 0x00000F81; //WLADJ - ON
1901 //DDR3A_PIR = 0x00000781; //WLADJ - OFF
1902
1903
1904//---------------------------------------------------------------------------------------------------------
1905
1906//7.e. Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010).
1907 do {
1908 read_val = DDR3A_PGSR0;
1909 } while ((read_val&0x00000001) != 0x00000001);
1910
1911
1912 /* End PHY Configuration */
1913//---------------------------------------------------------------------------------------------------------
1914/* START EMIF INITIALIZATION
1915 ++++++++++++++++++SDCFG Register Calculation+++++++++++++++++++
1916 | 31 - 29 | 28 |27 - 25 | 24 | 23 - 22| 21 - 17 |
1917 |SDRAM_TYPE|Rsvd|DDR_TERM| DDQS | DYN_ODT| Rsvd |
1918 | 0x011 | 0 | 0x011 | 0x1 | 0x00 | 0x0 |
1919
1920 | 16-14 |13 - 12 | 11 - 8 | 7 |6 - 5 | 4 | 3 | 2 | 1 - 0 |
1921 | CWL | NM | CL | Rsvd |IBANK | Rsvd|EBANK| Rsvd|PAGE_SIZE|
1922 | 0x11 | 0x00 | 0x1110 | 0x0 | 0x11 | 0x0 | 0 | 0 | 0x10 |
1923 SDCFG = 0x0110 0011 0010 0010 0011 0011 1011 0010
1924 SDCFG = 0x6700486A;//0x63223332
1925
1926 SDRAM_TYPE = 3
1927 DDR_TERM = 3 (RZQ/4 = 1; RZQ/6=3)
1928 DDQS = 1
1929 DYN_ODT = 0
1930
1931 CWL = 3 (CWL5=0; CWL6=1; CWL7=2; CWL8=3)
1932 NM = 0 (64-bit=0, 32-bit=1, 16-bit=2)
1933 CL = 14 (CL5=2; CL6=4; CL7=6; CL8=8; CL9=10; CL10=12; CL11=14)
1934 IBANK = 3 (8bank)
1935 EBANK = 0 (0 - pad_cs_o_n[0] , 1 - pad_cs_o_n[1:0])
1936 PAGE_SIZE = 2 (1024page-size=2; 2048page-size=3)
1937*/
1938/* Start DDR3A EMIF Configuration */
1939//8. Configure the EMIF through the VBUSM interface.
1940//8.a. Program all EMIF MMRís.
1941 DDR3A_SDCFG = 0x62005662; //0x62005662;
1942 DDR3A_SDTIM1 = 0x0E4C6835; //0x0E4C6833;//0x0E4C6833;
1943 DDR3A_SDTIM2 = 0x00001CC6; //0x00001CE7;
1944 DDR3A_SDTIM3 = 0x3169FF32; //0x323DFF32;
1945 DDR3A_SDTIM4 = 0x533F055F; //0x533F08AF;
1946
1947 DDR3A_ZQCFG = 0x70073200;//0xF0073200;
1948//8.b. Program reg_initref_dis=0 in the SDRAM Refresh Control Register (address offset 0x10).
1949 DDR3A_SDRFC = 0x00001044;
1950
1951 GEL_TextOut("DDR3A initialization complete \n");
1952 /* End DDR3A EMIF Configuration */
1953
1954 }
1955
1956
1957
1958/*----------------------------------------------------- DDR3A : DDR1333, 32bit--------------------------------------------------------------------------*/
1959
1960ddr3A_32bit_DDR1333_setup()
1961{
1962unsigned int multiplier = 19;
1963 unsigned int divider = 0;
1964 int temp;
1965 unsigned int OD_val = 6;
1966 KICK0 = 0x83E70B13;
1967 KICK1 = 0x95A4F1E0;
1968
1969
1970//1. Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010).
1971 do {
1972 read_val = DDR3A_PGSR0;
1973 } while ((read_val&0x00000001) != 0x00000001);
1974
1975//4. Clocks are enabled and frequency is stable---------------------------------------
1976//DDR3A PLL setup
1977 GEL_TextOut ( "DDR3 PLL (PLL2) Setup ... \n");
1978 //DDR3APLLCTL0 = DDR3APLLCTL0 & 0xFF7FFFFF;
1979 // Set ENSAT = 1
1980 DDR3APLLCTL1 |= 0x00000040;
1981 // Put the PLL in PLL Mode
1982 DDR3APLLCTL0 |= 0x00800000;
1983 // In PLL Controller, reset the PLL (bit 13 in DDR3APLLCTL1 register)
1984 DDR3APLLCTL1 |= 0x00002000;
1985 // Program the necessary multipliers/dividers and BW adjustments
1986 // Set the divider values
1987 DDR3APLLCTL0 &= ~(0x0000003F);
1988 DDR3APLLCTL0 |= (divider & 0x0000003F);
1989 /* Step 7: Programming OD[3:0] in the SECCTL register */
1990 DDR3APLLCTL0 &= OUTPUT_DIVIDE_MASK; // clear the OD bit field
1991 DDR3APLLCTL0 |= ~OUTPUT_DIVIDE_MASK & (OD_val - 1) << OUTPUT_DIVIDE_OFFSET; // set the OD[3:0] bit field of PLLD to OD_val
1992
1993 /* Set the Multipler values */
1994 DDR3APLLCTL0 &= ~(0x0007FFC0);
1995 DDR3APLLCTL0 |= ((multiplier << 6) & 0x0007FFC0 );
1996 temp = ((multiplier + 1) >> 1) - 1;
1997 DDR3APLLCTL0 &= ~(0xFF000000);
1998 DDR3APLLCTL0 |= ((temp << 24) & 0xFF000000);
1999 DDR3APLLCTL1 &= ~(0x0000000F);
2000 DDR3APLLCTL1 |= ((temp >> 8) & 0x0000000F);
2001 //In DDR3PLLCTL1, write PLLRST = 0 to bring PLL out of reset
2002 DDR3APLLCTL1 &= ~(0x00002000);
2003 // Put the PLL in PLL Mode
2004 DDR3APLLCTL0 &= ~(0x00800000); // ReSet the Bit 23
2005 GEL_TextOut( "DDR3 PLL Setup complete, DDR3A clock now running at 666 MHz.\n" );
2006//DDR3A PLL setup complete ---------------------------------------
2007
2008/*------------------------- Start PHY Configuration -------------------------------*/
2009
2010 //DDR3A_PGCR1 = 0x0280C487;
2011
2012 //5.a Program FRQSEL in the PLL Control Register (address offset 0x018).
2013 DDR3A_PLLCR = 0x5C000; //Set FRQSEL=11, for ctl_clk between 166-275MHz
2014
2015 //5.b. Program WLSTEP=1, IODDRM=1, and ZCKSEL in the PHY General Configuration Register 1 (address offset 0x00C).
2016 DDR3A_PGCR1 |= (1 << 2); //WLSTEP = 1
2017
2018 DDR3A_PGCR1 &= ~(IODDRM_MASK);
2019 DDR3A_PGCR1 |= (( 1 << 7) & IODDRM_MASK);
2020
2021
2022 DDR3A_PGCR1 &= ~(ZCKSEL_MASK);
2023 DDR3A_PGCR1 |= (( 1 << 23) & ZCKSEL_MASK);
2024
2025
2026 //5.c. Program PHY Timing Parameters Register 0-4 (address offset 0x01C - 0x02C).
2027
2028 DDR3A_PTR0 = 0x42C21590;
2029
2030 DDR3A_PTR1 = 0xD05612C0;
2031
2032// Maintaining default values of Phy Timing Parameters Register 2 in PUB
2033
2034 DDR3A_PTR3 = 0x0B4515C2;//0x072515C2; //0x0B4515C2;//0x18061A80;
2035
2036 DDR3A_PTR4 = 0x0A6E08B4;//0x0AAE7100;
2037
2038//5.d. Program PDQ, MPRDQ, and BYTEMASK in the DRAM Configuration Register (address offset 0x044).
2039// All other fields must be left at their default values.
2040
2041 DDR3A_DCR &= ~(PDQ_MASK); //PDQ = 0
2042
2043 DDR3A_DCR &= ~(MPRDQ_MASK); //MPRDQ = 0
2044
2045 DDR3A_DCR &= ~(BYTEMASK_MASK);
2046 DDR3A_DCR |= (( 1 << 10) & BYTEMASK_MASK);
2047
2048
2049DDR3A_DCR &= ~(NOSRA_MASK);
2050 DDR3A_DCR |= (( 1 << 27) & NOSRA_MASK);
2051
2052
2053 //DDR3A_DCR &= ~(UDIMM_MASK);
2054 //DDR3A_DCR |= (( 1 << 29) & UDIMM_MASK);
2055
2056
2057//5.e. Program DRAM Timing Parameters Register 0-2 (address offset 0x048 - 0x050).
2058
2059 DDR3A_DTPR0 = 0x8558AA75;//0x85589975;//0x8558AA55;
2060 DDR3A_DTPR1 = 0x12857280;//0x12835A80;//0x12857280;
2061 DDR3A_DTPR2 = 0x5002C200;
2062
2063//5.f. Program BL=0, CL, WR, and PD=1 in the Mode Register 0 (address offset 0x054).
2064 //All other fields must be left at their default values.
2065
2066DDR3A_MR0 = 0x00001A60; //50
2067
2068
2069//5.g. Program DIC, RTT, and TDQS in the Mode Register 1 (address offset 0x058).
2070 //All other fields must be left at their default values.
2071
2072DDR3A_MR1 = 0x00000006;
2073
2074
2075//---------------------------------------------------------------------------------------------------------
2076
2077//5.h. Program Mode Register 2 (address offset 0x05C).
2078 // Maintaining default values of Program Mode Register 2
2079 DDR3A_MR2 = 0x00000010;
2080
2081//5.i. Program DTMPR=1, DTEXD, DTEXG, RANKEN=1 or 3, and RFSHDT=7 in the Data Training Configuration Register (address offset 0x068).
2082 //All other fields must be left at their default values.
2083 DDR3A_DTCR = 0x710035C7; //0x730035C7;
2084
2085//5.j. Program tREFPRD=(5*tREFI/ddr_clk_period) in the PHY General Configuration Register 2 (address offset 0x08C).
2086 //All other fields must be left at their default values.
2087
2088 DDR3A_PGCR2 = 0x00F065B8; //NOBUB = 0, FXDLAT = 0
2089//DDR3A_PGCR2 = 0x00F83D09; //NOBUB = 0, FXDLAT = 1
2090
2091//Set Impedence Register
2092DDR3A_ZQ0CR1 = 0x0000005D;
2093DDR3A_ZQ1CR1 = 0x0000005B;
2094DDR3A_ZQ2CR1 = 0x0000005B;
2095//DDR3A_ZQ3CR1 = 0x0000005D;
2096
2097//6. Re-trigger PHY initialization in DDR PHY through the VBUSP interface.
2098//6.a. Program 0x00000033 to the PHY Initialization Register (address offset 0x004) to re-trigger PLL, ZCAL, and DCAL initialization.
2099
2100 DDR3A_PIR = 0x00000033;
2101
2102//6.b. Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010).
2103 do {
2104 read_val = DDR3A_PGSR0;
2105 } while ((read_val&0x00000001) != 0x00000001);
2106
2107//---------------------------------------------------------------------------------------------------------
2108
2109
2110
2111// 7. Trigger DDR3 initialization and leveling/training in DDR PHY through the VBUSP interface.
2112// a. If using a 16-bit wide DDR interface, program DXEN=0 in the DATX8 2-7 General Configuration Registers (address offsets 0x240, 0x280, 0x2C0, 0x300, 0x340, and 0x380) to disable the leveling/training for the upper byte lanes.
2113// b. If using a 32-bit wide DDR interface, program DXEN=0 in the DATX8 4-7 General Configuration Registers (address offsets 0x2C0, 0x300, 0x340, and 0x380) to disable the leveling/training for the upper byte lanes.
2114// c. If ECC is not required, program DXEN=0 in the DATX8 8 General Configuration Register (address offset 0x3C0) to disable the leveling/training for the ECC byte lane.
2115// NOTE: Setup supports 64-bit by default, ECC enable by default.
2116
2117//7.d. Program 0x0000XF81 to the PHY Initialization Register (address offset 0x004) to trigger DDR3 initialization and leveling/training sequences
2118
2119 DDR3A_PIR = 0x0000FF81; //WLADJ - ON
2120 //DDR3A_PIR = 0x00000781; //WLADJ - OFF
2121
2122
2123//---------------------------------------------------------------------------------------------------------
2124
2125//7.e. Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010).
2126 do {
2127 read_val = DDR3A_PGSR0;
2128 } while ((read_val&0x00000001) != 0x00000001);
2129
2130
2131 /* End PHY Configuration */
2132//---------------------------------------------------------------------------------------------------------
2133/* START EMIF INITIALIZATION
2134 ++++++++++++++++++SDCFG Register Calculation+++++++++++++++++++
2135 | 31 - 29 | 28 |27 - 25 | 24 | 23 - 22| 21 - 17 |
2136 |SDRAM_TYPE|Rsvd|DDR_TERM| DDQS | DYN_ODT| Rsvd |
2137 | 0x011 | 0 | 0x011 | 0x1 | 0x00 | 0x0 |
2138
2139 | 16-14 |13 - 12 | 11 - 8 | 7 |6 - 5 | 4 | 3 | 2 | 1 - 0 |
2140 | CWL | NM | CL | Rsvd |IBANK | Rsvd|EBANK| Rsvd|PAGE_SIZE|
2141 | 0x11 | 0x00 | 0x1110 | 0x0 | 0x11 | 0x0 | 0 | 0 | 0x10 |
2142 SDCFG = 0x0110 0011 0010 0010 0011 0011 1011 0010
2143 SDCFG = 0x6700486A;//0x63223332
2144
2145 SDRAM_TYPE = 3
2146 DDR_TERM = 3 (RZQ/4 = 1; RZQ/6=3)
2147 DDQS = 1
2148 DYN_ODT = 0
2149
2150 CWL = 3 (CWL5=0; CWL6=1; CWL7=2; CWL8=3)
2151 NM = 0 (64-bit=0, 32-bit=1, 16-bit=2)
2152 CL = 14 (CL5=2; CL6=4; CL7=6; CL8=8; CL9=10; CL10=12; CL11=14)
2153 IBANK = 3 (8bank)
2154 EBANK = 0 (0 - pad_cs_o_n[0] , 1 - pad_cs_o_n[1:0])
2155 PAGE_SIZE = 2 (1024page-size=2; 2048page-size=3)
2156*/
2157/* Start DDR3A EMIF Configuration */
2158//8. Configure the EMIF through the VBUSM interface.
2159//8.a. Program all EMIF MMRís.
2160 DDR3A_SDCFG = 0x62009C62; // 9A62//0x62008C62 ;//0x6600CE62=single rank,0x6600CE6A=dual rank
2161
2162 DDR3A_SDTIM1 = 0x125C8044;
2163 DDR3A_SDTIM2 = 0x00001D29;
2164 DDR3A_SDTIM3 = 0x32CDFF43;
2165 DDR3A_SDTIM4 = 0x543F0ADF;
2166
2167 DDR3A_ZQCFG = 0x70073200;
2168//8.b. Program reg_initref_dis=0 in the SDRAM Refresh Control Register (address offset 0x10).
2169 DDR3A_SDRFC = 0x00001457;
2170
2171 GEL_TextOut("DDR3A initialization complete \n");
2172 /* End DDR3A EMIF Configuration */
2173}
2174
2175
2176/*----------------------------------------------------- DDR3B : DDR800, 64bit--------------------------------------------------------------------------*/
2177ddr3B_64bit_DDR800_setup()
2178{
2179unsigned int multiplier = 15;
2180 unsigned int divider = 0;
2181 int temp;
2182 unsigned int OD_val = 8;
2183 KICK0 = 0x83E70B13;
2184 KICK1 = 0x95A4F1E0;
2185
2186
2187//1. Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010).
2188 do {
2189 read_val = DDR3B_PGSR0;
2190 } while ((read_val&0x00000001) != 0x00000001);
2191
2192//4. Clocks are enabled and frequency is stable---------------------------------------
2193//DDR3B PLL setup
2194 GEL_TextOut ( "DDR3 PLL (PLL2) Setup ... \n");
2195 //DDR3BPLLCTL0 = DDR3BPLLCTL0 & 0xFF7FFFFF;
2196 // Set ENSAT = 1
2197 DDR3BPLLCTL1 |= 0x00000040;
2198 // Put the PLL in PLL Mode
2199 DDR3BPLLCTL0 |= 0x00800000;
2200 // In PLL Controller, reset the PLL (bit 13 in DDR3BPLLCTL1 register)
2201 DDR3BPLLCTL1 |= 0x00002000;
2202 // Program the necessary multipliers/dividers and BW adjustments
2203 // Set the divider values
2204 DDR3BPLLCTL0 &= ~(0x0000003F);
2205 DDR3BPLLCTL0 |= (divider & 0x0000003F);
2206 /* Step 7: Programming OD[3:0] in the SECCTL register */
2207 DDR3BPLLCTL0 &= OUTPUT_DIVIDE_MASK; // clear the OD bit field
2208 DDR3BPLLCTL0 |= ~OUTPUT_DIVIDE_MASK & (OD_val - 1) << OUTPUT_DIVIDE_OFFSET; // set the OD[3:0] bit field of PLLD to OD_val
2209
2210 /* Set the Multipler values */
2211 DDR3BPLLCTL0 &= ~(0x0007FFC0);
2212 DDR3BPLLCTL0 |= ((multiplier << 6) & 0x0007FFC0 );
2213 temp = ((multiplier + 1) >> 1) - 1;
2214 DDR3BPLLCTL0 &= ~(0xFF000000);
2215 DDR3BPLLCTL0 |= ((temp << 24) & 0xFF000000);
2216 DDR3BPLLCTL1 &= ~(0x0000000F);
2217 DDR3BPLLCTL1 |= ((temp >> 8) & 0x0000000F);
2218 //In DDR3PLLCTL1, write PLLRST = 0 to bring PLL out of reset
2219 DDR3BPLLCTL1 &= ~(0x00002000);
2220 // Put the PLL in PLL Mode
2221 DDR3BPLLCTL0 &= ~(0x00800000); // ReSet the Bit 23
2222 GEL_TextOut( "DDR3 PLL Setup complete, DDR3B clock now running at 400MHz.\n" );
2223//DDR3B PLL setup complete ---------------------------------------
2224
2225/*------------------------- Start PHY Configuration -------------------------------*/
2226
2227 //DDR3B_PGCR1 = 0x0280C487;
2228
2229 //5.a Program FRQSEL in the PLL Control Register (address offset 0x018).
2230 DDR3B_PLLCR = 0xDC000; //Set FRQSEL=11, for ctl_clk between 166-275MHz
2231
2232 //5.b. Program WLSTEP=1, IODDRM=1, and ZCKSEL in the PHY General Configuration Register 1 (address offset 0x00C).
2233 DDR3B_PGCR1 |= (1 << 2); //WLSTEP = 1
2234
2235 DDR3B_PGCR1 &= ~(IODDRM_MASK);
2236 DDR3B_PGCR1 |= (( 1 << 7) & IODDRM_MASK);
2237
2238
2239 DDR3B_PGCR1 &= ~(ZCKSEL_MASK);
2240 DDR3B_PGCR1 |= (( 1 << 23) & ZCKSEL_MASK);
2241
2242 //RRMODE
2243 //DDR3B_DSGCR &= ~(RRMODE_MASK); //RR_MODE = 0
2244
2245//DDR3B_DSGCR &= ~(RRMODE_MASK); //RR_MODE = 1
2246 //DDR3B_DSGCR |= (( 1 << 18) & RRMODE_MASK);
2247
2248
2249 //5.c. Program PHY Timing Parameters Register 0-4 (address offset 0x01C - 0x02C).
2250
2251 DDR3B_PTR0 = 0x42C21590;
2252
2253 DDR3B_PTR1 = 0xD05612C0;
2254
2255// Maintaining default values of Phy Timing Parameters Register 2 in PUB
2256
2257 DDR3B_PTR3 = 0x06C30D40;//0x18061A80;
2258
2259 DDR3B_PTR4 = 0x6413880;//0x0AAE7100;
2260
2261//5.d. Program PDQ, MPRDQ, and BYTEMASK in the DRAM Configuration Register (address offset 0x044).
2262// All other fields must be left at their default values.
2263
2264 DDR3B_DCR &= ~(PDQ_MASK); //PDQ = 0
2265 DDR3B_DCR &= ~(MPRDQ_MASK); //MPRDQ = 0
2266
2267 DDR3B_DCR &= ~(BYTEMASK_MASK);
2268 DDR3B_DCR |= (( 1 << 10) & BYTEMASK_MASK);
2269
2270
2271DDR3B_DCR &= ~(NOSRA_MASK);
2272DDR3B_DCR |= (( 1 << 27) & NOSRA_MASK);
2273
2274
2275 //DDR3B_DCR &= ~(UDIMM_MASK);
2276 //DDR3B_DCR |= (( 1 << 29) & UDIMM_MASK);
2277
2278
2279//5.e. Program DRAM Timing Parameters Register 0-2 (address offset 0x048 - 0x050).
2280
2281 DDR3B_DTPR0 = 0x50CE6644;
2282 DDR3B_DTPR1 = 0x12834180;
2283 DDR3B_DTPR2 = 0x50022A00;
2284
2285//5.f. Program BL=0, CL, WR, and PD=1 in the Mode Register 0 (address offset 0x054).
2286 //All other fields must be left at their default values.
2287
2288DDR3B_MR0 = 0x00001420;
2289
2290
2291//5.g. Program DIC, RTT, and TDQS in the Mode Register 1 (address offset 0x058).
2292 //All other fields must be left at their default values.
2293
2294DDR3B_MR1 = 0x00000006;
2295
2296
2297//---------------------------------------------------------------------------------------------------------
2298
2299//5.h. Program Mode Register 2 (address offset 0x05C).
2300 // Maintaining default values of Program Mode Register 2
2301 // DDR3B_MR2 = 0x00000018;
2302
2303//5.i. Program DTMPR=1, DTEXD, DTEXG, RANKEN=1 or 3, and RFSHDT=7 in the Data Training Configuration Register (address offset 0x068).
2304 //All other fields must be left at their default values.
2305 DDR3B_DTCR = 0x710035C7; //0x710035C7;
2306
2307//5.j. Program tREFPRD=(5*tREFI/ddr_clk_period) in the PHY General Configuration Register 2 (address offset 0x08C).
2308 //All other fields must be left at their default values.
2309
2310 DDR3B_PGCR2 = 0x00F03D09; //NOBUB = 0, FXDLAT = 0
2311//DDR3B_PGCR2 = 0x00F83D09; //NOBUB = 0, FXDLAT = 1
2312
2313//Set Impedence Register
2314DDR3B_ZQ0CR1 = 0x0000005D;
2315DDR3B_ZQ1CR1 = 0x0000005B;
2316DDR3B_ZQ2CR1 = 0x0000005B;
2317
2318
2319//6. Re-trigger PHY initialization in DDR PHY through the VBUSP interface.
2320//6.a. Program 0x00000033 to the PHY Initialization Register (address offset 0x004) to re-trigger PLL, ZCAL, and DCAL initialization.
2321
2322 DDR3B_PIR = 0x00000033;
2323
2324//6.b. Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010).
2325 do {
2326 read_val = DDR3B_PGSR0;
2327 } while ((read_val&0x00000001) != 0x00000001);
2328
2329//---------------------------------------------------------------------------------------------------------
2330
2331
2332
2333// 7. Trigger DDR3 initialization and leveling/training in DDR PHY through the VBUSP interface.
2334// a. If using a 16-bit wide DDR interface, program DXEN=0 in the DATX8 2-7 General Configuration Registers (address offsets 0x240, 0x280, 0x2C0, 0x300, 0x340, and 0x380) to disable the leveling/training for the upper byte lanes.
2335// b. If using a 32-bit wide DDR interface, program DXEN=0 in the DATX8 4-7 General Configuration Registers (address offsets 0x2C0, 0x300, 0x340, and 0x380) to disable the leveling/training for the upper byte lanes.
2336// c. If ECC is not required, program DXEN=0 in the DATX8 8 General Configuration Register (address offset 0x3C0) to disable the leveling/training for the ECC byte lane.
2337// NOTE: Setup supports 64-bit by default, ECC enable by default.
2338
2339//7.d. Program 0x0000XF81 to the PHY Initialization Register (address offset 0x004) to trigger DDR3 initialization and leveling/training sequences
2340
2341 DDR3B_PIR = 0x00000F81; //WLADJ - ON
2342 //DDR3B_PIR = 0x00000781; //WLADJ - OFF
2343
2344//---------------------------------------------------------------------------------------------------------
2345
2346//7.e. Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010).
2347 do {
2348 read_val = DDR3B_PGSR0;
2349 } while ((read_val&0x00000001) != 0x00000001);
2350
2351
2352 /* End PHY Configuration */
2353//---------------------------------------------------------------------------------------------------------
2354/* START EMIF INITIALIZATION
2355 ++++++++++++++++++SDCFG Register Calculation+++++++++++++++++++
2356 | 31 - 29 | 28 |27 - 25 | 24 | 23 - 22| 21 - 17 |
2357 |SDRAM_TYPE|Rsvd|DDR_TERM| DDQS | DYN_ODT| Rsvd |
2358 | 0x011 | 0 | 0x011 | 0x1 | 0x00 | 0x0 |
2359
2360 | 16-14 |13 - 12 | 11 - 8 | 7 |6 - 5 | 4 | 3 | 2 | 1 - 0 |
2361 | CWL | NM | CL | Rsvd |IBANK | Rsvd|EBANK| Rsvd|PAGE_SIZE|
2362 | 0x11 | 0x00 | 0x1110 | 0x0 | 0x11 | 0x0 | 0 | 0 | 0x10 |
2363 SDCFG = 0x0110 0011 0010 0010 0011 0011 1011 0010
2364 SDCFG = 0x6700486A;//0x63223332
2365
2366 SDRAM_TYPE = 3
2367 DDR_TERM = 3 (RZQ/4 = 1; RZQ/6=3)
2368 DDQS = 1
2369 DYN_ODT = 0
2370
2371 CWL = 3 (CWL5=0; CWL6=1; CWL7=2; CWL8=3)
2372 NM = 0 (64-bit=0, 32-bit=1, 16-bit=2)
2373 CL = 14 (CL5=2; CL6=4; CL7=6; CL8=8; CL9=10; CL10=12; CL11=14)
2374 IBANK = 3 (8bank)
2375 EBANK = 0 (0 - pad_cs_o_n[0] , 1 - pad_cs_o_n[1:0])
2376 PAGE_SIZE = 2 (1024page-size=2; 2048page-size=3)
2377*/
2378/* Start DDR3B EMIF Configuration */
2379//8. Configure the EMIF through the VBUSM interface.
2380//8.a. Program all EMIF MMRís.
2381 DDR3B_SDCFG = 0x62000462 ;
2382
2383 DDR3B_SDTIM1 = 0x0A384C23;
2384 DDR3B_SDTIM2 = 0x00001CA5;
2385 DDR3B_SDTIM3 = 0x21ADFF32;
2386 DDR3B_SDTIM4 = 0x533F067F;
2387
2388 DDR3B_ZQCFG = 0xF0073200;
2389//8.b. Program reg_initref_dis=0 in the SDRAM Refresh Control Register (address offset 0x10).
2390 DDR3B_SDRFC = 0x00000C34;
2391
2392 GEL_TextOut("DDR3B initialization complete \n");
2393 /* End DDR3B EMIF Configuration */
2394
2395}
2396
2397/*----------------------------------------------------- DDR3B : DDR1066, 64bit--------------------------------------------------------------------------*/
2398ddr3B_64bit_DDR1066_setup()
2399{
2400unsigned int multiplier = 15;
2401 unsigned int divider = 0;
2402 int temp;
2403 unsigned int OD_val = 6;
2404 KICK0 = 0x83E70B13;
2405 KICK1 = 0x95A4F1E0;
2406
2407
2408//1. Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010).
2409 do {
2410 read_val = DDR3B_PGSR0;
2411 } while ((read_val&0x00000001) != 0x00000001);
2412
2413//4. Clocks are enabled and frequency is stable---------------------------------------
2414//DDR3B PLL setup
2415 GEL_TextOut ( "DDR3 PLL (PLL2) Setup ... \n");
2416 //DDR3BPLLCTL0 = DDR3BPLLCTL0 & 0xFF7FFFFF;
2417 // Set ENSAT = 1
2418 DDR3BPLLCTL1 |= 0x00000040;
2419 // Put the PLL in PLL Mode
2420 DDR3BPLLCTL0 |= 0x00800000;
2421 // In PLL Controller, reset the PLL (bit 13 in DDR3BPLLCTL1 register)
2422 DDR3BPLLCTL1 |= 0x00002000;
2423 // Program the necessary multipliers/dividers and BW adjustments
2424 // Set the divider values
2425 DDR3BPLLCTL0 &= ~(0x0000003F);
2426 DDR3BPLLCTL0 |= (divider & 0x0000003F);
2427 /* Step 7: Programming OD[3:0] in the SECCTL register */
2428 DDR3BPLLCTL0 &= OUTPUT_DIVIDE_MASK; // clear the OD bit field
2429 DDR3BPLLCTL0 |= ~OUTPUT_DIVIDE_MASK & (OD_val - 1) << OUTPUT_DIVIDE_OFFSET; // set the OD[3:0] bit field of PLLD to OD_val
2430
2431 /* Set the Multipler values */
2432 DDR3BPLLCTL0 &= ~(0x0007FFC0);
2433 DDR3BPLLCTL0 |= ((multiplier << 6) & 0x0007FFC0 );
2434 temp = ((multiplier + 1) >> 1) - 1;
2435 DDR3BPLLCTL0 &= ~(0xFF000000);
2436 DDR3BPLLCTL0 |= ((temp << 24) & 0xFF000000);
2437 DDR3BPLLCTL1 &= ~(0x0000000F);
2438 DDR3BPLLCTL1 |= ((temp >> 8) & 0x0000000F);
2439 //In DDR3PLLCTL1, write PLLRST = 0 to bring PLL out of reset
2440 DDR3BPLLCTL1 &= ~(0x00002000);
2441 // Put the PLL in PLL Mode
2442 DDR3BPLLCTL0 &= ~(0x00800000); // ReSet the Bit 23
2443 GEL_TextOut( "DDR3 PLL Setup complete, DDR3B clock now running at 533MHz.\n" );
2444//DDR3B PLL setup complete ---------------------------------------
2445
2446/*------------------------- Start PHY Configuration -------------------------------*/
2447
2448 //DDR3B_PGCR1 = 0x0280C487;
2449
2450 //5.a Program FRQSEL in the PLL Control Register (address offset 0x018).
2451 DDR3B_PLLCR = 0xDC000; //Set FRQSEL=11, for ctl_clk between 166-275MHz
2452
2453 //5.b. Program WLSTEP=1, IODDRM=1, and ZCKSEL in the PHY General Configuration Register 1 (address offset 0x00C).
2454 DDR3B_PGCR1 |= (1 << 2); //WLSTEP = 1
2455
2456 DDR3B_PGCR1 &= ~(IODDRM_MASK);
2457 DDR3B_PGCR1 |= (( 1 << 7) & IODDRM_MASK);
2458
2459
2460 DDR3B_PGCR1 &= ~(ZCKSEL_MASK);
2461 DDR3B_PGCR1 |= (( 1 << 23) & ZCKSEL_MASK);
2462
2463
2464 //5.c. Program PHY Timing Parameters Register 0-4 (address offset 0x01C - 0x02C).
2465
2466 DDR3B_PTR0 = 0x42C21590;
2467
2468 DDR3B_PTR1 = 0xD05612C0;
2469
2470// Maintaining default values of Phy Timing Parameters Register 2 in PUB
2471
2472 DDR3B_PTR3 = 0x09041104;//0x18061A80;
2473
2474 DDR3B_PTR4 = 0x0855A068;//0x0AAE7100;
2475
2476//5.d. Program PDQ, MPRDQ, and BYTEMASK in the DRAM Configuration Register (address offset 0x044).
2477// All other fields must be left at their default values.
2478
2479 DDR3B_DCR &= ~(PDQ_MASK); //PDQ = 0
2480
2481 DDR3B_DCR &= ~(MPRDQ_MASK); //MPRDQ = 0
2482
2483 DDR3B_DCR &= ~(BYTEMASK_MASK);
2484 DDR3B_DCR |= (( 1 << 10) & BYTEMASK_MASK);
2485
2486
2487DDR3B_DCR &= ~(NOSRA_MASK);
2488DDR3B_DCR |= (( 1 << 27) & NOSRA_MASK);
2489
2490//DDR3B_DCR &= ~(UDIMM_MASK);
2491//DDR3B_DCR |= (( 1 << 29) & UDIMM_MASK);
2492
2493
2494//5.e. Program DRAM Timing Parameters Register 0-2 (address offset 0x048 - 0x050).
2495
2496 DDR3B_DTPR0 = 0x6D148844;
2497 DDR3B_DTPR1 = 0x12845A00;
2498 DDR3B_DTPR2 = 0x50023600;
2499
2500//5.f. Program BL=0, CL, WR, and PD=1 in the Mode Register 0 (address offset 0x054).
2501 //All other fields must be left at their default values.
2502
2503DDR3B_MR0 = 0x00001830; //0x00001870
2504
2505
2506//5.g. Program DIC, RTT, and TDQS in the Mode Register 1 (address offset 0x058).
2507 //All other fields must be left at their default values.
2508
2509DDR3B_MR1 = 0x00000006;
2510
2511
2512//---------------------------------------------------------------------------------------------------------
2513
2514//5.h. Program Mode Register 2 (address offset 0x05C).
2515 // Maintaining default values of Program Mode Register 2
2516 DDR3B_MR2 = 0x00000008;
2517
2518//5.i. Program DTMPR=1, DTEXD, DTEXG, RANKEN=1 or 3, and RFSHDT=7 in the Data Training Configuration Register (address offset 0x068).
2519 //All other fields must be left at their default values.
2520 DDR3B_DTCR = 0x710035C7; //0x730035C7;
2521
2522//5.j. Program tREFPRD=(5*tREFI/ddr_clk_period) in the PHY General Configuration Register 2 (address offset 0x08C).
2523 //All other fields must be left at their default values.
2524
2525 DDR3B_PGCR2 = 0x00F05159; //NOBUB = 0, FXDLAT = 0
2526//DDR3B_PGCR2 = 0x00F83D09; //NOBUB = 0, FXDLAT = 1
2527
2528//Set Impedence Register
2529DDR3B_ZQ0CR1 = 0x0000005D;
2530DDR3B_ZQ1CR1 = 0x0000005B;
2531DDR3B_ZQ2CR1 = 0x0000005B;
2532
2533
2534//6. Re-trigger PHY initialization in DDR PHY through the VBUSP interface.
2535//6.a. Program 0x00000033 to the PHY Initialization Register (address offset 0x004) to re-trigger PLL, ZCAL, and DCAL initialization.
2536
2537 DDR3B_PIR = 0x00000033;
2538
2539//6.b. Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010).
2540 do {
2541 read_val = DDR3B_PGSR0;
2542 } while ((read_val&0x00000001) != 0x00000001);
2543
2544//---------------------------------------------------------------------------------------------------------
2545
2546
2547
2548// 7. Trigger DDR3 initialization and leveling/training in DDR PHY through the VBUSP interface.
2549// a. If using a 16-bit wide DDR interface, program DXEN=0 in the DATX8 2-7 General Configuration Registers (address offsets 0x240, 0x280, 0x2C0, 0x300, 0x340, and 0x380) to disable the leveling/training for the upper byte lanes.
2550// b. If using a 32-bit wide DDR interface, program DXEN=0 in the DATX8 4-7 General Configuration Registers (address offsets 0x2C0, 0x300, 0x340, and 0x380) to disable the leveling/training for the upper byte lanes.
2551// c. If ECC is not required, program DXEN=0 in the DATX8 8 General Configuration Register (address offset 0x3C0) to disable the leveling/training for the ECC byte lane.
2552// NOTE: Setup supports 64-bit by default, ECC enable by default.
2553
2554//7.d. Program 0x0000XF81 to the PHY Initialization Register (address offset 0x004) to trigger DDR3 initialization and leveling/training sequences
2555
2556 DDR3B_PIR = 0x00000F81; //WLADJ - ON
2557 //DDR3B_PIR = 0x00000781; //WLADJ - OFF
2558
2559
2560//---------------------------------------------------------------------------------------------------------
2561
2562//7.e. Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010).
2563 do {
2564 read_val = DDR3B_PGSR0;
2565 } while ((read_val&0x00000001) != 0x00000001);
2566
2567
2568 /* End PHY Configuration */
2569//---------------------------------------------------------------------------------------------------------
2570/* START EMIF INITIALIZATION
2571 ++++++++++++++++++SDCFG Register Calculation+++++++++++++++++++
2572 | 31 - 29 | 28 |27 - 25 | 24 | 23 - 22| 21 - 17 |
2573 |SDRAM_TYPE|Rsvd|DDR_TERM| DDQS | DYN_ODT| Rsvd |
2574 | 0x011 | 0 | 0x011 | 0x1 | 0x00 | 0x0 |
2575
2576 | 16-14 |13 - 12 | 11 - 8 | 7 |6 - 5 | 4 | 3 | 2 | 1 - 0 |
2577 | CWL | NM | CL | Rsvd |IBANK | Rsvd|EBANK| Rsvd|PAGE_SIZE|
2578 | 0x11 | 0x00 | 0x1110 | 0x0 | 0x11 | 0x0 | 0 | 0 | 0x10 |
2579 SDCFG = 0x0110 0011 0010 0010 0011 0011 1011 0010
2580 SDCFG = 0x6700486A;//0x63223332
2581
2582 SDRAM_TYPE = 3
2583 DDR_TERM = 3 (RZQ/4 = 1; RZQ/6=3)
2584 DDQS = 1
2585 DYN_ODT = 0
2586
2587 CWL = 3 (CWL5=0; CWL6=1; CWL7=2; CWL8=3)
2588 NM = 0 (64-bit=0, 32-bit=1, 16-bit=2)
2589 CL = 14 (CL5=2; CL6=4; CL7=6; CL8=8; CL9=10; CL10=12; CL11=14)
2590 IBANK = 3 (8bank)
2591 EBANK = 0 (0 - pad_cs_o_n[0] , 1 - pad_cs_o_n[1:0])
2592 PAGE_SIZE = 2 (1024page-size=2; 2048page-size=3)
2593*/
2594/* Start DDR3B EMIF Configuration */
2595//8. Configure the EMIF through the VBUSM interface.
2596//8.a. Program all EMIF MMRís.
2597 DDR3B_SDCFG = 0x62004662; //0x6600CE62=single rank, 0x6600CE6A=dual rank
2598 DDR3B_SDTIM1 = 0x0E4C6833;
2599 DDR3B_SDTIM2 = 0x00001CE7;
2600 DDR3B_SDTIM3 = 0x323DFF32;
2601 DDR3B_SDTIM4 = 0x533F08AF;
2602
2603 DDR3B_ZQCFG = 0xF0073200;
2604//8.b. Program reg_initref_dis=0 in the SDRAM Refresh Control Register (address offset 0x10).
2605 DDR3B_SDRFC = 0x00001044;
2606
2607 GEL_TextOut("DDR3B initialization complete \n");
2608 /* End DDR3B EMIF Configuration */
2609}
2610
2611/*----------------------------------------------------- DDR3B : DDR1333, 64bit--------------------------------------------------------------------------*/
2612ddr3B_64bit_DDR1333_setup()
2613{
2614unsigned int multiplier = 19;
2615 unsigned int divider = 0;
2616 int temp;
2617 unsigned int OD_val = 6;
2618 KICK0 = 0x83E70B13;
2619 KICK1 = 0x95A4F1E0;
2620
2621
2622//1. Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010).
2623 do {
2624 read_val = DDR3B_PGSR0;
2625 } while ((read_val&0x00000001) != 0x00000001);
2626
2627//4. Clocks are enabled and frequency is stable---------------------------------------
2628//DDR3B PLL setup
2629 GEL_TextOut ( "DDR3 PLL (PLL2) Setup ... \n");
2630 //DDR3BPLLCTL0 = DDR3BPLLCTL0 & 0xFF7FFFFF;
2631 // Set ENSAT = 1
2632 DDR3BPLLCTL1 |= 0x00000040;
2633 // Put the PLL in PLL Mode
2634 DDR3BPLLCTL0 |= 0x00800000;
2635 // In PLL Controller, reset the PLL (bit 13 in DDR3BPLLCTL1 register)
2636 DDR3BPLLCTL1 |= 0x00002000;
2637 // Program the necessary multipliers/dividers and BW adjustments
2638 // Set the divider values
2639 DDR3BPLLCTL0 &= ~(0x0000003F);
2640 DDR3BPLLCTL0 |= (divider & 0x0000003F);
2641 /* Step 7: Programming OD[3:0] in the SECCTL register */
2642 DDR3BPLLCTL0 &= OUTPUT_DIVIDE_MASK; // clear the OD bit field
2643 DDR3BPLLCTL0 |= ~OUTPUT_DIVIDE_MASK & (OD_val - 1) << OUTPUT_DIVIDE_OFFSET; // set the OD[3:0] bit field of PLLD to OD_val
2644
2645 /* Set the Multipler values */
2646 DDR3BPLLCTL0 &= ~(0x0007FFC0);
2647 DDR3BPLLCTL0 |= ((multiplier << 6) & 0x0007FFC0 );
2648 temp = ((multiplier + 1) >> 1) - 1;
2649 DDR3BPLLCTL0 &= ~(0xFF000000);
2650 DDR3BPLLCTL0 |= ((temp << 24) & 0xFF000000);
2651 DDR3BPLLCTL1 &= ~(0x0000000F);
2652 DDR3BPLLCTL1 |= ((temp >> 8) & 0x0000000F);
2653 //In DDR3PLLCTL1, write PLLRST = 0 to bring PLL out of reset
2654 DDR3BPLLCTL1 &= ~(0x00002000);
2655 // Put the PLL in PLL Mode
2656 DDR3BPLLCTL0 &= ~(0x00800000); // ReSet the Bit 23
2657 GEL_TextOut( "DDR3 PLL Setup complete, DDR3B clock now running at 666 MHz.\n" );
2658//DDR3B PLL setup complete ---------------------------------------
2659
2660/*------------------------- Start PHY Configuration -------------------------------*/
2661
2662 //DDR3B_PGCR1 = 0x0280C487;
2663
2664 //5.a Program FRQSEL in the PLL Control Register (address offset 0x018).
2665 DDR3B_PLLCR = 0x5C000; //Set FRQSEL=11, for ctl_clk between 166-275MHz
2666
2667 //5.b. Program WLSTEP=1, IODDRM=1, and ZCKSEL in the PHY General Configuration Register 1 (address offset 0x00C).
2668 DDR3B_PGCR1 |= (1 << 2); //WLSTEP = 1
2669
2670 DDR3B_PGCR1 &= ~(IODDRM_MASK);
2671 DDR3B_PGCR1 |= (( 1 << 7) & IODDRM_MASK);
2672
2673
2674 DDR3B_PGCR1 &= ~(ZCKSEL_MASK);
2675 DDR3B_PGCR1 |= (( 1 << 23) & ZCKSEL_MASK);
2676
2677
2678 //5.c. Program PHY Timing Parameters Register 0-4 (address offset 0x01C - 0x02C).
2679
2680 DDR3B_PTR0 = 0x42C21590;
2681
2682 DDR3B_PTR1 = 0xD05612C0;
2683
2684// Maintaining default values of Phy Timing Parameters Register 2 in PUB
2685
2686 DDR3B_PTR3 = 0x0B4515C2;//0x18061A80;
2687
2688 DDR3B_PTR4 = 0x0A6E08B4;//0x0AAE7100;
2689
2690//5.d. Program PDQ, MPRDQ, and BYTEMASK in the DRAM Configuration Register (address offset 0x044).
2691// All other fields must be left at their default values.
2692
2693 DDR3B_DCR &= ~(PDQ_MASK); //PDQ = 0
2694
2695 DDR3B_DCR &= ~(MPRDQ_MASK); //MPRDQ = 0
2696
2697 DDR3B_DCR &= ~(BYTEMASK_MASK);
2698 DDR3B_DCR |= (( 1 << 10) & BYTEMASK_MASK);
2699
2700
2701 DDR3B_DCR &= ~(NOSRA_MASK);
2702 DDR3B_DCR |= (( 1 << 27) & NOSRA_MASK);
2703
2704
2705 // DDR3B_DCR &= ~(UDIMM_MASK);
2706 // DDR3B_DCR |= (( 1 << 29) & UDIMM_MASK);
2707
2708
2709//5.e. Program DRAM Timing Parameters Register 0-2 (address offset 0x048 - 0x050).
2710
2711 DDR3B_DTPR0 = 0x8558AA55;
2712 DDR3B_DTPR1 = 0x12857280;
2713 DDR3B_DTPR2 = 0x5002C200;
2714
2715//5.f. Program BL=0, CL, WR, and PD=1 in the Mode Register 0 (address offset 0x054).
2716 //All other fields must be left at their default values.
2717
2718DDR3B_MR0 = 0x00001A60;
2719
2720
2721//5.g. Program DIC, RTT, and TDQS in the Mode Register 1 (address offset 0x058).
2722 //All other fields must be left at their default values.
2723
2724DDR3B_MR1 = 0x00000006;
2725
2726
2727//---------------------------------------------------------------------------------------------------------
2728
2729//5.h. Program Mode Register 2 (address offset 0x05C).
2730 // Maintaining default values of Program Mode Register 2
2731 DDR3B_MR2 = 0x00000010;
2732
2733//5.i. Program DTMPR=1, DTEXD, DTEXG, RANKEN=1 or 3, and RFSHDT=7 in the Data Training Configuration Register (address offset 0x068).
2734 //All other fields must be left at their default values.
2735 DDR3B_DTCR = 0x710035C7; //0x730035C7;
2736
2737//5.j. Program tREFPRD=(5*tREFI/ddr_clk_period) in the PHY General Configuration Register 2 (address offset 0x08C).
2738 //All other fields must be left at their default values.
2739
2740 DDR3B_PGCR2 = 0x00F065B8; //NOBUB = 0, FXDLAT = 0
2741//DDR3B_PGCR2 = 0x00F83D09; //NOBUB = 0, FXDLAT = 1
2742
2743//Set Impedence Register
2744DDR3B_ZQ0CR1 = 0x0000005D;
2745DDR3B_ZQ1CR1 = 0x0000005B;
2746DDR3B_ZQ2CR1 = 0x0000005B;
2747//DDR3B_ZQ3CR1 = 0x0000005D;
2748
2749//6. Re-trigger PHY initialization in DDR PHY through the VBUSP interface.
2750//6.a. Program 0x00000033 to the PHY Initialization Register (address offset 0x004) to re-trigger PLL, ZCAL, and DCAL initialization.
2751
2752 DDR3B_PIR = 0x00000033;
2753
2754//6.b. Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010).
2755 do {
2756 read_val = DDR3B_PGSR0;
2757 } while ((read_val&0x00000001) != 0x00000001);
2758
2759//---------------------------------------------------------------------------------------------------------
2760
2761
2762
2763// 7. Trigger DDR3 initialization and leveling/training in DDR PHY through the VBUSP interface.
2764// a. If using a 16-bit wide DDR interface, program DXEN=0 in the DATX8 2-7 General Configuration Registers (address offsets 0x240, 0x280, 0x2C0, 0x300, 0x340, and 0x380) to disable the leveling/training for the upper byte lanes.
2765// b. If using a 32-bit wide DDR interface, program DXEN=0 in the DATX8 4-7 General Configuration Registers (address offsets 0x2C0, 0x300, 0x340, and 0x380) to disable the leveling/training for the upper byte lanes.
2766// c. If ECC is not required, program DXEN=0 in the DATX8 8 General Configuration Register (address offset 0x3C0) to disable the leveling/training for the ECC byte lane.
2767// NOTE: Setup supports 64-bit by default, ECC enable by default.
2768
2769//7.d. Program 0x0000XF81 to the PHY Initialization Register (address offset 0x004) to trigger DDR3 initialization and leveling/training sequences
2770
2771 DDR3B_PIR = 0x0000FF81; //WLADJ - ON
2772 //DDR3B_PIR = 0x00000781; //WLADJ - OFF
2773
2774
2775//---------------------------------------------------------------------------------------------------------
2776
2777//7.e. Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010).
2778 do {
2779 read_val = DDR3B_PGSR0;
2780 } while ((read_val&0x00000001) != 0x00000001);
2781
2782
2783 /* End PHY Configuration */
2784//---------------------------------------------------------------------------------------------------------
2785/* START EMIF INITIALIZATION
2786 ++++++++++++++++++SDCFG Register Calculation+++++++++++++++++++
2787 | 31 - 29 | 28 |27 - 25 | 24 | 23 - 22| 21 - 17 |
2788 |SDRAM_TYPE|Rsvd|DDR_TERM| DDQS | DYN_ODT| Rsvd |
2789 | 0x011 | 0 | 0x011 | 0x1 | 0x00 | 0x0 |
2790
2791 | 16-14 |13 - 12 | 11 - 8 | 7 |6 - 5 | 4 | 3 | 2 | 1 - 0 |
2792 | CWL | NM | CL | Rsvd |IBANK | Rsvd|EBANK| Rsvd|PAGE_SIZE|
2793 | 0x11 | 0x00 | 0x1110 | 0x0 | 0x11 | 0x0 | 0 | 0 | 0x10 |
2794 SDCFG = 0x0110 0011 0010 0010 0011 0011 1011 0010
2795 SDCFG = 0x6700486A;//0x63223332
2796
2797 SDRAM_TYPE = 3
2798 DDR_TERM = 3 (RZQ/4 = 1; RZQ/6=3)
2799 DDQS = 1
2800 DYN_ODT = 0
2801
2802 CWL = 3 (CWL5=0; CWL6=1; CWL7=2; CWL8=3)
2803 NM = 0 (64-bit=0, 32-bit=1, 16-bit=2)
2804 CL = 14 (CL5=2; CL6=4; CL7=6; CL8=8; CL9=10; CL10=12; CL11=14)
2805 IBANK = 3 (8bank)
2806 EBANK = 0 (0 - pad_cs_o_n[0] , 1 - pad_cs_o_n[1:0])
2807 PAGE_SIZE = 2 (1024page-size=2; 2048page-size=3)
2808*/
2809/* Start DDR3B EMIF Configuration */
2810//8. Configure the EMIF through the VBUSM interface.
2811//8.a. Program all EMIF MMRís.
2812 DDR3B_SDCFG = 0x62008C62 ;//0x6600CE62=single rank,0x6600CE6A=dual rank
2813
2814 DDR3B_SDTIM1 = 0x125C8044;
2815 DDR3B_SDTIM2 = 0x00001D29;
2816 DDR3B_SDTIM3 = 0x32CDFF43;
2817 DDR3B_SDTIM4 = 0x543F0ADF;
2818
2819 DDR3B_ZQCFG = 0xF0073200;
2820//8.b. Program reg_initref_dis=0 in the SDRAM Refresh Control Register (address offset 0x10).
2821 DDR3B_SDRFC = 0x00001457;
2822
2823 GEL_TextOut("DDR3B initialization complete \n");
2824 /* End DDR3B EMIF Configuration */
2825
2826}
2827
2828/*----------------------------------------------------- DDR3B : DDR1600, 64bit--------------------------------------------------------------------------*/
2829ddr3B_64bit_DDR1600_setup()
2830{
2831unsigned int multiplier = 15;
2832 unsigned int divider = 0;
2833 int temp;
2834 unsigned int OD_val = 4;
2835 KICK0 = 0x83E70B13;
2836 KICK1 = 0x95A4F1E0;
2837
2838
2839//1. Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010).
2840 do {
2841 read_val = DDR3B_PGSR0;
2842 } while ((read_val&0x00000001) != 0x00000001);
2843
2844//4. Clocks are enabled and frequency is stable---------------------------------------
2845//DDR3B PLL setup
2846 GEL_TextOut ( "DDR3 PLL Setup ... \n");
2847 //DDR3BPLLCTL0 = DDR3BPLLCTL0 & 0xFF7FFFFF;
2848 // Set ENSAT = 1
2849 DDR3BPLLCTL1 |= 0x00000040;
2850 // Put the PLL in PLL Mode
2851 DDR3BPLLCTL0 |= 0x00800000;
2852 // In PLL Controller, reset the PLL (bit 13 in DDR3BPLLCTL1 register)
2853 DDR3BPLLCTL1 |= 0x00002000;
2854 // Program the necessary multipliers/dividers and BW adjustments
2855 // Set the divider values
2856 DDR3BPLLCTL0 &= ~(0x0000003F);
2857 DDR3BPLLCTL0 |= (divider & 0x0000003F);
2858 /* Step 7: Programming OD[3:0] in the SECCTL register */
2859 DDR3BPLLCTL0 &= OUTPUT_DIVIDE_MASK; // clear the OD bit field
2860 DDR3BPLLCTL0 |= ~OUTPUT_DIVIDE_MASK & (OD_val - 1) << OUTPUT_DIVIDE_OFFSET; // set the OD[3:0] bit field of PLLD to OD_val
2861
2862 //DDR3BPLLCTL0 &= ~(0x00780000);
2863 //DDR3BPLLCTL0 |= ((OD_val << 19)& 0x00780000);
2864
2865 /* Set the Multipler values */
2866 DDR3BPLLCTL0 &= ~(0x0007FFC0);
2867 DDR3BPLLCTL0 |= ((multiplier << 6) & 0x0007FFC0 );
2868 temp = ((multiplier + 1) >> 1) - 1;
2869 DDR3BPLLCTL0 &= ~(0xFF000000);
2870 DDR3BPLLCTL0 |= ((temp << 24) & 0xFF000000);
2871 DDR3BPLLCTL1 &= ~(0x0000000F);
2872 DDR3BPLLCTL1 |= ((temp >> 8) & 0x0000000F);
2873 //In DDR3PLLCTL1, write PLLRST = 0 to bring PLL out of reset
2874 DDR3BPLLCTL1 &= ~(0x00002000);
2875 // Put the PLL in PLL Mode
2876 DDR3BPLLCTL0 &= ~(0x00800000); // ReSet the Bit 23
2877 GEL_TextOut( "DDR3 PLL Setup complete, DDR3B clock now running at 800MHz.\n" );
2878//DDR3B PLL setup complete ---------------------------------------
2879
2880/*------------------------- Start PHY Configuration -------------------------------*/
2881
2882 //DDR3B_PGCR1 = 0x0280C487;
2883
2884 //5.a Program FRQSEL in the PLL Control Register (address offset 0x018).
2885 DDR3B_PLLCR = 0x1C000; //Set FRQSEL=11, for ctl_clk between 166-275MHz
2886
2887 //5.b. Program WLSTEP=1, IODDRM=1, and ZCKSEL in the PHY General Configuration Register 1 (address offset 0x00C).
2888 DDR3B_PGCR1 |= (1 << 2); //WLSTEP = 1
2889
2890 DDR3B_PGCR1 &= ~(IODDRM_MASK);
2891 DDR3B_PGCR1 |= (( 1 << 7) & IODDRM_MASK);
2892
2893
2894 DDR3B_PGCR1 &= ~(ZCKSEL_MASK);
2895 DDR3B_PGCR1 |= (( 1 << 23) & ZCKSEL_MASK);
2896
2897
2898 //5.c. Program PHY Timing Parameters Register 0-4 (address offset 0x01C - 0x02C).
2899
2900 DDR3B_PTR0 = 0x42C21590;
2901
2902 DDR3B_PTR1 = 0xD05612C0;
2903
2904// Maintaining default values of Phy Timing Parameters Register 2 in PUB
2905
2906 DDR3B_PTR3 = 0x0D861A80;//
2907
2908 DDR3B_PTR4 = 0x0C827100;
2909
2910//5.d. Program PDQ, MPRDQ, and BYTEMASK in the DRAM Configuration Register (address offset 0x044).
2911// All other fields must be left at their default values.
2912
2913 DDR3B_DCR &= ~(PDQ_MASK); //PDQ = 0
2914
2915 DDR3B_DCR &= ~(MPRDQ_MASK); //MPRDQ = 0
2916
2917 DDR3B_DCR &= ~(BYTEMASK_MASK);
2918 DDR3B_DCR |= (( 1 << 10) & BYTEMASK_MASK);
2919
2920
2921 DDR3B_DCR &= ~(NOSRA_MASK);
2922 DDR3B_DCR |= (( 1 << 27) & NOSRA_MASK);
2923
2924
2925 //DDR3B_DCR &= ~(UDIMM_MASK);
2926 //DDR3B_DCR |= (( 1 << 29) & UDIMM_MASK);
2927
2928
2929//5.e. Program DRAM Timing Parameters Register 0-2 (address offset 0x048 - 0x050).
2930
2931 DDR3B_DTPR0 = 0xA19DBB66;
2932 DDR3B_DTPR1 = 0x12868300;
2933 DDR3B_DTPR2 = 0x50035200;
2934
2935//5.f. Program BL=0, CL, WR, and PD=1 in the Mode Register 0 (address offset 0x054).
2936 //All other fields must be left at their default values.
2937
2938DDR3B_MR0 = 0x00001C70; //-CL - 11, CWL -8
2939
2940
2941//5.g. Program DIC, RTT, and TDQS in the Mode Register 1 (address offset 0x058).
2942 //All other fields must be left at their default values.
2943
2944DDR3B_MR1 = 0x00000006;
2945
2946
2947//---------------------------------------------------------------------------------------------------------
2948
2949//5.h. Program Mode Register 2 (address offset 0x05C).
2950 // Maintaining default values of Program Mode Register 2
2951 // DDR3B_MR2 = 0x00000018;
2952
2953 DDR3B_MR2 = 0x00000018;
2954
2955//5.i. Program DTMPR=1, DTEXD, DTEXG, RANKEN=1 or 3, and RFSHDT=7 in the Data Training Configuration Register (address offset 0x068).
2956 //All other fields must be left at their default values.
2957 DDR3B_DTCR = 0x710035C7; //0x730035C7;
2958
2959//5.j. Program tREFPRD=(5*tREFI/ddr_clk_period) in the PHY General Configuration Register 2 (address offset 0x08C).
2960 //All other fields must be left at their default values.
2961
2962 DDR3B_PGCR2 = 0x00F07A12; //NOBUB = 0, FXDLAT = 0
2963//DDR3B_PGCR2 = 0x00F83D09; //NOBUB = 0, FXDLAT = 1
2964
2965//Set Impedence Register
2966DDR3B_ZQ0CR1 = 0x0000005D;
2967DDR3B_ZQ1CR1 = 0x0000005B;
2968DDR3B_ZQ2CR1 = 0x0000005B;
2969//DDR3B_ZQ3CR1 = 0x0000005D;
2970
2971//DDR3B_DATX8_8 &= ~(ECC_MASK);
2972
2973//6. Re-trigger PHY initialization in DDR PHY through the VBUSP interface.
2974//6.a. Program 0x00000033 to the PHY Initialization Register (address offset 0x004) to re-trigger PLL, ZCAL, and DCAL initialization.
2975
2976 DDR3B_PIR = 0x00000033;
2977
2978//6.b. Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010).
2979 do {
2980 read_val = DDR3B_PGSR0;
2981 } while ((read_val&0x00000001) != 0x00000001);
2982
2983//---------------------------------------------------------------------------------------------------------
2984
2985
2986
2987// 7. Trigger DDR3 initialization and leveling/training in DDR PHY through the VBUSP interface.
2988// a. If using a 16-bit wide DDR interface, program DXEN=0 in the DATX8 2-7 General Configuration Registers (address offsets 0x240, 0x280, 0x2C0, 0x300, 0x340, and 0x380) to disable the leveling/training for the upper byte lanes.
2989// b. If using a 32-bit wide DDR interface, program DXEN=0 in the DATX8 4-7 General Configuration Registers (address offsets 0x2C0, 0x300, 0x340, and 0x380) to disable the leveling/training for the upper byte lanes.
2990// c. If ECC is not required, program DXEN=0 in the DATX8 8 General Configuration Register (address offset 0x3C0) to disable the leveling/training for the ECC byte lane.
2991// NOTE: Setup supports 64-bit by default, ECC enable by default.
2992
2993//7.d. Program 0x0000XF81 to the PHY Initialization Register (address offset 0x004) to trigger DDR3 initialization and leveling/training sequences
2994
2995 DDR3B_PIR = 0x0000FF81; //WLADJ - ON
2996 //DDR3B_PIR = 0x00000781; //WLADJ - OFF
2997
2998
2999//---------------------------------------------------------------------------------------------------------
3000
3001//7.e. Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010).
3002 do {
3003 read_val = DDR3B_PGSR0;
3004 } while ((read_val&0x00000001) != 0x00000001);
3005
3006
3007 /* End PHY Configuration */
3008//---------------------------------------------------------------------------------------------------------
3009/* START EMIF INITIALIZATION
3010 ++++++++++++++++++SDCFG Register Calculation+++++++++++++++++++
3011 | 31 - 29 | 28 |27 - 25 | 24 | 23 - 22| 21 - 17 |
3012 |SDRAM_TYPE|Rsvd|DDR_TERM| DDQS | DYN_ODT| Rsvd |
3013 | 0x011 | 0 | 0x011 | 0x1 | 0x00 | 0x0 |
3014
3015 | 16-14 |13 - 12 | 11 - 8 | 7 |6 - 5 | 4 | 3 | 2 | 1 - 0 |
3016 | CWL | NM | CL | Rsvd |IBANK | Rsvd|EBANK| Rsvd|PAGE_SIZE|
3017 | 0x11 | 0x00 | 0x1110 | 0x0 | 0x11 | 0x0 | 0 | 0 | 0x10 |
3018 SDCFG = 0x0110 0011 0010 0010 0011 0011 1011 0010
3019 SDCFG = 0x6700486A;//0x63223332
3020
3021 SDRAM_TYPE = 3
3022 DDR_TERM = 3 (RZQ/4 = 1; RZQ/6=3)
3023 DDQS = 1
3024 DYN_ODT = 0
3025
3026 CWL = 3 (CWL5=0; CWL6=1; CWL7=2; CWL8=3)
3027 NM = 0 (64-bit=0, 32-bit=1, 16-bit=2)
3028 CL = 14 (CL5=2; CL6=4; CL7=6; CL8=8; CL9=10; CL10=12; CL11=14)
3029 IBANK = 3 (8bank)
3030 EBANK = 0 (0 - pad_cs_o_n[0] , 1 - pad_cs_o_n[1:0])
3031 PAGE_SIZE = 2 (1024page-size=2; 2048page-size=3)
3032*/
3033/* Start DDR3B EMIF Configuration */
3034//8. Configure the EMIF through the VBUSM interface.
3035//8.a. Program all EMIF MMRís.
3036 DDR3B_SDCFG = 0x6200CE62 ;//0x66004862=single rank, 0x6600486A=dual rank CL- 11
3037
3038 DDR3B_SDTIM1 = 0x16709C55;
3039 DDR3B_SDTIM2 = 0x00001D4A;
3040 DDR3B_SDTIM3 = 0x435DFF54;
3041 DDR3B_SDTIM4 = 0x553F0CFF;
3042
3043 DDR3B_ZQCFG = 0xF0073200;
3044//8.b. Program reg_initref_dis=0 in the SDRAM Refresh Control Register (address offset 0x10).
3045 DDR3B_SDRFC = 0x00001869;
3046
3047 GEL_TextOut("DDR3B initialization complete \n");
3048 /* End DDR3B EMIF Configuration */
3049
3050}
3051
3052
3053
3054
3055/*--------------------------------------------------------------*/
3056/* TCI66x MENU */
3057/*--------------------------------------------------------------*/
3058
3059menuitem "TCI66x Functions";
3060
3061/****************************************************************************
3062 *
3063 * NAME
3064 * Global_Default_Setup
3065 *
3066 * PURPOSE:
3067 * Setup almost everything ready for a new debug session:
3068 * DSP modules and EVM board modules.
3069 *
3070 * USAGE
3071 * This routine can be called as:
3072 *
3073 * Global_Default_Setup()
3074 *
3075 * RETURN VALUE
3076 * NONE
3077 *
3078 * REFERENCE
3079 *
3080 ****************************************************************************/
3081hotmenu Global_Default_Setup()
3082{
3083 GEL_TextOut( "Global Default Setup...\n" );
3084 Global_Default_Setup_Silent();
3085 GEL_TextOut( "Global Default Setup... Done.\n" );
3086}
3087
3088hotmenu Reset()
3089{
3090 GEL_Reset();
3091}
3092
3093hotmenu InitXMC()
3094{
3095 xmc_setup();
3096}
3097
3098hotmenu CORE_PLL_INIT_122_88MHZ_to_614_4MHz()
3099{
3100 Set_Pll1(1); // call Set_Pll1 with index = 1 -> 122.88 MHz to 614.4 MHz operation
3101}
3102
3103hotmenu CORE_PLL_INIT_122_88MHZ_to_737_28MHz()
3104{
3105 Set_Pll1(2); // call Set_Pll1 with index = 2 -> 122.88 MHz to 737.28 MHz operation
3106}
3107
3108hotmenu CORE_PLL_INIT_122_88MHZ_to_983_04MHz()
3109{
3110 Set_Pll1(3); // call Set_Pll1 with index = 3 -> 122.88 MHz to 983.04 MHz operation
3111}
3112
3113hotmenu CORE_PLL_INIT_122_88MHZ_to_1_2GHz()
3114{
3115 Set_Pll1(4); // call Set_Pll1 with index = 4 -> 122.88 MHz to 1.2 GHz operation
3116}
3117
3118
3119hotmenu CORE_PLL_INIT_122_88MHZ_to_1_3Gz()
3120{
3121 Set_Pll1(5); // call Set_Pll1 with index = 4 -> 122.88 MHz to 1.2 GHz operation
3122}
3123
3124hotmenu TETRIS_POWERUP_AND_PLL_INIT_100MHZ_to_1000MHz()
3125{
3126 Set_Tetris_Pll(1); // 100 MHz to 1.0 GHz operation
3127}
3128
3129hotmenu TETRIS_POWERUP_AND_PLL_INIT_100MHZ_to_1400MHz()
3130{
3131 Set_Tetris_Pll(2); // 100 MHz to 1.4 GHz operation
3132}
3133
3134hotmenu TETRIS_POWERUP_AND_PLL_INIT_175MHZ_to_1400MHz()
3135{
3136 Set_Tetris_Pll(3); // 175 MHz to 1.4 GHz operation
3137}
3138
3139
3140hotmenu PA_PLL_COnfig()
3141{
3142 PaPllConfig();
3143}
3144
3145hotmenu InitDDR3A_32bit_DDR800()
3146{
3147 ddr3A_32bit_DDR800_setup();
3148}
3149
3150hotmenu InitDDR3A_32bit_DDR1066()
3151{
3152 ddr3A_32bit_DDR1066_setup();
3153}
3154
3155hotmenu InitDDR3A_32bit_DDR1333()
3156{
3157 ddr3A_32bit_DDR1333_setup();
3158}
3159
3160
3161hotmenu InitDDR3B_64bit_DDR800()
3162{
3163 ddr3B_64bit_DDR800_setup();
3164}
3165
3166
3167hotmenu InitDDR3B_64bit_DDR1066()
3168{
3169 ddr3B_64bit_DDR1066_setup();
3170}
3171
3172hotmenu InitDDR3B_64bit_DDR1333()
3173{
3174 ddr3B_64bit_DDR1333_setup();
3175}
3176
3177hotmenu InitDDR3B_64bit_DDR1600()
3178{
3179 ddr3B_64bit_DDR1600_setup();
3180}
3181
3182
3183///* Function to enable CORE PLL observation clock for PLL output *///
3184hotmenu ENABLE_CORE_PLL_OBSCLK()
3185{
3186 /* Unlock Chip Level Registers */
3187 KICK0 = KICK0_UNLOCK;
3188 KICK1 = KICK1_UNLOCK;
3189
3190 /* set bit 1 to enable power to the CORE PLL observation clock, clear bit 0 to view the CORE PLL observation (output) clock */
3191 OBSCLKCTL |= (1 << 1); /* set bit 1 to enable power to the observation clock */
3192 OBSCLKCTL &= ~(1 << 0); /* clear bit 0 to view the CORE PLL clock */
3193
3194 /* Lock Chip Level Registers */
3195 KICK0 = 0x00000000;
3196 KICK1 = 0x00000000;
3197
3198 GEL_TextOut("CORE PLL observation clock enabled and configured to show CORE PLL output\n");
3199}
3200
3201/* Function to enable DDR PLL observation clock for PLL output */
3202hotmenu ENABLE_DDR_PLL_OBSCLK ()
3203{
3204 /* Unlock Chip Level Registers */
3205 KICK0 = KICK0_UNLOCK;
3206 KICK1 = KICK1_UNLOCK;
3207
3208 /* set bit 1 to enable power to the CORE PLL observation clock, clear bit 0 to view the CORE PLL observation (output) clock */
3209 OBSCLKCTL |= (1 << 3); /* set bit 3 to enable power to the observation clock */
3210 OBSCLKCTL |= (1 << 2); /* set bit 2 to view the DDR PLL clock */
3211
3212 /* Lock Chip Level Registers */
3213 //KICK0 = 0x00000000;
3214 // KICK1 = 0x00000000;
3215
3216 GEL_TextOut("DDR PLL observation clock enabled and configured to show DDR PLL output\n");
3217}
3218
3219hotmenu ENABLE_ARM_PLL_OBSCLK ()
3220{
3221 /* Unlock Chip Level Registers */
3222 KICK0 = KICK0_UNLOCK;
3223 KICK1 = KICK1_UNLOCK;
3224
3225 /* set bit 1 to enable power to the CORE PLL observation clock, clear bit 0 to view the CORE PLL observation (output) clock */
3226 //OBSCLKCTL |= (1 << 3); /* set bit 3 to enable power to the observation clock */
3227 OBSCLKCTL |= (1 << 6); /* set bit 2 to view the DDR PLL clock */
3228
3229 /* Lock Chip Level Registers */
3230 KICK0 = 0x00000000;
3231 KICK1 = 0x00000000;
3232
3233 GEL_TextOut("DDR PLL observation clock enabled and configured to show DDR PLL output\n");
3234}
3235
3236hotmenu ENABLE_PA_PLL_OBSCLK ()
3237{
3238 /* Unlock Chip Level Registers */
3239 KICK0 = KICK0_UNLOCK;
3240 KICK1 = KICK1_UNLOCK;
3241
3242 /* set bit 1 to enable power to the CORE PLL observation clock, clear bit 0 to view the CORE PLL observation (output) clock */
3243 OBSCLKCTL |= (1 << 4); /* set bit 3 to enable power to the observation clock */
3244 OBSCLKCTL |= (1 << 5); /* set bit 2 to view the DDR PLL clock */
3245
3246 /* Lock Chip Level Registers */
3247 KICK0 = 0x00000000;
3248 KICK1 = 0x00000000;
3249
3250 GEL_TextOut("DDR PLL observation clock enabled and configured to show DDR PLL output\n");
3251}
3252
3253hotmenu ddr3A_write_read_test()
3254{
3255//int data_set[4];
3256 //= {0xAAAAAAAA, 0x55555555, 0xFFFFFFFF, 0x00000000};
3257 unsigned int write_data = 0xAAAAAAAA;
3258 unsigned int read_data = 0x0;
3259 unsigned int errors = 0;
3260 int dw;
3261 unsigned int i, mem_start, mem_size, mem_location;
3262 mem_start = DDR3A_BASE_ADDRESS + (DNUM * 0x01000000);
3263 mem_size = 0x100;
3264 for(dw=0;dw<4;dw++)
3265 {
3266 if (dw == 0) write_data = 0xAAAAAAAA;
3267 if (dw == 1) write_data = 0x55555555;
3268 if (dw == 2) write_data = 0xFFFFFFFF;
3269 if (dw == 3) write_data = 0x00000000;
3270 mem_location = mem_start;
3271 GEL_TextOut( "Memory Test Write Core: %d, Mem Start: 0x%x, Mem Size: 0x%x, value: 0x%x ...\n",,2,,,DNUM,mem_start,mem_size,write_data);
3272 for(i=0;i<mem_size;i++)
3273 {
3274 *( unsigned int* )(mem_location) = write_data;
3275 mem_location += 4;
3276 }
3277 mem_location = mem_start;
3278 GEL_TextOut( "Memory Test Read Core: %d, Mem Start: 0x%x, Mem Size: 0x%x ...\n",,2,,,DNUM,mem_start,mem_size);
3279 for (i=0;i<mem_size;i++)
3280 {
3281 read_data = *( unsigned int* )(mem_location);
3282 if (read_data != write_data)
3283 {
3284 GEL_TextOut("DDR3 Data Error: DSP Core: %d, Mem Addr: 0x%x, read: 0x%x, expected: 0x%x \n",,2,,,DNUM,(DDR3_BASE_ADDRESS + (i * 4)),read_data,write_data);
3285 errors++;
3286 }
3287 mem_location += 4;
3288 }
3289 if (errors == 0)
3290 {
3291 GEL_TextOut( "Memory Test Done, no errors found.\n" );
3292 }
3293 else
3294 {
3295 GEL_TextOut("Memory Test Done, %d errors were encounterd. \n",,2,,,errors);
3296 }
3297 }
3298 GEL_TextOut( "All Memory Test Completed on core: %d with %d errors.\n",,2,,,DNUM,errors);
3299
3300}
3301
3302
3303hotmenu ddr3B_write_read_test()
3304{
3305//int data_set[4];
3306 //= {0xAAAAAAAA, 0x55555555, 0xFFFFFFFF, 0x00000000};
3307 unsigned int write_data = 0xAAAAAAAA;
3308 unsigned int read_data = 0x0;
3309 unsigned int errors = 0;
3310 int dw;
3311 unsigned int i, mem_start, mem_size, mem_location;
3312 mem_start = DDR3B_BASE_ADDRESS + (DNUM * 0x01000000);
3313 mem_size = 0x100;
3314 for(dw=0;dw<4;dw++)
3315 {
3316 if (dw == 0) write_data = 0xAAAAAAAA;
3317 if (dw == 1) write_data = 0x55555555;
3318 if (dw == 2) write_data = 0xFFFFFFFF;
3319 if (dw == 3) write_data = 0x00000000;
3320 mem_location = mem_start;
3321 GEL_TextOut( "Memory Test Write Core: %d, Mem Start: 0x%x, Mem Size: 0x%x, value: 0x%x ...\n",,2,,,DNUM,mem_start,mem_size,write_data);
3322 for(i=0;i<mem_size;i++)
3323 {
3324 *( unsigned int* )(mem_location) = write_data;
3325 mem_location += 4;
3326 }
3327 mem_location = mem_start;
3328 GEL_TextOut( "Memory Test Read Core: %d, Mem Start: 0x%x, Mem Size: 0x%x ...\n",,2,,,DNUM,mem_start,mem_size);
3329 for (i=0;i<mem_size;i++)
3330 {
3331 read_data = *( unsigned int* )(mem_location);
3332 if (read_data != write_data)
3333 {
3334 GEL_TextOut("DDR3 Data Error: DSP Core: %d, Mem Addr: 0x%x, read: 0x%x, expected: 0x%x \n",,2,,,DNUM,(DDR3_BASE_ADDRESS + (i * 4)),read_data,write_data);
3335 errors++;
3336 }
3337 mem_location += 4;
3338 }
3339 if (errors == 0)
3340 {
3341 GEL_TextOut( "Memory Test Done, no errors found.\n" );
3342 }
3343 else
3344 {
3345 GEL_TextOut("Memory Test Done, %d errors were encounterd. \n",,2,,,errors);
3346 }
3347 }
3348 GEL_TextOut( "All Memory Test Completed on core: %d with %d errors.\n",,2,,,DNUM,errors);
3349}
3350
3351menuitem "DSP CLOCK Estimation";
3352
3353#define TIMER_TSC (1) // The timer used for polling TSCH/TSCL
3354#define TIMER_TSC_POLL_PERIOD (10) // Every 10 seconds
3355unsigned int gPollPeriod = TIMER_TISC_POLL_PERIOD;
3356unsigned int gTSCL = 0;
3357unsigned int gTSCH = 0; // Global var for holding previous read of TSCL/H
3358unsigned int gNumberPoll=0; // Number of pulling */
3359unsigned int gLoopCount=0;
3360
3361
3362
3363hotmenu dspEnableTsc()
3364{
3365 //GEL_TextOut( "dspEnableTsc - write a value to TSCL to enable it\n" );
3366 if( GEL_IsHalted() ) {
3367 TSCL = 0; // A write to TSCL will enable TSC (timestamp counter)
3368 GEL_Run();
3369 } else {
3370 GEL_Halt();
3371 TSCL = 0;
3372 GEL_Run();
3373 }
3374}
3375
3376
3377hotmenu dspDumpTsc()
3378{
3379 unsigned int tscl, tsch;
3380 tscl = TSCL; /* note: need to read TSCL first */
3381 tsch = TSCH;
3382 GEL_TextOut( "dspEnableTsc - TSCH=%x, TSCL=%x\n",,,,, tscl, tsch );
3383}
3384
3385
3386dspPollTsc()
3387{
3388 unsigned int tscl, tsch;
3389 unsigned long long tsc1, tsc2;
3390
3391 if( gLoopCount <= gNumberPoll) {
3392 //GEL_EnableRealtime();
3393 GEL_Halt();
3394 tscl = TSCL; /* The read time can be considered as variations */
3395 tsch = TSCH; /* The read won't cause variation */
3396 //GEL_DisableRealtime();
3397 GEL_Run();
3398 tsc2 = (((unsigned long long) tsch)<<32) + tscl;
3399 tsc1 = (((unsigned long long)gTSCH)<<32) + gTSCL;
3400 gTSCL = tscl;
3401 gTSCH = tsch;
3402
3403 //tsc1 = (tsc2-tsc1)/TIMER_TSC_POLL_PERIOD;
3404 tsc1 = (tsc2-tsc1)/gPollPeriod;
3405
3406 GEL_TextOut( "dspPollTsc - [TSCH,TSCL] = [%x, %x], freq=%dhz, i=%d\n",,,,,
3407 gTSCH, gTSCL, (tsc1), gLoopCount);
3408 }
3409
3410 if( gLoopCount>=gNumberPoll ) {
3411 dspCancelTscTimer();
3412 } else {
3413 gLoopCount++;
3414 }
3415}
3416
3417
3418//
3419// To cancel the Timer - TIMER_TSC, after using it. Otherwise, it will continue running.
3420//
3421hotmenu dspCancelTscTimer()
3422{
3423 GEL_TextOut( "dspCancelTscTimer\n");
3424 GEL_CancelTimer( TIMER_TSC );
3425}
3426
3427
3428//
3429// To poll the DSP clock.
3430//
3431dialog dspPollDSPClockFreq(
3432 pollPeriod "Polling period (sec) - the longer, the more accurate!",
3433 numberOfPoll "Number of Polls" )
3434{
3435 gPollPeriod = pollPeriod;
3436
3437 GEL_TextOut( "dspPollDSPClockFreq with - pollPeriod=%dsec, numberOfPoll=%d\n"
3438 ,,,,, gPollPeriod, numberOfPoll);
3439
3440 gNumberPoll = numberOfPoll-1;
3441 gLoopCount = 0;
3442 dspEnableTsc();
3443
3444 // Get the initial value of TSC
3445 //GEL_EnableRealtime();
3446 GEL_Halt();
3447 gTSCL = TSCL; /* The read time can be considered as variations */
3448 gTSCH = TSCH; /* The read won't cause variation */
3449 //GEL_DisableRealtime();
3450 GEL_Run();
3451
3452 GEL_SetTimer( gPollPeriod*1000, TIMER_TSC, "dspPollTsc()");
3453
3454}