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author | Sam Nelson | 2014-08-07 13:19:18 -0500 |
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committer | Sam Nelson | 2014-08-07 13:19:18 -0500 |
commit | 81f652b34db78a58f4831d1c61e998b40e79e1bf (patch) | |
tree | 7b9d79cc9cc239e6b039ba7cb675035865042519 /program_evm/gel | |
parent | e312b0e9f7d69305f899137dd30214cfb3fd48b1 (diff) | |
download | mcsdk-tools-81f652b34db78a58f4831d1c61e998b40e79e1bf.tar.gz mcsdk-tools-81f652b34db78a58f4831d1c61e998b40e79e1bf.tar.xz mcsdk-tools-81f652b34db78a58f4831d1c61e998b40e79e1bf.zip |
program_evm: update k2e gel dos2unix conversionDEV.MCSDK-03.01.00.03B
- Updated README
Signed-off-by: Sam Nelson <sam.nelson@ti.com>
Diffstat (limited to 'program_evm/gel')
-rw-r--r-- | program_evm/gel/README.txt | 14 | ||||
-rw-r--r-- | program_evm/gel/evmk2e.gel | 5820 |
2 files changed, 2915 insertions, 2919 deletions
diff --git a/program_evm/gel/README.txt b/program_evm/gel/README.txt index decdcb0..c284998 100644 --- a/program_evm/gel/README.txt +++ b/program_evm/gel/README.txt | |||
@@ -1,15 +1,11 @@ | |||
1 | Steps to update GELs for C66x EVMs | 1 | Notes regarding program-evm |
2 | ---------------------------------- | 2 | ---------------------------------- |
3 | 3 | ||
4 | 1: There are one or more GEL files provided in this directory | 4 | 1: There are one or more GEL files provided in this directory. The gels are specifically meant for |
5 | Program evm and not recommended to be use for other debugging purposes | ||
5 | 6 | ||
6 | 2: These GEL files needs to be copied to CCS installation | 7 | 2: The Program EVM assume the CCS is installed in <CCS_INSTALL_DIR> (which is typically C:\Program Files\Texas Instruments\ccsv5 for Windows XP and ~/ti/ccsv5 for Linux) |
7 | 8 | ||
8 | 3: The following steps will assume the CCS is installed in <CCS_INSTALL_DIR> (which is typically C:\Program Files\Texas Instruments\ccsv5 for Windows XP and ~/ti/ccsv5 for Linux) | 9 | 3: Close CCS if open |
9 | 10 | ||
10 | 4: Close CCS if open | ||
11 | |||
12 | 5: Replace the GEL file present in the <CCS_INSTALL_DIR>/ccs_base/emulation/boards/<BOARD_NAME>/gel directory with the <BOARD_NAME>.gel file present in this directory | ||
13 | |||
14 | 6: Repeat step 5 for all gel files present in this directory | ||
15 | 11 | ||
diff --git a/program_evm/gel/evmk2e.gel b/program_evm/gel/evmk2e.gel index 329dcc0..7f52d83 100644 --- a/program_evm/gel/evmk2e.gel +++ b/program_evm/gel/evmk2e.gel | |||
@@ -1,2910 +1,2910 @@ | |||
1 | /****************************************************************************** | 1 | /****************************************************************************** |
2 | * Copyright (c) 2012 Texas Instruments Incorporated - http://www.ti.com | 2 | * Copyright (c) 2012 Texas Instruments Incorporated - http://www.ti.com |
3 | * | 3 | * |
4 | * Redistribution and use in source and binary forms, with or without | 4 | * Redistribution and use in source and binary forms, with or without |
5 | * modification, are permitted provided that the following conditions | 5 | * modification, are permitted provided that the following conditions |
6 | * | 6 | * |
7 | * are met: | 7 | * are met: |
8 | * | 8 | * |
9 | * Redistributions of source code must retain the above copyright | 9 | * Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. | 10 | * notice, this list of conditions and the following disclaimer. |
11 | * | 11 | * |
12 | * | 12 | * |
13 | * Redistributions in binary form must reproduce the above copyright | 13 | * Redistributions in binary form must reproduce the above copyright |
14 | * notice, this list of conditions and the following disclaimer in the | 14 | * notice, this list of conditions and the following disclaimer in the |
15 | * documentation and/or other materials provided with the | 15 | * documentation and/or other materials provided with the |
16 | * | 16 | * |
17 | * distribution. | 17 | * distribution. |
18 | * | 18 | * |
19 | * | 19 | * |
20 | * Neither the name of Texas Instruments Incorporated nor the names of | 20 | * Neither the name of Texas Instruments Incorporated nor the names of |
21 | * its contributors may be used to endorse or promote products derived | 21 | * its contributors may be used to endorse or promote products derived |
22 | * from this software without specific prior written permission. | 22 | * from this software without specific prior written permission. |
23 | * | 23 | * |
24 | * | 24 | * |
25 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | 25 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
26 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | 26 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
27 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | 27 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
28 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | 28 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
29 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | 29 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
30 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | 30 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
31 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | 31 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
32 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | 32 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
33 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | 33 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
34 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | 34 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
35 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | 35 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
36 | * | 36 | * |
37 | ***************************************************************************** | 37 | ***************************************************************************** |
38 | * | 38 | * |
39 | * Filename: evmtci6638k2k.gel | 39 | * Filename: evmtci6638k2k.gel |
40 | * Description: Utility GEL for use with the TCI6638K2K EVM. This GEL has | 40 | * Description: Utility GEL for use with the TCI6638K2K EVM. This GEL has |
41 | * functions that initialize the chip PLL's and the DDR3A interfaces. | 41 | * functions that initialize the chip PLL's and the DDR3A interfaces. |
42 | * | 42 | * |
43 | * It also includes general utilities that are useful for EVM development | 43 | * It also includes general utilities that are useful for EVM development |
44 | * | 44 | * |
45 | * More functions will be added as needed. | 45 | * More functions will be added as needed. |
46 | * | 46 | * |
47 | * Author: Randy Rosales | 47 | * Author: Randy Rosales |
48 | * Revision History: | 48 | * Revision History: |
49 | * | 49 | * |
50 | * Revision 0.1 | 50 | * Revision 0.1 |
51 | * - Initial revision based on the Kepler VDB GEL 32bit_DDR-800_Kepler_PLL_and_DDR3_Init_Silicon_Rev15.gel put together for Kepler bringup by Pragna Paranji | 51 | * - Initial revision based on the Kepler VDB GEL 32bit_DDR-800_Kepler_PLL_and_DDR3_Init_Silicon_Rev15.gel put together for Kepler bringup by Pragna Paranji |
52 | * - Added in GEL system clock frequency estimation functions written by WenZhong Liu to help debug core PLL instability | 52 | * - Added in GEL system clock frequency estimation functions written by WenZhong Liu to help debug core PLL instability |
53 | * + dspPollDSPClockFreq will estimate the clock based on a comparison with windows system clock time | 53 | * + dspPollDSPClockFreq will estimate the clock based on a comparison with windows system clock time |
54 | * Revision 0.2 - pparanji | 54 | * Revision 0.2 - pparanji |
55 | * - Added DDR3A memory test capabilities. | 55 | * - Added DDR3A memory test capabilities. |
56 | * Revision 0.3 - pparanji | 56 | * Revision 0.3 - pparanji |
57 | * - Added the following configurations | 57 | * - Added the following configurations |
58 | * DDR3A 32bit - DDR800, DDR1066, DDR1333 | 58 | * DDR3A 32bit - DDR800, DDR1066, DDR1333 |
59 | * | 59 | * |
60 | * DSP core PLL @ 122.88 MHz to 614.4 MHz operation | 60 | * DSP core PLL @ 122.88 MHz to 614.4 MHz operation |
61 | * 122.88 MHz to 737.28 MHz operation | 61 | * 122.88 MHz to 737.28 MHz operation |
62 | * 122.88 MHz to 983.04 MHz operation | 62 | * 122.88 MHz to 983.04 MHz operation |
63 | * 122.88 MHz to 1.2 GHz operation | 63 | * 122.88 MHz to 1.2 GHz operation |
64 | * 122.88 MHz to 1.2 GHz operation | 64 | * 122.88 MHz to 1.2 GHz operation |
65 | * | 65 | * |
66 | * ARM PLL @ 100 MHz to 1.0 GHz operation | 66 | * ARM PLL @ 100 MHz to 1.0 GHz operation |
67 | * 100 MHz to 1.4 GHz operation | 67 | * 100 MHz to 1.4 GHz operation |
68 | * 175 MHz to 1.4 GHz operation | 68 | * 175 MHz to 1.4 GHz operation |
69 | * Rev 1.2 - - pparanji | 69 | * Rev 1.2 - - pparanji |
70 | * ------ Updates DDR3A to single rank configurations | 70 | * ------ Updates DDR3A to single rank configurations |
71 | * Rev 1.3 - pparanji | 71 | * Rev 1.3 - pparanji |
72 | * ------ Updated timing on DDR3A-1066 and DDR3A-1333 | 72 | * ------ Updated timing on DDR3A-1066 and DDR3A-1333 |
73 | * Rev 1.4 - csmith | 73 | * Rev 1.4 - csmith |
74 | * ------ Updated PA PLL config and Tetris PLL config | 74 | * ------ Updated PA PLL config and Tetris PLL config |
75 | * | 75 | * |
76 | ---------------------------------------------------------------------------*/ | 76 | ---------------------------------------------------------------------------*/ |
77 | 77 | ||
78 | #define GEL_VERSION 1.0 | 78 | #define GEL_VERSION 1.0 |
79 | 79 | ||
80 | // Timeout definitions | 80 | // Timeout definitions |
81 | int _GEL_Global_Timeout1 = 0; | 81 | int _GEL_Global_Timeout1 = 0; |
82 | 82 | ||
83 | #define TIMEOUT_ID 10 | 83 | #define TIMEOUT_ID 10 |
84 | // Global timeout value | 84 | // Global timeout value |
85 | #define GTIMEOUT 2000 | 85 | #define GTIMEOUT 2000 |
86 | //***************************************************** | 86 | //***************************************************** |
87 | // Power definitions | 87 | // Power definitions |
88 | #define PSC_BASE 0x02350000 | 88 | #define PSC_BASE 0x02350000 |
89 | #define PSC_PTCMD *( unsigned int* )( PSC_BASE+0x120 ) | 89 | #define PSC_PTCMD *( unsigned int* )( PSC_BASE+0x120 ) |
90 | #define PSC_PTSTAT *( unsigned int* )( PSC_BASE+0x128 ) | 90 | #define PSC_PTSTAT *( unsigned int* )( PSC_BASE+0x128 ) |
91 | #define PSC_PDCTL_BASE ( PSC_BASE+0x300 ) | 91 | #define PSC_PDCTL_BASE ( PSC_BASE+0x300 ) |
92 | #define PSC_MDSTAT_BASE ( PSC_BASE+0x800 ) | 92 | #define PSC_MDSTAT_BASE ( PSC_BASE+0x800 ) |
93 | #define PSC_MDCTL_BASE ( PSC_BASE+0xA00 ) | 93 | #define PSC_MDCTL_BASE ( PSC_BASE+0xA00 ) |
94 | 94 | ||
95 | // Modules on power domain 0 | 95 | // Modules on power domain 0 |
96 | // Always on | 96 | // Always on |
97 | // Modules on power domain 0 | 97 | // Modules on power domain 0 |
98 | #define LPSC_TSIP (4) | 98 | #define LPSC_TSIP (4) |
99 | // Modules on power domain 1 | 99 | // Modules on power domain 1 |
100 | #define LPSC_DEBUG (5) | 100 | #define LPSC_DEBUG (5) |
101 | #define LPSC_TETB (6) | 101 | #define LPSC_TETB (6) |
102 | 102 | ||
103 | // Modules on power domain 2 | 103 | // Modules on power domain 2 |
104 | #define LPSC_PA (7) | 104 | #define LPSC_PA (7) |
105 | #define LPSC_SGMII (8) | 105 | #define LPSC_SGMII (8) |
106 | #define LPSC_SA (9) | 106 | #define LPSC_SA (9) |
107 | 107 | ||
108 | // Modules on power domain 3 | 108 | // Modules on power domain 3 |
109 | #define LPSC_PCIE (10) | 109 | #define LPSC_PCIE (10) |
110 | 110 | ||
111 | 111 | ||
112 | // Modules on power domain 5 | 112 | // Modules on power domain 5 |
113 | #define LPSC_HYPERLINK (12) | 113 | #define LPSC_HYPERLINK (12) |
114 | 114 | ||
115 | // Modules on power domain 6 | 115 | // Modules on power domain 6 |
116 | #define LPSC_SR (13) | 116 | #define LPSC_SR (13) |
117 | 117 | ||
118 | // Modules on power domain 7 | 118 | // Modules on power domain 7 |
119 | #define LPSC_MSMCRAM (14) | 119 | #define LPSC_MSMCRAM (14) |
120 | 120 | ||
121 | // Modules on power domain 8 | 121 | // Modules on power domain 8 |
122 | #define LPSC_C66X_COREPAC_0 (15) | 122 | #define LPSC_C66X_COREPAC_0 (15) |
123 | 123 | ||
124 | // Modules on power domain 16 | 124 | // Modules on power domain 16 |
125 | #define LPSC_DDR3_0 (23) | 125 | #define LPSC_DDR3_0 (23) |
126 | 126 | ||
127 | // Modules on power domain 18 | 127 | // Modules on power domain 18 |
128 | #define LPSC_PCIE_1 (27) | 128 | #define LPSC_PCIE_1 (27) |
129 | 129 | ||
130 | // Modules on power domain 29 | 130 | // Modules on power domain 29 |
131 | #define LPSC_XGE (50) | 131 | #define LPSC_XGE (50) |
132 | 132 | ||
133 | // Modules on power domain 31 | 133 | // Modules on power domain 31 |
134 | #define LPSC_ARM (52) | 134 | #define LPSC_ARM (52) |
135 | 135 | ||
136 | 136 | ||
137 | // Power domains definitions | 137 | // Power domains definitions |
138 | #define PD0 (0) // Power Domain-0 | 138 | #define PD0 (0) // Power Domain-0 |
139 | #define PD1 (1) // Power Domain-1 | 139 | #define PD1 (1) // Power Domain-1 |
140 | #define PD2 (2) // Power Domain-2 | 140 | #define PD2 (2) // Power Domain-2 |
141 | #define PD3 (3) // Power Domain-3 | 141 | #define PD3 (3) // Power Domain-3 |
142 | #define PD5 (5) // Power Domain-5 | 142 | #define PD5 (5) // Power Domain-5 |
143 | #define PD6 (6) // Power Domain-6 | 143 | #define PD6 (6) // Power Domain-6 |
144 | #define PD7 (7) // Power Domain-7 | 144 | #define PD7 (7) // Power Domain-7 |
145 | #define PD8 (8) // Power Domain-8 | 145 | #define PD8 (8) // Power Domain-8 |
146 | #define PD16 (16) // Power Domain-16 | 146 | #define PD16 (16) // Power Domain-16 |
147 | #define PD18 (18) // Power Domain-18 | 147 | #define PD18 (18) // Power Domain-18 |
148 | #define PD29 (29) // Power Domain-29 | 148 | #define PD29 (29) // Power Domain-29 |
149 | #define PD31 (31) // Power Domain-31 | 149 | #define PD31 (31) // Power Domain-31 |
150 | 150 | ||
151 | #define PSC_SYNCRESET (0x1) | 151 | #define PSC_SYNCRESET (0x1) |
152 | #define PSC_DISABLE (0x2) | 152 | #define PSC_DISABLE (0x2) |
153 | #define PSC_ENABLE (0x3) | 153 | #define PSC_ENABLE (0x3) |
154 | 154 | ||
155 | #define CHIP_LEVEL_REG 0x02620000 | 155 | #define CHIP_LEVEL_REG 0x02620000 |
156 | 156 | ||
157 | /******************* PLL registers **********************************/ | 157 | /******************* PLL registers **********************************/ |
158 | /*Boot cfg registers*/ | 158 | /*Boot cfg registers*/ |
159 | #define KICK0 *(unsigned int*)(CHIP_LEVEL_REG + 0x0038) | 159 | #define KICK0 *(unsigned int*)(CHIP_LEVEL_REG + 0x0038) |
160 | #define KICK1 *(unsigned int*)(CHIP_LEVEL_REG + 0x003C) | 160 | #define KICK1 *(unsigned int*)(CHIP_LEVEL_REG + 0x003C) |
161 | #define KICK0_UNLOCK (0x83E70B13) | 161 | #define KICK0_UNLOCK (0x83E70B13) |
162 | #define KICK1_UNLOCK (0x95A4F1E0) | 162 | #define KICK1_UNLOCK (0x95A4F1E0) |
163 | #define KICK_LOCK 0 | 163 | #define KICK_LOCK 0 |
164 | #define TINPSEL *(unsigned int*)(CHIP_LEVEL_REG + 0x0300) | 164 | #define TINPSEL *(unsigned int*)(CHIP_LEVEL_REG + 0x0300) |
165 | #define TOUTPSEL *(unsigned int*)(CHIP_LEVEL_REG + 0x0304) | 165 | #define TOUTPSEL *(unsigned int*)(CHIP_LEVEL_REG + 0x0304) |
166 | #define MAINPLLCTL0 *(unsigned int*)(CHIP_LEVEL_REG + 0x0350) | 166 | #define MAINPLLCTL0 *(unsigned int*)(CHIP_LEVEL_REG + 0x0350) |
167 | #define MAINPLLCTL1 *(unsigned int*)(CHIP_LEVEL_REG + 0x0354) | 167 | #define MAINPLLCTL1 *(unsigned int*)(CHIP_LEVEL_REG + 0x0354) |
168 | #define MAIN_PLLD_OFFSET 0 | 168 | #define MAIN_PLLD_OFFSET 0 |
169 | #define MAIN_PLLD_MASK 0xFFFFFFC0 | 169 | #define MAIN_PLLD_MASK 0xFFFFFFC0 |
170 | #define MAIN_PLLM_OFFSET 12 | 170 | #define MAIN_PLLM_OFFSET 12 |
171 | #define MAIN_PLLM_MASK 0xFFF80FFF | 171 | #define MAIN_PLLM_MASK 0xFFF80FFF |
172 | #define MAIN_BWADJ0_OFFSET 24 | 172 | #define MAIN_BWADJ0_OFFSET 24 |
173 | #define MAIN_BWADJ0_MASK 0x00FFFFFF | 173 | #define MAIN_BWADJ0_MASK 0x00FFFFFF |
174 | #define MAIN_ENSAT_OFFSET 6 | 174 | #define MAIN_ENSAT_OFFSET 6 |
175 | #define MAIN_ENSAT_MASK 0xFFFFFFBF | 175 | #define MAIN_ENSAT_MASK 0xFFFFFFBF |
176 | #define MAIN_BWADJ1_OFFSET 0 | 176 | #define MAIN_BWADJ1_OFFSET 0 |
177 | #define MAIN_BWADJ1_MASK 0xFFFFFFF0 | 177 | #define MAIN_BWADJ1_MASK 0xFFFFFFF0 |
178 | 178 | ||
179 | #define OBSCLKCTL *(unsigned int*)(CHIP_LEVEL_REG + 0x0C80) //TODO: Reserved in K2H datashet | 179 | #define OBSCLKCTL *(unsigned int*)(CHIP_LEVEL_REG + 0x0C80) //TODO: Reserved in K2H datashet |
180 | 180 | ||
181 | /* PA PLL Registers */ | 181 | /* PA PLL Registers */ |
182 | #define BYPASS_BIT_SHIFT 23 | 182 | #define BYPASS_BIT_SHIFT 23 |
183 | #define CLKF_BIT_SHIFT 6 | 183 | #define CLKF_BIT_SHIFT 6 |
184 | #define CLKD_BIT_SHIFT 0 | 184 | #define CLKD_BIT_SHIFT 0 |
185 | #define DEVSTAT (*((unsigned int *) 0x02620020)) | 185 | #define DEVSTAT (*((unsigned int *) 0x02620020)) |
186 | #define PAPLLCTL0 *(unsigned int*)(CHIP_LEVEL_REG + 0x0358) | 186 | #define PAPLLCTL0 *(unsigned int*)(CHIP_LEVEL_REG + 0x0358) |
187 | #define PAPLLCTL1 *(unsigned int*)(CHIP_LEVEL_REG + 0x035C) | 187 | #define PAPLLCTL1 *(unsigned int*)(CHIP_LEVEL_REG + 0x035C) |
188 | #define PASSCLKSEL_MASK (1 << 17) /* Tells the configuration of the PASSCLKSEL pin */ | 188 | #define PASSCLKSEL_MASK (1 << 17) /* Tells the configuration of the PASSCLKSEL pin */ |
189 | #define PA_PLL_BYPASS_MASK (1 << BYPASS_BIT_SHIFT) /* Tells whether the PA PLL is in BYPASS mode or not */ | 189 | #define PA_PLL_BYPASS_MASK (1 << BYPASS_BIT_SHIFT) /* Tells whether the PA PLL is in BYPASS mode or not */ |
190 | #define PA_PLL_CLKOD_MASK (0x00780000) /* Tells the output divider value for the PA PLL */ | 190 | #define PA_PLL_CLKOD_MASK (0x00780000) /* Tells the output divider value for the PA PLL */ |
191 | #define PA_PLL_CLKF_MASK (0x0007FFC0) /* Tells the multiplier value for the PA PLL */ | 191 | #define PA_PLL_CLKF_MASK (0x0007FFC0) /* Tells the multiplier value for the PA PLL */ |
192 | #define PA_PLL_CLKR_MASK (0x0000003F) /* Tells the divider value for the PA PLL */ | 192 | #define PA_PLL_CLKR_MASK (0x0000003F) /* Tells the divider value for the PA PLL */ |
193 | #define PA_PLL_RESET_MASK (0x00004000) | 193 | #define PA_PLL_RESET_MASK (0x00004000) |
194 | 194 | ||
195 | 195 | ||
196 | #define CHIP_MISC1 *(unsigned int*)(CHIP_LEVEL_REG + 0x0C7C) | 196 | #define CHIP_MISC1 *(unsigned int*)(CHIP_LEVEL_REG + 0x0C7C) |
197 | #define ARMPLL_ENABLE_OFFSET 13 | 197 | #define ARMPLL_ENABLE_OFFSET 13 |
198 | 198 | ||
199 | 199 | ||
200 | #define DDR3APLLCTL0 *(unsigned int*)(CHIP_LEVEL_REG + 0x0360) | 200 | #define DDR3APLLCTL0 *(unsigned int*)(CHIP_LEVEL_REG + 0x0360) |
201 | #define DDR3APLLCTL1 *(unsigned int*)(CHIP_LEVEL_REG + 0x0364) | 201 | #define DDR3APLLCTL1 *(unsigned int*)(CHIP_LEVEL_REG + 0x0364) |
202 | 202 | ||
203 | //****************************************************** | 203 | //****************************************************** |
204 | // PLL 1 definitions (DSP and ARM clock and subsystems) | 204 | // PLL 1 definitions (DSP and ARM clock and subsystems) |
205 | #define PLL1_BASE 0x02310000 | 205 | #define PLL1_BASE 0x02310000 |
206 | #define PLL1_PLLCTL (*(unsigned int*)(PLL1_BASE + 0x100)) // PLL1 Control | 206 | #define PLL1_PLLCTL (*(unsigned int*)(PLL1_BASE + 0x100)) // PLL1 Control |
207 | #define PLL1_SECCTL (*(unsigned int*)(PLL1_BASE + 0x108)) // PLL1 Secondary Control | 207 | #define PLL1_SECCTL (*(unsigned int*)(PLL1_BASE + 0x108)) // PLL1 Secondary Control |
208 | #define PLL1_PLLM (*(unsigned int*)(PLL1_BASE + 0x110)) // PLL1 Multiplier | 208 | #define PLL1_PLLM (*(unsigned int*)(PLL1_BASE + 0x110)) // PLL1 Multiplier |
209 | #define PLL1_DIV1 (*(unsigned int*)(PLL1_BASE + 0x118)) // DIV1 divider | 209 | #define PLL1_DIV1 (*(unsigned int*)(PLL1_BASE + 0x118)) // DIV1 divider |
210 | #define PLL1_DIV2 (*(unsigned int*)(PLL1_BASE + 0x11C)) // DIV2 divider | 210 | #define PLL1_DIV2 (*(unsigned int*)(PLL1_BASE + 0x11C)) // DIV2 divider |
211 | #define PLL1_DIV3 (*(unsigned int*)(PLL1_BASE + 0x120)) // DIV3 divider | 211 | #define PLL1_DIV3 (*(unsigned int*)(PLL1_BASE + 0x120)) // DIV3 divider |
212 | #define PLL1_CMD (*(unsigned int*)(PLL1_BASE + 0x138)) // CMD control | 212 | #define PLL1_CMD (*(unsigned int*)(PLL1_BASE + 0x138)) // CMD control |
213 | #define PLL1_STAT (*(unsigned int*)(PLL1_BASE + 0x13C)) // STAT control | 213 | #define PLL1_STAT (*(unsigned int*)(PLL1_BASE + 0x13C)) // STAT control |
214 | #define PLL1_ALNCTL (*(unsigned int*)(PLL1_BASE + 0x140)) // ALNCTL control | 214 | #define PLL1_ALNCTL (*(unsigned int*)(PLL1_BASE + 0x140)) // ALNCTL control |
215 | #define PLL1_DCHANGE (*(unsigned int*)(PLL1_BASE + 0x144)) // DCHANGE status | 215 | #define PLL1_DCHANGE (*(unsigned int*)(PLL1_BASE + 0x144)) // DCHANGE status |
216 | #define PLL1_CKEN (*(unsigned int*)(PLL1_BASE + 0x148)) // CKEN control | 216 | #define PLL1_CKEN (*(unsigned int*)(PLL1_BASE + 0x148)) // CKEN control |
217 | #define PLL1_CKSTAT (*(unsigned int*)(PLL1_BASE + 0x14C)) // CKSTAT status | 217 | #define PLL1_CKSTAT (*(unsigned int*)(PLL1_BASE + 0x14C)) // CKSTAT status |
218 | #define PLL1_SYSTAT (*(unsigned int*)(PLL1_BASE + 0x150)) // SYSTAT status | 218 | #define PLL1_SYSTAT (*(unsigned int*)(PLL1_BASE + 0x150)) // SYSTAT status |
219 | #define PLL1_DIV4 (*(unsigned int*)(PLL1_BASE + 0x160)) // DIV4 divider | 219 | #define PLL1_DIV4 (*(unsigned int*)(PLL1_BASE + 0x160)) // DIV4 divider |
220 | #define PLL1_DIV5 (*(unsigned int*)(PLL1_BASE + 0x164)) // DIV5 divider | 220 | #define PLL1_DIV5 (*(unsigned int*)(PLL1_BASE + 0x164)) // DIV5 divider |
221 | #define PLL1_DIV6 (*(unsigned int*)(PLL1_BASE + 0x168)) // DIV6 divider | 221 | #define PLL1_DIV6 (*(unsigned int*)(PLL1_BASE + 0x168)) // DIV6 divider |
222 | #define PLL1_DIV7 (*(unsigned int*)(PLL1_BASE + 0x16C)) // DIV7 divider | 222 | #define PLL1_DIV7 (*(unsigned int*)(PLL1_BASE + 0x16C)) // DIV7 divider |
223 | #define PLL1_DIV8 (*(unsigned int*)(PLL1_BASE + 0x170)) // DIV8 divider | 223 | #define PLL1_DIV8 (*(unsigned int*)(PLL1_BASE + 0x170)) // DIV8 divider |
224 | #define PLL1_DIV9 (*(unsigned int*)(PLL1_BASE + 0x174)) // DIV9 divider | 224 | #define PLL1_DIV9 (*(unsigned int*)(PLL1_BASE + 0x174)) // DIV9 divider |
225 | #define PLL1_DIV10 (*(unsigned int*)(PLL1_BASE + 0x178)) // DIV10 divider | 225 | #define PLL1_DIV10 (*(unsigned int*)(PLL1_BASE + 0x178)) // DIV10 divider |
226 | #define PLL1_DIV11 (*(unsigned int*)(PLL1_BASE + 0x17C)) // DIV11 divider | 226 | #define PLL1_DIV11 (*(unsigned int*)(PLL1_BASE + 0x17C)) // DIV11 divider |
227 | #define PLL1_DIV12 (*(unsigned int*)(PLL1_BASE + 0x180)) // DIV12 divider | 227 | #define PLL1_DIV12 (*(unsigned int*)(PLL1_BASE + 0x180)) // DIV12 divider |
228 | #define PLL1_DIV13 (*(unsigned int*)(PLL1_BASE + 0x184)) // DIV13 divider | 228 | #define PLL1_DIV13 (*(unsigned int*)(PLL1_BASE + 0x184)) // DIV13 divider |
229 | #define PLL1_DIV14 (*(unsigned int*)(PLL1_BASE + 0x188)) // DIV14 divider | 229 | #define PLL1_DIV14 (*(unsigned int*)(PLL1_BASE + 0x188)) // DIV14 divider |
230 | #define PLL1_DIV15 (*(unsigned int*)(PLL1_BASE + 0x18C)) // DIV15 divider | 230 | #define PLL1_DIV15 (*(unsigned int*)(PLL1_BASE + 0x18C)) // DIV15 divider |
231 | #define PLL1_DIV16 (*(unsigned int*)(PLL1_BASE + 0x190)) // DIV16 divider | 231 | #define PLL1_DIV16 (*(unsigned int*)(PLL1_BASE + 0x190)) // DIV16 divider |
232 | #define PLLPWRDN_OFFSET 1 | 232 | #define PLLPWRDN_OFFSET 1 |
233 | #define PLLPWRDN_MASK 0xFFFFFFFD | 233 | #define PLLPWRDN_MASK 0xFFFFFFFD |
234 | #define PLLRST_OFFSET 3 | 234 | #define PLLRST_OFFSET 3 |
235 | #define PLLRST_MASK 0xFFFFFFF7 | 235 | #define PLLRST_MASK 0xFFFFFFF7 |
236 | #define PLLENSRC_OFFSET 5 | 236 | #define PLLENSRC_OFFSET 5 |
237 | #define PLLENSRC_MASK 0xFFFFFFDF | 237 | #define PLLENSRC_MASK 0xFFFFFFDF |
238 | #define PLLEN_OFFSET 0 | 238 | #define PLLEN_OFFSET 0 |
239 | #define PLLEN_MASK 0xFFFFFFFE | 239 | #define PLLEN_MASK 0xFFFFFFFE |
240 | #define OUTPUT_DIVIDE_OFFSET 19 | 240 | #define OUTPUT_DIVIDE_OFFSET 19 |
241 | #define OUTPUT_DIVIDE_MASK 0xFF87FFFF | 241 | #define OUTPUT_DIVIDE_MASK 0xFF87FFFF |
242 | #define BYPASS_OFFSET 23 | 242 | #define BYPASS_OFFSET 23 |
243 | #define BYPASS_MASK 0xFF7FFFFF | 243 | #define BYPASS_MASK 0xFF7FFFFF |
244 | #define PLLM_OFFSET 0 | 244 | #define PLLM_OFFSET 0 |
245 | #define PLLM_MASK 0xFFFFFFC0 | 245 | #define PLLM_MASK 0xFFFFFFC0 |
246 | #define GOSET_OFFSET 0 | 246 | #define GOSET_OFFSET 0 |
247 | #define GOSET_MASK 0xFFFFFFFE | 247 | #define GOSET_MASK 0xFFFFFFFE |
248 | #define GOSTAT_OFFSET 0 | 248 | #define GOSTAT_OFFSET 0 |
249 | #define GOSTAT_MASK 0xFFFFFFFE | 249 | #define GOSTAT_MASK 0xFFFFFFFE |
250 | 250 | ||
251 | #define OUTPUT_DIVIDE_OFFSET 19 | 251 | #define OUTPUT_DIVIDE_OFFSET 19 |
252 | #define OUTPUT_DIVIDE_MASK 0xFF87FFFF | 252 | #define OUTPUT_DIVIDE_MASK 0xFF87FFFF |
253 | 253 | ||
254 | // ARMPLL definitions | 254 | // ARMPLL definitions |
255 | #define SEC_PLLCTL0_PLLM_OFFSET 6 | 255 | #define SEC_PLLCTL0_PLLM_OFFSET 6 |
256 | #define SEC_PLLCTL0_PLLM_MASK 0xFFFF003F | 256 | #define SEC_PLLCTL0_PLLM_MASK 0xFFFF003F |
257 | #define SEC_PLLCTL0_BWADJ_OFFSET 24 | 257 | #define SEC_PLLCTL0_BWADJ_OFFSET 24 |
258 | #define SEC_PLLCTL0_BWADJ_MASK 0x00FFFFFF | 258 | #define SEC_PLLCTL0_BWADJ_MASK 0x00FFFFFF |
259 | #define SEC_PLLCTL0_OD_OFFSET 19 | 259 | #define SEC_PLLCTL0_OD_OFFSET 19 |
260 | #define SEC_PLLCTL0_OD_MASK 0xFF87FFFF | 260 | #define SEC_PLLCTL0_OD_MASK 0xFF87FFFF |
261 | #define SEC_PLLCTL0_BYPASS_OFFSET 23 | 261 | #define SEC_PLLCTL0_BYPASS_OFFSET 23 |
262 | #define SEC_PLLCTL0_BYPASS_MASK 0xFF7FFFFF | 262 | #define SEC_PLLCTL0_BYPASS_MASK 0xFF7FFFFF |
263 | #define SEC_PLLCTL1_RESET_OFFSET 14 | 263 | #define SEC_PLLCTL1_RESET_OFFSET 14 |
264 | #define SEC_PLLCTL1_RESET_MASK 0xFFFFBFFF | 264 | #define SEC_PLLCTL1_RESET_MASK 0xFFFFBFFF |
265 | #define SEC_PLLCTL1_PWRDWN_OFFSET 15 | 265 | #define SEC_PLLCTL1_PWRDWN_OFFSET 15 |
266 | #define SEC_PLLCTL1_PWRDWN_MASK 0xFFFF7FFF | 266 | #define SEC_PLLCTL1_PWRDWN_MASK 0xFFFF7FFF |
267 | #define SEC_PLLCTL1_ENSTAT_OFFSET 6 | 267 | #define SEC_PLLCTL1_ENSTAT_OFFSET 6 |
268 | #define SEC_PLLCTL1_ENSTAT_MASK 0xFFFFFFBF | 268 | #define SEC_PLLCTL1_ENSTAT_MASK 0xFFFFFFBF |
269 | 269 | ||
270 | /*----------------DDR3A Register definition---------------------*/ | 270 | /*----------------DDR3A Register definition---------------------*/ |
271 | 271 | ||
272 | #define DDR3A_BASE_ADDR (0x21010000) | 272 | #define DDR3A_BASE_ADDR (0x21010000) |
273 | #define DDR3A_STATUS (*(int*)(DDR3A_BASE_ADDR + 0x00000004)) | 273 | #define DDR3A_STATUS (*(int*)(DDR3A_BASE_ADDR + 0x00000004)) |
274 | #define DDR3A_SDCFG (*(int*)(DDR3A_BASE_ADDR + 0x00000008)) | 274 | #define DDR3A_SDCFG (*(int*)(DDR3A_BASE_ADDR + 0x00000008)) |
275 | #define DDR3A_SDRFC (*(int*)(DDR3A_BASE_ADDR + 0x00000010)) | 275 | #define DDR3A_SDRFC (*(int*)(DDR3A_BASE_ADDR + 0x00000010)) |
276 | #define DDR3A_SDTIM1 (*(int*)(DDR3A_BASE_ADDR + 0x00000018)) | 276 | #define DDR3A_SDTIM1 (*(int*)(DDR3A_BASE_ADDR + 0x00000018)) |
277 | #define DDR3A_SDTIM2 (*(int*)(DDR3A_BASE_ADDR + 0x0000001C)) | 277 | #define DDR3A_SDTIM2 (*(int*)(DDR3A_BASE_ADDR + 0x0000001C)) |
278 | #define DDR3A_SDTIM3 (*(int*)(DDR3A_BASE_ADDR + 0x00000020)) | 278 | #define DDR3A_SDTIM3 (*(int*)(DDR3A_BASE_ADDR + 0x00000020)) |
279 | #define DDR3A_SDTIM4 (*(int*)(DDR3A_BASE_ADDR + 0x00000028)) | 279 | #define DDR3A_SDTIM4 (*(int*)(DDR3A_BASE_ADDR + 0x00000028)) |
280 | #define DDR3A_ZQCFG (*(int*)(DDR3A_BASE_ADDR + 0x000000C8)) | 280 | #define DDR3A_ZQCFG (*(int*)(DDR3A_BASE_ADDR + 0x000000C8)) |
281 | #define DDR3A_TMPALRT (*(int*)(DDR3A_BASE_ADDR + 0x000000CC)) | 281 | #define DDR3A_TMPALRT (*(int*)(DDR3A_BASE_ADDR + 0x000000CC)) |
282 | #define DDR3A_DDRPHYC (*(int*)(DDR3A_BASE_ADDR + 0x000000E4)) | 282 | #define DDR3A_DDRPHYC (*(int*)(DDR3A_BASE_ADDR + 0x000000E4)) |
283 | 283 | ||
284 | #define DDR3A_PHY_CFG_BASE (0x02329000) | 284 | #define DDR3A_PHY_CFG_BASE (0x02329000) |
285 | #define DDR3A_PIR (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000004)) | 285 | #define DDR3A_PIR (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000004)) |
286 | #define DDR3A_PGCR0 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000008)) | 286 | #define DDR3A_PGCR0 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000008)) |
287 | #define DDR3A_PGCR1 (*(int*)(DDR3A_PHY_CFG_BASE + 0x0000000C)) | 287 | #define DDR3A_PGCR1 (*(int*)(DDR3A_PHY_CFG_BASE + 0x0000000C)) |
288 | #define DDR3A_PGCR2 (*(int*)(DDR3A_PHY_CFG_BASE + 0x0000008C)) | 288 | #define DDR3A_PGCR2 (*(int*)(DDR3A_PHY_CFG_BASE + 0x0000008C)) |
289 | #define DDR3A_PGSR0 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000010)) | 289 | #define DDR3A_PGSR0 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000010)) |
290 | #define DDR3A_PGSR1 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000014)) | 290 | #define DDR3A_PGSR1 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000014)) |
291 | #define DDR3A_PLLCR (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000018)) | 291 | #define DDR3A_PLLCR (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000018)) |
292 | #define DDR3A_PTR0 (*(int*)(DDR3A_PHY_CFG_BASE + 0x0000001C)) | 292 | #define DDR3A_PTR0 (*(int*)(DDR3A_PHY_CFG_BASE + 0x0000001C)) |
293 | #define DDR3A_PTR1 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000020)) | 293 | #define DDR3A_PTR1 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000020)) |
294 | #define DDR3A_PTR2 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000024)) | 294 | #define DDR3A_PTR2 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000024)) |
295 | #define DDR3A_PTR3 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000028)) | 295 | #define DDR3A_PTR3 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000028)) |
296 | #define DDR3A_PTR4 (*(int*)(DDR3A_PHY_CFG_BASE + 0x0000002C)) | 296 | #define DDR3A_PTR4 (*(int*)(DDR3A_PHY_CFG_BASE + 0x0000002C)) |
297 | #define DDR3A_DSGCR (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000040)) | 297 | #define DDR3A_DSGCR (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000040)) |
298 | #define DDR3A_DCR (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000044)) | 298 | #define DDR3A_DCR (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000044)) |
299 | #define DDR3A_MR0 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000054)) | 299 | #define DDR3A_MR0 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000054)) |
300 | #define DDR3A_MR1 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000058)) | 300 | #define DDR3A_MR1 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000058)) |
301 | #define DDR3A_MR2 (*(int*)(DDR3A_PHY_CFG_BASE + 0x0000005C)) | 301 | #define DDR3A_MR2 (*(int*)(DDR3A_PHY_CFG_BASE + 0x0000005C)) |
302 | #define DDR3A_DTCR (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000068)) | 302 | #define DDR3A_DTCR (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000068)) |
303 | #define DDR3A_DTPR0 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000048)) | 303 | #define DDR3A_DTPR0 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000048)) |
304 | #define DDR3A_DTPR1 (*(int*)(DDR3A_PHY_CFG_BASE + 0x0000004C)) | 304 | #define DDR3A_DTPR1 (*(int*)(DDR3A_PHY_CFG_BASE + 0x0000004C)) |
305 | #define DDR3A_DTPR2 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000050)) | 305 | #define DDR3A_DTPR2 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000050)) |
306 | 306 | ||
307 | #define DDR3A_ZQ0CR1 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000184)) | 307 | #define DDR3A_ZQ0CR1 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000184)) |
308 | #define DDR3A_ZQ1CR1 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000194)) | 308 | #define DDR3A_ZQ1CR1 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000194)) |
309 | #define DDR3A_ZQ2CR1 (*(int*)(DDR3A_PHY_CFG_BASE + 0x000001A4)) | 309 | #define DDR3A_ZQ2CR1 (*(int*)(DDR3A_PHY_CFG_BASE + 0x000001A4)) |
310 | #define DDR3A_ZQ3CR1 (*(int*)(DDR3A_PHY_CFG_BASE + 0x000001B4)) | 310 | #define DDR3A_ZQ3CR1 (*(int*)(DDR3A_PHY_CFG_BASE + 0x000001B4)) |
311 | 311 | ||
312 | #define DDR3A_DATX8_8 (*(int*)(DDR3A_PHY_CFG_BASE + 0x000003C0)) | 312 | #define DDR3A_DATX8_8 (*(int*)(DDR3A_PHY_CFG_BASE + 0x000003C0)) |
313 | 313 | ||
314 | 314 | ||
315 | #define DDR3_TEST_START_ADDRESS (*(int*)(0x80000000)) | 315 | #define DDR3_TEST_START_ADDRESS (*(int*)(0x80000000)) |
316 | 316 | ||
317 | #define IODDRM_MASK 0x00000180 | 317 | #define IODDRM_MASK 0x00000180 |
318 | #define ZCKSEL_MASK 0x01800000 | 318 | #define ZCKSEL_MASK 0x01800000 |
319 | #define CL_MASK 0x00000072 | 319 | #define CL_MASK 0x00000072 |
320 | #define WR_MASK 0x00000E00 | 320 | #define WR_MASK 0x00000E00 |
321 | #define BL_MASK 0x00000003 | 321 | #define BL_MASK 0x00000003 |
322 | #define RRMODE_MASK 0x00040000 | 322 | #define RRMODE_MASK 0x00040000 |
323 | #define UDIMM_MASK 0x20000000 | 323 | #define UDIMM_MASK 0x20000000 |
324 | #define BYTEMASK_MASK 0x0000FC00 | 324 | #define BYTEMASK_MASK 0x0000FC00 |
325 | #define MPRDQ_MASK 0x00000080 | 325 | #define MPRDQ_MASK 0x00000080 |
326 | #define PDQ_MASK 0x00000070 | 326 | #define PDQ_MASK 0x00000070 |
327 | #define NOSRA_MASK 0x08000000 | 327 | #define NOSRA_MASK 0x08000000 |
328 | #define ECC_MASK 0x00000001 | 328 | #define ECC_MASK 0x00000001 |
329 | #define RRMODE_MASK 0x00040000 | 329 | #define RRMODE_MASK 0x00040000 |
330 | 330 | ||
331 | #define DDR3A_DX0GSR0 (*(int*)(DDR3A_PHY_CFG_BASE + 0x000001C4)) //0x71 | 331 | #define DDR3A_DX0GSR0 (*(int*)(DDR3A_PHY_CFG_BASE + 0x000001C4)) //0x71 |
332 | #define DDR3A_DX1GSR0 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000204)) //0x81 | 332 | #define DDR3A_DX1GSR0 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000204)) //0x81 |
333 | #define DDR3A_DX2GSR0 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000244)) //0x91 | 333 | #define DDR3A_DX2GSR0 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000244)) //0x91 |
334 | #define DDR3A_DX3GSR0 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000284)) //0xA1 | 334 | #define DDR3A_DX3GSR0 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000284)) //0xA1 |
335 | #define DDR3A_DX4GSR0 (*(int*)(DDR3A_PHY_CFG_BASE + 0x000002C4)) //0xB1 | 335 | #define DDR3A_DX4GSR0 (*(int*)(DDR3A_PHY_CFG_BASE + 0x000002C4)) //0xB1 |
336 | #define DDR3A_DX5GSR0 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000304)) //0xC1 | 336 | #define DDR3A_DX5GSR0 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000304)) //0xC1 |
337 | #define DDR3A_DX6GSR0 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000344)) //0xD1 | 337 | #define DDR3A_DX6GSR0 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000344)) //0xD1 |
338 | #define DDR3A_DX7GSR0 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000384)) //0xE1 | 338 | #define DDR3A_DX7GSR0 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000384)) //0xE1 |
339 | #define DDR3A_DX8GSR0 (*(int*)(DDR3A_PHY_CFG_BASE + 0x000003C4)) //0xF1 | 339 | #define DDR3A_DX8GSR0 (*(int*)(DDR3A_PHY_CFG_BASE + 0x000003C4)) //0xF1 |
340 | 340 | ||
341 | #define DDR3A_TEST_START_ADDRESS (0x80000000) | 341 | #define DDR3A_TEST_START_ADDRESS (0x80000000) |
342 | 342 | ||
343 | #define DDR3A_TEST_END_ADDRESS (DDR3A_TEST_START_ADDRESS + (4 * 100)) | 343 | #define DDR3A_TEST_END_ADDRESS (DDR3A_TEST_START_ADDRESS + (4 * 100)) |
344 | #define DDR3A_BASE_ADDRESS 0x80000000 | 344 | #define DDR3A_BASE_ADDRESS 0x80000000 |
345 | 345 | ||
346 | 346 | ||
347 | 347 | ||
348 | #define TETRIS_BASE 0x01E80000 | 348 | #define TETRIS_BASE 0x01E80000 |
349 | 349 | ||
350 | #define TETRIS_CPU0_PTCMD *(unsigned int*)(TETRIS_BASE + 0x0400) | 350 | #define TETRIS_CPU0_PTCMD *(unsigned int*)(TETRIS_BASE + 0x0400) |
351 | #define TETRIS_CPU0_PDSTAT *(unsigned int*)(TETRIS_BASE + 0x0404) | 351 | #define TETRIS_CPU0_PDSTAT *(unsigned int*)(TETRIS_BASE + 0x0404) |
352 | #define TETRIS_CPU0_PDCTL *(unsigned int*)(TETRIS_BASE + 0x0408) | 352 | #define TETRIS_CPU0_PDCTL *(unsigned int*)(TETRIS_BASE + 0x0408) |
353 | 353 | ||
354 | #define TETRIS_CPU1_PTCMD *(unsigned int*)(TETRIS_BASE + 0x040C) | 354 | #define TETRIS_CPU1_PTCMD *(unsigned int*)(TETRIS_BASE + 0x040C) |
355 | #define TETRIS_CPU1_PDSTAT *(unsigned int*)(TETRIS_BASE + 0x0410) | 355 | #define TETRIS_CPU1_PDSTAT *(unsigned int*)(TETRIS_BASE + 0x0410) |
356 | #define TETRIS_CPU1_PDCTL *(unsigned int*)(TETRIS_BASE + 0x0414) | 356 | #define TETRIS_CPU1_PDCTL *(unsigned int*)(TETRIS_BASE + 0x0414) |
357 | 357 | ||
358 | #define TETRIS_CPU2_PTCMD *(unsigned int*)(TETRIS_BASE + 0x0418) | 358 | #define TETRIS_CPU2_PTCMD *(unsigned int*)(TETRIS_BASE + 0x0418) |
359 | #define TETRIS_CPU2_PDSTAT *(unsigned int*)(TETRIS_BASE + 0x041C) | 359 | #define TETRIS_CPU2_PDSTAT *(unsigned int*)(TETRIS_BASE + 0x041C) |
360 | #define TETRIS_CPU2_PDCTL *(unsigned int*)(TETRIS_BASE + 0x0420) | 360 | #define TETRIS_CPU2_PDCTL *(unsigned int*)(TETRIS_BASE + 0x0420) |
361 | 361 | ||
362 | #define TETRIS_CPU3_PTCMD *(unsigned int*)(TETRIS_BASE + 0x0424) | 362 | #define TETRIS_CPU3_PTCMD *(unsigned int*)(TETRIS_BASE + 0x0424) |
363 | #define TETRIS_CPU3_PDSTAT *(unsigned int*)(TETRIS_BASE + 0x0428) | 363 | #define TETRIS_CPU3_PDSTAT *(unsigned int*)(TETRIS_BASE + 0x0428) |
364 | #define TETRIS_CPU3_PDCTL *(unsigned int*)(TETRIS_BASE + 0x042C) | 364 | #define TETRIS_CPU3_PDCTL *(unsigned int*)(TETRIS_BASE + 0x042C) |
365 | 365 | ||
366 | #define SECPLLCTL0 *(unsigned int*)(CHIP_LEVEL_REG + 0x0370) | 366 | #define SECPLLCTL0 *(unsigned int*)(CHIP_LEVEL_REG + 0x0370) |
367 | #define SECPLLCTL1 *(unsigned int*)(CHIP_LEVEL_REG + 0x0374) | 367 | #define SECPLLCTL1 *(unsigned int*)(CHIP_LEVEL_REG + 0x0374) |
368 | unsigned int read_val; | 368 | unsigned int read_val; |
369 | 369 | ||
370 | /**************************************************************************** | 370 | /**************************************************************************** |
371 | * | 371 | * |
372 | * NAME | 372 | * NAME |
373 | * OnTargetConnect | 373 | * OnTargetConnect |
374 | * | 374 | * |
375 | * PURPOSE: | 375 | * PURPOSE: |
376 | * Setup almost everything ready for a new debug session: | 376 | * Setup almost everything ready for a new debug session: |
377 | * DSP modules and EVM board modules, at target connection. | 377 | * DSP modules and EVM board modules, at target connection. |
378 | * Do nothing if target is in realtime mode. | 378 | * Do nothing if target is in realtime mode. |
379 | * This routine is called when you connect to the target board. | 379 | * This routine is called when you connect to the target board. |
380 | * | 380 | * |
381 | * IMPORTANT: this routine won't attempt to connect to the target | 381 | * IMPORTANT: this routine won't attempt to connect to the target |
382 | * if the target is not in real-time mode and that the dsp boot | 382 | * if the target is not in real-time mode and that the dsp boot |
383 | * mode switches are not set in emulation boot mode. | 383 | * mode switches are not set in emulation boot mode. |
384 | * | 384 | * |
385 | * USAGE | 385 | * USAGE |
386 | * This routine is a callback routine and called by CCS only. | 386 | * This routine is a callback routine and called by CCS only. |
387 | * | 387 | * |
388 | * RETURN VALUE | 388 | * RETURN VALUE |
389 | * NONE | 389 | * NONE |
390 | * | 390 | * |
391 | * REFERENCE | 391 | * REFERENCE |
392 | * | 392 | * |
393 | ****************************************************************************/ | 393 | ****************************************************************************/ |
394 | OnTargetConnect() | 394 | OnTargetConnect() |
395 | { | 395 | { |
396 | /*------------------------------------------------------*/ | 396 | /*------------------------------------------------------*/ |
397 | /* GEL_Reset() is used to deal with the worst case */ | 397 | /* GEL_Reset() is used to deal with the worst case */ |
398 | /* senario of unknown target state. If for some reason */ | 398 | /* senario of unknown target state. If for some reason */ |
399 | /* a reset is not desired upon target connection, */ | 399 | /* a reset is not desired upon target connection, */ |
400 | /* GEL_Reset() may be removed and replaced with */ | 400 | /* GEL_Reset() may be removed and replaced with */ |
401 | /* something "less brutal" like a cache initialization */ | 401 | /* something "less brutal" like a cache initialization */ |
402 | /* function. */ | 402 | /* function. */ |
403 | /*------------------------------------------------------*/ | 403 | /*------------------------------------------------------*/ |
404 | //GEL_Reset(); | 404 | //GEL_Reset(); |
405 | //xmc_setup(); | 405 | //xmc_setup(); |
406 | //ddr3_setup(); | 406 | //ddr3_setup(); |
407 | 407 | ||
408 | GEL_TextOut("\nConnecting Target...\n"); | 408 | GEL_TextOut("\nConnecting Target...\n"); |
409 | 409 | ||
410 | // Check if target is not in real-time mode. If it is in stop mode, | 410 | // Check if target is not in real-time mode. If it is in stop mode, |
411 | // initialize everything. In real-time mode, do nothing to connect | 411 | // initialize everything. In real-time mode, do nothing to connect |
412 | // unobtrusively... | 412 | // unobtrusively... |
413 | if (!GEL_IsInRealtimeMode()) | 413 | if (!GEL_IsInRealtimeMode()) |
414 | { | 414 | { |
415 | // Validates if emulation boot mode | 415 | // Validates if emulation boot mode |
416 | if (DEVSTAT & 0x0000000E) | 416 | if (DEVSTAT & 0x0000000E) |
417 | { | 417 | { |
418 | GEL_TextOut("No initialization performed since bootmode = %x \n",,,,,(DEVSTAT >> 1 ) & 0xF); | 418 | GEL_TextOut("No initialization performed since bootmode = %x \n",,,,,(DEVSTAT >> 1 ) & 0xF); |
419 | GEL_TextOut("You can manually initialize with GlobalDefaultSetup\n"); | 419 | GEL_TextOut("You can manually initialize with GlobalDefaultSetup\n"); |
420 | } | 420 | } |
421 | else | 421 | else |
422 | { | 422 | { |
423 | // Comment the following line at production application test | 423 | // Comment the following line at production application test |
424 | // when the application need to initialize everything, but not the | 424 | // when the application need to initialize everything, but not the |
425 | // GEL file. | 425 | // GEL file. |
426 | Global_Default_Setup_Silent(); | 426 | Global_Default_Setup_Silent(); |
427 | } | 427 | } |
428 | } else { | 428 | } else { |
429 | GEL_TextOut("No initialization performed in real time mode\n"); | 429 | GEL_TextOut("No initialization performed in real time mode\n"); |
430 | } | 430 | } |
431 | } | 431 | } |
432 | 432 | ||
433 | /*--------------------------------------------------------------*/ | 433 | /*--------------------------------------------------------------*/ |
434 | /* OnReset() */ | 434 | /* OnReset() */ |
435 | /* This function is called by CCS when you do Debug->Resest. */ | 435 | /* This function is called by CCS when you do Debug->Resest. */ |
436 | /* The goal is to put the C6x into a known good state with */ | 436 | /* The goal is to put the C6x into a known good state with */ |
437 | /* respect to cache, edma and interrupts. */ | 437 | /* respect to cache, edma and interrupts. */ |
438 | /*--------------------------------------------------------------*/ | 438 | /*--------------------------------------------------------------*/ |
439 | OnReset( int nErrorCode ) | 439 | OnReset( int nErrorCode ) |
440 | { | 440 | { |
441 | } | 441 | } |
442 | 442 | ||
443 | /*--------------------------------------------------------------*/ | 443 | /*--------------------------------------------------------------*/ |
444 | /* xmc_setup() */ | 444 | /* xmc_setup() */ |
445 | /* XMC MPAX register setting to access DDR3 config space */ | 445 | /* XMC MPAX register setting to access DDR3 config space */ |
446 | /*--------------------------------------------------------------*/ | 446 | /*--------------------------------------------------------------*/ |
447 | 447 | ||
448 | #define XMC_BASE_ADDR (0x08000000) | 448 | #define XMC_BASE_ADDR (0x08000000) |
449 | #define XMPAX2_L (*(int*)(XMC_BASE_ADDR + 0x00000010)) | 449 | #define XMPAX2_L (*(int*)(XMC_BASE_ADDR + 0x00000010)) |
450 | #define XMPAX2_H (*(int*)(XMC_BASE_ADDR + 0x00000014)) | 450 | #define XMPAX2_H (*(int*)(XMC_BASE_ADDR + 0x00000014)) |
451 | 451 | ||
452 | xmc_setup() | 452 | xmc_setup() |
453 | { | 453 | { |
454 | /* mapping for ddr emif registers XMPAX*2 */ | 454 | /* mapping for ddr emif registers XMPAX*2 */ |
455 | 455 | ||
456 | XMPAX2_L = 0x121010FF; /* replacement addr + perm */ | 456 | XMPAX2_L = 0x121010FF; /* replacement addr + perm */ |
457 | XMPAX2_H = 0x2101000B; /* base addr + seg size (64KB)*/ //"1B"-->"B" by xj | 457 | XMPAX2_H = 0x2101000B; /* base addr + seg size (64KB)*/ //"1B"-->"B" by xj |
458 | GEL_TextOut("XMC setup complete.\n"); | 458 | GEL_TextOut("XMC setup complete.\n"); |
459 | } | 459 | } |
460 | 460 | ||
461 | /**************************************************************************** | 461 | /**************************************************************************** |
462 | * | 462 | * |
463 | * NAME | 463 | * NAME |
464 | * Global_Default_Setup_Silent | 464 | * Global_Default_Setup_Silent |
465 | * | 465 | * |
466 | * PURPOSE: | 466 | * PURPOSE: |
467 | * Setup almost everything ready for a new debug session: | 467 | * Setup almost everything ready for a new debug session: |
468 | * DSP modules and EVM board modules. | 468 | * DSP modules and EVM board modules. |
469 | * | 469 | * |
470 | * USAGE | 470 | * USAGE |
471 | * This routine can be called as: | 471 | * This routine can be called as: |
472 | * | 472 | * |
473 | * Global_Default_Setup_Silent() | 473 | * Global_Default_Setup_Silent() |
474 | * | 474 | * |
475 | * RETURN VALUE | 475 | * RETURN VALUE |
476 | * NONE | 476 | * NONE |
477 | * | 477 | * |
478 | * REFERENCE | 478 | * REFERENCE |
479 | * | 479 | * |
480 | ****************************************************************************/ | 480 | ****************************************************************************/ |
481 | Global_Default_Setup_Silent() | 481 | Global_Default_Setup_Silent() |
482 | { | 482 | { |
483 | float gel_ver = GEL_VERSION; | 483 | float gel_ver = GEL_VERSION; |
484 | 484 | ||
485 | // Set DSP cache to pre defined values... | 485 | // Set DSP cache to pre defined values... |
486 | GEL_TextOut( "TCI6636K2E GEL file Ver is %f \n",,,,, (float) (gel_ver/1.0)); | 486 | GEL_TextOut( "TCI6636K2E GEL file Ver is %f \n",,,,, (float) (gel_ver/1.0)); |
487 | 487 | ||
488 | //Set_DSP_Cache(); | 488 | //Set_DSP_Cache(); |
489 | 489 | ||
490 | // Only core 0 can set these | 490 | // Only core 0 can set these |
491 | if (DNUM == 0) | 491 | if (DNUM == 0) |
492 | { | 492 | { |
493 | // Setup main PLL DSP @ 1 GHz | 493 | // Setup main PLL DSP @ 1 GHz |
494 | Set_Pll1(3); // call Set_Pll1 with index = 3 -> 100 MHz to 1 GHz operation | 494 | Set_Pll1(3); // call Set_Pll1 with index = 3 -> 100 MHz to 1 GHz operation |
495 | 495 | ||
496 | // Setup all Power Domains on | 496 | // Setup all Power Domains on |
497 | Set_Psc_All_On(); | 497 | Set_Psc_All_On(); |
498 | 498 | ||
499 | // Setup PA PLL | 499 | // Setup PA PLL |
500 | PaPllConfig(); | 500 | PaPllConfig(); |
501 | 501 | ||
502 | GEL_TextOut("DDR begin\n"); | 502 | GEL_TextOut("DDR begin\n"); |
503 | xmc_setup(); | 503 | xmc_setup(); |
504 | ddr3A_64bit_DDR1600_setup(); | 504 | ddr3A_64bit_DDR1600_setup(); |
505 | GEL_TextOut("DDR done\n"); | 505 | GEL_TextOut("DDR done\n"); |
506 | } | 506 | } |
507 | } | 507 | } |
508 | 508 | ||
509 | /**************************************************************************** | 509 | /**************************************************************************** |
510 | * | 510 | * |
511 | * NAME | 511 | * NAME |
512 | * Set_PSC_State | 512 | * Set_PSC_State |
513 | * | 513 | * |
514 | * PURPOSE: | 514 | * PURPOSE: |
515 | * Set a new power state for the specified domain id in a power controler | 515 | * Set a new power state for the specified domain id in a power controler |
516 | * domain. Wait for the power transition to complete. | 516 | * domain. Wait for the power transition to complete. |
517 | * | 517 | * |
518 | * USAGE | 518 | * USAGE |
519 | * This routine can be called as: | 519 | * This routine can be called as: |
520 | * | 520 | * |
521 | * Set_PSC_State(unsigned int pd,unsigned int id,unsigned int state) | 521 | * Set_PSC_State(unsigned int pd,unsigned int id,unsigned int state) |
522 | * | 522 | * |
523 | * pd - (i) power domain. | 523 | * pd - (i) power domain. |
524 | * | 524 | * |
525 | * id - (i) module id to use for module in the specified power domain | 525 | * id - (i) module id to use for module in the specified power domain |
526 | * | 526 | * |
527 | * state - (i) new state value to set | 527 | * state - (i) new state value to set |
528 | * 0 = RESET | 528 | * 0 = RESET |
529 | * 1 = SYNC RESET | 529 | * 1 = SYNC RESET |
530 | * 2 = DISABLE | 530 | * 2 = DISABLE |
531 | * 3 = ENABLE | 531 | * 3 = ENABLE |
532 | * | 532 | * |
533 | * RETURN VALUE | 533 | * RETURN VALUE |
534 | * 0 if ok, !=0 for error | 534 | * 0 if ok, !=0 for error |
535 | * | 535 | * |
536 | * REFERENCE | 536 | * REFERENCE |
537 | * | 537 | * |
538 | ****************************************************************************/ | 538 | ****************************************************************************/ |
539 | Set_PSC_State(unsigned int pd,unsigned int id,unsigned int state) | 539 | Set_PSC_State(unsigned int pd,unsigned int id,unsigned int state) |
540 | { | 540 | { |
541 | unsigned int* mdctl; | 541 | unsigned int* mdctl; |
542 | unsigned int* mdstat; | 542 | unsigned int* mdstat; |
543 | unsigned int* pdctl; | 543 | unsigned int* pdctl; |
544 | int ret=0; | 544 | int ret=0; |
545 | 545 | ||
546 | // Only core0 can set PSC | 546 | // Only core0 can set PSC |
547 | if (DNUM == 0) | 547 | if (DNUM == 0) |
548 | { | 548 | { |
549 | mdctl = ( unsigned int* )(PSC_MDCTL_BASE + ( 4 * id )); | 549 | mdctl = ( unsigned int* )(PSC_MDCTL_BASE + ( 4 * id )); |
550 | mdstat = ( unsigned int* )( PSC_MDSTAT_BASE + ( 4 * id )); | 550 | mdstat = ( unsigned int* )( PSC_MDSTAT_BASE + ( 4 * id )); |
551 | pdctl = ( unsigned int* )(PSC_PDCTL_BASE + ( 4 * pd )); | 551 | pdctl = ( unsigned int* )(PSC_PDCTL_BASE + ( 4 * pd )); |
552 | 552 | ||
553 | // If state is already set, do nothing | 553 | // If state is already set, do nothing |
554 | if ( ( *mdstat & 0x1f ) == state ) | 554 | if ( ( *mdstat & 0x1f ) == state ) |
555 | { | 555 | { |
556 | return(0); | 556 | return(0); |
557 | } | 557 | } |
558 | 558 | ||
559 | // Wait for GOSTAT to clear | 559 | // Wait for GOSTAT to clear |
560 | Set_Timeout(GTIMEOUT); | 560 | Set_Timeout(GTIMEOUT); |
561 | while( Get_Timeout() && (PSC_PTSTAT & (0x1 << pd)) != 0 ); | 561 | while( Get_Timeout() && (PSC_PTSTAT & (0x1 << pd)) != 0 ); |
562 | 562 | ||
563 | // Check if we got timeout error while waiting | 563 | // Check if we got timeout error while waiting |
564 | if (!Get_Timeout()) | 564 | if (!Get_Timeout()) |
565 | { | 565 | { |
566 | GEL_TextOut( "Set_PSC_State... Timeout Error #01 pd=%d, md=%d!\n",,2,,,pd,id); | 566 | GEL_TextOut( "Set_PSC_State... Timeout Error #01 pd=%d, md=%d!\n",,2,,,pd,id); |
567 | ret=1; | 567 | ret=1; |
568 | } | 568 | } |
569 | else | 569 | else |
570 | { | 570 | { |
571 | // Set power domain control | 571 | // Set power domain control |
572 | *pdctl = (*pdctl) | 0x00000001; | 572 | *pdctl = (*pdctl) | 0x00000001; |
573 | 573 | ||
574 | // Set MDCTL NEXT to new state | 574 | // Set MDCTL NEXT to new state |
575 | *mdctl = ((*mdctl) & ~(0x1f)) | state; | 575 | *mdctl = ((*mdctl) & ~(0x1f)) | state; |
576 | 576 | ||
577 | // Start power transition by setting PTCMD GO to 1 | 577 | // Start power transition by setting PTCMD GO to 1 |
578 | PSC_PTCMD = (PSC_PTCMD) | (0x1<<pd); | 578 | PSC_PTCMD = (PSC_PTCMD) | (0x1<<pd); |
579 | 579 | ||
580 | // Wait for PTSTAT GOSTAT to clear | 580 | // Wait for PTSTAT GOSTAT to clear |
581 | Set_Timeout(GTIMEOUT); | 581 | Set_Timeout(GTIMEOUT); |
582 | while( Get_Timeout() && (PSC_PTSTAT & (0x1 << pd)) != 0 ); | 582 | while( Get_Timeout() && (PSC_PTSTAT & (0x1 << pd)) != 0 ); |
583 | 583 | ||
584 | // Check if we got timeout error while waiting | 584 | // Check if we got timeout error while waiting |
585 | if (!Get_Timeout()) | 585 | if (!Get_Timeout()) |
586 | { | 586 | { |
587 | GEL_TextOut( "Set_PSC_State... Timeout Error #02 pd=%d, md=%d!\n",,2,,,pd,id); | 587 | GEL_TextOut( "Set_PSC_State... Timeout Error #02 pd=%d, md=%d!\n",,2,,,pd,id); |
588 | ret=2; | 588 | ret=2; |
589 | } | 589 | } |
590 | else | 590 | else |
591 | { | 591 | { |
592 | // Verify state changed | 592 | // Verify state changed |
593 | Set_Timeout(GTIMEOUT); | 593 | Set_Timeout(GTIMEOUT); |
594 | while(Get_Timeout() && ( *mdstat & 0x1f ) != state ); | 594 | while(Get_Timeout() && ( *mdstat & 0x1f ) != state ); |
595 | 595 | ||
596 | // Check if we got timeout error while waiting | 596 | // Check if we got timeout error while waiting |
597 | if (!Get_Timeout()) | 597 | if (!Get_Timeout()) |
598 | { | 598 | { |
599 | GEL_TextOut( "Set_PSC_State... Timeout Error #03 pd=%d, md=%d!\n",,2,,,pd,id); | 599 | GEL_TextOut( "Set_PSC_State... Timeout Error #03 pd=%d, md=%d!\n",,2,,,pd,id); |
600 | ret=3; | 600 | ret=3; |
601 | } | 601 | } |
602 | } | 602 | } |
603 | } | 603 | } |
604 | 604 | ||
605 | // Kill the currently running timeout | 605 | // Kill the currently running timeout |
606 | Kill_Timeout(); | 606 | Kill_Timeout(); |
607 | } | 607 | } |
608 | else | 608 | else |
609 | { | 609 | { |
610 | GEL_TextOut("DSP core #%d cannot set PSC.\n",,2,,,DNUM); | 610 | GEL_TextOut("DSP core #%d cannot set PSC.\n",,2,,,DNUM); |
611 | } | 611 | } |
612 | 612 | ||
613 | return(ret); | 613 | return(ret); |
614 | } | 614 | } |
615 | 615 | ||
616 | /**************************************************************************** | 616 | /**************************************************************************** |
617 | * | 617 | * |
618 | * NAME | 618 | * NAME |
619 | * Set_Timeout | 619 | * Set_Timeout |
620 | * | 620 | * |
621 | * PURPOSE: | 621 | * PURPOSE: |
622 | * Starts a timeout period of msec. The running timeout period can be | 622 | * Starts a timeout period of msec. The running timeout period can be |
623 | * query with Get_Timeout. To kill a running timeout before the end, | 623 | * query with Get_Timeout. To kill a running timeout before the end, |
624 | * call Kill_Timeout. Only one timeout period can be used at any time. | 624 | * call Kill_Timeout. Only one timeout period can be used at any time. |
625 | * A timeout period can be used to measure a period of time while doing | 625 | * A timeout period can be used to measure a period of time while doing |
626 | * anything else. Not accurate, sets timer at least as big as desired. | 626 | * anything else. Not accurate, sets timer at least as big as desired. |
627 | * | 627 | * |
628 | * USAGE | 628 | * USAGE |
629 | * This routine can be called as: | 629 | * This routine can be called as: |
630 | * | 630 | * |
631 | * Set_Timeout(msec) | 631 | * Set_Timeout(msec) |
632 | * | 632 | * |
633 | * msec - (i) timeout period in msec (not very precise < sec range) | 633 | * msec - (i) timeout period in msec (not very precise < sec range) |
634 | * | 634 | * |
635 | * RETURN VALUE | 635 | * RETURN VALUE |
636 | * NONE | 636 | * NONE |
637 | * | 637 | * |
638 | * REFERENCE | 638 | * REFERENCE |
639 | * | 639 | * |
640 | ****************************************************************************/ | 640 | ****************************************************************************/ |
641 | Set_Timeout(msec) | 641 | Set_Timeout(msec) |
642 | { | 642 | { |
643 | // Cancel the current timer if not already expired | 643 | // Cancel the current timer if not already expired |
644 | GEL_CancelTimer(TIMEOUT_ID); | 644 | GEL_CancelTimer(TIMEOUT_ID); |
645 | 645 | ||
646 | // Starts the timeout period | 646 | // Starts the timeout period |
647 | _GEL_Global_Timeout1=1; | 647 | _GEL_Global_Timeout1=1; |
648 | 648 | ||
649 | // Setup a callback routine with specified timeout | 649 | // Setup a callback routine with specified timeout |
650 | GEL_SetTimer(msec, TIMEOUT_ID, "_Timeout_Callback()"); | 650 | GEL_SetTimer(msec, TIMEOUT_ID, "_Timeout_Callback()"); |
651 | } | 651 | } |
652 | 652 | ||
653 | /**************************************************************************** | 653 | /**************************************************************************** |
654 | * | 654 | * |
655 | * NAME | 655 | * NAME |
656 | * Get_Timeout | 656 | * Get_Timeout |
657 | * | 657 | * |
658 | * PURPOSE: | 658 | * PURPOSE: |
659 | * Query the running state of a timeout period started by Set_Timeout. | 659 | * Query the running state of a timeout period started by Set_Timeout. |
660 | * (see Set_Timeout for more info). | 660 | * (see Set_Timeout for more info). |
661 | * | 661 | * |
662 | * USAGE | 662 | * USAGE |
663 | * This routine can be called as: | 663 | * This routine can be called as: |
664 | * | 664 | * |
665 | * Get_Timeout() | 665 | * Get_Timeout() |
666 | * | 666 | * |
667 | * RETURN VALUE | 667 | * RETURN VALUE |
668 | * 0:expired, 1:running | 668 | * 0:expired, 1:running |
669 | * | 669 | * |
670 | * REFERENCE | 670 | * REFERENCE |
671 | * | 671 | * |
672 | ****************************************************************************/ | 672 | ****************************************************************************/ |
673 | Get_Timeout() | 673 | Get_Timeout() |
674 | { | 674 | { |
675 | if (!_GEL_Global_Timeout1) | 675 | if (!_GEL_Global_Timeout1) |
676 | { | 676 | { |
677 | // Cancel the current timer | 677 | // Cancel the current timer |
678 | GEL_CancelTimer(TIMEOUT_ID); | 678 | GEL_CancelTimer(TIMEOUT_ID); |
679 | } | 679 | } |
680 | 680 | ||
681 | // Return the global timeout status 1=running, 0=expired | 681 | // Return the global timeout status 1=running, 0=expired |
682 | return _GEL_Global_Timeout1; | 682 | return _GEL_Global_Timeout1; |
683 | } | 683 | } |
684 | 684 | ||
685 | /**************************************************************************** | 685 | /**************************************************************************** |
686 | * | 686 | * |
687 | * NAME | 687 | * NAME |
688 | * Kill_Timeout | 688 | * Kill_Timeout |
689 | * | 689 | * |
690 | * PURPOSE: | 690 | * PURPOSE: |
691 | * Cancel a running timeout period before it expires | 691 | * Cancel a running timeout period before it expires |
692 | * (see Set_Timeout for more info). | 692 | * (see Set_Timeout for more info). |
693 | * | 693 | * |
694 | * USAGE | 694 | * USAGE |
695 | * This routine can be called as: | 695 | * This routine can be called as: |
696 | * | 696 | * |
697 | * Kill_Timeout() | 697 | * Kill_Timeout() |
698 | * | 698 | * |
699 | * RETURN VALUE | 699 | * RETURN VALUE |
700 | * NONE | 700 | * NONE |
701 | * | 701 | * |
702 | * REFERENCE | 702 | * REFERENCE |
703 | * | 703 | * |
704 | ****************************************************************************/ | 704 | ****************************************************************************/ |
705 | Kill_Timeout() | 705 | Kill_Timeout() |
706 | { | 706 | { |
707 | // Cancel the current timer | 707 | // Cancel the current timer |
708 | GEL_CancelTimer(TIMEOUT_ID); | 708 | GEL_CancelTimer(TIMEOUT_ID); |
709 | 709 | ||
710 | // The timeout period is expired | 710 | // The timeout period is expired |
711 | _GEL_Global_Timeout1=0; | 711 | _GEL_Global_Timeout1=0; |
712 | } | 712 | } |
713 | 713 | ||
714 | /**************************************************************************** | 714 | /**************************************************************************** |
715 | * | 715 | * |
716 | * NAME | 716 | * NAME |
717 | * _Timeout_Callback | 717 | * _Timeout_Callback |
718 | * | 718 | * |
719 | * PURPOSE: | 719 | * PURPOSE: |
720 | * Internal Callback function used by Set_timeout | 720 | * Internal Callback function used by Set_timeout |
721 | * (see Set_Timeout for more info). | 721 | * (see Set_Timeout for more info). |
722 | * | 722 | * |
723 | * USAGE | 723 | * USAGE |
724 | * This routine must not be called by itself. | 724 | * This routine must not be called by itself. |
725 | * | 725 | * |
726 | * RETURN VALUE | 726 | * RETURN VALUE |
727 | * NONE | 727 | * NONE |
728 | * | 728 | * |
729 | * REFERENCE | 729 | * REFERENCE |
730 | * | 730 | * |
731 | ****************************************************************************/ | 731 | ****************************************************************************/ |
732 | _Timeout_Callback() | 732 | _Timeout_Callback() |
733 | { | 733 | { |
734 | // The timeout period is expired | 734 | // The timeout period is expired |
735 | _GEL_Global_Timeout1=0; | 735 | _GEL_Global_Timeout1=0; |
736 | } | 736 | } |
737 | 737 | ||
738 | 738 | ||
739 | /**************************************************************************** | 739 | /**************************************************************************** |
740 | * | 740 | * |
741 | * NAME | 741 | * NAME |
742 | * Set_Psc_All_On | 742 | * Set_Psc_All_On |
743 | * | 743 | * |
744 | * PURPOSE: | 744 | * PURPOSE: |
745 | * Enable all PSC modules and DSP power domains on ALWAYSON, and wait | 745 | * Enable all PSC modules and DSP power domains on ALWAYSON, and wait |
746 | * for these power transitions to complete. | 746 | * for these power transitions to complete. |
747 | * | 747 | * |
748 | * USAGE | 748 | * USAGE |
749 | * This routine can be called as: | 749 | * This routine can be called as: |
750 | * | 750 | * |
751 | * Set_Psc_All_On() | 751 | * Set_Psc_All_On() |
752 | * | 752 | * |
753 | * RETURN VALUE | 753 | * RETURN VALUE |
754 | * NONE | 754 | * NONE |
755 | * | 755 | * |
756 | * REFERENCE | 756 | * REFERENCE |
757 | * | 757 | * |
758 | ****************************************************************************/ | 758 | ****************************************************************************/ |
759 | hotmenu Set_Psc_All_On( ) | 759 | hotmenu Set_Psc_All_On( ) |
760 | { | 760 | { |
761 | unsigned int i=0; | 761 | unsigned int i=0; |
762 | 762 | ||
763 | // Only core0 can set PSC | 763 | // Only core0 can set PSC |
764 | if (DNUM == 0) | 764 | if (DNUM == 0) |
765 | { | 765 | { |
766 | GEL_TextOut( "Power on all PSC modules and DSP domains... \n"); | 766 | GEL_TextOut( "Power on all PSC modules and DSP domains... \n"); |
767 | 767 | ||
768 | Set_PSC_State(PD0, LPSC_TSIP, PSC_ENABLE); | 768 | Set_PSC_State(PD0, LPSC_TSIP, PSC_ENABLE); |
769 | Set_PSC_State(PD1, LPSC_DEBUG, PSC_ENABLE); | 769 | Set_PSC_State(PD1, LPSC_DEBUG, PSC_ENABLE); |
770 | Set_PSC_State(PD1, LPSC_TETB, PSC_ENABLE); | 770 | Set_PSC_State(PD1, LPSC_TETB, PSC_ENABLE); |
771 | Set_PSC_State(PD2, LPSC_PA, PSC_ENABLE); | 771 | Set_PSC_State(PD2, LPSC_PA, PSC_ENABLE); |
772 | Set_PSC_State(PD2, LPSC_SGMII, PSC_ENABLE); | 772 | Set_PSC_State(PD2, LPSC_SGMII, PSC_ENABLE); |
773 | // Set_PSC_State(PD2, LPSC_SA, PSC_ENABLE); | 773 | // Set_PSC_State(PD2, LPSC_SA, PSC_ENABLE); |
774 | Set_PSC_State(PD3, LPSC_PCIE, PSC_ENABLE); | 774 | Set_PSC_State(PD3, LPSC_PCIE, PSC_ENABLE); |
775 | Set_PSC_State(PD5, LPSC_HYPERLINK, PSC_ENABLE); | 775 | Set_PSC_State(PD5, LPSC_HYPERLINK, PSC_ENABLE); |
776 | Set_PSC_State(PD6, LPSC_SR, PSC_ENABLE); | 776 | Set_PSC_State(PD6, LPSC_SR, PSC_ENABLE); |
777 | Set_PSC_State(PD7, LPSC_MSMCRAM, PSC_ENABLE); | 777 | Set_PSC_State(PD7, LPSC_MSMCRAM, PSC_ENABLE); |
778 | Set_PSC_State(PD8, LPSC_C66X_COREPAC_0, PSC_ENABLE); | 778 | Set_PSC_State(PD8, LPSC_C66X_COREPAC_0, PSC_ENABLE); |
779 | Set_PSC_State(PD16, LPSC_DDR3_0, PSC_ENABLE); | 779 | Set_PSC_State(PD16, LPSC_DDR3_0, PSC_ENABLE); |
780 | Set_PSC_State(PD18, LPSC_PCIE_1, PSC_ENABLE); | 780 | Set_PSC_State(PD18, LPSC_PCIE_1, PSC_ENABLE); |
781 | Set_PSC_State(PD29, LPSC_XGE, PSC_ENABLE); | 781 | Set_PSC_State(PD29, LPSC_XGE, PSC_ENABLE); |
782 | Set_PSC_State(PD31, LPSC_ARM, PSC_ENABLE); | 782 | Set_PSC_State(PD31, LPSC_ARM, PSC_ENABLE); |
783 | 783 | ||
784 | GEL_TextOut( "Power on all PSC modules and DSP domains... Done.\n" ); | 784 | GEL_TextOut( "Power on all PSC modules and DSP domains... Done.\n" ); |
785 | } | 785 | } |
786 | else | 786 | else |
787 | { | 787 | { |
788 | GEL_TextOut("DSP core #%d cannot set PSC.\n",,2,,,DNUM); | 788 | GEL_TextOut("DSP core #%d cannot set PSC.\n",,2,,,DNUM); |
789 | } | 789 | } |
790 | } | 790 | } |
791 | 791 | ||
792 | 792 | ||
793 | //******************************************************************************************************************************** | 793 | //******************************************************************************************************************************** |
794 | //******************************************************************************************************************************** | 794 | //******************************************************************************************************************************** |
795 | /* | 795 | /* |
796 | Set_Pll1() - This function executes the main PLL initialization | 796 | Set_Pll1() - This function executes the main PLL initialization |
797 | sequence needed to get the main PLL up after coming out of an initial power up | 797 | sequence needed to get the main PLL up after coming out of an initial power up |
798 | before it is locked or after it is already locked. | 798 | before it is locked or after it is already locked. |
799 | 799 | ||
800 | Index value determines multiplier, divier used and clock reference assumed for | 800 | Index value determines multiplier, divier used and clock reference assumed for |
801 | output display. | 801 | output display. |
802 | */ | 802 | */ |
803 | Set_Pll1(int index) | 803 | Set_Pll1(int index) |
804 | { | 804 | { |
805 | int i, TEMP; | 805 | int i, TEMP; |
806 | unsigned int BYPASS_val; | 806 | unsigned int BYPASS_val; |
807 | unsigned int BWADJ_val; | 807 | unsigned int BWADJ_val; |
808 | unsigned int OD_val; | 808 | unsigned int OD_val; |
809 | 809 | ||
810 | float CLKIN_val; | 810 | float CLKIN_val; |
811 | unsigned int PLLM_val; | 811 | unsigned int PLLM_val; |
812 | unsigned int PLLD_val; | 812 | unsigned int PLLD_val; |
813 | unsigned int PLLDIV3_val; //example value for SYSCLK2 (from 6614 spec) Default /2 - Fast Peripherals, (L2, MSMC, DDR3 EMIF, EDMA0...) | 813 | unsigned int PLLDIV3_val; //example value for SYSCLK2 (from 6614 spec) Default /2 - Fast Peripherals, (L2, MSMC, DDR3 EMIF, EDMA0...) |
814 | unsigned int PLLDIV4_val; //example value for SYSCLK3 (from 6614 spec) Default /3 - Switch Fabric | 814 | unsigned int PLLDIV4_val; //example value for SYSCLK3 (from 6614 spec) Default /3 - Switch Fabric |
815 | unsigned int PLLDIV7_val; //example value for SYSCLK6 (from 6614 spec) Defualt /6 - Slow Peripherals (UART, SPI, I2C, GPIO...) | 815 | unsigned int PLLDIV7_val; //example value for SYSCLK6 (from 6614 spec) Defualt /6 - Slow Peripherals (UART, SPI, I2C, GPIO...) |
816 | 816 | ||
817 | unsigned int debug_info_on; | 817 | unsigned int debug_info_on; |
818 | unsigned int delay; | 818 | unsigned int delay; |
819 | 819 | ||
820 | if(index == 1){ // 100 MHz -> 614.28 MHz | 820 | if(index == 1){ // 100 MHz -> 614.28 MHz |
821 | CLKIN_val = 100; // setup CLKIN to 614.28 MHz | 821 | CLKIN_val = 100; // setup CLKIN to 614.28 MHz |
822 | PLLM_val = 43; // setup PLLM (PLL multiplier) to x43 | 822 | PLLM_val = 43; // setup PLLM (PLL multiplier) to x43 |
823 | PLLD_val = 1; // setup PLLD (reference divider) to /1 | 823 | PLLD_val = 1; // setup PLLD (reference divider) to /1 |
824 | OD_val = 7; // setup OD to /7 | 824 | OD_val = 7; // setup OD to /7 |
825 | } | 825 | } |
826 | else if(index == 2){ // 100MHz -> 737.5 MHz | 826 | else if(index == 2){ // 100MHz -> 737.5 MHz |
827 | CLKIN_val = 100; // setup CLKIN to 100 MHz | 827 | CLKIN_val = 100; // setup CLKIN to 100 MHz |
828 | PLLM_val = 59; // setup PLLM (PLL multiplier) to x59 | 828 | PLLM_val = 59; // setup PLLM (PLL multiplier) to x59 |
829 | PLLD_val = 1; // setup PLLD (reference divider) to /1 | 829 | PLLD_val = 1; // setup PLLD (reference divider) to /1 |
830 | OD_val = 8; // setup OD to /8 | 830 | OD_val = 8; // setup OD to /8 |
831 | } | 831 | } |
832 | 832 | ||
833 | else if(index == 3){ // 100MHz -> 1 GHz | 833 | else if(index == 3){ // 100MHz -> 1 GHz |
834 | CLKIN_val = 100; // setup CLKIN to 100 MHz | 834 | CLKIN_val = 100; // setup CLKIN to 100 MHz |
835 | PLLM_val = 20; // setup PLLM (PLL multiplier) to x20 | 835 | PLLM_val = 20; // setup PLLM (PLL multiplier) to x20 |
836 | PLLD_val = 1; // setup PLLD (reference divider) to /1 | 836 | PLLD_val = 1; // setup PLLD (reference divider) to /1 |
837 | OD_val = 2; // setup OD to /2 | 837 | OD_val = 2; // setup OD to /2 |
838 | } | 838 | } |
839 | 839 | ||
840 | else if(index == 4){ // 100 MHz -> 1.2 GHz | 840 | else if(index == 4){ // 100 MHz -> 1.2 GHz |
841 | CLKIN_val = 100; // setup CLKIN to 100 MHz | 841 | CLKIN_val = 100; // setup CLKIN to 100 MHz |
842 | PLLM_val = 24; // setup PLLM (PLL multiplier) to x24 | 842 | PLLM_val = 24; // setup PLLM (PLL multiplier) to x24 |
843 | PLLD_val = 1; // setup PLLD (reference divider) to /1 | 843 | PLLD_val = 1; // setup PLLD (reference divider) to /1 |
844 | OD_val = 2; // setup OD to /2 | 844 | OD_val = 2; // setup OD to /2 |
845 | } | 845 | } |
846 | else if(index == 5){ // 100 MHz -> 1.35 GHz | 846 | else if(index == 5){ // 100 MHz -> 1.35 GHz |
847 | CLKIN_val = 100; // setup CLKIN to 100 MHz | 847 | CLKIN_val = 100; // setup CLKIN to 100 MHz |
848 | PLLM_val = 27; // setup PLLM (PLL multiplier) to x27 | 848 | PLLM_val = 27; // setup PLLM (PLL multiplier) to x27 |
849 | PLLD_val = 1; // setup PLLD (reference divider) to /1 | 849 | PLLD_val = 1; // setup PLLD (reference divider) to /1 |
850 | OD_val = 2; // setup OD to /2 | 850 | OD_val = 2; // setup OD to /2 |
851 | } | 851 | } |
852 | 852 | ||
853 | 853 | ||
854 | 854 | ||
855 | 855 | ||
856 | PLLDIV3_val = 3; // setup PLL output divider 3 to /3 | 856 | PLLDIV3_val = 3; // setup PLL output divider 3 to /3 |
857 | PLLDIV4_val = 5; // setup PLL output divider 4 to /3 | 857 | PLLDIV4_val = 5; // setup PLL output divider 4 to /3 |
858 | PLLDIV7_val = 6; // setup PLL output divider 7 to /6 | 858 | PLLDIV7_val = 6; // setup PLL output divider 7 to /6 |
859 | 859 | ||
860 | BYPASS_val = PLL1_SECCTL & ~BYPASS_MASK; // get value of the BYPASS field | 860 | BYPASS_val = PLL1_SECCTL & ~BYPASS_MASK; // get value of the BYPASS field |
861 | BWADJ_val = (PLLM_val) >> 1; // setup BWADJ to be 1/2 the value of PLLM | 861 | BWADJ_val = (PLLM_val) >> 1; // setup BWADJ to be 1/2 the value of PLLM |
862 | //OD_val = 2; // setup OD to a fixed /2 | 862 | //OD_val = 2; // setup OD to a fixed /2 |
863 | 863 | ||
864 | debug_info_on = 1; | 864 | debug_info_on = 1; |
865 | delay = 1000; // fix this! | 865 | delay = 1000; // fix this! |
866 | 866 | ||
867 | /* Step 1: Unlock Boot Config Registers */ | 867 | /* Step 1: Unlock Boot Config Registers */ |
868 | KICK0 = KICK0_UNLOCK; | 868 | KICK0 = KICK0_UNLOCK; |
869 | KICK1 = KICK1_UNLOCK; | 869 | KICK1 = KICK1_UNLOCK; |
870 | 870 | ||
871 | /* Step 2: Check if SECCTL bypass is low or high indicating what state the Main PLL is currently in. if | 871 | /* Step 2: Check if SECCTL bypass is low or high indicating what state the Main PLL is currently in. if |
872 | the Main PLL is in bypass still (not yet setup) execute the following steps. */ | 872 | the Main PLL is in bypass still (not yet setup) execute the following steps. */ |
873 | 873 | ||
874 | if(BYPASS_val != 0x00000000){ // PLL bypass enabled - Execute PLL setup for PLL fresh out of power on reset | 874 | if(BYPASS_val != 0x00000000){ // PLL bypass enabled - Execute PLL setup for PLL fresh out of power on reset |
875 | if(debug_info_on){ | 875 | if(debug_info_on){ |
876 | GEL_TextOut("Detected PLL bypass enabled: SECCTL[BYPASS] = %x\n",,,,, BYPASS_val); | 876 | GEL_TextOut("Detected PLL bypass enabled: SECCTL[BYPASS] = %x\n",,,,, BYPASS_val); |
877 | } | 877 | } |
878 | /* Step 2a: Set MAINPLLCTL1[ENSAT] = 1 - This enables proper biasing of PLL analog circuitry */ | 878 | /* Step 2a: Set MAINPLLCTL1[ENSAT] = 1 - This enables proper biasing of PLL analog circuitry */ |
879 | MAINPLLCTL1 |= (1 << MAIN_ENSAT_OFFSET); | 879 | MAINPLLCTL1 |= (1 << MAIN_ENSAT_OFFSET); |
880 | if(debug_info_on){ | 880 | if(debug_info_on){ |
881 | GEL_TextOut("(2a) MAINPLLCTL1 = %x\n",,,,, MAINPLLCTL1); | 881 | GEL_TextOut("(2a) MAINPLLCTL1 = %x\n",,,,, MAINPLLCTL1); |
882 | } | 882 | } |
883 | 883 | ||
884 | /* Step 2b: Set PLLCTL[PLLEN] = 0 This enables bypass in PLL controller MUX */ | 884 | /* Step 2b: Set PLLCTL[PLLEN] = 0 This enables bypass in PLL controller MUX */ |
885 | PLL1_PLLCTL &= ~(1 << PLLEN_OFFSET); | 885 | PLL1_PLLCTL &= ~(1 << PLLEN_OFFSET); |
886 | if(debug_info_on){ | 886 | if(debug_info_on){ |
887 | GEL_TextOut("(2b) PLLCTL = %x\n",,,,, PLL1_PLLCTL); | 887 | GEL_TextOut("(2b) PLLCTL = %x\n",,,,, PLL1_PLLCTL); |
888 | } | 888 | } |
889 | 889 | ||
890 | /* Step 2c: Set PLLCTL[PLLENSRC] = 0 - This enables PLLEN to control PLL controller MUX */ | 890 | /* Step 2c: Set PLLCTL[PLLENSRC] = 0 - This enables PLLEN to control PLL controller MUX */ |
891 | PLL1_PLLCTL &= ~(1 << PLLENSRC_OFFSET); | 891 | PLL1_PLLCTL &= ~(1 << PLLENSRC_OFFSET); |
892 | if(debug_info_on){ | 892 | if(debug_info_on){ |
893 | GEL_TextOut("(2c) PLLCTL = %x\n",,,,, PLL1_PLLCTL); | 893 | GEL_TextOut("(2c) PLLCTL = %x\n",,,,, PLL1_PLLCTL); |
894 | } | 894 | } |
895 | 895 | ||
896 | /* Step 2d: Wait 4 reference clock cycles (slowest of ALTCORE or SYSCLK) to make sure | 896 | /* Step 2d: Wait 4 reference clock cycles (slowest of ALTCORE or SYSCLK) to make sure |
897 | that the PLL controller MUX switches properly to bypass. */ | 897 | that the PLL controller MUX switches properly to bypass. */ |
898 | if(debug_info_on){ | 898 | if(debug_info_on){ |
899 | GEL_TextOut("(2d) Delay...\n",,,,,); | 899 | GEL_TextOut("(2d) Delay...\n",,,,,); |
900 | } | 900 | } |
901 | for(i = 0; i < delay; i++); // this delay is much more than required | 901 | for(i = 0; i < delay; i++); // this delay is much more than required |
902 | 902 | ||
903 | /* Step 2e: Set SECCTL[BYPASS] = 1 - enables bypass in PLL MUX */ | 903 | /* Step 2e: Set SECCTL[BYPASS] = 1 - enables bypass in PLL MUX */ |
904 | PLL1_SECCTL |= (1 << BYPASS_OFFSET); | 904 | PLL1_SECCTL |= (1 << BYPASS_OFFSET); |
905 | if(debug_info_on){ | 905 | if(debug_info_on){ |
906 | GEL_TextOut("(2e) SECCTL = %x\n",,,,, PLL1_SECCTL); | 906 | GEL_TextOut("(2e) SECCTL = %x\n",,,,, PLL1_SECCTL); |
907 | } | 907 | } |
908 | 908 | ||
909 | /* Step 2f: Set PLLCTL[PLLPWRDN] = 1 - power down the PLL */ | 909 | /* Step 2f: Set PLLCTL[PLLPWRDN] = 1 - power down the PLL */ |
910 | PLL1_PLLCTL |= (1 << PLLPWRDN_OFFSET); | 910 | PLL1_PLLCTL |= (1 << PLLPWRDN_OFFSET); |
911 | if(debug_info_on){ | 911 | if(debug_info_on){ |
912 | GEL_TextOut("(2f) PLLCTL = %x\n",,,,, PLL1_PLLCTL); | 912 | GEL_TextOut("(2f) PLLCTL = %x\n",,,,, PLL1_PLLCTL); |
913 | } | 913 | } |
914 | 914 | ||
915 | /* Step 2g: Wait for at least 5us for the PLL to power down */ | 915 | /* Step 2g: Wait for at least 5us for the PLL to power down */ |
916 | if(debug_info_on){ | 916 | if(debug_info_on){ |
917 | GEL_TextOut("(2g) Delay...\n",,,,,); | 917 | GEL_TextOut("(2g) Delay...\n",,,,,); |
918 | } | 918 | } |
919 | for(i = 0; i < delay; i++); // this delay is much more than required | 919 | for(i = 0; i < delay; i++); // this delay is much more than required |
920 | 920 | ||
921 | /* Step 2h: Set PLLCTL[PLLPWRDN] = 0 - Power the PLL back up */ | 921 | /* Step 2h: Set PLLCTL[PLLPWRDN] = 0 - Power the PLL back up */ |
922 | PLL1_PLLCTL &= ~(1 << PLLPWRDN_OFFSET); | 922 | PLL1_PLLCTL &= ~(1 << PLLPWRDN_OFFSET); |
923 | if(debug_info_on){ | 923 | if(debug_info_on){ |
924 | GEL_TextOut("(2h) PLLCTL = %x\n",,,,, PLL1_PLLCTL); | 924 | GEL_TextOut("(2h) PLLCTL = %x\n",,,,, PLL1_PLLCTL); |
925 | } | 925 | } |
926 | 926 | ||
927 | } | 927 | } |
928 | else{ // PLL bypass disabled - Execute PLL setup for PLL that has previously been locked (skip to Step 3) | 928 | else{ // PLL bypass disabled - Execute PLL setup for PLL that has previously been locked (skip to Step 3) |
929 | if(debug_info_on){ | 929 | if(debug_info_on){ |
930 | GEL_TextOut("Detected PLL bypass disabled: SECCTL[BYPASS] = %x\n",,,,, BYPASS_val); | 930 | GEL_TextOut("Detected PLL bypass disabled: SECCTL[BYPASS] = %x\n",,,,, BYPASS_val); |
931 | } | 931 | } |
932 | 932 | ||
933 | /* Step 3a: Set PLLCTL[PLLEN] = 0 This enables bypass in PLL controller MUX */ | 933 | /* Step 3a: Set PLLCTL[PLLEN] = 0 This enables bypass in PLL controller MUX */ |
934 | PLL1_PLLCTL &= ~(1 << PLLEN_OFFSET); | 934 | PLL1_PLLCTL &= ~(1 << PLLEN_OFFSET); |
935 | if(debug_info_on){ | 935 | if(debug_info_on){ |
936 | GEL_TextOut("(3a) PLLCTL = %x\n",,,,, PLL1_PLLCTL); | 936 | GEL_TextOut("(3a) PLLCTL = %x\n",,,,, PLL1_PLLCTL); |
937 | } | 937 | } |
938 | 938 | ||
939 | /* Step 3b: Set PLLCTL[PLLENSRC] = 0 - This enables PLLEN to control PLL controller MUX */ | 939 | /* Step 3b: Set PLLCTL[PLLENSRC] = 0 - This enables PLLEN to control PLL controller MUX */ |
940 | PLL1_PLLCTL &= ~(1 << PLLENSRC_OFFSET); | 940 | PLL1_PLLCTL &= ~(1 << PLLENSRC_OFFSET); |
941 | if(debug_info_on){ | 941 | if(debug_info_on){ |
942 | GEL_TextOut("(3b) PLLCTL = %x\n",,,,, PLL1_PLLCTL); | 942 | GEL_TextOut("(3b) PLLCTL = %x\n",,,,, PLL1_PLLCTL); |
943 | } | 943 | } |
944 | 944 | ||
945 | /* Step 3c: Wait 4 reference clock cycles (slowest of ALTCORE or SYSCLK) to make sure | 945 | /* Step 3c: Wait 4 reference clock cycles (slowest of ALTCORE or SYSCLK) to make sure |
946 | that the PLL controller MUX switches properly to bypass. */ | 946 | that the PLL controller MUX switches properly to bypass. */ |
947 | if(debug_info_on){ | 947 | if(debug_info_on){ |
948 | GEL_TextOut("(3c) Delay...\n",,,,,); | 948 | GEL_TextOut("(3c) Delay...\n",,,,,); |
949 | } | 949 | } |
950 | for(i = 0; i < delay; i++); // this delay is much more than required | 950 | for(i = 0; i < delay; i++); // this delay is much more than required |
951 | 951 | ||
952 | } | 952 | } |
953 | 953 | ||
954 | 954 | ||
955 | /* Step 4: Programming PLLM[5:0] in the PLLM register of the PLL controller and | 955 | /* Step 4: Programming PLLM[5:0] in the PLLM register of the PLL controller and |
956 | programming PLLM[12:6] in the MAINPLLCTL0 register */ | 956 | programming PLLM[12:6] in the MAINPLLCTL0 register */ |
957 | PLL1_PLLM &= PLLM_MASK; // clear the PLLM[5:0] bit field | 957 | PLL1_PLLM &= PLLM_MASK; // clear the PLLM[5:0] bit field |
958 | PLL1_PLLM |= ~PLLM_MASK & (PLLM_val - 1); // set the PLLM[5:0] bit field to the 6 LSB of PLLM_val | 958 | PLL1_PLLM |= ~PLLM_MASK & (PLLM_val - 1); // set the PLLM[5:0] bit field to the 6 LSB of PLLM_val |
959 | 959 | ||
960 | if(debug_info_on){ | 960 | if(debug_info_on){ |
961 | GEL_TextOut("(4)PLLM[PLLM] = %x\n",,,,, PLL1_PLLM); | 961 | GEL_TextOut("(4)PLLM[PLLM] = %x\n",,,,, PLL1_PLLM); |
962 | } | 962 | } |
963 | 963 | ||
964 | MAINPLLCTL0 &= MAIN_PLLM_MASK; // clear the PLLM[12:6] bit field | 964 | MAINPLLCTL0 &= MAIN_PLLM_MASK; // clear the PLLM[12:6] bit field |
965 | MAINPLLCTL0 |= ~MAIN_PLLM_MASK & (( (PLLM_val - 1) >> 6) << MAIN_PLLM_OFFSET); // set the PLLM[12:6] bit field to the 7 MSB of PLL_val | 965 | MAINPLLCTL0 |= ~MAIN_PLLM_MASK & (( (PLLM_val - 1) >> 6) << MAIN_PLLM_OFFSET); // set the PLLM[12:6] bit field to the 7 MSB of PLL_val |
966 | 966 | ||
967 | if(debug_info_on){ | 967 | if(debug_info_on){ |
968 | GEL_TextOut("MAINPLLCTL0 = %x\n",,,,, MAINPLLCTL0); | 968 | GEL_TextOut("MAINPLLCTL0 = %x\n",,,,, MAINPLLCTL0); |
969 | } | 969 | } |
970 | 970 | ||
971 | /* Step 5: Programming BWADJ[7:0] in the MAINPLLCTL0 register and BWADJ[11:8] in MAINPLLCTL1 register */ | 971 | /* Step 5: Programming BWADJ[7:0] in the MAINPLLCTL0 register and BWADJ[11:8] in MAINPLLCTL1 register */ |
972 | MAINPLLCTL0 &= MAIN_BWADJ0_MASK; // clear the MAIN_BWADJ0 bit field | 972 | MAINPLLCTL0 &= MAIN_BWADJ0_MASK; // clear the MAIN_BWADJ0 bit field |
973 | MAINPLLCTL0 |= ~MAIN_BWADJ0_MASK & ((BWADJ_val - 1) << MAIN_BWADJ0_OFFSET); // set the MAIN_BWADJ[7:0] bit field to the 8 LSB of BWADJ_val | 973 | MAINPLLCTL0 |= ~MAIN_BWADJ0_MASK & ((BWADJ_val - 1) << MAIN_BWADJ0_OFFSET); // set the MAIN_BWADJ[7:0] bit field to the 8 LSB of BWADJ_val |
974 | 974 | ||
975 | if(debug_info_on){ | 975 | if(debug_info_on){ |
976 | GEL_TextOut("(5) MAINPLLCTL0 = %x\n",,,,, MAINPLLCTL0); | 976 | GEL_TextOut("(5) MAINPLLCTL0 = %x\n",,,,, MAINPLLCTL0); |
977 | } | 977 | } |
978 | 978 | ||
979 | MAINPLLCTL1 &= MAIN_BWADJ1_MASK; // clear the MAIN_BWADJ1 bit field | 979 | MAINPLLCTL1 &= MAIN_BWADJ1_MASK; // clear the MAIN_BWADJ1 bit field |
980 | MAINPLLCTL1 |= ~MAIN_BWADJ1_MASK & (( (BWADJ_val - 1) >> 8) << MAIN_BWADJ1_OFFSET); // set the MAIN_BWADJ[11:8] bit field to the 4 MSB of BWADJ_val | 980 | MAINPLLCTL1 |= ~MAIN_BWADJ1_MASK & (( (BWADJ_val - 1) >> 8) << MAIN_BWADJ1_OFFSET); // set the MAIN_BWADJ[11:8] bit field to the 4 MSB of BWADJ_val |
981 | 981 | ||
982 | if(debug_info_on){ | 982 | if(debug_info_on){ |
983 | GEL_TextOut("(5) MAINPLLCTL1 = %x\n",,,,, MAINPLLCTL1); | 983 | GEL_TextOut("(5) MAINPLLCTL1 = %x\n",,,,, MAINPLLCTL1); |
984 | } | 984 | } |
985 | 985 | ||
986 | /* Step 6: Programming PLLD[5:0] in the MAINPLLCTL0 register */ | 986 | /* Step 6: Programming PLLD[5:0] in the MAINPLLCTL0 register */ |
987 | MAINPLLCTL0 &= MAIN_PLLD_MASK; // clear the PLLD bit field | 987 | MAINPLLCTL0 &= MAIN_PLLD_MASK; // clear the PLLD bit field |
988 | MAINPLLCTL0 |= ~MAIN_PLLD_MASK & (PLLD_val - 1); // set the PLLD[5:0] bit field of PLLD to PLLD_val | 988 | MAINPLLCTL0 |= ~MAIN_PLLD_MASK & (PLLD_val - 1); // set the PLLD[5:0] bit field of PLLD to PLLD_val |
989 | 989 | ||
990 | if(debug_info_on){ | 990 | if(debug_info_on){ |
991 | GEL_TextOut("(6) MAINPLLCTL0 = %x\n",,,,, MAINPLLCTL0); | 991 | GEL_TextOut("(6) MAINPLLCTL0 = %x\n",,,,, MAINPLLCTL0); |
992 | } | 992 | } |
993 | 993 | ||
994 | /* Step 7: Programming OD[3:0] in the SECCTL register */ | 994 | /* Step 7: Programming OD[3:0] in the SECCTL register */ |
995 | PLL1_SECCTL &= OUTPUT_DIVIDE_MASK; // clear the OD bit field | 995 | PLL1_SECCTL &= OUTPUT_DIVIDE_MASK; // clear the OD bit field |
996 | PLL1_SECCTL |= ~OUTPUT_DIVIDE_MASK & (OD_val - 1) << OUTPUT_DIVIDE_OFFSET; // set the OD[3:0] bit field of PLLD to OD_val | 996 | PLL1_SECCTL |= ~OUTPUT_DIVIDE_MASK & (OD_val - 1) << OUTPUT_DIVIDE_OFFSET; // set the OD[3:0] bit field of PLLD to OD_val |
997 | 997 | ||
998 | if(debug_info_on){ | 998 | if(debug_info_on){ |
999 | GEL_TextOut("(7) SECCTL = %x\n",,,,, PLL1_SECCTL); | 999 | GEL_TextOut("(7) SECCTL = %x\n",,,,, PLL1_SECCTL); |
1000 | } | 1000 | } |
1001 | 1001 | ||
1002 | /* Step 8: Following steps are needed to change the default output dividers */ | 1002 | /* Step 8: Following steps are needed to change the default output dividers */ |
1003 | 1003 | ||
1004 | /* Step 8a: Check that the GOSTAT bit in PLLSTAT is cleared to show that no GO | 1004 | /* Step 8a: Check that the GOSTAT bit in PLLSTAT is cleared to show that no GO |
1005 | operation is currently in progress*/ | 1005 | operation is currently in progress*/ |
1006 | if(debug_info_on){ | 1006 | if(debug_info_on){ |
1007 | GEL_TextOut("(8a) Delay...\n",,,,,); | 1007 | GEL_TextOut("(8a) Delay...\n",,,,,); |
1008 | } | 1008 | } |
1009 | while((PLL1_STAT) & 0x00000001); | 1009 | while((PLL1_STAT) & 0x00000001); |
1010 | 1010 | ||
1011 | /* Step 8b: Program the RATIO field in PLLDIVn to the desired new divide-down rate. | 1011 | /* Step 8b: Program the RATIO field in PLLDIVn to the desired new divide-down rate. |
1012 | If RATIO field is changed, the PLL controller will flag the change in the | 1012 | If RATIO field is changed, the PLL controller will flag the change in the |
1013 | corresponding bit of DCHANGE*/ | 1013 | corresponding bit of DCHANGE*/ |
1014 | PLL1_DIV3 = (PLLDIV3_val-1) | 0x8000; //Set PLLDIV3 | 1014 | PLL1_DIV3 = (PLLDIV3_val-1) | 0x8000; //Set PLLDIV3 |
1015 | PLL1_DIV4 = (PLLDIV4_val-1) | 0x8000; //Set PLLDIV4 | 1015 | PLL1_DIV4 = (PLLDIV4_val-1) | 0x8000; //Set PLLDIV4 |
1016 | PLL1_DIV7 = (PLLDIV7_val-1) | 0x8000; //Set PLLDIV7 | 1016 | PLL1_DIV7 = (PLLDIV7_val-1) | 0x8000; //Set PLLDIV7 |
1017 | 1017 | ||
1018 | if(debug_info_on){ | 1018 | if(debug_info_on){ |
1019 | GEL_TextOut("PLL1_DIV3 = %x\n",,,,, PLL1_DIV3); | 1019 | GEL_TextOut("PLL1_DIV3 = %x\n",,,,, PLL1_DIV3); |
1020 | GEL_TextOut("PLL1_DIV4 = %x\n",,,,, PLL1_DIV4); | 1020 | GEL_TextOut("PLL1_DIV4 = %x\n",,,,, PLL1_DIV4); |
1021 | GEL_TextOut("PLL1_DIV7 = %x\n",,,,, PLL1_DIV7); | 1021 | GEL_TextOut("PLL1_DIV7 = %x\n",,,,, PLL1_DIV7); |
1022 | } | 1022 | } |
1023 | 1023 | ||
1024 | /* Step 8c: Set GOSET bit in PLLCMD to initiate the GO operation to change the divide | 1024 | /* Step 8c: Set GOSET bit in PLLCMD to initiate the GO operation to change the divide |
1025 | values and align the SYSCLKs as programmed */ | 1025 | values and align the SYSCLKs as programmed */ |
1026 | PLL1_CMD |= 0x00000001; | 1026 | PLL1_CMD |= 0x00000001; |
1027 | 1027 | ||
1028 | /*Step 8d/e: Read the GOSTAT bit in PLLSTAT to make sure the bit returns to 0 to | 1028 | /*Step 8d/e: Read the GOSTAT bit in PLLSTAT to make sure the bit returns to 0 to |
1029 | indicate that the GO operation has completed */ | 1029 | indicate that the GO operation has completed */ |
1030 | if(debug_info_on){ | 1030 | if(debug_info_on){ |
1031 | GEL_TextOut("(8d/e) Delay...\n",,,,,); | 1031 | GEL_TextOut("(8d/e) Delay...\n",,,,,); |
1032 | } | 1032 | } |
1033 | while((PLL1_STAT) & 0x00000001); | 1033 | while((PLL1_STAT) & 0x00000001); |
1034 | 1034 | ||
1035 | /* Step 9: Set PLLCTL[PLLRST] = 1 - Assert PLL reset (Previously Step 3)*/ | 1035 | /* Step 9: Set PLLCTL[PLLRST] = 1 - Assert PLL reset (Previously Step 3)*/ |
1036 | PLL1_PLLCTL |= (1 << PLLRST_OFFSET); | 1036 | PLL1_PLLCTL |= (1 << PLLRST_OFFSET); |
1037 | 1037 | ||
1038 | /* Step 10: Wait for the at least 7us for the PLL reset properly (128 CLKIN1 cycles) */ | 1038 | /* Step 10: Wait for the at least 7us for the PLL reset properly (128 CLKIN1 cycles) */ |
1039 | if(debug_info_on){ | 1039 | if(debug_info_on){ |
1040 | GEL_TextOut("(10) Delay...\n",,,,,); | 1040 | GEL_TextOut("(10) Delay...\n",,,,,); |
1041 | } | 1041 | } |
1042 | for(i=0;i<delay;i++); | 1042 | for(i=0;i<delay;i++); |
1043 | 1043 | ||
1044 | /* Step 11: Set PLLCTL[PLLRST] = 0 - De-Assert PLL reset */ | 1044 | /* Step 11: Set PLLCTL[PLLRST] = 0 - De-Assert PLL reset */ |
1045 | PLL1_PLLCTL &= ~(1 << PLLRST_OFFSET); | 1045 | PLL1_PLLCTL &= ~(1 << PLLRST_OFFSET); |
1046 | 1046 | ||
1047 | /* Step 12: Wait for PLL to lock (2000 CLKIN1 cycles) */ | 1047 | /* Step 12: Wait for PLL to lock (2000 CLKIN1 cycles) */ |
1048 | if(debug_info_on){ | 1048 | if(debug_info_on){ |
1049 | GEL_TextOut("(12) Delay...\n",,,,,); | 1049 | GEL_TextOut("(12) Delay...\n",,,,,); |
1050 | } | 1050 | } |
1051 | for(i=0;i<delay;i++); | 1051 | for(i=0;i<delay;i++); |
1052 | 1052 | ||
1053 | /* Step 13: In SECCTL, write BYPASS = 0 (enable PLL mux to switch to PLL mode) */ | 1053 | /* Step 13: In SECCTL, write BYPASS = 0 (enable PLL mux to switch to PLL mode) */ |
1054 | PLL1_SECCTL &= ~(1 << BYPASS_OFFSET); | 1054 | PLL1_SECCTL &= ~(1 << BYPASS_OFFSET); |
1055 | if(debug_info_on){ | 1055 | if(debug_info_on){ |
1056 | GEL_TextOut("(13) SECCTL = %x\n",,,,, PLL1_SECCTL); | 1056 | GEL_TextOut("(13) SECCTL = %x\n",,,,, PLL1_SECCTL); |
1057 | } | 1057 | } |
1058 | if(debug_info_on){ | 1058 | if(debug_info_on){ |
1059 | GEL_TextOut("(Delay...\n",,,,,); | 1059 | GEL_TextOut("(Delay...\n",,,,,); |
1060 | } | 1060 | } |
1061 | for(i=0;i<delay;i++); | 1061 | for(i=0;i<delay;i++); |
1062 | if(debug_info_on){ | 1062 | if(debug_info_on){ |
1063 | GEL_TextOut("(Delay...\n",,,,,); | 1063 | GEL_TextOut("(Delay...\n",,,,,); |
1064 | } | 1064 | } |
1065 | for(i=0;i<delay;i++); | 1065 | for(i=0;i<delay;i++); |
1066 | 1066 | ||
1067 | /* Step 14: In PLLCTL, write PLLEN = 1 to enable PLL mode */ | 1067 | /* Step 14: In PLLCTL, write PLLEN = 1 to enable PLL mode */ |
1068 | PLL1_PLLCTL |= (1 << PLLEN_OFFSET); | 1068 | PLL1_PLLCTL |= (1 << PLLEN_OFFSET); |
1069 | if(debug_info_on){ | 1069 | if(debug_info_on){ |
1070 | GEL_TextOut("(14) PLLCTL = %x\n",,,,, PLL1_PLLCTL); | 1070 | GEL_TextOut("(14) PLLCTL = %x\n",,,,, PLL1_PLLCTL); |
1071 | } | 1071 | } |
1072 | 1072 | ||
1073 | /* Step 15: Lock Boot Config Registers */ | 1073 | /* Step 15: Lock Boot Config Registers */ |
1074 | KICK0 = 0x00000000; | 1074 | KICK0 = 0x00000000; |
1075 | KICK1 = 0x00000000; | 1075 | KICK1 = 0x00000000; |
1076 | 1076 | ||
1077 | GEL_TextOut("PLL has been configured (CLKIN * PLLM / PLLD / PLLOD = PLLOUT):\n",,,,,); | 1077 | GEL_TextOut("PLL has been configured (CLKIN * PLLM / PLLD / PLLOD = PLLOUT):\n",,,,,); |
1078 | GEL_TextOut("PLL has been configured (%f MHz * %d / %d / %d = %f MHz)\n",,,,, CLKIN_val, PLLM_val, PLLD_val,OD_val,(CLKIN_val * PLLM_val / PLLD_val / OD_val) ); | 1078 | GEL_TextOut("PLL has been configured (%f MHz * %d / %d / %d = %f MHz)\n",,,,, CLKIN_val, PLLM_val, PLLD_val,OD_val,(CLKIN_val * PLLM_val / PLLD_val / OD_val) ); |
1079 | 1079 | ||
1080 | } | 1080 | } |
1081 | 1081 | ||
1082 | 1082 | ||
1083 | //TODO: May need to change, as currently information is not available | 1083 | //TODO: May need to change, as currently information is not available |
1084 | Set_Tetris_Pll(int index) | 1084 | Set_Tetris_Pll(int index) |
1085 | { | 1085 | { |
1086 | 1086 | ||
1087 | unsigned int BWADJ_val; | 1087 | unsigned int BWADJ_val; |
1088 | unsigned int OD_val; | 1088 | unsigned int OD_val; |
1089 | unsigned int PLLM_val; | 1089 | unsigned int PLLM_val; |
1090 | float CLKIN_val; | 1090 | float CLKIN_val; |
1091 | int i; | 1091 | int i; |
1092 | 1092 | ||
1093 | GEL_TextOut("Switching on ARM Core 0\n",,,,,); | 1093 | GEL_TextOut("Switching on ARM Core 0\n",,,,,); |
1094 | TETRIS_CPU0_PDCTL = 0x00000000; | 1094 | TETRIS_CPU0_PDCTL = 0x00000000; |
1095 | TETRIS_CPU0_PTCMD = 0x00000001; | 1095 | TETRIS_CPU0_PTCMD = 0x00000001; |
1096 | 1096 | ||
1097 | GEL_TextOut("Switching on ARM Core 1\n",,,,,); | 1097 | GEL_TextOut("Switching on ARM Core 1\n",,,,,); |
1098 | TETRIS_CPU1_PDCTL = 0x00000000; | 1098 | TETRIS_CPU1_PDCTL = 0x00000000; |
1099 | TETRIS_CPU1_PTCMD = 0x00000001; | 1099 | TETRIS_CPU1_PTCMD = 0x00000001; |
1100 | 1100 | ||
1101 | GEL_TextOut("Switching on ARM Core 2\n",,,,,); | 1101 | GEL_TextOut("Switching on ARM Core 2\n",,,,,); |
1102 | TETRIS_CPU2_PDCTL = 0x00000000; | 1102 | TETRIS_CPU2_PDCTL = 0x00000000; |
1103 | TETRIS_CPU2_PTCMD = 0x00000001; | 1103 | TETRIS_CPU2_PTCMD = 0x00000001; |
1104 | 1104 | ||
1105 | GEL_TextOut("Switching on ARM Core 3\n",,,,,); | 1105 | GEL_TextOut("Switching on ARM Core 3\n",,,,,); |
1106 | TETRIS_CPU3_PDCTL = 0x00000000; | 1106 | TETRIS_CPU3_PDCTL = 0x00000000; |
1107 | TETRIS_CPU3_PTCMD = 0x00000001; | 1107 | TETRIS_CPU3_PTCMD = 0x00000001; |
1108 | 1108 | ||
1109 | if(index == 1){ // 100 MHz -> 1.0 GHz | 1109 | if(index == 1){ // 100 MHz -> 1.0 GHz |
1110 | CLKIN_val = 125; // setup CLKIN to 125 MHz | 1110 | CLKIN_val = 125; // setup CLKIN to 125 MHz |
1111 | PLLM_val = 16; // setup PLLM (PLL multiplier) to x20 | 1111 | PLLM_val = 16; // setup PLLM (PLL multiplier) to x20 |
1112 | OD_val = 2; // setup OD to a fixed /2 | 1112 | OD_val = 2; // setup OD to a fixed /2 |
1113 | } | 1113 | } |
1114 | else if(index == 2){ // 100 MHz -> 1.4 GHz | 1114 | else if(index == 2){ // 100 MHz -> 1.4 GHz |
1115 | CLKIN_val = 125; // setup CLKIN to 125 MHz | 1115 | CLKIN_val = 125; // setup CLKIN to 125 MHz |
1116 | PLLM_val = 22; // setup PLLM (PLL multiplier) to x28 | 1116 | PLLM_val = 22; // setup PLLM (PLL multiplier) to x28 |
1117 | OD_val = 2; // setup OD to a fixed /2 | 1117 | OD_val = 2; // setup OD to a fixed /2 |
1118 | } | 1118 | } |
1119 | else if(index == 3){ // 174.825MHz -> 1.4 GHz //TODO: From where this freq will be available? Not shown in schematic. | 1119 | else if(index == 3){ // 174.825MHz -> 1.4 GHz //TODO: From where this freq will be available? Not shown in schematic. |
1120 | 1120 | ||
1121 | CLKIN_val = 174.825; // setup CLKIN to 174.825 MHz | 1121 | CLKIN_val = 174.825; // setup CLKIN to 174.825 MHz |
1122 | PLLM_val = 16; // setup PLLM (PLL multiplier) to x16 | 1122 | PLLM_val = 16; // setup PLLM (PLL multiplier) to x16 |
1123 | OD_val = 2; // setup OD to a fixed /2 | 1123 | OD_val = 2; // setup OD to a fixed /2 |
1124 | } | 1124 | } |
1125 | 1125 | ||
1126 | BWADJ_val = (PLLM_val-1) >> 1; // setup BWADJ to be 1/2 the value of PLLM | 1126 | BWADJ_val = (PLLM_val-1) >> 1; // setup BWADJ to be 1/2 the value of PLLM |
1127 | OD_val = 2; // setup OD to a fixed /2 | 1127 | OD_val = 2; // setup OD to a fixed /2 |
1128 | 1128 | ||
1129 | /* Step 1: Unlock Boot Config Registers */ | 1129 | /* Step 1: Unlock Boot Config Registers */ |
1130 | KICK0 = KICK0_UNLOCK; | 1130 | KICK0 = KICK0_UNLOCK; |
1131 | KICK1 = KICK1_UNLOCK; | 1131 | KICK1 = KICK1_UNLOCK; |
1132 | 1132 | ||
1133 | //Step 1 : Assert SEC PLL Reset | 1133 | //Step 1 : Assert SEC PLL Reset |
1134 | SECPLLCTL1 = ((1 << SEC_PLLCTL1_RESET_OFFSET) | (1 << SEC_PLLCTL1_ENSTAT_OFFSET)); | 1134 | SECPLLCTL1 = ((1 << SEC_PLLCTL1_RESET_OFFSET) | (1 << SEC_PLLCTL1_ENSTAT_OFFSET)); |
1135 | 1135 | ||
1136 | //Step 2 : Change CLKF/OD/BWADJ etc. for SEC PLL | 1136 | //Step 2 : Change CLKF/OD/BWADJ etc. for SEC PLL |
1137 | SECPLLCTL0 = ((BWADJ_val << SEC_PLLCTL0_BWADJ_OFFSET) | | 1137 | SECPLLCTL0 = ((BWADJ_val << SEC_PLLCTL0_BWADJ_OFFSET) | |
1138 | ((OD_val-1) << SEC_PLLCTL0_OD_OFFSET)| | 1138 | ((OD_val-1) << SEC_PLLCTL0_OD_OFFSET)| |
1139 | ((PLLM_val-1) << SEC_PLLCTL0_PLLM_OFFSET)); | 1139 | ((PLLM_val-1) << SEC_PLLCTL0_PLLM_OFFSET)); |
1140 | 1140 | ||
1141 | //Step 3 : Make sure the resets are held for 5us | 1141 | //Step 3 : Make sure the resets are held for 5us |
1142 | for(i = 0; i < 200000; i++); | 1142 | for(i = 0; i < 200000; i++); |
1143 | 1143 | ||
1144 | //Step 4 : Remove SEC PLL reset | 1144 | //Step 4 : Remove SEC PLL reset |
1145 | SECPLLCTL1 = (1 << SEC_PLLCTL1_ENSTAT_OFFSET); | 1145 | SECPLLCTL1 = (1 << SEC_PLLCTL1_ENSTAT_OFFSET); |
1146 | 1146 | ||
1147 | //Step 5 : Wait for PLL to lock (4000 CLKIN1 cycles) | 1147 | //Step 5 : Wait for PLL to lock (4000 CLKIN1 cycles) |
1148 | for(i = 0; i < 4000; i++); | 1148 | for(i = 0; i < 4000; i++); |
1149 | 1149 | ||
1150 | //Step 6 : Get the PLL out of Bypass | 1150 | //Step 6 : Get the PLL out of Bypass |
1151 | //SECPLLCTL0 &= ~(1 << SEC_PLLCTL0_BYPASS_OFFSET); | 1151 | //SECPLLCTL0 &= ~(1 << SEC_PLLCTL0_BYPASS_OFFSET); |
1152 | CHIP_MISC1 |= (1 << ARMPLL_ENABLE_OFFSET); | 1152 | CHIP_MISC1 |= (1 << ARMPLL_ENABLE_OFFSET); |
1153 | 1153 | ||
1154 | 1154 | ||
1155 | //Step 6 : Lock Boot Config Registers | 1155 | //Step 6 : Lock Boot Config Registers |
1156 | KICK0 = 0x00000000; | 1156 | KICK0 = 0x00000000; |
1157 | KICK1 = 0x00000000; | 1157 | KICK1 = 0x00000000; |
1158 | 1158 | ||
1159 | GEL_TextOut("ARM PLL has been configured (%f MHz * %d / %d = %f MHz)\n",,,,, CLKIN_val, PLLM_val, OD_val, (CLKIN_val * PLLM_val)/OD_val); | 1159 | GEL_TextOut("ARM PLL has been configured (%f MHz * %d / %d = %f MHz)\n",,,,, CLKIN_val, PLLM_val, OD_val, (CLKIN_val * PLLM_val)/OD_val); |
1160 | 1160 | ||
1161 | } | 1161 | } |
1162 | 1162 | ||
1163 | 1163 | ||
1164 | /* Set the desired PA PLL configuration */ | 1164 | /* Set the desired PA PLL configuration */ |
1165 | PaPllConfig() | 1165 | PaPllConfig() |
1166 | { | 1166 | { |
1167 | unsigned int passclksel = (DEVSTAT & PASSCLKSEL_MASK); | 1167 | unsigned int passclksel = (DEVSTAT & PASSCLKSEL_MASK); |
1168 | unsigned int papllctl0val_orig = PAPLLCTL0; | 1168 | unsigned int papllctl0val_orig = PAPLLCTL0; |
1169 | unsigned int papllctl1val_orig = PAPLLCTL1; | 1169 | unsigned int papllctl1val_orig = PAPLLCTL1; |
1170 | unsigned int papllctl0val_final; | 1170 | unsigned int papllctl0val_final; |
1171 | unsigned int papllctl1val_final; | 1171 | unsigned int papllctl1val_final; |
1172 | unsigned int papllclkf = 19; //204; // 204; 20 (if PASSREFCLK == 100mhz) Multiply by clkf + 1 | 1172 | unsigned int papllclkf = 19; //204; // 204; 20 (if PASSREFCLK == 100mhz) Multiply by clkf + 1 |
1173 | unsigned int papllclkd = 0; //11; // 11; 1 (if PASSREFCLK == 100mhz) Divide by clkd + 1 | 1173 | unsigned int papllclkd = 0; //11; // 11; 1 (if PASSREFCLK == 100mhz) Divide by clkd + 1 |
1174 | unsigned int i = 0; | 1174 | unsigned int i = 0; |
1175 | 1175 | ||
1176 | if (passclksel != PASSCLKSEL_MASK) GEL_TextOut("WARNING: SYSCLK is the input to the PA PLL.\n"); | 1176 | if (passclksel != PASSCLKSEL_MASK) GEL_TextOut("WARNING: SYSCLK is the input to the PA PLL.\n"); |
1177 | 1177 | ||
1178 | /* Unlock Chip Level Registers */ | 1178 | /* Unlock Chip Level Registers */ |
1179 | KICK0 = KICK0_UNLOCK; | 1179 | KICK0 = KICK0_UNLOCK; |
1180 | KICK1 = KICK1_UNLOCK; | 1180 | KICK1 = KICK1_UNLOCK; |
1181 | 1181 | ||
1182 | // PAPLLCTL1 = PAPLLCTL1 | 0x00000040; //Set ENSAT = 1; Set PLL Select to 0 (for SYCLK0 as input of PASS) | 1182 | // PAPLLCTL1 = PAPLLCTL1 | 0x00000040; //Set ENSAT = 1; Set PLL Select to 0 (for SYCLK0 as input of PASS) |
1183 | PAPLLCTL1 = PAPLLCTL1 | 0x00002040; //Set ENSAT = 1; Set PLL Select to 1 (for PA PLL as input of PASS) | 1183 | PAPLLCTL1 = PAPLLCTL1 | 0x00002040; //Set ENSAT = 1; Set PLL Select to 1 (for PA PLL as input of PASS) |
1184 | 1184 | ||
1185 | /*in PAPLLCTL0, clear bypass bit to set the PA PLL in Bypass Mode*/ | 1185 | /*in PAPLLCTL0, clear bypass bit to set the PA PLL in Bypass Mode*/ |
1186 | //PAPLLCTL0 &= ~(1<<BYPASS_BIT_SHIFT); // Not setting Bypass bit | 1186 | //PAPLLCTL0 &= ~(1<<BYPASS_BIT_SHIFT); // Not setting Bypass bit |
1187 | PAPLLCTL0 |= (1<<BYPASS_BIT_SHIFT); // Actually setting bypass bit | 1187 | PAPLLCTL0 |= (1<<BYPASS_BIT_SHIFT); // Actually setting bypass bit |
1188 | 1188 | ||
1189 | /*Wait 4 cycles for the slowest of PLLOUT or reference clock source (CLKIN)*/ | 1189 | /*Wait 4 cycles for the slowest of PLLOUT or reference clock source (CLKIN)*/ |
1190 | for(i=0;i<100;i++); | 1190 | for(i=0;i<100;i++); |
1191 | 1191 | ||
1192 | /*In PAPLLCTL1, write PLL reset bit to put the PLL in reset*/ | 1192 | /*In PAPLLCTL1, write PLL reset bit to put the PLL in reset*/ |
1193 | PAPLLCTL1 |= PA_PLL_RESET_MASK; | 1193 | PAPLLCTL1 |= PA_PLL_RESET_MASK; |
1194 | 1194 | ||
1195 | /* Program the multiplier value */ | 1195 | /* Program the multiplier value */ |
1196 | PAPLLCTL0 &= (~PA_PLL_CLKF_MASK); //clear multiplier value | 1196 | PAPLLCTL0 &= (~PA_PLL_CLKF_MASK); //clear multiplier value |
1197 | PAPLLCTL0 &= (~PA_PLL_CLKR_MASK); //clear divider value | 1197 | PAPLLCTL0 &= (~PA_PLL_CLKR_MASK); //clear divider value |
1198 | PAPLLCTL0 |= (papllclkf<<CLKF_BIT_SHIFT); // set PLLM | 1198 | PAPLLCTL0 |= (papllclkf<<CLKF_BIT_SHIFT); // set PLLM |
1199 | PAPLLCTL0 |= (papllclkd<<CLKD_BIT_SHIFT); // set PLLD | 1199 | PAPLLCTL0 |= (papllclkd<<CLKD_BIT_SHIFT); // set PLLD |
1200 | 1200 | ||
1201 | 1201 | ||
1202 | PAPLLCTL0 &= 0x00FFFFFF; | 1202 | PAPLLCTL0 &= 0x00FFFFFF; |
1203 | PAPLLCTL0 |= ((((papllclkf + 1)>>1)-1)<<24); | 1203 | PAPLLCTL0 |= ((((papllclkf + 1)>>1)-1)<<24); |
1204 | 1204 | ||
1205 | //PAPLLCTL1 = PAPLLCTL1 | 0x00002000; | 1205 | //PAPLLCTL1 = PAPLLCTL1 | 0x00002000; |
1206 | 1206 | ||
1207 | /*Wait for PLL to properly reset (128 CLKIN1 cycles) */ | 1207 | /*Wait for PLL to properly reset (128 CLKIN1 cycles) */ |
1208 | for(i=0;i<1000;i++); | 1208 | for(i=0;i<1000;i++); |
1209 | 1209 | ||
1210 | /* take the PA PLL out of reset */ | 1210 | /* take the PA PLL out of reset */ |
1211 | PAPLLCTL1 &= (~PA_PLL_RESET_MASK); | 1211 | PAPLLCTL1 &= (~PA_PLL_RESET_MASK); |
1212 | 1212 | ||
1213 | /*Wait for PLL to lock (2000 CLKIN1 cycles) */ | 1213 | /*Wait for PLL to lock (2000 CLKIN1 cycles) */ |
1214 | for(i=0;i<5000;i++); | 1214 | for(i=0;i<5000;i++); |
1215 | 1215 | ||
1216 | /* enable PLL mode */ | 1216 | /* enable PLL mode */ |
1217 | PAPLLCTL0 &= ~(1<<BYPASS_BIT_SHIFT); // actually setting PLL MODE | 1217 | PAPLLCTL0 &= ~(1<<BYPASS_BIT_SHIFT); // actually setting PLL MODE |
1218 | 1218 | ||
1219 | for(i=0;i<4000;i++); | 1219 | for(i=0;i<4000;i++); |
1220 | 1220 | ||
1221 | /* Lock Chip Level Registers */ | 1221 | /* Lock Chip Level Registers */ |
1222 | KICK0 = KICK_LOCK; | 1222 | KICK0 = KICK_LOCK; |
1223 | KICK1 = KICK_LOCK; | 1223 | KICK1 = KICK_LOCK; |
1224 | 1224 | ||
1225 | papllctl0val_final = PAPLLCTL0; | 1225 | papllctl0val_final = PAPLLCTL0; |
1226 | papllctl1val_final = PAPLLCTL1; | 1226 | papllctl1val_final = PAPLLCTL1; |
1227 | 1227 | ||
1228 | GEL_TextOut("Completed PA PLL Setup\n"); | 1228 | GEL_TextOut("Completed PA PLL Setup\n"); |
1229 | GEL_TextOut("PAPLLCTL0 - before: 0x%x\t after: 0x%x\n",,,,, papllctl0val_orig, papllctl0val_final); | 1229 | GEL_TextOut("PAPLLCTL0 - before: 0x%x\t after: 0x%x\n",,,,, papllctl0val_orig, papllctl0val_final); |
1230 | GEL_TextOut("PAPLLCTL1 - before: 0x%x\t after: 0x%x\n",,,,, papllctl1val_orig, papllctl1val_final); | 1230 | GEL_TextOut("PAPLLCTL1 - before: 0x%x\t after: 0x%x\n",,,,, papllctl1val_orig, papllctl1val_final); |
1231 | 1231 | ||
1232 | if ((papllctl0val_final != 0x09080500) || (papllctl1val_final != 0x00002040)) | 1232 | if ((papllctl0val_final != 0x09080500) || (papllctl1val_final != 0x00002040)) |
1233 | { | 1233 | { |
1234 | return 1; | 1234 | return 1; |
1235 | } | 1235 | } |
1236 | 1236 | ||
1237 | return 0; | 1237 | return 0; |
1238 | 1238 | ||
1239 | } | 1239 | } |
1240 | 1240 | ||
1241 | //************************************************************************************************* | 1241 | //************************************************************************************************* |
1242 | //************************************************************************************************* | 1242 | //************************************************************************************************* |
1243 | //************************************************************************************************* | 1243 | //************************************************************************************************* |
1244 | //************************************************************************************************* | 1244 | //************************************************************************************************* |
1245 | //************************************************************************************************* | 1245 | //************************************************************************************************* |
1246 | //************************************************************************************************* | 1246 | //************************************************************************************************* |
1247 | 1247 | ||
1248 | //--------DDR3A Memory test---------------------- | 1248 | //--------DDR3A Memory test---------------------- |
1249 | 1249 | ||
1250 | ddr3A_memory_test () | 1250 | ddr3A_memory_test () |
1251 | { | 1251 | { |
1252 | unsigned int index, value; | 1252 | unsigned int index, value; |
1253 | 1253 | ||
1254 | GEL_TextOut( "DDR3A memory test... Started\n" ); | 1254 | GEL_TextOut( "DDR3A memory test... Started\n" ); |
1255 | 1255 | ||
1256 | /* Write a pattern */ | 1256 | /* Write a pattern */ |
1257 | for (index = DDR3A_TEST_START_ADDRESS; index < DDR3A_TEST_END_ADDRESS; index += 4) { | 1257 | for (index = DDR3A_TEST_START_ADDRESS; index < DDR3A_TEST_END_ADDRESS; index += 4) { |
1258 | *index = index; | 1258 | *index = index; |
1259 | } | 1259 | } |
1260 | 1260 | ||
1261 | /* Read and check the pattern */ | 1261 | /* Read and check the pattern */ |
1262 | for (index = DDR3A_TEST_START_ADDRESS; index < DDR3A_TEST_END_ADDRESS; index += 4) { | 1262 | for (index = DDR3A_TEST_START_ADDRESS; index < DDR3A_TEST_END_ADDRESS; index += 4) { |
1263 | 1263 | ||
1264 | value = *index; | 1264 | value = *index; |
1265 | 1265 | ||
1266 | if (value != index) { | 1266 | if (value != index) { |
1267 | GEL_TextOut( "DDR3A memory test... Failed\n" ); | 1267 | GEL_TextOut( "DDR3A memory test... Failed\n" ); |
1268 | return -1; | 1268 | return -1; |
1269 | } | 1269 | } |
1270 | } | 1270 | } |
1271 | 1271 | ||
1272 | /* Write a pattern for complementary values */ | 1272 | /* Write a pattern for complementary values */ |
1273 | for (index = DDR3A_TEST_START_ADDRESS; index < DDR3A_TEST_END_ADDRESS; index += 4) { | 1273 | for (index = DDR3A_TEST_START_ADDRESS; index < DDR3A_TEST_END_ADDRESS; index += 4) { |
1274 | *index = ~index; | 1274 | *index = ~index; |
1275 | } | 1275 | } |
1276 | 1276 | ||
1277 | /* Read and check the pattern */ | 1277 | /* Read and check the pattern */ |
1278 | for (index = DDR3A_TEST_START_ADDRESS; index < DDR3A_TEST_END_ADDRESS; index += 4) { | 1278 | for (index = DDR3A_TEST_START_ADDRESS; index < DDR3A_TEST_END_ADDRESS; index += 4) { |
1279 | 1279 | ||
1280 | value = *index; | 1280 | value = *index; |
1281 | 1281 | ||
1282 | if (value != ~index) { | 1282 | if (value != ~index) { |
1283 | GEL_TextOut( "DDR3A memory test... Failed\n" ); | 1283 | GEL_TextOut( "DDR3A memory test... Failed\n" ); |
1284 | return -1; | 1284 | return -1; |
1285 | } | 1285 | } |
1286 | } | 1286 | } |
1287 | 1287 | ||
1288 | GEL_TextOut( "DDR3A memory test... Passed\n" ); | 1288 | GEL_TextOut( "DDR3A memory test... Passed\n" ); |
1289 | return 0; | 1289 | return 0; |
1290 | 1290 | ||
1291 | } | 1291 | } |
1292 | 1292 | ||
1293 | 1293 | ||
1294 | 1294 | ||
1295 | /**************************************************************************** | 1295 | /**************************************************************************** |
1296 | * | 1296 | * |
1297 | * NAME | 1297 | * NAME |
1298 | * Setup_Memory_Map | 1298 | * Setup_Memory_Map |
1299 | * | 1299 | * |
1300 | * PURPOSE: | 1300 | * PURPOSE: |
1301 | * Setup the Memory Map for EVMC6678L. | 1301 | * Setup the Memory Map for EVMC6678L. |
1302 | * Defined memory location avoid debugger access outside these locations. | 1302 | * Defined memory location avoid debugger access outside these locations. |
1303 | * | 1303 | * |
1304 | * USAGE | 1304 | * USAGE |
1305 | * This routine can be called as: | 1305 | * This routine can be called as: |
1306 | * | 1306 | * |
1307 | * Setup_Memory_Map() | 1307 | * Setup_Memory_Map() |
1308 | * | 1308 | * |
1309 | * RETURN VALUE | 1309 | * RETURN VALUE |
1310 | * NONE | 1310 | * NONE |
1311 | * | 1311 | * |
1312 | * REFERENCE | 1312 | * REFERENCE |
1313 | * Based on TMS320C6678 datasheet. | 1313 | * Based on TMS320C6678 datasheet. |
1314 | * | 1314 | * |
1315 | ****************************************************************************/ | 1315 | ****************************************************************************/ |
1316 | hotmenu Setup_Memory_Map( ) | 1316 | hotmenu Setup_Memory_Map( ) |
1317 | { | 1317 | { |
1318 | GEL_TextOut("Setup_Memory_Map...\n",,); | 1318 | GEL_TextOut("Setup_Memory_Map...\n",,); |
1319 | 1319 | ||
1320 | GEL_MapOn( ); | 1320 | GEL_MapOn( ); |
1321 | GEL_MapReset( ); | 1321 | GEL_MapReset( ); |
1322 | 1322 | ||
1323 | GEL_MapAddStr( 0x00000000, 0, 0x21400000, "R|W|AS4", 0 ); // | 1323 | GEL_MapAddStr( 0x00000000, 0, 0x21400000, "R|W|AS4", 0 ); // |
1324 | GEL_MapAddStr( 0x21400000,0, 0x00000080, "R|W|AS4", 0 ); // Hyperlink Config (remote) | 1324 | GEL_MapAddStr( 0x21400000,0, 0x00000080, "R|W|AS4", 0 ); // Hyperlink Config (remote) |
1325 | //GEL_MapAddStr( 0x21400080,0, 0x00000080, "R|W|AS4", 0 ); // Hyperlink Config (remote) | 1325 | //GEL_MapAddStr( 0x21400080,0, 0x00000080, "R|W|AS4", 0 ); // Hyperlink Config (remote) |
1326 | GEL_MapAddStr( 0x21400200, 0, 0xdebffe00, "R|W|AS4", 0 ); // | 1326 | GEL_MapAddStr( 0x21400200, 0, 0xdebffe00, "R|W|AS4", 0 ); // |
1327 | GEL_TextOut( "Setup_Memory_Map... Done.\n" ); | 1327 | GEL_TextOut( "Setup_Memory_Map... Done.\n" ); |
1328 | } | 1328 | } |
1329 | 1329 | ||
1330 | /*----------------------------------------------------- DDR3A : DDR800, 32bit--------------------------------------------------------------------------*/ | 1330 | /*----------------------------------------------------- DDR3A : DDR800, 32bit--------------------------------------------------------------------------*/ |
1331 | ddr3A_32bit_DDR800_setup() | 1331 | ddr3A_32bit_DDR800_setup() |
1332 | { | 1332 | { |
1333 | unsigned int multiplier = 3; | 1333 | unsigned int multiplier = 3; |
1334 | unsigned int divider = 0; | 1334 | unsigned int divider = 0; |
1335 | int temp; | 1335 | int temp; |
1336 | unsigned int OD_val = 2; | 1336 | unsigned int OD_val = 2; |
1337 | KICK0 = 0x83E70B13; | 1337 | KICK0 = 0x83E70B13; |
1338 | KICK1 = 0x95A4F1E0; | 1338 | KICK1 = 0x95A4F1E0; |
1339 | 1339 | ||
1340 | 1340 | ||
1341 | //1. Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010). | 1341 | //1. Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010). |
1342 | do { | 1342 | do { |
1343 | read_val = DDR3A_PGSR0; | 1343 | read_val = DDR3A_PGSR0; |
1344 | } while ((read_val&0x00000001) != 0x00000001); | 1344 | } while ((read_val&0x00000001) != 0x00000001); |
1345 | 1345 | ||
1346 | //4. Clocks are enabled and frequency is stable--------------------------------------- | 1346 | //4. Clocks are enabled and frequency is stable--------------------------------------- |
1347 | //DDR3A PLL setup | 1347 | //DDR3A PLL setup |
1348 | GEL_TextOut ( "DDR3 PLL (PLL2) Setup ... \n"); | 1348 | GEL_TextOut ( "DDR3 PLL (PLL2) Setup ... \n"); |
1349 | //DDR3APLLCTL0 = DDR3APLLCTL0 & 0xFF7FFFFF; | 1349 | //DDR3APLLCTL0 = DDR3APLLCTL0 & 0xFF7FFFFF; |
1350 | // Set ENSAT = 1 | 1350 | // Set ENSAT = 1 |
1351 | DDR3APLLCTL1 |= 0x00000040; | 1351 | DDR3APLLCTL1 |= 0x00000040; |
1352 | // Put the PLL in PLL Mode | 1352 | // Put the PLL in PLL Mode |
1353 | DDR3APLLCTL0 |= 0x00800000; | 1353 | DDR3APLLCTL0 |= 0x00800000; |
1354 | // In PLL Controller, reset the PLL (bit 13 in DDR3APLLCTL1 register) | 1354 | // In PLL Controller, reset the PLL (bit 13 in DDR3APLLCTL1 register) |
1355 | DDR3APLLCTL1 |= 0x00002000; | 1355 | DDR3APLLCTL1 |= 0x00002000; |
1356 | // Program the necessary multipliers/dividers and BW adjustments | 1356 | // Program the necessary multipliers/dividers and BW adjustments |
1357 | // Set the divider values | 1357 | // Set the divider values |
1358 | DDR3APLLCTL0 &= ~(0x0000003F); | 1358 | DDR3APLLCTL0 &= ~(0x0000003F); |
1359 | DDR3APLLCTL0 |= (divider & 0x0000003F); | 1359 | DDR3APLLCTL0 |= (divider & 0x0000003F); |
1360 | /* Step 7: Programming OD[3:0] in the SECCTL register */ | 1360 | /* Step 7: Programming OD[3:0] in the SECCTL register */ |
1361 | DDR3APLLCTL0 &= OUTPUT_DIVIDE_MASK; // clear the OD bit field | 1361 | DDR3APLLCTL0 &= OUTPUT_DIVIDE_MASK; // clear the OD bit field |
1362 | DDR3APLLCTL0 |= ~OUTPUT_DIVIDE_MASK & (OD_val - 1) << OUTPUT_DIVIDE_OFFSET; // set the OD[3:0] bit field of PLLD to OD_val | 1362 | DDR3APLLCTL0 |= ~OUTPUT_DIVIDE_MASK & (OD_val - 1) << OUTPUT_DIVIDE_OFFSET; // set the OD[3:0] bit field of PLLD to OD_val |
1363 | 1363 | ||
1364 | /* Set the Multipler values */ | 1364 | /* Set the Multipler values */ |
1365 | DDR3APLLCTL0 &= ~(0x0007FFC0); | 1365 | DDR3APLLCTL0 &= ~(0x0007FFC0); |
1366 | DDR3APLLCTL0 |= ((multiplier << 6) & 0x0007FFC0 ); | 1366 | DDR3APLLCTL0 |= ((multiplier << 6) & 0x0007FFC0 ); |
1367 | temp = ((multiplier + 1) >> 1) - 1; | 1367 | temp = ((multiplier + 1) >> 1) - 1; |
1368 | DDR3APLLCTL0 &= ~(0xFF000000); | 1368 | DDR3APLLCTL0 &= ~(0xFF000000); |
1369 | DDR3APLLCTL0 |= ((temp << 24) & 0xFF000000); | 1369 | DDR3APLLCTL0 |= ((temp << 24) & 0xFF000000); |
1370 | DDR3APLLCTL1 &= ~(0x0000000F); | 1370 | DDR3APLLCTL1 &= ~(0x0000000F); |
1371 | DDR3APLLCTL1 |= ((temp >> 8) & 0x0000000F); | 1371 | DDR3APLLCTL1 |= ((temp >> 8) & 0x0000000F); |
1372 | //In DDR3PLLCTL1, write PLLRST = 0 to bring PLL out of reset | 1372 | //In DDR3PLLCTL1, write PLLRST = 0 to bring PLL out of reset |
1373 | DDR3APLLCTL1 &= ~(0x00002000); | 1373 | DDR3APLLCTL1 &= ~(0x00002000); |
1374 | // Put the PLL in PLL Mode | 1374 | // Put the PLL in PLL Mode |
1375 | DDR3APLLCTL0 &= ~(0x00800000); // ReSet the Bit 23 | 1375 | DDR3APLLCTL0 &= ~(0x00800000); // ReSet the Bit 23 |
1376 | GEL_TextOut( "DDR3 PLL Setup complete, DDR3A clock now running at 400MHz.\n" ); | 1376 | GEL_TextOut( "DDR3 PLL Setup complete, DDR3A clock now running at 400MHz.\n" ); |
1377 | //DDR3A PLL setup complete --------------------------------------- | 1377 | //DDR3A PLL setup complete --------------------------------------- |
1378 | 1378 | ||
1379 | /*------------------------- Start PHY Configuration -------------------------------*/ | 1379 | /*------------------------- Start PHY Configuration -------------------------------*/ |
1380 | 1380 | ||
1381 | //DDR3A_PGCR1 = 0x0280C487; | 1381 | //DDR3A_PGCR1 = 0x0280C487; |
1382 | 1382 | ||
1383 | //5.a Program FRQSEL in the PLL Control Register (address offset 0x018). | 1383 | //5.a Program FRQSEL in the PLL Control Register (address offset 0x018). |
1384 | DDR3A_PLLCR = 0xDC000; //Set FRQSEL=11, for ctl_clk between 166-275MHz | 1384 | DDR3A_PLLCR = 0xDC000; //Set FRQSEL=11, for ctl_clk between 166-275MHz |
1385 | 1385 | ||
1386 | //5.b. Program WLSTEP=1, IODDRM=1, and ZCKSEL in the PHY General Configuration Register 1 (address offset 0x00C). | 1386 | //5.b. Program WLSTEP=1, IODDRM=1, and ZCKSEL in the PHY General Configuration Register 1 (address offset 0x00C). |
1387 | DDR3A_PGCR1 |= (1 << 2); //WLSTEP = 1 | 1387 | DDR3A_PGCR1 |= (1 << 2); //WLSTEP = 1 |
1388 | 1388 | ||
1389 | DDR3A_PGCR1 &= ~(IODDRM_MASK); | 1389 | DDR3A_PGCR1 &= ~(IODDRM_MASK); |
1390 | DDR3A_PGCR1 |= (( 1 << 7) & IODDRM_MASK); | 1390 | DDR3A_PGCR1 |= (( 1 << 7) & IODDRM_MASK); |
1391 | 1391 | ||
1392 | 1392 | ||
1393 | DDR3A_PGCR1 &= ~(ZCKSEL_MASK); | 1393 | DDR3A_PGCR1 &= ~(ZCKSEL_MASK); |
1394 | DDR3A_PGCR1 |= (( 1 << 23) & ZCKSEL_MASK); | 1394 | DDR3A_PGCR1 |= (( 1 << 23) & ZCKSEL_MASK); |
1395 | 1395 | ||
1396 | 1396 | ||
1397 | //5.c. Program PHY Timing Parameters Register 0-4 (address offset 0x01C - 0x02C). | 1397 | //5.c. Program PHY Timing Parameters Register 0-4 (address offset 0x01C - 0x02C). |
1398 | 1398 | ||
1399 | DDR3A_PTR0 = 0x42C21590; | 1399 | DDR3A_PTR0 = 0x42C21590; |
1400 | 1400 | ||
1401 | DDR3A_PTR1 = 0xCFC712B3; | 1401 | DDR3A_PTR1 = 0xCFC712B3; |
1402 | 1402 | ||
1403 | // Maintaining default values of Phy Timing Parameters Register 2 in PUB | 1403 | // Maintaining default values of Phy Timing Parameters Register 2 in PUB |
1404 | 1404 | ||
1405 | DDR3A_PTR3 = 0x04430D40;//0x18061A80; | 1405 | DDR3A_PTR3 = 0x04430D40;//0x18061A80; |
1406 | 1406 | ||
1407 | DDR3A_PTR4 = 0x06413880;//0x0AAE7100; | 1407 | DDR3A_PTR4 = 0x06413880;//0x0AAE7100; |
1408 | 1408 | ||
1409 | //5.d. Program PDQ, MPRDQ, and BYTEMASK in the DRAM Configuration Register (address offset 0x044). | 1409 | //5.d. Program PDQ, MPRDQ, and BYTEMASK in the DRAM Configuration Register (address offset 0x044). |
1410 | // All other fields must be left at their default values. | 1410 | // All other fields must be left at their default values. |
1411 | 1411 | ||
1412 | DDR3A_DCR &= ~(PDQ_MASK); //PDQ = 0 | 1412 | DDR3A_DCR &= ~(PDQ_MASK); //PDQ = 0 |
1413 | DDR3A_DCR &= ~(MPRDQ_MASK); //MPRDQ = 0 | 1413 | DDR3A_DCR &= ~(MPRDQ_MASK); //MPRDQ = 0 |
1414 | 1414 | ||
1415 | DDR3A_DCR &= ~(BYTEMASK_MASK); | 1415 | DDR3A_DCR &= ~(BYTEMASK_MASK); |
1416 | DDR3A_DCR |= (( 1 << 10) & BYTEMASK_MASK); | 1416 | DDR3A_DCR |= (( 1 << 10) & BYTEMASK_MASK); |
1417 | 1417 | ||
1418 | 1418 | ||
1419 | DDR3A_DCR &= ~(NOSRA_MASK); | 1419 | DDR3A_DCR &= ~(NOSRA_MASK); |
1420 | DDR3A_DCR |= (( 1 << 27) & NOSRA_MASK); | 1420 | DDR3A_DCR |= (( 1 << 27) & NOSRA_MASK); |
1421 | 1421 | ||
1422 | 1422 | ||
1423 | DDR3A_DCR &= ~(UDIMM_MASK); | 1423 | DDR3A_DCR &= ~(UDIMM_MASK); |
1424 | DDR3A_DCR |= (( 1 << 29) & UDIMM_MASK); | 1424 | DDR3A_DCR |= (( 1 << 29) & UDIMM_MASK); |
1425 | 1425 | ||
1426 | 1426 | ||
1427 | //5.e. Program DRAM Timing Parameters Register 0-2 (address offset 0x048 - 0x050). | 1427 | //5.e. Program DRAM Timing Parameters Register 0-2 (address offset 0x048 - 0x050). |
1428 | 1428 | ||
1429 | DDR3A_DTPR0 = 0x008F6633; //0x50CE6644; | 1429 | DDR3A_DTPR0 = 0x008F6633; //0x50CE6644; |
1430 | DDR3A_DTPR1 = 0x12820180; | 1430 | DDR3A_DTPR1 = 0x12820180; |
1431 | DDR3A_DTPR2 = 0x50022A00; | 1431 | DDR3A_DTPR2 = 0x50022A00; |
1432 | 1432 | ||
1433 | //5.f. Program BL=0, CL, WR, and PD=1 in the Mode Register 0 (address offset 0x054). | 1433 | //5.f. Program BL=0, CL, WR, and PD=1 in the Mode Register 0 (address offset 0x054). |
1434 | //All other fields must be left at their default values. | 1434 | //All other fields must be left at their default values. |
1435 | 1435 | ||
1436 | DDR3A_MR0 = 0x00001620; | 1436 | DDR3A_MR0 = 0x00001620; |
1437 | 1437 | ||
1438 | 1438 | ||
1439 | //5.g. Program DIC, RTT, and TDQS in the Mode Register 1 (address offset 0x058). | 1439 | //5.g. Program DIC, RTT, and TDQS in the Mode Register 1 (address offset 0x058). |
1440 | //All other fields must be left at their default values. | 1440 | //All other fields must be left at their default values. |
1441 | 1441 | ||
1442 | DDR3A_MR1 = 0x00000006; | 1442 | DDR3A_MR1 = 0x00000006; |
1443 | 1443 | ||
1444 | 1444 | ||
1445 | //--------------------------------------------------------------------------------------------------------- | 1445 | //--------------------------------------------------------------------------------------------------------- |
1446 | 1446 | ||
1447 | //5.h. Program Mode Register 2 (address offset 0x05C). | 1447 | //5.h. Program Mode Register 2 (address offset 0x05C). |
1448 | // Maintaining default values of Program Mode Register 2 | 1448 | // Maintaining default values of Program Mode Register 2 |
1449 | DDR3A_MR2 = 0x00000040; | 1449 | DDR3A_MR2 = 0x00000040; |
1450 | 1450 | ||
1451 | //5.i. Program DTMPR=1, DTEXD, DTEXG, RANKEN=1 or 3, and RFSHDT=7 in the Data Training Configuration Register (address offset 0x068). | 1451 | //5.i. Program DTMPR=1, DTEXD, DTEXG, RANKEN=1 or 3, and RFSHDT=7 in the Data Training Configuration Register (address offset 0x068). |
1452 | //All other fields must be left at their default values. | 1452 | //All other fields must be left at their default values. |
1453 | DDR3A_DTCR = 0x710035C7; //0x710035C7; | 1453 | DDR3A_DTCR = 0x710035C7; //0x710035C7; |
1454 | 1454 | ||
1455 | //5.j. Program tREFPRD=(5*tREFI/ddr_clk_period) in the PHY General Configuration Register 2 (address offset 0x08C). | 1455 | //5.j. Program tREFPRD=(5*tREFI/ddr_clk_period) in the PHY General Configuration Register 2 (address offset 0x08C). |
1456 | //All other fields must be left at their default values. | 1456 | //All other fields must be left at their default values. |
1457 | 1457 | ||
1458 | DDR3A_PGCR2 = 0x00F03D09; //NOBUB = 0, FXDLAT = 0 | 1458 | DDR3A_PGCR2 = 0x00F03D09; //NOBUB = 0, FXDLAT = 0 |
1459 | //DDR3A_PGCR2 = 0x00F83D09; //NOBUB = 0, FXDLAT = 1 | 1459 | //DDR3A_PGCR2 = 0x00F83D09; //NOBUB = 0, FXDLAT = 1 |
1460 | 1460 | ||
1461 | //Set Impedence Register | 1461 | //Set Impedence Register |
1462 | DDR3A_ZQ0CR1 = 0x0000007B; | 1462 | DDR3A_ZQ0CR1 = 0x0000007B; |
1463 | DDR3A_ZQ1CR1 = 0x0000007B; | 1463 | DDR3A_ZQ1CR1 = 0x0000007B; |
1464 | DDR3A_ZQ2CR1 = 0x0000007B; | 1464 | DDR3A_ZQ2CR1 = 0x0000007B; |
1465 | 1465 | ||
1466 | 1466 | ||
1467 | //6. Re-trigger PHY initialization in DDR PHY through the VBUSP interface. | 1467 | //6. Re-trigger PHY initialization in DDR PHY through the VBUSP interface. |
1468 | //6.a. Program 0x00000033 to the PHY Initialization Register (address offset 0x004) to re-trigger PLL, ZCAL, and DCAL initialization. | 1468 | //6.a. Program 0x00000033 to the PHY Initialization Register (address offset 0x004) to re-trigger PLL, ZCAL, and DCAL initialization. |
1469 | 1469 | ||
1470 | DDR3A_PIR = 0x00000033; | 1470 | DDR3A_PIR = 0x00000033; |
1471 | 1471 | ||
1472 | //6.b. Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010). | 1472 | //6.b. Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010). |
1473 | do { | 1473 | do { |
1474 | read_val = DDR3A_PGSR0; | 1474 | read_val = DDR3A_PGSR0; |
1475 | } while ((read_val&0x00000001) != 0x00000001); | 1475 | } while ((read_val&0x00000001) != 0x00000001); |
1476 | 1476 | ||
1477 | //--------------------------------------------------------------------------------------------------------- | 1477 | //--------------------------------------------------------------------------------------------------------- |
1478 | 1478 | ||
1479 | 1479 | ||
1480 | 1480 | ||
1481 | // 7. Trigger DDR3 initialization and leveling/training in DDR PHY through the VBUSP interface. | 1481 | // 7. Trigger DDR3 initialization and leveling/training in DDR PHY through the VBUSP interface. |
1482 | // a. If using a 16-bit wide DDR interface, program DXEN=0 in the DATX8 2-7 General Configuration Registers (address offsets 0x240, 0x280, 0x2C0, 0x300, 0x340, and 0x380) to disable the leveling/training for the upper byte lanes. | 1482 | // a. If using a 16-bit wide DDR interface, program DXEN=0 in the DATX8 2-7 General Configuration Registers (address offsets 0x240, 0x280, 0x2C0, 0x300, 0x340, and 0x380) to disable the leveling/training for the upper byte lanes. |
1483 | // b. If using a 32-bit wide DDR interface, program DXEN=0 in the DATX8 4-7 General Configuration Registers (address offsets 0x2C0, 0x300, 0x340, and 0x380) to disable the leveling/training for the upper byte lanes. | 1483 | // b. If using a 32-bit wide DDR interface, program DXEN=0 in the DATX8 4-7 General Configuration Registers (address offsets 0x2C0, 0x300, 0x340, and 0x380) to disable the leveling/training for the upper byte lanes. |
1484 | // c. If ECC is not required, program DXEN=0 in the DATX8 8 General Configuration Register (address offset 0x3C0) to disable the leveling/training for the ECC byte lane. | 1484 | // c. If ECC is not required, program DXEN=0 in the DATX8 8 General Configuration Register (address offset 0x3C0) to disable the leveling/training for the ECC byte lane. |
1485 | // NOTE: Setup supports 64-bit by default, ECC enable by default. | 1485 | // NOTE: Setup supports 64-bit by default, ECC enable by default. |
1486 | 1486 | ||
1487 | //7.d. Program 0x0000XF81 to the PHY Initialization Register (address offset 0x004) to trigger DDR3 initialization and leveling/training sequences | 1487 | //7.d. Program 0x0000XF81 to the PHY Initialization Register (address offset 0x004) to trigger DDR3 initialization and leveling/training sequences |
1488 | 1488 | ||
1489 | DDR3A_PIR = 0x0000FF81; //WLADJ - ON | 1489 | DDR3A_PIR = 0x0000FF81; //WLADJ - ON |
1490 | //DDR3A_PIR = 0x00000781; //WLADJ - OFF | 1490 | //DDR3A_PIR = 0x00000781; //WLADJ - OFF |
1491 | 1491 | ||
1492 | //--------------------------------------------------------------------------------------------------------- | 1492 | //--------------------------------------------------------------------------------------------------------- |
1493 | 1493 | ||
1494 | //7.e. Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010). | 1494 | //7.e. Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010). |
1495 | do { | 1495 | do { |
1496 | read_val = DDR3A_PGSR0; | 1496 | read_val = DDR3A_PGSR0; |
1497 | } while ((read_val&0x00000001) != 0x00000001); | 1497 | } while ((read_val&0x00000001) != 0x00000001); |
1498 | 1498 | ||
1499 | 1499 | ||
1500 | /* End PHY Configuration */ | 1500 | /* End PHY Configuration */ |
1501 | //--------------------------------------------------------------------------------------------------------- | 1501 | //--------------------------------------------------------------------------------------------------------- |
1502 | /* START EMIF INITIALIZATION | 1502 | /* START EMIF INITIALIZATION |
1503 | ++++++++++++++++++SDCFG Register Calculation+++++++++++++++++++ | 1503 | ++++++++++++++++++SDCFG Register Calculation+++++++++++++++++++ |
1504 | | 31 - 29 | 28 |27 - 25 | 24 | 23 - 22| 21 - 17 | | 1504 | | 31 - 29 | 28 |27 - 25 | 24 | 23 - 22| 21 - 17 | |
1505 | |SDRAM_TYPE|Rsvd|DDR_TERM| DDQS | DYN_ODT| Rsvd | | 1505 | |SDRAM_TYPE|Rsvd|DDR_TERM| DDQS | DYN_ODT| Rsvd | |
1506 | | 0x011 | 0 | 0x011 | 0x1 | 0x00 | 0x0 | | 1506 | | 0x011 | 0 | 0x011 | 0x1 | 0x00 | 0x0 | |
1507 | 1507 | ||
1508 | | 16-14 |13 - 12 | 11 - 8 | 7 |6 - 5 | 4 | 3 | 2 | 1 - 0 | | 1508 | | 16-14 |13 - 12 | 11 - 8 | 7 |6 - 5 | 4 | 3 | 2 | 1 - 0 | |
1509 | | CWL | NM | CL | Rsvd |IBANK | Rsvd|EBANK| Rsvd|PAGE_SIZE| | 1509 | | CWL | NM | CL | Rsvd |IBANK | Rsvd|EBANK| Rsvd|PAGE_SIZE| |
1510 | | 0x11 | 0x00 | 0x1110 | 0x0 | 0x11 | 0x0 | 0 | 0 | 0x10 | | 1510 | | 0x11 | 0x00 | 0x1110 | 0x0 | 0x11 | 0x0 | 0 | 0 | 0x10 | |
1511 | SDCFG = 0x0110 0011 0010 0010 0011 0011 1011 0010 | 1511 | SDCFG = 0x0110 0011 0010 0010 0011 0011 1011 0010 |
1512 | SDCFG = 0x6700486A;//0x63223332 | 1512 | SDCFG = 0x6700486A;//0x63223332 |
1513 | 1513 | ||
1514 | SDRAM_TYPE = 3 | 1514 | SDRAM_TYPE = 3 |
1515 | DDR_TERM = 3 (RZQ/4 = 1; RZQ/6=3) | 1515 | DDR_TERM = 3 (RZQ/4 = 1; RZQ/6=3) |
1516 | DDQS = 1 | 1516 | DDQS = 1 |
1517 | DYN_ODT = 0 | 1517 | DYN_ODT = 0 |
1518 | 1518 | ||
1519 | CWL = 3 (CWL5=0; CWL6=1; CWL7=2; CWL8=3) | 1519 | CWL = 3 (CWL5=0; CWL6=1; CWL7=2; CWL8=3) |
1520 | NM = 0 (64-bit=0, 32-bit=1, 16-bit=2) | 1520 | NM = 0 (64-bit=0, 32-bit=1, 16-bit=2) |
1521 | CL = 14 (CL5=2; CL6=4; CL7=6; CL8=8; CL9=10; CL10=12; CL11=14) | 1521 | CL = 14 (CL5=2; CL6=4; CL7=6; CL8=8; CL9=10; CL10=12; CL11=14) |
1522 | IBANK = 3 (8bank) | 1522 | IBANK = 3 (8bank) |
1523 | EBANK = 0 (0 - pad_cs_o_n[0] , 1 - pad_cs_o_n[1:0]) | 1523 | EBANK = 0 (0 - pad_cs_o_n[0] , 1 - pad_cs_o_n[1:0]) |
1524 | PAGE_SIZE = 2 (1024page-size=2; 2048page-size=3) | 1524 | PAGE_SIZE = 2 (1024page-size=2; 2048page-size=3) |
1525 | */ | 1525 | */ |
1526 | /* Start DDR3A EMIF Configuration */ | 1526 | /* Start DDR3A EMIF Configuration */ |
1527 | //8. Configure the EMIF through the VBUSM interface. | 1527 | //8. Configure the EMIF through the VBUSM interface. |
1528 | //8.a. Program all EMIF MMR\92s. | 1528 | //8.a. Program all EMIF MMR\92s. |
1529 | DDR3A_SDCFG = 0x62001462 ; //0x6200046A | 1529 | DDR3A_SDCFG = 0x62001462 ; //0x6200046A |
1530 | 1530 | ||
1531 | DDR3A_SDTIM1 = 0x0A385022; | 1531 | DDR3A_SDTIM1 = 0x0A385022; |
1532 | DDR3A_SDTIM2 = 0x00001CA5; | 1532 | DDR3A_SDTIM2 = 0x00001CA5; |
1533 | DDR3A_SDTIM3 = 0x210DFF22; | 1533 | DDR3A_SDTIM3 = 0x210DFF22; |
1534 | DDR3A_SDTIM4 = 0x533F03FF; | 1534 | DDR3A_SDTIM4 = 0x533F03FF; |
1535 | 1535 | ||
1536 | DDR3A_ZQCFG = 0x70073200; | 1536 | DDR3A_ZQCFG = 0x70073200; |
1537 | //8.b. Program reg_initref_dis=0 in the SDRAM Refresh Control Register (address offset 0x10). | 1537 | //8.b. Program reg_initref_dis=0 in the SDRAM Refresh Control Register (address offset 0x10). |
1538 | DDR3A_SDRFC = 0x00000C34; | 1538 | DDR3A_SDRFC = 0x00000C34; |
1539 | 1539 | ||
1540 | GEL_TextOut("DDR3A initialization complete \n"); | 1540 | GEL_TextOut("DDR3A initialization complete \n"); |
1541 | /* End DDR3A EMIF Configuration */ | 1541 | /* End DDR3A EMIF Configuration */ |
1542 | 1542 | ||
1543 | } | 1543 | } |
1544 | 1544 | ||
1545 | 1545 | ||
1546 | /*----------------------------------------------------- DDR3A : DDR1066, 32bit--------------------------------------------------------------------------*/ | 1546 | /*----------------------------------------------------- DDR3A : DDR1066, 32bit--------------------------------------------------------------------------*/ |
1547 | ddr3A_32bit_DDR1066_setup() | 1547 | ddr3A_32bit_DDR1066_setup() |
1548 | { | 1548 | { |
1549 | 1549 | ||
1550 | unsigned int multiplier = 15; | 1550 | unsigned int multiplier = 15; |
1551 | unsigned int divider = 0; | 1551 | unsigned int divider = 0; |
1552 | int temp; | 1552 | int temp; |
1553 | unsigned int OD_val = 6; | 1553 | unsigned int OD_val = 6; |
1554 | KICK0 = 0x83E70B13; | 1554 | KICK0 = 0x83E70B13; |
1555 | KICK1 = 0x95A4F1E0; | 1555 | KICK1 = 0x95A4F1E0; |
1556 | 1556 | ||
1557 | 1557 | ||
1558 | //1. Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010). | 1558 | //1. Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010). |
1559 | do { | 1559 | do { |
1560 | read_val = DDR3A_PGSR0; | 1560 | read_val = DDR3A_PGSR0; |
1561 | } while ((read_val&0x00000001) != 0x00000001); | 1561 | } while ((read_val&0x00000001) != 0x00000001); |
1562 | 1562 | ||
1563 | //4. Clocks are enabled and frequency is stable--------------------------------------- | 1563 | //4. Clocks are enabled and frequency is stable--------------------------------------- |
1564 | //DDR3A PLL setup | 1564 | //DDR3A PLL setup |
1565 | GEL_TextOut ( "DDR3 PLL (PLL2) Setup ... \n"); | 1565 | GEL_TextOut ( "DDR3 PLL (PLL2) Setup ... \n"); |
1566 | //DDR3APLLCTL0 = DDR3APLLCTL0 & 0xFF7FFFFF; | 1566 | //DDR3APLLCTL0 = DDR3APLLCTL0 & 0xFF7FFFFF; |
1567 | // Set ENSAT = 1 | 1567 | // Set ENSAT = 1 |
1568 | DDR3APLLCTL1 |= 0x00000040; | 1568 | DDR3APLLCTL1 |= 0x00000040; |
1569 | // Put the PLL in PLL Mode | 1569 | // Put the PLL in PLL Mode |
1570 | DDR3APLLCTL0 |= 0x00800000; | 1570 | DDR3APLLCTL0 |= 0x00800000; |
1571 | // In PLL Controller, reset the PLL (bit 13 in DDR3APLLCTL1 register) | 1571 | // In PLL Controller, reset the PLL (bit 13 in DDR3APLLCTL1 register) |
1572 | DDR3APLLCTL1 |= 0x00002000; | 1572 | DDR3APLLCTL1 |= 0x00002000; |
1573 | // Program the necessary multipliers/dividers and BW adjustments | 1573 | // Program the necessary multipliers/dividers and BW adjustments |
1574 | // Set the divider values | 1574 | // Set the divider values |
1575 | DDR3APLLCTL0 &= ~(0x0000003F); | 1575 | DDR3APLLCTL0 &= ~(0x0000003F); |
1576 | DDR3APLLCTL0 |= (divider & 0x0000003F); | 1576 | DDR3APLLCTL0 |= (divider & 0x0000003F); |
1577 | /* Step 7: Programming OD[3:0] in the SECCTL register */ | 1577 | /* Step 7: Programming OD[3:0] in the SECCTL register */ |
1578 | DDR3APLLCTL0 &= OUTPUT_DIVIDE_MASK; // clear the OD bit field | 1578 | DDR3APLLCTL0 &= OUTPUT_DIVIDE_MASK; // clear the OD bit field |
1579 | DDR3APLLCTL0 |= ~OUTPUT_DIVIDE_MASK & (OD_val - 1) << OUTPUT_DIVIDE_OFFSET; // set the OD[3:0] bit field of PLLD to OD_val | 1579 | DDR3APLLCTL0 |= ~OUTPUT_DIVIDE_MASK & (OD_val - 1) << OUTPUT_DIVIDE_OFFSET; // set the OD[3:0] bit field of PLLD to OD_val |
1580 | 1580 | ||
1581 | /* Set the Multipler values */ | 1581 | /* Set the Multipler values */ |
1582 | DDR3APLLCTL0 &= ~(0x0007FFC0); | 1582 | DDR3APLLCTL0 &= ~(0x0007FFC0); |
1583 | DDR3APLLCTL0 |= ((multiplier << 6) & 0x0007FFC0 ); | 1583 | DDR3APLLCTL0 |= ((multiplier << 6) & 0x0007FFC0 ); |
1584 | temp = ((multiplier + 1) >> 1) - 1; | 1584 | temp = ((multiplier + 1) >> 1) - 1; |
1585 | DDR3APLLCTL0 &= ~(0xFF000000); | 1585 | DDR3APLLCTL0 &= ~(0xFF000000); |
1586 | DDR3APLLCTL0 |= ((temp << 24) & 0xFF000000); | 1586 | DDR3APLLCTL0 |= ((temp << 24) & 0xFF000000); |
1587 | DDR3APLLCTL1 &= ~(0x0000000F); | 1587 | DDR3APLLCTL1 &= ~(0x0000000F); |
1588 | DDR3APLLCTL1 |= ((temp >> 8) & 0x0000000F); | 1588 | DDR3APLLCTL1 |= ((temp >> 8) & 0x0000000F); |
1589 | //In DDR3PLLCTL1, write PLLRST = 0 to bring PLL out of reset | 1589 | //In DDR3PLLCTL1, write PLLRST = 0 to bring PLL out of reset |
1590 | DDR3APLLCTL1 &= ~(0x00002000); | 1590 | DDR3APLLCTL1 &= ~(0x00002000); |
1591 | // Put the PLL in PLL Mode | 1591 | // Put the PLL in PLL Mode |
1592 | DDR3APLLCTL0 &= ~(0x00800000); // ReSet the Bit 23 | 1592 | DDR3APLLCTL0 &= ~(0x00800000); // ReSet the Bit 23 |
1593 | GEL_TextOut( "DDR3 PLL Setup complete, DDR3A clock now running at 533MHz.\n" ); | 1593 | GEL_TextOut( "DDR3 PLL Setup complete, DDR3A clock now running at 533MHz.\n" ); |
1594 | //DDR3A PLL setup complete --------------------------------------- | 1594 | //DDR3A PLL setup complete --------------------------------------- |
1595 | 1595 | ||
1596 | /*------------------------- Start PHY Configuration -------------------------------*/ | 1596 | /*------------------------- Start PHY Configuration -------------------------------*/ |
1597 | 1597 | ||
1598 | //DDR3A_PGCR1 = 0x0280C487; | 1598 | //DDR3A_PGCR1 = 0x0280C487; |
1599 | 1599 | ||
1600 | //5.a Program FRQSEL in the PLL Control Register (address offset 0x018). | 1600 | //5.a Program FRQSEL in the PLL Control Register (address offset 0x018). |
1601 | DDR3A_PLLCR = 0xDC000; //Set FRQSEL=11, for ctl_clk between 166-275MHz | 1601 | DDR3A_PLLCR = 0xDC000; //Set FRQSEL=11, for ctl_clk between 166-275MHz |
1602 | 1602 | ||
1603 | //5.b. Program WLSTEP=1, IODDRM=1, and ZCKSEL in the PHY General Configuration Register 1 (address offset 0x00C). | 1603 | //5.b. Program WLSTEP=1, IODDRM=1, and ZCKSEL in the PHY General Configuration Register 1 (address offset 0x00C). |
1604 | DDR3A_PGCR1 |= (1 << 2); //WLSTEP = 1 | 1604 | DDR3A_PGCR1 |= (1 << 2); //WLSTEP = 1 |
1605 | 1605 | ||
1606 | DDR3A_PGCR1 &= ~(IODDRM_MASK); | 1606 | DDR3A_PGCR1 &= ~(IODDRM_MASK); |
1607 | DDR3A_PGCR1 |= (( 1 << 7) & IODDRM_MASK); | 1607 | DDR3A_PGCR1 |= (( 1 << 7) & IODDRM_MASK); |
1608 | 1608 | ||
1609 | 1609 | ||
1610 | DDR3A_PGCR1 &= ~(ZCKSEL_MASK); | 1610 | DDR3A_PGCR1 &= ~(ZCKSEL_MASK); |
1611 | DDR3A_PGCR1 |= (( 1 << 23) & ZCKSEL_MASK); | 1611 | DDR3A_PGCR1 |= (( 1 << 23) & ZCKSEL_MASK); |
1612 | 1612 | ||
1613 | 1613 | ||
1614 | //5.c. Program PHY Timing Parameters Register 0-4 (address offset 0x01C - 0x02C). | 1614 | //5.c. Program PHY Timing Parameters Register 0-4 (address offset 0x01C - 0x02C). |
1615 | 1615 | ||
1616 | DDR3A_PTR0 = 0x426213CF; | 1616 | DDR3A_PTR0 = 0x426213CF; |
1617 | 1617 | ||
1618 | DDR3A_PTR1 = 0xCFC712B3; | 1618 | DDR3A_PTR1 = 0xCFC712B3; |
1619 | 1619 | ||
1620 | // Maintaining default values of Phy Timing Parameters Register 2 in PUB | 1620 | // Maintaining default values of Phy Timing Parameters Register 2 in PUB |
1621 | 1621 | ||
1622 | DDR3A_PTR3 = 0x05B411AA;//0x09041104;//0x18061A80; | 1622 | DDR3A_PTR3 = 0x05B411AA;//0x09041104;//0x18061A80; |
1623 | 1623 | ||
1624 | DDR3A_PTR4 = 0x0855A0AA;//0x0AAE7100; | 1624 | DDR3A_PTR4 = 0x0855A0AA;//0x0AAE7100; |
1625 | 1625 | ||
1626 | //5.d. Program PDQ, MPRDQ, and BYTEMASK in the DRAM Configuration Register (address offset 0x044). | 1626 | //5.d. Program PDQ, MPRDQ, and BYTEMASK in the DRAM Configuration Register (address offset 0x044). |
1627 | // All other fields must be left at their default values. | 1627 | // All other fields must be left at their default values. |
1628 | 1628 | ||
1629 | DDR3A_DCR &= ~(PDQ_MASK); //PDQ = 0 | 1629 | DDR3A_DCR &= ~(PDQ_MASK); //PDQ = 0 |
1630 | 1630 | ||
1631 | DDR3A_DCR &= ~(MPRDQ_MASK); //MPRDQ = 0 | 1631 | DDR3A_DCR &= ~(MPRDQ_MASK); //MPRDQ = 0 |
1632 | 1632 | ||
1633 | DDR3A_DCR &= ~(BYTEMASK_MASK); | 1633 | DDR3A_DCR &= ~(BYTEMASK_MASK); |
1634 | DDR3A_DCR |= (( 1 << 10) & BYTEMASK_MASK); | 1634 | DDR3A_DCR |= (( 1 << 10) & BYTEMASK_MASK); |
1635 | 1635 | ||
1636 | 1636 | ||
1637 | DDR3A_DCR &= ~(NOSRA_MASK); | 1637 | DDR3A_DCR &= ~(NOSRA_MASK); |
1638 | DDR3A_DCR |= (( 1 << 27) & NOSRA_MASK); | 1638 | DDR3A_DCR |= (( 1 << 27) & NOSRA_MASK); |
1639 | 1639 | ||
1640 | //DDR3A_DCR &= ~(UDIMM_MASK); | 1640 | //DDR3A_DCR &= ~(UDIMM_MASK); |
1641 | //DDR3A_DCR |= (( 1 << 29) & UDIMM_MASK); | 1641 | //DDR3A_DCR |= (( 1 << 29) & UDIMM_MASK); |
1642 | 1642 | ||
1643 | //RRMODE | 1643 | //RRMODE |
1644 | //DDR3A_DSGCR &= ~(RRMODE_MASK); //RR_MODE = 0 | 1644 | //DDR3A_DSGCR &= ~(RRMODE_MASK); //RR_MODE = 0 |
1645 | 1645 | ||
1646 | //DDR3A_DSGCR &= ~(RRMODE_MASK); //RR_MODE = 1 | 1646 | //DDR3A_DSGCR &= ~(RRMODE_MASK); //RR_MODE = 1 |
1647 | //DDR3A_DSGCR |= (( 1 << 18) & RRMODE_MASK); | 1647 | //DDR3A_DSGCR |= (( 1 << 18) & RRMODE_MASK); |
1648 | 1648 | ||
1649 | 1649 | ||
1650 | //5.e. Program DRAM Timing Parameters Register 0-2 (address offset 0x048 - 0x050). | 1650 | //5.e. Program DRAM Timing Parameters Register 0-2 (address offset 0x048 - 0x050). |
1651 | 1651 | ||
1652 | DDR3A_DTPR0 = 0x54D47744;//0x6D148844; //0x6D148844; 0x69137764 ---changed in rev 1.3 | 1652 | DDR3A_DTPR0 = 0x54D47744;//0x6D148844; //0x6D148844; 0x69137764 ---changed in rev 1.3 |
1653 | 1653 | ||
1654 | DDR3A_DTPR1 = 0x1282AA00;//0x12845A00; | 1654 | DDR3A_DTPR1 = 0x1282AA00;//0x12845A00; |
1655 | DDR3A_DTPR2 = 0x50023200; | 1655 | DDR3A_DTPR2 = 0x50023200; |
1656 | 1656 | ||
1657 | //5.f. Program BL=0, CL, WR, and PD=1 in the Mode Register 0 (address offset 0x054). | 1657 | //5.f. Program BL=0, CL, WR, and PD=1 in the Mode Register 0 (address offset 0x054). |
1658 | //All other fields must be left at their default values. | 1658 | //All other fields must be left at their default values. |
1659 | 1659 | ||
1660 | DDR3A_MR0 = 0x00001830; //0x00001870; | 1660 | DDR3A_MR0 = 0x00001830; //0x00001870; |
1661 | 1661 | ||
1662 | 1662 | ||
1663 | //5.g. Program DIC, RTT, and TDQS in the Mode Register 1 (address offset 0x058). | 1663 | //5.g. Program DIC, RTT, and TDQS in the Mode Register 1 (address offset 0x058). |
1664 | //All other fields must be left at their default values. | 1664 | //All other fields must be left at their default values. |
1665 | 1665 | ||
1666 | DDR3A_MR1 = 0x00000006; //0x00000044; ---changed in rev 1.3 | 1666 | DDR3A_MR1 = 0x00000006; //0x00000044; ---changed in rev 1.3 |
1667 | 1667 | ||
1668 | 1668 | ||
1669 | //--------------------------------------------------------------------------------------------------------- | 1669 | //--------------------------------------------------------------------------------------------------------- |
1670 | 1670 | ||
1671 | //5.h. Program Mode Register 2 (address offset 0x05C). | 1671 | //5.h. Program Mode Register 2 (address offset 0x05C). |
1672 | // Maintaining default values of Program Mode Register 2 | 1672 | // Maintaining default values of Program Mode Register 2 |
1673 | DDR3A_MR2 = 0x00000048; //18 ---changed in rev 1.3 | 1673 | DDR3A_MR2 = 0x00000048; //18 ---changed in rev 1.3 |
1674 | 1674 | ||
1675 | 1675 | ||
1676 | //5.i. Program DTMPR=1, DTEXD, DTEXG, RANKEN=1 or 3, and RFSHDT=7 in the Data Training Configuration Register (address offset 0x068). | 1676 | //5.i. Program DTMPR=1, DTEXD, DTEXG, RANKEN=1 or 3, and RFSHDT=7 in the Data Training Configuration Register (address offset 0x068). |
1677 | //All other fields must be left at their default values. | 1677 | //All other fields must be left at their default values. |
1678 | DDR3A_DTCR = 0x710035C7; //0x730035C7; | 1678 | DDR3A_DTCR = 0x710035C7; //0x730035C7; |
1679 | 1679 | ||
1680 | //5.j. Program tREFPRD=(5*tREFI/ddr_clk_period) in the PHY General Configuration Register 2 (address offset 0x08C). | 1680 | //5.j. Program tREFPRD=(5*tREFI/ddr_clk_period) in the PHY General Configuration Register 2 (address offset 0x08C). |
1681 | //All other fields must be left at their default values. | 1681 | //All other fields must be left at their default values. |
1682 | 1682 | ||
1683 | DDR3A_PGCR2 = 0x00F05161; //NOBUB = 0, FXDLAT = 0 | 1683 | DDR3A_PGCR2 = 0x00F05161; //NOBUB = 0, FXDLAT = 0 |
1684 | //DDR3A_PGCR2 = 0x00F83D09; //NOBUB = 0, FXDLAT = 1 | 1684 | //DDR3A_PGCR2 = 0x00F83D09; //NOBUB = 0, FXDLAT = 1 |
1685 | 1685 | ||
1686 | 1686 | ||
1687 | //Set Impedence Register | 1687 | //Set Impedence Register |
1688 | DDR3A_ZQ0CR1 = 0x0000007B; | 1688 | DDR3A_ZQ0CR1 = 0x0000007B; |
1689 | DDR3A_ZQ1CR1 = 0x0000007B; | 1689 | DDR3A_ZQ1CR1 = 0x0000007B; |
1690 | DDR3A_ZQ2CR1 = 0x0000007B; | 1690 | DDR3A_ZQ2CR1 = 0x0000007B; |
1691 | 1691 | ||
1692 | 1692 | ||
1693 | 1693 | ||
1694 | //6. Re-trigger PHY initialization in DDR PHY through the VBUSP interface. | 1694 | //6. Re-trigger PHY initialization in DDR PHY through the VBUSP interface. |
1695 | //6.a. Program 0x00000033 to the PHY Initialization Register (address offset 0x004) to re-trigger PLL, ZCAL, and DCAL initialization. | 1695 | //6.a. Program 0x00000033 to the PHY Initialization Register (address offset 0x004) to re-trigger PLL, ZCAL, and DCAL initialization. |
1696 | 1696 | ||
1697 | DDR3A_PIR = 0x00000033; | 1697 | DDR3A_PIR = 0x00000033; |
1698 | 1698 | ||
1699 | //6.b. Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010). | 1699 | //6.b. Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010). |
1700 | do { | 1700 | do { |
1701 | read_val = DDR3A_PGSR0; | 1701 | read_val = DDR3A_PGSR0; |
1702 | } while ((read_val&0x00000001) != 0x00000001); | 1702 | } while ((read_val&0x00000001) != 0x00000001); |
1703 | 1703 | ||
1704 | //--------------------------------------------------------------------------------------------------------- | 1704 | //--------------------------------------------------------------------------------------------------------- |
1705 | 1705 | ||
1706 | 1706 | ||
1707 | 1707 | ||
1708 | // 7. Trigger DDR3 initialization and leveling/training in DDR PHY through the VBUSP interface. | 1708 | // 7. Trigger DDR3 initialization and leveling/training in DDR PHY through the VBUSP interface. |
1709 | // a. If using a 16-bit wide DDR interface, program DXEN=0 in the DATX8 2-7 General Configuration Registers (address offsets 0x240, 0x280, 0x2C0, 0x300, 0x340, and 0x380) to disable the leveling/training for the upper byte lanes. | 1709 | // a. If using a 16-bit wide DDR interface, program DXEN=0 in the DATX8 2-7 General Configuration Registers (address offsets 0x240, 0x280, 0x2C0, 0x300, 0x340, and 0x380) to disable the leveling/training for the upper byte lanes. |
1710 | // b. If using a 32-bit wide DDR interface, program DXEN=0 in the DATX8 4-7 General Configuration Registers (address offsets 0x2C0, 0x300, 0x340, and 0x380) to disable the leveling/training for the upper byte lanes. | 1710 | // b. If using a 32-bit wide DDR interface, program DXEN=0 in the DATX8 4-7 General Configuration Registers (address offsets 0x2C0, 0x300, 0x340, and 0x380) to disable the leveling/training for the upper byte lanes. |
1711 | // c. If ECC is not required, program DXEN=0 in the DATX8 8 General Configuration Register (address offset 0x3C0) to disable the leveling/training for the ECC byte lane. | 1711 | // c. If ECC is not required, program DXEN=0 in the DATX8 8 General Configuration Register (address offset 0x3C0) to disable the leveling/training for the ECC byte lane. |
1712 | // NOTE: Setup supports 64-bit by default, ECC enable by default. | 1712 | // NOTE: Setup supports 64-bit by default, ECC enable by default. |
1713 | 1713 | ||
1714 | //7.d. Program 0x0000XF81 to the PHY Initialization Register (address offset 0x004) to trigger DDR3 initialization and leveling/training sequences | 1714 | //7.d. Program 0x0000XF81 to the PHY Initialization Register (address offset 0x004) to trigger DDR3 initialization and leveling/training sequences |
1715 | 1715 | ||
1716 | DDR3A_PIR = 0x0000FF81; //WLADJ - ON | 1716 | DDR3A_PIR = 0x0000FF81; //WLADJ - ON |
1717 | //DDR3A_PIR = 0x00000781; //WLADJ - OFF | 1717 | //DDR3A_PIR = 0x00000781; //WLADJ - OFF |
1718 | 1718 | ||
1719 | 1719 | ||
1720 | //--------------------------------------------------------------------------------------------------------- | 1720 | //--------------------------------------------------------------------------------------------------------- |
1721 | 1721 | ||
1722 | //7.e. Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010). | 1722 | //7.e. Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010). |
1723 | do { | 1723 | do { |
1724 | read_val = DDR3A_PGSR0; | 1724 | read_val = DDR3A_PGSR0; |
1725 | } while ((read_val&0x00000001) != 0x00000001); | 1725 | } while ((read_val&0x00000001) != 0x00000001); |
1726 | 1726 | ||
1727 | 1727 | ||
1728 | /* End PHY Configuration */ | 1728 | /* End PHY Configuration */ |
1729 | //--------------------------------------------------------------------------------------------------------- | 1729 | //--------------------------------------------------------------------------------------------------------- |
1730 | /* START EMIF INITIALIZATION | 1730 | /* START EMIF INITIALIZATION |
1731 | ++++++++++++++++++SDCFG Register Calculation+++++++++++++++++++ | 1731 | ++++++++++++++++++SDCFG Register Calculation+++++++++++++++++++ |
1732 | | 31 - 29 | 28 |27 - 25 | 24 | 23 - 22| 21 - 17 | | 1732 | | 31 - 29 | 28 |27 - 25 | 24 | 23 - 22| 21 - 17 | |
1733 | |SDRAM_TYPE|Rsvd|DDR_TERM| DDQS | DYN_ODT| Rsvd | | 1733 | |SDRAM_TYPE|Rsvd|DDR_TERM| DDQS | DYN_ODT| Rsvd | |
1734 | | 0x011 | 0 | 0x011 | 0x1 | 0x00 | 0x0 | | 1734 | | 0x011 | 0 | 0x011 | 0x1 | 0x00 | 0x0 | |
1735 | 1735 | ||
1736 | | 16-14 |13 - 12 | 11 - 8 | 7 |6 - 5 | 4 | 3 | 2 | 1 - 0 | | 1736 | | 16-14 |13 - 12 | 11 - 8 | 7 |6 - 5 | 4 | 3 | 2 | 1 - 0 | |
1737 | | CWL | NM | CL | Rsvd |IBANK | Rsvd|EBANK| Rsvd|PAGE_SIZE| | 1737 | | CWL | NM | CL | Rsvd |IBANK | Rsvd|EBANK| Rsvd|PAGE_SIZE| |
1738 | | 0x11 | 0x00 | 0x1110 | 0x0 | 0x11 | 0x0 | 0 | 0 | 0x10 | | 1738 | | 0x11 | 0x00 | 0x1110 | 0x0 | 0x11 | 0x0 | 0 | 0 | 0x10 | |
1739 | SDCFG = 0x0110 0011 0010 0010 0011 0011 1011 0010 | 1739 | SDCFG = 0x0110 0011 0010 0010 0011 0011 1011 0010 |
1740 | SDCFG = 0x6700486A;//0x63223332 | 1740 | SDCFG = 0x6700486A;//0x63223332 |
1741 | 1741 | ||
1742 | SDRAM_TYPE = 3 | 1742 | SDRAM_TYPE = 3 |
1743 | DDR_TERM = 3 (RZQ/4 = 1; RZQ/6=3) | 1743 | DDR_TERM = 3 (RZQ/4 = 1; RZQ/6=3) |
1744 | DDQS = 1 | 1744 | DDQS = 1 |
1745 | DYN_ODT = 0 | 1745 | DYN_ODT = 0 |
1746 | 1746 | ||
1747 | CWL = 3 (CWL5=0; CWL6=1; CWL7=2; CWL8=3) | 1747 | CWL = 3 (CWL5=0; CWL6=1; CWL7=2; CWL8=3) |
1748 | NM = 0 (64-bit=0, 32-bit=1, 16-bit=2) | 1748 | NM = 0 (64-bit=0, 32-bit=1, 16-bit=2) |
1749 | CL = 14 (CL5=2; CL6=4; CL7=6; CL8=8; CL9=10; CL10=12; CL11=14) | 1749 | CL = 14 (CL5=2; CL6=4; CL7=6; CL8=8; CL9=10; CL10=12; CL11=14) |
1750 | IBANK = 3 (8bank) | 1750 | IBANK = 3 (8bank) |
1751 | EBANK = 0 (0 - pad_cs_o_n[0] , 1 - pad_cs_o_n[1:0]) | 1751 | EBANK = 0 (0 - pad_cs_o_n[0] , 1 - pad_cs_o_n[1:0]) |
1752 | PAGE_SIZE = 2 (1024page-size=2; 2048page-size=3) | 1752 | PAGE_SIZE = 2 (1024page-size=2; 2048page-size=3) |
1753 | */ | 1753 | */ |
1754 | /* Start DDR3A EMIF Configuration */ | 1754 | /* Start DDR3A EMIF Configuration */ |
1755 | //8. Configure the EMIF through the VBUSM interface. | 1755 | //8. Configure the EMIF through the VBUSM interface. |
1756 | //8.a. Program all EMIF MMR\92s. | 1756 | //8.a. Program all EMIF MMR\92s. |
1757 | DDR3A_SDCFG = 0x62005662; //0x62005662; | 1757 | DDR3A_SDCFG = 0x62005662; //0x62005662; |
1758 | DDR3A_SDTIM1 = 0x0E4C6833; //0x0E4C6833;//0x0E4C6833; | 1758 | DDR3A_SDTIM1 = 0x0E4C6833; //0x0E4C6833;//0x0E4C6833; |
1759 | DDR3A_SDTIM2 = 0x00001CC6; //0x00001CE7; | 1759 | DDR3A_SDTIM2 = 0x00001CC6; //0x00001CE7; |
1760 | DDR3A_SDTIM3 = 0x3169FF32; //0x323DFF32; | 1760 | DDR3A_SDTIM3 = 0x3169FF32; //0x323DFF32; |
1761 | DDR3A_SDTIM4 = 0x533F054F; //0x533F08AF; | 1761 | DDR3A_SDTIM4 = 0x533F054F; //0x533F08AF; |
1762 | 1762 | ||
1763 | DDR3A_ZQCFG = 0x70073200;//0xF0073200; | 1763 | DDR3A_ZQCFG = 0x70073200;//0xF0073200; |
1764 | //8.b. Program reg_initref_dis=0 in the SDRAM Refresh Control Register (address offset 0x10). | 1764 | //8.b. Program reg_initref_dis=0 in the SDRAM Refresh Control Register (address offset 0x10). |
1765 | DDR3A_SDRFC = 0x00001045; | 1765 | DDR3A_SDRFC = 0x00001045; |
1766 | 1766 | ||
1767 | GEL_TextOut("DDR3A initialization complete \n"); | 1767 | GEL_TextOut("DDR3A initialization complete \n"); |
1768 | /* End DDR3A EMIF Configuration */ | 1768 | /* End DDR3A EMIF Configuration */ |
1769 | 1769 | ||
1770 | } | 1770 | } |
1771 | 1771 | ||
1772 | /*-------------------------------------------------- | 1772 | /*-------------------------------------------------- |
1773 | DDR3A : DDR1333,32bit | 1773 | DDR3A : DDR1333,32bit |
1774 | ---------------------------------------------------*/ | 1774 | ---------------------------------------------------*/ |
1775 | 1775 | ||
1776 | ddr3A_32bit_DDR1333_setup() | 1776 | ddr3A_32bit_DDR1333_setup() |
1777 | { | 1777 | { |
1778 | unsigned int multiplier = 19; | 1778 | unsigned int multiplier = 19; |
1779 | unsigned int divider = 0; | 1779 | unsigned int divider = 0; |
1780 | int temp; | 1780 | int temp; |
1781 | unsigned int OD_val = 6; | 1781 | unsigned int OD_val = 6; |
1782 | KICK0 = 0x83E70B13; | 1782 | KICK0 = 0x83E70B13; |
1783 | KICK1 = 0x95A4F1E0; | 1783 | KICK1 = 0x95A4F1E0; |
1784 | 1784 | ||
1785 | 1785 | ||
1786 | //1. Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010). | 1786 | //1. Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010). |
1787 | do { | 1787 | do { |
1788 | read_val = DDR3A_PGSR0; | 1788 | read_val = DDR3A_PGSR0; |
1789 | } while ((read_val&0x00000001) != 0x00000001); | 1789 | } while ((read_val&0x00000001) != 0x00000001); |
1790 | 1790 | ||
1791 | //4. Clocks are enabled and frequency is stable--------------------------------------- | 1791 | //4. Clocks are enabled and frequency is stable--------------------------------------- |
1792 | //DDR3A PLL setup | 1792 | //DDR3A PLL setup |
1793 | GEL_TextOut ( "DDR3 PLL (PLL2) Setup ... \n"); | 1793 | GEL_TextOut ( "DDR3 PLL (PLL2) Setup ... \n"); |
1794 | //DDR3APLLCTL0 = DDR3APLLCTL0 & 0xFF7FFFFF; | 1794 | //DDR3APLLCTL0 = DDR3APLLCTL0 & 0xFF7FFFFF; |
1795 | // Set ENSAT = 1 | 1795 | // Set ENSAT = 1 |
1796 | DDR3APLLCTL1 |= 0x00000040; | 1796 | DDR3APLLCTL1 |= 0x00000040; |
1797 | // Put the PLL in PLL Mode | 1797 | // Put the PLL in PLL Mode |
1798 | DDR3APLLCTL0 |= 0x00800000; | 1798 | DDR3APLLCTL0 |= 0x00800000; |
1799 | // In PLL Controller, reset the PLL (bit 13 in DDR3APLLCTL1 register) | 1799 | // In PLL Controller, reset the PLL (bit 13 in DDR3APLLCTL1 register) |
1800 | DDR3APLLCTL1 |= 0x00002000; | 1800 | DDR3APLLCTL1 |= 0x00002000; |
1801 | // Program the necessary multipliers/dividers and BW adjustments | 1801 | // Program the necessary multipliers/dividers and BW adjustments |
1802 | // Set the divider values | 1802 | // Set the divider values |
1803 | DDR3APLLCTL0 &= ~(0x0000003F); | 1803 | DDR3APLLCTL0 &= ~(0x0000003F); |
1804 | DDR3APLLCTL0 |= (divider & 0x0000003F); | 1804 | DDR3APLLCTL0 |= (divider & 0x0000003F); |
1805 | /* Step 7: Programming OD[3:0] in the SECCTL register */ | 1805 | /* Step 7: Programming OD[3:0] in the SECCTL register */ |
1806 | DDR3APLLCTL0 &= OUTPUT_DIVIDE_MASK; // clear the OD bit field | 1806 | DDR3APLLCTL0 &= OUTPUT_DIVIDE_MASK; // clear the OD bit field |
1807 | DDR3APLLCTL0 |= ~OUTPUT_DIVIDE_MASK & (OD_val - 1) << OUTPUT_DIVIDE_OFFSET; // set the OD[3:0] bit field of PLLD to OD_val | 1807 | DDR3APLLCTL0 |= ~OUTPUT_DIVIDE_MASK & (OD_val - 1) << OUTPUT_DIVIDE_OFFSET; // set the OD[3:0] bit field of PLLD to OD_val |
1808 | 1808 | ||
1809 | /* Set the Multipler values */ | 1809 | /* Set the Multipler values */ |
1810 | DDR3APLLCTL0 &= ~(0x0007FFC0); | 1810 | DDR3APLLCTL0 &= ~(0x0007FFC0); |
1811 | DDR3APLLCTL0 |= ((multiplier << 6) & 0x0007FFC0 ); | 1811 | DDR3APLLCTL0 |= ((multiplier << 6) & 0x0007FFC0 ); |
1812 | temp = ((multiplier + 1) >> 1) - 1; | 1812 | temp = ((multiplier + 1) >> 1) - 1; |
1813 | DDR3APLLCTL0 &= ~(0xFF000000); | 1813 | DDR3APLLCTL0 &= ~(0xFF000000); |
1814 | DDR3APLLCTL0 |= ((temp << 24) & 0xFF000000); | 1814 | DDR3APLLCTL0 |= ((temp << 24) & 0xFF000000); |
1815 | DDR3APLLCTL1 &= ~(0x0000000F); | 1815 | DDR3APLLCTL1 &= ~(0x0000000F); |
1816 | DDR3APLLCTL1 |= ((temp >> 8) & 0x0000000F); | 1816 | DDR3APLLCTL1 |= ((temp >> 8) & 0x0000000F); |
1817 | //In DDR3PLLCTL1, write PLLRST = 0 to bring PLL out of reset | 1817 | //In DDR3PLLCTL1, write PLLRST = 0 to bring PLL out of reset |
1818 | DDR3APLLCTL1 &= ~(0x00002000); | 1818 | DDR3APLLCTL1 &= ~(0x00002000); |
1819 | // Put the PLL in PLL Mode | 1819 | // Put the PLL in PLL Mode |
1820 | DDR3APLLCTL0 &= ~(0x00800000); // ReSet the Bit 23 | 1820 | DDR3APLLCTL0 &= ~(0x00800000); // ReSet the Bit 23 |
1821 | GEL_TextOut( "DDR3 PLL Setup complete, DDR3A clock now running at 666 MHz.\n" ); | 1821 | GEL_TextOut( "DDR3 PLL Setup complete, DDR3A clock now running at 666 MHz.\n" ); |
1822 | //DDR3A PLL setup complete --------------------------------------- | 1822 | //DDR3A PLL setup complete --------------------------------------- |
1823 | 1823 | ||
1824 | /*------------------------- Start PHY Configuration -------------------------------*/ | 1824 | /*------------------------- Start PHY Configuration -------------------------------*/ |
1825 | 1825 | ||
1826 | //DDR3A_PGCR1 = 0x0280C487; | 1826 | //DDR3A_PGCR1 = 0x0280C487; |
1827 | 1827 | ||
1828 | //5.a Program FRQSEL in the PLL Control Register (address offset 0x018). | 1828 | //5.a Program FRQSEL in the PLL Control Register (address offset 0x018). |
1829 | DDR3A_PLLCR = 0x0005C000; //Set FRQSEL=01, for ctl_clk between 225-385MHz | 1829 | DDR3A_PLLCR = 0x0005C000; //Set FRQSEL=01, for ctl_clk between 225-385MHz |
1830 | 1830 | ||
1831 | //5.b. Program WLSTEP=1, IODDRM=1, and ZCKSEL in the PHY General Configuration Register 1 (address offset 0x00C). | 1831 | //5.b. Program WLSTEP=1, IODDRM=1, and ZCKSEL in the PHY General Configuration Register 1 (address offset 0x00C). |
1832 | DDR3A_PGCR1 |= (1 << 2); //WLSTEP = 1 | 1832 | DDR3A_PGCR1 |= (1 << 2); //WLSTEP = 1 |
1833 | 1833 | ||
1834 | DDR3A_PGCR1 &= ~(IODDRM_MASK); | 1834 | DDR3A_PGCR1 &= ~(IODDRM_MASK); |
1835 | DDR3A_PGCR1 |= (( 1 << 7) & IODDRM_MASK); | 1835 | DDR3A_PGCR1 |= (( 1 << 7) & IODDRM_MASK); |
1836 | 1836 | ||
1837 | 1837 | ||
1838 | DDR3A_PGCR1 &= ~(ZCKSEL_MASK); | 1838 | DDR3A_PGCR1 &= ~(ZCKSEL_MASK); |
1839 | DDR3A_PGCR1 |= (( 1 << 23) & ZCKSEL_MASK); | 1839 | DDR3A_PGCR1 |= (( 1 << 23) & ZCKSEL_MASK); |
1840 | 1840 | ||
1841 | 1841 | ||
1842 | //5.c. Program PHY Timing Parameters Register 0-4 (address offset 0x01C - 0x02C). | 1842 | //5.c. Program PHY Timing Parameters Register 0-4 (address offset 0x01C - 0x02C). |
1843 | 1843 | ||
1844 | DDR3A_PTR0 = 0x426213CF; | 1844 | DDR3A_PTR0 = 0x426213CF; |
1845 | 1845 | ||
1846 | DDR3A_PTR1 = 0xCFC712B3; | 1846 | DDR3A_PTR1 = 0xCFC712B3; |
1847 | 1847 | ||
1848 | // Maintaining default values of Phy Timing Parameters Register 2 in PUB | 1848 | // Maintaining default values of Phy Timing Parameters Register 2 in PUB |
1849 | 1849 | ||
1850 | DDR3A_PTR3 = 0x07151615;//0x072515C2; //0x0B4515C2;//0x18061A80; | 1850 | DDR3A_PTR3 = 0x07151615;//0x072515C2; //0x0B4515C2;//0x18061A80; |
1851 | 1851 | ||
1852 | DDR3A_PTR4 = 0x0A6A08D5;//0x0AAE7100; | 1852 | DDR3A_PTR4 = 0x0A6A08D5;//0x0AAE7100; |
1853 | 1853 | ||
1854 | //5.d. Program PDQ, MPRDQ, and BYTEMASK in the DRAM Configuration Register (address offset 0x044). | 1854 | //5.d. Program PDQ, MPRDQ, and BYTEMASK in the DRAM Configuration Register (address offset 0x044). |
1855 | // All other fields must be left at their default values. | 1855 | // All other fields must be left at their default values. |
1856 | 1856 | ||
1857 | DDR3A_DCR &= ~(PDQ_MASK); //PDQ = 0 | 1857 | DDR3A_DCR &= ~(PDQ_MASK); //PDQ = 0 |
1858 | 1858 | ||
1859 | DDR3A_DCR &= ~(MPRDQ_MASK); //MPRDQ = 0 | 1859 | DDR3A_DCR &= ~(MPRDQ_MASK); //MPRDQ = 0 |
1860 | 1860 | ||
1861 | DDR3A_DCR &= ~(BYTEMASK_MASK); | 1861 | DDR3A_DCR &= ~(BYTEMASK_MASK); |
1862 | DDR3A_DCR |= (( 1 << 10) & BYTEMASK_MASK); | 1862 | DDR3A_DCR |= (( 1 << 10) & BYTEMASK_MASK); |
1863 | 1863 | ||
1864 | 1864 | ||
1865 | DDR3A_DCR &= ~(NOSRA_MASK); | 1865 | DDR3A_DCR &= ~(NOSRA_MASK); |
1866 | DDR3A_DCR |= (( 1 << 27) & NOSRA_MASK); | 1866 | DDR3A_DCR |= (( 1 << 27) & NOSRA_MASK); |
1867 | 1867 | ||
1868 | 1868 | ||
1869 | //DDR3A_DCR &= ~(UDIMM_MASK); | 1869 | //DDR3A_DCR &= ~(UDIMM_MASK); |
1870 | //DDR3A_DCR |= (( 1 << 29) & UDIMM_MASK); | 1870 | //DDR3A_DCR |= (( 1 << 29) & UDIMM_MASK); |
1871 | 1871 | ||
1872 | 1872 | ||
1873 | //5.e. Program DRAM Timing Parameters Register 0-2 (address offset 0x048 - 0x050). | 1873 | //5.e. Program DRAM Timing Parameters Register 0-2 (address offset 0x048 - 0x050). |
1874 | 1874 | ||
1875 | DDR3A_DTPR0 = 0xAD189955;//0x85589975;//0x8558AA55; | 1875 | DDR3A_DTPR0 = 0xAD189955;//0x85589975;//0x8558AA55; |
1876 | DDR3A_DTPR1 = 0x12835A80;//0x12835A80;//0x12857280; | 1876 | DDR3A_DTPR1 = 0x12835A80;//0x12835A80;//0x12857280; |
1877 | DDR3A_DTPR2 = 0x5002C200; | 1877 | DDR3A_DTPR2 = 0x5002C200; |
1878 | 1878 | ||
1879 | //5.f. Program BL=0, CL, WR, and PD=1 in the Mode Register 0 (address offset 0x054). | 1879 | //5.f. Program BL=0, CL, WR, and PD=1 in the Mode Register 0 (address offset 0x054). |
1880 | //All other fields must be left at their default values. | 1880 | //All other fields must be left at their default values. |
1881 | 1881 | ||
1882 | DDR3A_MR0 = 0x00001A60; //50 | 1882 | DDR3A_MR0 = 0x00001A60; //50 |
1883 | 1883 | ||
1884 | 1884 | ||
1885 | //5.g. Program DIC, RTT, and TDQS in the Mode Register 1 (address offset 0x058). | 1885 | //5.g. Program DIC, RTT, and TDQS in the Mode Register 1 (address offset 0x058). |
1886 | //All other fields must be left at their default values. | 1886 | //All other fields must be left at their default values. |
1887 | 1887 | ||
1888 | DDR3A_MR1 = 0x00000006; | 1888 | DDR3A_MR1 = 0x00000006; |
1889 | 1889 | ||
1890 | 1890 | ||
1891 | //--------------------------------------------------------------------------------------------------------- | 1891 | //--------------------------------------------------------------------------------------------------------- |
1892 | 1892 | ||
1893 | //5.h. Program Mode Register 2 (address offset 0x05C). | 1893 | //5.h. Program Mode Register 2 (address offset 0x05C). |
1894 | // Maintaining default values of Program Mode Register 2 | 1894 | // Maintaining default values of Program Mode Register 2 |
1895 | DDR3A_MR2 = 0x00000050; | 1895 | DDR3A_MR2 = 0x00000050; |
1896 | 1896 | ||
1897 | //5.i. Program DTMPR=1, DTEXD, DTEXG, RANKEN=1 or 3, and RFSHDT=7 in the Data Training Configuration Register (address offset 0x068). | 1897 | //5.i. Program DTMPR=1, DTEXD, DTEXG, RANKEN=1 or 3, and RFSHDT=7 in the Data Training Configuration Register (address offset 0x068). |
1898 | //All other fields must be left at their default values. | 1898 | //All other fields must be left at their default values. |
1899 | DDR3A_DTCR = 0x710035C7; //0x730035C7; | 1899 | DDR3A_DTCR = 0x710035C7; //0x730035C7; |
1900 | 1900 | ||
1901 | //5.j. Program tREFPRD=(5*tREFI/ddr_clk_period) in the PHY General Configuration Register 2 (address offset 0x08C). | 1901 | //5.j. Program tREFPRD=(5*tREFI/ddr_clk_period) in the PHY General Configuration Register 2 (address offset 0x08C). |
1902 | //All other fields must be left at their default values. | 1902 | //All other fields must be left at their default values. |
1903 | 1903 | ||
1904 | DDR3A_PGCR2 = 0x00F065B9; //NOBUB = 0, FXDLAT = 0 | 1904 | DDR3A_PGCR2 = 0x00F065B9; //NOBUB = 0, FXDLAT = 0 |
1905 | //DDR3A_PGCR2 = 0x00F83D09; //NOBUB = 0, FXDLAT = 1 | 1905 | //DDR3A_PGCR2 = 0x00F83D09; //NOBUB = 0, FXDLAT = 1 |
1906 | 1906 | ||
1907 | //Set Impedence Register | 1907 | //Set Impedence Register |
1908 | DDR3A_ZQ0CR1 = 0x0000007B; | 1908 | DDR3A_ZQ0CR1 = 0x0000007B; |
1909 | DDR3A_ZQ1CR1 = 0x0000007B; | 1909 | DDR3A_ZQ1CR1 = 0x0000007B; |
1910 | DDR3A_ZQ2CR1 = 0x0000007B; | 1910 | DDR3A_ZQ2CR1 = 0x0000007B; |
1911 | //DDR3A_ZQ3CR1 = 0x0000005D; | 1911 | //DDR3A_ZQ3CR1 = 0x0000005D; |
1912 | 1912 | ||
1913 | //6. Re-trigger PHY initialization in DDR PHY through the VBUSP interface. | 1913 | //6. Re-trigger PHY initialization in DDR PHY through the VBUSP interface. |
1914 | //6.a. Program 0x00000033 to the PHY Initialization Register (address offset 0x004) to re-trigger PLL, ZCAL, and DCAL initialization. | 1914 | //6.a. Program 0x00000033 to the PHY Initialization Register (address offset 0x004) to re-trigger PLL, ZCAL, and DCAL initialization. |
1915 | 1915 | ||
1916 | DDR3A_PIR = 0x00000033; | 1916 | DDR3A_PIR = 0x00000033; |
1917 | 1917 | ||
1918 | //6.b. Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010). | 1918 | //6.b. Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010). |
1919 | do { | 1919 | do { |
1920 | read_val = DDR3A_PGSR0; | 1920 | read_val = DDR3A_PGSR0; |
1921 | } while ((read_val&0x00000001) != 0x00000001); | 1921 | } while ((read_val&0x00000001) != 0x00000001); |
1922 | 1922 | ||
1923 | //--------------------------------------------------------------------------------------------------------- | 1923 | //--------------------------------------------------------------------------------------------------------- |
1924 | 1924 | ||
1925 | 1925 | ||
1926 | 1926 | ||
1927 | // 7. Trigger DDR3 initialization and leveling/training in DDR PHY through the VBUSP interface. | 1927 | // 7. Trigger DDR3 initialization and leveling/training in DDR PHY through the VBUSP interface. |
1928 | // a. If using a 16-bit wide DDR interface, program DXEN=0 in the DATX8 2-7 General Configuration Registers (address offsets 0x240, 0x280, 0x2C0, 0x300, 0x340, and 0x380) to disable the leveling/training for the upper byte lanes. | 1928 | // a. If using a 16-bit wide DDR interface, program DXEN=0 in the DATX8 2-7 General Configuration Registers (address offsets 0x240, 0x280, 0x2C0, 0x300, 0x340, and 0x380) to disable the leveling/training for the upper byte lanes. |
1929 | // b. If using a 32-bit wide DDR interface, program DXEN=0 in the DATX8 4-7 General Configuration Registers (address offsets 0x2C0, 0x300, 0x340, and 0x380) to disable the leveling/training for the upper byte lanes. | 1929 | // b. If using a 32-bit wide DDR interface, program DXEN=0 in the DATX8 4-7 General Configuration Registers (address offsets 0x2C0, 0x300, 0x340, and 0x380) to disable the leveling/training for the upper byte lanes. |
1930 | // c. If ECC is not required, program DXEN=0 in the DATX8 8 General Configuration Register (address offset 0x3C0) to disable the leveling/training for the ECC byte lane. | 1930 | // c. If ECC is not required, program DXEN=0 in the DATX8 8 General Configuration Register (address offset 0x3C0) to disable the leveling/training for the ECC byte lane. |
1931 | // NOTE: Setup supports 64-bit by default, ECC enable by default. | 1931 | // NOTE: Setup supports 64-bit by default, ECC enable by default. |
1932 | 1932 | ||
1933 | //7.d. Program 0x0000XF81 to the PHY Initialization Register (address offset 0x004) to trigger DDR3 initialization and leveling/training sequences | 1933 | //7.d. Program 0x0000XF81 to the PHY Initialization Register (address offset 0x004) to trigger DDR3 initialization and leveling/training sequences |
1934 | 1934 | ||
1935 | DDR3A_PIR = 0x0000FF81; //WLADJ - ON | 1935 | DDR3A_PIR = 0x0000FF81; //WLADJ - ON |
1936 | //DDR3A_PIR = 0x00000781; //WLADJ - OFF | 1936 | //DDR3A_PIR = 0x00000781; //WLADJ - OFF |
1937 | 1937 | ||
1938 | 1938 | ||
1939 | //--------------------------------------------------------------------------------------------------------- | 1939 | //--------------------------------------------------------------------------------------------------------- |
1940 | 1940 | ||
1941 | //7.e. Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010). | 1941 | //7.e. Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010). |
1942 | do { | 1942 | do { |
1943 | read_val = DDR3A_PGSR0; | 1943 | read_val = DDR3A_PGSR0; |
1944 | } while ((read_val&0x00000001) != 0x00000001); | 1944 | } while ((read_val&0x00000001) != 0x00000001); |
1945 | 1945 | ||
1946 | 1946 | ||
1947 | /* End PHY Configuration */ | 1947 | /* End PHY Configuration */ |
1948 | //--------------------------------------------------------------------------------------------------------- | 1948 | //--------------------------------------------------------------------------------------------------------- |
1949 | /* START EMIF INITIALIZATION | 1949 | /* START EMIF INITIALIZATION |
1950 | ++++++++++++++++++SDCFG Register Calculation+++++++++++++++++++ | 1950 | ++++++++++++++++++SDCFG Register Calculation+++++++++++++++++++ |
1951 | | 31 - 29 | 28 |27 - 25 | 24 | 23 - 22| 21 - 17 | | 1951 | | 31 - 29 | 28 |27 - 25 | 24 | 23 - 22| 21 - 17 | |
1952 | |SDRAM_TYPE|Rsvd|DDR_TERM| DDQS | DYN_ODT| Rsvd | | 1952 | |SDRAM_TYPE|Rsvd|DDR_TERM| DDQS | DYN_ODT| Rsvd | |
1953 | | 0x011 | 0 | 0x011 | 0x1 | 0x00 | 0x0 | | 1953 | | 0x011 | 0 | 0x011 | 0x1 | 0x00 | 0x0 | |
1954 | 1954 | ||
1955 | | 16-14 |13 - 12 | 11 - 8 | 7 |6 - 5 | 4 | 3 | 2 | 1 - 0 | | 1955 | | 16-14 |13 - 12 | 11 - 8 | 7 |6 - 5 | 4 | 3 | 2 | 1 - 0 | |
1956 | | CWL | NM | CL | Rsvd |IBANK | Rsvd|EBANK| Rsvd|PAGE_SIZE| | 1956 | | CWL | NM | CL | Rsvd |IBANK | Rsvd|EBANK| Rsvd|PAGE_SIZE| |
1957 | | 0x11 | 0x00 | 0x1110 | 0x0 | 0x11 | 0x0 | 0 | 0 | 0x10 | | 1957 | | 0x11 | 0x00 | 0x1110 | 0x0 | 0x11 | 0x0 | 0 | 0 | 0x10 | |
1958 | SDCFG = 0x0110 0011 0010 0010 0011 0011 1011 0010 | 1958 | SDCFG = 0x0110 0011 0010 0010 0011 0011 1011 0010 |
1959 | SDCFG = 0x6700486A;//0x63223332 | 1959 | SDCFG = 0x6700486A;//0x63223332 |
1960 | 1960 | ||
1961 | SDRAM_TYPE = 3 | 1961 | SDRAM_TYPE = 3 |
1962 | DDR_TERM = 3 (RZQ/4 = 1; RZQ/6=3) | 1962 | DDR_TERM = 3 (RZQ/4 = 1; RZQ/6=3) |
1963 | DDQS = 1 | 1963 | DDQS = 1 |
1964 | DYN_ODT = 0 | 1964 | DYN_ODT = 0 |
1965 | 1965 | ||
1966 | CWL = 3 (CWL5=0; CWL6=1; CWL7=2; CWL8=3) | 1966 | CWL = 3 (CWL5=0; CWL6=1; CWL7=2; CWL8=3) |
1967 | NM = 0 (64-bit=0, 32-bit=1, 16-bit=2) | 1967 | NM = 0 (64-bit=0, 32-bit=1, 16-bit=2) |
1968 | CL = 14 (CL5=2; CL6=4; CL7=6; CL8=8; CL9=10; CL10=12; CL11=14) | 1968 | CL = 14 (CL5=2; CL6=4; CL7=6; CL8=8; CL9=10; CL10=12; CL11=14) |
1969 | IBANK = 3 (8bank) | 1969 | IBANK = 3 (8bank) |
1970 | EBANK = 0 (0 - pad_cs_o_n[0] , 1 - pad_cs_o_n[1:0]) | 1970 | EBANK = 0 (0 - pad_cs_o_n[0] , 1 - pad_cs_o_n[1:0]) |
1971 | PAGE_SIZE = 2 (1024page-size=2; 2048page-size=3) | 1971 | PAGE_SIZE = 2 (1024page-size=2; 2048page-size=3) |
1972 | */ | 1972 | */ |
1973 | /* Start DDR3A EMIF Configuration */ | 1973 | /* Start DDR3A EMIF Configuration */ |
1974 | //8. Configure the EMIF through the VBUSM interface. | 1974 | //8. Configure the EMIF through the VBUSM interface. |
1975 | //8.a. Program all EMIF MMR\92s. | 1975 | //8.a. Program all EMIF MMR\92s. |
1976 | DDR3A_SDCFG = 0x62009C62; // 9A62//0x62008C62 ;//0x6600CE62=single rank,0x6600CE6A=dual rank | 1976 | DDR3A_SDCFG = 0x62009C62; // 9A62//0x62008C62 ;//0x6600CE62=single rank,0x6600CE6A=dual rank |
1977 | 1977 | ||
1978 | DDR3A_SDTIM1 = 0x125C7C44; | 1978 | DDR3A_SDTIM1 = 0x125C7C44; |
1979 | DDR3A_SDTIM2 = 0x00001D08; | 1979 | DDR3A_SDTIM2 = 0x00001D08; |
1980 | DDR3A_SDTIM3 = 0x31C1FF43; | 1980 | DDR3A_SDTIM3 = 0x31C1FF43; |
1981 | DDR3A_SDTIM4 = 0x543F06AF; | 1981 | DDR3A_SDTIM4 = 0x543F06AF; |
1982 | 1982 | ||
1983 | DDR3A_ZQCFG = 0x70073200; | 1983 | DDR3A_ZQCFG = 0x70073200; |
1984 | //8.b. Program reg_initref_dis=0 in the SDRAM Refresh Control Register (address offset 0x10). | 1984 | //8.b. Program reg_initref_dis=0 in the SDRAM Refresh Control Register (address offset 0x10). |
1985 | DDR3A_SDRFC = 0x00001457; | 1985 | DDR3A_SDRFC = 0x00001457; |
1986 | 1986 | ||
1987 | GEL_TextOut("DDR3A initialization complete \n"); | 1987 | GEL_TextOut("DDR3A initialization complete \n"); |
1988 | /* End DDR3A EMIF Configuration */ | 1988 | /* End DDR3A EMIF Configuration */ |
1989 | } | 1989 | } |
1990 | 1990 | ||
1991 | 1991 | ||
1992 | /*-------------------------------------------------- | 1992 | /*-------------------------------------------------- |
1993 | DDR3A : DDR1600,64bit | 1993 | DDR3A : DDR1600,64bit |
1994 | ---------------------------------------------------*/ | 1994 | ---------------------------------------------------*/ |
1995 | 1995 | ||
1996 | ddr3A_64bit_DDR1600_setup() | 1996 | ddr3A_64bit_DDR1600_setup() |
1997 | { | 1997 | { |
1998 | unsigned int multiplier = 7; | 1998 | unsigned int multiplier = 7; |
1999 | unsigned int divider = 0; | 1999 | unsigned int divider = 0; |
2000 | int temp; | 2000 | int temp; |
2001 | unsigned int OD_val = 2; | 2001 | unsigned int OD_val = 2; |
2002 | KICK0 = 0x83E70B13; | 2002 | KICK0 = 0x83E70B13; |
2003 | KICK1 = 0x95A4F1E0; | 2003 | KICK1 = 0x95A4F1E0; |
2004 | 2004 | ||
2005 | 2005 | ||
2006 | //1. Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010). | 2006 | //1. Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010). |
2007 | do { | 2007 | do { |
2008 | read_val = DDR3A_PGSR0; | 2008 | read_val = DDR3A_PGSR0; |
2009 | } while ((read_val&0x00000001) != 0x00000001); | 2009 | } while ((read_val&0x00000001) != 0x00000001); |
2010 | 2010 | ||
2011 | //4. Clocks are enabled and frequency is stable--------------------------------------- | 2011 | //4. Clocks are enabled and frequency is stable--------------------------------------- |
2012 | //DDR3A PLL setup | 2012 | //DDR3A PLL setup |
2013 | GEL_TextOut ( "DDR3 PLL (PLL2) Setup ... \n"); | 2013 | GEL_TextOut ( "DDR3 PLL (PLL2) Setup ... \n"); |
2014 | //DDR3APLLCTL0 = DDR3APLLCTL0 & 0xFF7FFFFF; | 2014 | //DDR3APLLCTL0 = DDR3APLLCTL0 & 0xFF7FFFFF; |
2015 | // Set ENSAT = 1 | 2015 | // Set ENSAT = 1 |
2016 | DDR3APLLCTL1 |= 0x00000040; | 2016 | DDR3APLLCTL1 |= 0x00000040; |
2017 | // Put the PLL in PLL Mode | 2017 | // Put the PLL in PLL Mode |
2018 | DDR3APLLCTL0 |= 0x00800000; | 2018 | DDR3APLLCTL0 |= 0x00800000; |
2019 | // In PLL Controller, reset the PLL (bit 13 in DDR3APLLCTL1 register) | 2019 | // In PLL Controller, reset the PLL (bit 13 in DDR3APLLCTL1 register) |
2020 | DDR3APLLCTL1 |= 0x00002000; | 2020 | DDR3APLLCTL1 |= 0x00002000; |
2021 | // Program the necessary multipliers/dividers and BW adjustments | 2021 | // Program the necessary multipliers/dividers and BW adjustments |
2022 | // Set the divider values | 2022 | // Set the divider values |
2023 | DDR3APLLCTL0 &= ~(0x0000003F); | 2023 | DDR3APLLCTL0 &= ~(0x0000003F); |
2024 | DDR3APLLCTL0 |= (divider & 0x0000003F); | 2024 | DDR3APLLCTL0 |= (divider & 0x0000003F); |
2025 | /* Step 7: Programming OD[3:0] in the SECCTL register */ | 2025 | /* Step 7: Programming OD[3:0] in the SECCTL register */ |
2026 | DDR3APLLCTL0 &= OUTPUT_DIVIDE_MASK; // clear the OD bit field | 2026 | DDR3APLLCTL0 &= OUTPUT_DIVIDE_MASK; // clear the OD bit field |
2027 | DDR3APLLCTL0 |= ~OUTPUT_DIVIDE_MASK & (OD_val - 1) << OUTPUT_DIVIDE_OFFSET; // set the OD[3:0] bit field of PLLD to OD_val | 2027 | DDR3APLLCTL0 |= ~OUTPUT_DIVIDE_MASK & (OD_val - 1) << OUTPUT_DIVIDE_OFFSET; // set the OD[3:0] bit field of PLLD to OD_val |
2028 | 2028 | ||
2029 | /* Set the Multipler values */ | 2029 | /* Set the Multipler values */ |
2030 | DDR3APLLCTL0 &= ~(0x0007FFC0); | 2030 | DDR3APLLCTL0 &= ~(0x0007FFC0); |
2031 | DDR3APLLCTL0 |= ((multiplier << 6) & 0x0007FFC0 ); | 2031 | DDR3APLLCTL0 |= ((multiplier << 6) & 0x0007FFC0 ); |
2032 | temp = ((multiplier + 1) >> 1) - 1; | 2032 | temp = ((multiplier + 1) >> 1) - 1; |
2033 | DDR3APLLCTL0 &= ~(0xFF000000); | 2033 | DDR3APLLCTL0 &= ~(0xFF000000); |
2034 | DDR3APLLCTL0 |= ((temp << 24) & 0xFF000000); | 2034 | DDR3APLLCTL0 |= ((temp << 24) & 0xFF000000); |
2035 | DDR3APLLCTL1 &= ~(0x0000000F); | 2035 | DDR3APLLCTL1 &= ~(0x0000000F); |
2036 | DDR3APLLCTL1 |= ((temp >> 8) & 0x0000000F); | 2036 | DDR3APLLCTL1 |= ((temp >> 8) & 0x0000000F); |
2037 | //In DDR3PLLCTL1, write PLLRST = 0 to bring PLL out of reset | 2037 | //In DDR3PLLCTL1, write PLLRST = 0 to bring PLL out of reset |
2038 | DDR3APLLCTL1 &= ~(0x00002000); | 2038 | DDR3APLLCTL1 &= ~(0x00002000); |
2039 | // Put the PLL in PLL Mode | 2039 | // Put the PLL in PLL Mode |
2040 | DDR3APLLCTL0 &= ~(0x00800000); // ReSet the Bit 23 | 2040 | DDR3APLLCTL0 &= ~(0x00800000); // ReSet the Bit 23 |
2041 | GEL_TextOut( "DDR3 PLL Setup complete, DDR3A clock now running at 666 MHz.\n" ); | 2041 | GEL_TextOut( "DDR3 PLL Setup complete, DDR3A clock now running at 666 MHz.\n" ); |
2042 | //DDR3A PLL setup complete --------------------------------------- | 2042 | //DDR3A PLL setup complete --------------------------------------- |
2043 | 2043 | ||
2044 | /*------------------------- Start PHY Configuration -------------------------------*/ | 2044 | /*------------------------- Start PHY Configuration -------------------------------*/ |
2045 | 2045 | ||
2046 | //DDR3A_PGCR1 = 0x0280C487; | 2046 | //DDR3A_PGCR1 = 0x0280C487; |
2047 | 2047 | ||
2048 | //5.a Program FRQSEL in the PLL Control Register (address offset 0x018). | 2048 | //5.a Program FRQSEL in the PLL Control Register (address offset 0x018). |
2049 | DDR3A_PLLCR = 0x1C000; //Set FRQSEL=00, for ctl_clk between 335-533MHz | 2049 | DDR3A_PLLCR = 0x1C000; //Set FRQSEL=00, for ctl_clk between 335-533MHz |
2050 | 2050 | ||
2051 | //5.b. Program WLSTEP=1, IODDRM=1, and ZCKSEL in the PHY General Configuration Register 1 (address offset 0x00C). | 2051 | //5.b. Program WLSTEP=1, IODDRM=1, and ZCKSEL in the PHY General Configuration Register 1 (address offset 0x00C). |
2052 | DDR3A_PGCR1 |= (1 << 2); //WLSTEP = 1 | 2052 | DDR3A_PGCR1 |= (1 << 2); //WLSTEP = 1 |
2053 | 2053 | ||
2054 | DDR3A_PGCR1 &= ~(IODDRM_MASK); | 2054 | DDR3A_PGCR1 &= ~(IODDRM_MASK); |
2055 | DDR3A_PGCR1 |= (( 1 << 7) & IODDRM_MASK); | 2055 | DDR3A_PGCR1 |= (( 1 << 7) & IODDRM_MASK); |
2056 | 2056 | ||
2057 | 2057 | ||
2058 | DDR3A_PGCR1 &= ~(ZCKSEL_MASK); | 2058 | DDR3A_PGCR1 &= ~(ZCKSEL_MASK); |
2059 | DDR3A_PGCR1 |= (( 1 << 23) & ZCKSEL_MASK); | 2059 | DDR3A_PGCR1 |= (( 1 << 23) & ZCKSEL_MASK); |
2060 | 2060 | ||
2061 | 2061 | ||
2062 | //5.c. Program PHY Timing Parameters Register 0-4 (address offset 0x01C - 0x02C). | 2062 | //5.c. Program PHY Timing Parameters Register 0-4 (address offset 0x01C - 0x02C). |
2063 | 2063 | ||
2064 | DDR3A_PTR0 = 0x426213CF; | 2064 | DDR3A_PTR0 = 0x426213CF; |
2065 | 2065 | ||
2066 | DDR3A_PTR1 = 0xCFC712B3; | 2066 | DDR3A_PTR1 = 0xCFC712B3; |
2067 | 2067 | ||
2068 | // Maintaining default values of Phy Timing Parameters Register 2 in PUB | 2068 | // Maintaining default values of Phy Timing Parameters Register 2 in PUB |
2069 | 2069 | ||
2070 | DDR3A_PTR3 = 0x08861A80;//0x072515C2; //0x0B4515C2;//0x18061A80; | 2070 | DDR3A_PTR3 = 0x08861A80;//0x072515C2; //0x0B4515C2;//0x18061A80; |
2071 | 2071 | ||
2072 | DDR3A_PTR4 = 0x0C827100;//0x0AAE7100; | 2072 | DDR3A_PTR4 = 0x0C827100;//0x0AAE7100; |
2073 | 2073 | ||
2074 | //5.d. Program PDQ, MPRDQ, and BYTEMASK in the DRAM Configuration Register (address offset 0x044). | 2074 | //5.d. Program PDQ, MPRDQ, and BYTEMASK in the DRAM Configuration Register (address offset 0x044). |
2075 | // All other fields must be left at their default values. | 2075 | // All other fields must be left at their default values. |
2076 | 2076 | ||
2077 | DDR3A_DCR &= ~(PDQ_MASK); //PDQ = 0 | 2077 | DDR3A_DCR &= ~(PDQ_MASK); //PDQ = 0 |
2078 | 2078 | ||
2079 | DDR3A_DCR &= ~(MPRDQ_MASK); //MPRDQ = 0 | 2079 | DDR3A_DCR &= ~(MPRDQ_MASK); //MPRDQ = 0 |
2080 | 2080 | ||
2081 | DDR3A_DCR &= ~(BYTEMASK_MASK); | 2081 | DDR3A_DCR &= ~(BYTEMASK_MASK); |
2082 | DDR3A_DCR |= (( 1 << 10) & BYTEMASK_MASK); | 2082 | DDR3A_DCR |= (( 1 << 10) & BYTEMASK_MASK); |
2083 | 2083 | ||
2084 | 2084 | ||
2085 | DDR3A_DCR &= ~(NOSRA_MASK); | 2085 | DDR3A_DCR &= ~(NOSRA_MASK); |
2086 | DDR3A_DCR |= (( 1 << 27) & NOSRA_MASK); | 2086 | DDR3A_DCR |= (( 1 << 27) & NOSRA_MASK); |
2087 | 2087 | ||
2088 | 2088 | ||
2089 | //DDR3A_DCR &= ~(UDIMM_MASK); | 2089 | //DDR3A_DCR &= ~(UDIMM_MASK); |
2090 | //DDR3A_DCR |= (( 1 << 29) & UDIMM_MASK); | 2090 | //DDR3A_DCR |= (( 1 << 29) & UDIMM_MASK); |
2091 | 2091 | ||
2092 | 2092 | ||
2093 | //5.e. Program DRAM Timing Parameters Register 0-2 (address offset 0x048 - 0x050). | 2093 | //5.e. Program DRAM Timing Parameters Register 0-2 (address offset 0x048 - 0x050). |
2094 | 2094 | ||
2095 | DDR3A_DTPR0 = 0x011CBB66;//0x85589975;//0x8558AA55; | 2095 | DDR3A_DTPR0 = 0x011CBB66;//0x85589975;//0x8558AA55; |
2096 | DDR3A_DTPR1 = 0x12840300;//0x12835A80;//0x12857280; | 2096 | DDR3A_DTPR1 = 0x12840300;//0x12835A80;//0x12857280; |
2097 | DDR3A_DTPR2 = 0x5002CE00; | 2097 | DDR3A_DTPR2 = 0x5002CE00; |
2098 | 2098 | ||
2099 | //5.f. Program BL=0, CL, WR, and PD=1 in the Mode Register 0 (address offset 0x054). | 2099 | //5.f. Program BL=0, CL, WR, and PD=1 in the Mode Register 0 (address offset 0x054). |
2100 | //All other fields must be left at their default values. | 2100 | //All other fields must be left at their default values. |
2101 | 2101 | ||
2102 | DDR3A_MR0 = 0x00001C70; //50 | 2102 | DDR3A_MR0 = 0x00001C70; //50 |
2103 | 2103 | ||
2104 | 2104 | ||
2105 | //5.g. Program DIC, RTT, and TDQS in the Mode Register 1 (address offset 0x058). | 2105 | //5.g. Program DIC, RTT, and TDQS in the Mode Register 1 (address offset 0x058). |
2106 | //All other fields must be left at their default values. | 2106 | //All other fields must be left at their default values. |
2107 | 2107 | ||
2108 | DDR3A_MR1 = 0x00000006; | 2108 | DDR3A_MR1 = 0x00000006; |
2109 | 2109 | ||
2110 | 2110 | ||
2111 | //--------------------------------------------------------------------------------------------------------- | 2111 | //--------------------------------------------------------------------------------------------------------- |
2112 | 2112 | ||
2113 | //5.h. Program Mode Register 2 (address offset 0x05C). | 2113 | //5.h. Program Mode Register 2 (address offset 0x05C). |
2114 | // Maintaining default values of Program Mode Register 2 | 2114 | // Maintaining default values of Program Mode Register 2 |
2115 | DDR3A_MR2 = 0x00000058; | 2115 | DDR3A_MR2 = 0x00000058; |
2116 | 2116 | ||
2117 | //5.i. Program DTMPR=1, DTEXD, DTEXG, RANKEN=1 or 3, and RFSHDT=7 in the Data Training Configuration Register (address offset 0x068). | 2117 | //5.i. Program DTMPR=1, DTEXD, DTEXG, RANKEN=1 or 3, and RFSHDT=7 in the Data Training Configuration Register (address offset 0x068). |
2118 | //All other fields must be left at their default values. | 2118 | //All other fields must be left at their default values. |
2119 | DDR3A_DTCR = 0x710035C7; //0x730035C7; | 2119 | DDR3A_DTCR = 0x710035C7; //0x730035C7; |
2120 | 2120 | ||
2121 | //5.j. Program tREFPRD=(5*tREFI/ddr_clk_period) in the PHY General Configuration Register 2 (address offset 0x08C). | 2121 | //5.j. Program tREFPRD=(5*tREFI/ddr_clk_period) in the PHY General Configuration Register 2 (address offset 0x08C). |
2122 | //All other fields must be left at their default values. | 2122 | //All other fields must be left at their default values. |
2123 | 2123 | ||
2124 | DDR3A_PGCR2 = 0x00F07A12; //NOBUB = 0, FXDLAT = 0 | 2124 | DDR3A_PGCR2 = 0x00F07A12; //NOBUB = 0, FXDLAT = 0 |
2125 | //DDR3A_PGCR2 = 0x00F83D09; //NOBUB = 0, FXDLAT = 1 | 2125 | //DDR3A_PGCR2 = 0x00F83D09; //NOBUB = 0, FXDLAT = 1 |
2126 | 2126 | ||
2127 | //Set Impedence Register | 2127 | //Set Impedence Register |
2128 | DDR3A_ZQ0CR1 = 0x0000007B; | 2128 | DDR3A_ZQ0CR1 = 0x0000007B; |
2129 | DDR3A_ZQ1CR1 = 0x0000007B; | 2129 | DDR3A_ZQ1CR1 = 0x0000007B; |
2130 | DDR3A_ZQ2CR1 = 0x0000007B; | 2130 | DDR3A_ZQ2CR1 = 0x0000007B; |
2131 | //DDR3A_ZQ3CR1 = 0x0000005D; | 2131 | //DDR3A_ZQ3CR1 = 0x0000005D; |
2132 | 2132 | ||
2133 | //6. Re-trigger PHY initialization in DDR PHY through the VBUSP interface. | 2133 | //6. Re-trigger PHY initialization in DDR PHY through the VBUSP interface. |
2134 | //6.a. Program 0x00000033 to the PHY Initialization Register (address offset 0x004) to re-trigger PLL, ZCAL, and DCAL initialization. | 2134 | //6.a. Program 0x00000033 to the PHY Initialization Register (address offset 0x004) to re-trigger PLL, ZCAL, and DCAL initialization. |
2135 | 2135 | ||
2136 | DDR3A_PIR = 0x00000033; | 2136 | DDR3A_PIR = 0x00000033; |
2137 | 2137 | ||
2138 | //6.b. Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010). | 2138 | //6.b. Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010). |
2139 | do { | 2139 | do { |
2140 | read_val = DDR3A_PGSR0; | 2140 | read_val = DDR3A_PGSR0; |
2141 | } while ((read_val&0x00000001) != 0x00000001); | 2141 | } while ((read_val&0x00000001) != 0x00000001); |
2142 | 2142 | ||
2143 | //--------------------------------------------------------------------------------------------------------- | 2143 | //--------------------------------------------------------------------------------------------------------- |
2144 | 2144 | ||
2145 | 2145 | ||
2146 | 2146 | ||
2147 | // 7. Trigger DDR3 initialization and leveling/training in DDR PHY through the VBUSP interface. | 2147 | // 7. Trigger DDR3 initialization and leveling/training in DDR PHY through the VBUSP interface. |
2148 | // a. If using a 16-bit wide DDR interface, program DXEN=0 in the DATX8 2-7 General Configuration Registers (address offsets 0x240, 0x280, 0x2C0, 0x300, 0x340, and 0x380) to disable the leveling/training for the upper byte lanes. | 2148 | // a. If using a 16-bit wide DDR interface, program DXEN=0 in the DATX8 2-7 General Configuration Registers (address offsets 0x240, 0x280, 0x2C0, 0x300, 0x340, and 0x380) to disable the leveling/training for the upper byte lanes. |
2149 | // b. If using a 32-bit wide DDR interface, program DXEN=0 in the DATX8 4-7 General Configuration Registers (address offsets 0x2C0, 0x300, 0x340, and 0x380) to disable the leveling/training for the upper byte lanes. | 2149 | // b. If using a 32-bit wide DDR interface, program DXEN=0 in the DATX8 4-7 General Configuration Registers (address offsets 0x2C0, 0x300, 0x340, and 0x380) to disable the leveling/training for the upper byte lanes. |
2150 | // c. If ECC is not required, program DXEN=0 in the DATX8 8 General Configuration Register (address offset 0x3C0) to disable the leveling/training for the ECC byte lane. | 2150 | // c. If ECC is not required, program DXEN=0 in the DATX8 8 General Configuration Register (address offset 0x3C0) to disable the leveling/training for the ECC byte lane. |
2151 | // NOTE: Setup supports 64-bit by default, ECC enable by default. | 2151 | // NOTE: Setup supports 64-bit by default, ECC enable by default. |
2152 | 2152 | ||
2153 | //7.d. Program 0x0000XF81 to the PHY Initialization Register (address offset 0x004) to trigger DDR3 initialization and leveling/training sequences | 2153 | //7.d. Program 0x0000XF81 to the PHY Initialization Register (address offset 0x004) to trigger DDR3 initialization and leveling/training sequences |
2154 | 2154 | ||
2155 | DDR3A_PIR = 0x0000FF81; //WLADJ - ON | 2155 | DDR3A_PIR = 0x0000FF81; //WLADJ - ON |
2156 | //DDR3A_PIR = 0x00000781; //WLADJ - OFF | 2156 | // |