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-rw-r--r--post/docs/README.txt18
1 files changed, 8 insertions, 10 deletions
diff --git a/post/docs/README.txt b/post/docs/README.txt
index 82092e7..285d59c 100644
--- a/post/docs/README.txt
+++ b/post/docs/README.txt
@@ -36,18 +36,16 @@ Steps to run POST in CCSv5:
36 36
37Steps to program POST to EEPROM: 37Steps to program POST to EEPROM:
38 38
391. Be sure that IBL romparse.exe is pre-built under tools\boot_loader\ibl\src\util\romparse, if IBL is not built, 391. Copy tools\post\evmc66xxl\bin\post_i2crom.bin to tools\writer\eeprom\evmc66xxl\bin directory
40 refer to tools\boot_loader\ibl\doc\README.txt on how to build IBL for EVMC66xxL.
41 40
422. Go to the tools\post\evmc66xxl\bin directory in Windows Explorer and open the post_romparse.bat in a text editor, 412. Navigate to tools\writer\eeprom\evmc66xxl\bin\ and open eepromwriter_input.txt. Make the following changes:
43 change "C6000_CG_DIR", "TARGET", "ENDIAN" and "IBL_ROOT_DIR" parameters accordingly. 42 - Set the file_name to post_i2crom.bin
43 - Set the bus_addr to 0x50
44 - Set start_addr to 0
45 - Set swap_data to 0
46 Save and close eepromwriter_input.txt
44 47
453. Double click post_romparse.bat. This will generate a CCS format image file "post_i2crom.dat", which can be programmed 483. Refer to tools\writer\eeprom\evmc66xxl\docs\README.txt on how to program the raw binary file to EEPROM
46 to I2C EEPROM slave bus address 0x50, below are the steps how to program the EEPROM using the EEPROM writer utility:
47
48 * Copy post_i2crom.dat to tools\writer\eeprom\evmc66xxl\bin directory and rename it to "app.dat".
49 * Change bus_addr to 0x50 and swap_data to "0" in tools\writer\eeprom\evmc66xxl\bin\eepromwriter_input.txt and save the file.
50 * Refer to tools\writer\eeprom\evmc66xxl\docs\README.txt on how to program the CCS data file to EEPROM.
51 49
524. Once the programming is completed successfully, user can set the boot mode to I2C mode with bus address 0x50 and 504. Once the programming is completed successfully, user can set the boot mode to I2C mode with bus address 0x50 and
53 boot the POST directly from the EEPROM after POR. The boot status and test result can be monitored using the Hyper 51 boot the POST directly from the EEPROM after POR. The boot status and test result can be monitored using the Hyper