summaryrefslogtreecommitdiffstats
blob: 31c75fecc5522beaa50830870ab8ac864c3a90ad (plain) (blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311
2312
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432
2433
2434
2435
2436
2437
2438
2439
2440
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467
2468
2469
2470
2471
2472
2473
2474
2475
2476
2477
2478
2479
2480
2481
2482
2483
2484
2485
2486
2487
2488
2489
2490
2491
2492
2493
2494
2495
2496
2497
2498
2499
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510
2511
2512
2513
2514
2515
2516
2517
2518
2519
2520
2521
2522
2523
2524
2525
2526
2527
2528
2529
2530
2531
2532
2533
2534
2535
2536
2537
2538
2539
2540
2541
2542
2543
2544
2545
2546
2547
2548
2549
2550
2551
2552
2553
2554
2555
2556
2557
2558
2559
2560
2561
2562
2563
2564
2565
2566
2567
2568
2569
2570
2571
2572
2573
2574
2575
2576
2577
2578
2579
2580
2581
2582
2583
2584
2585
2586
2587
2588
2589
2590
2591
2592
2593
2594
2595
2596
2597
2598
2599
2600
2601
2602
2603
2604
2605
2606
2607
2608
2609
2610
2611
2612
2613
2614
2615
2616
2617
2618
2619
2620
2621
2622
2623
2624
2625
2626
2627
2628
2629
2630
2631
2632
2633
2634
2635
2636
2637
2638
2639
2640
2641
2642
2643
2644
2645
2646
2647
2648
2649
2650
2651
2652
2653
2654
2655
2656
2657
2658
2659
2660
2661
2662
2663
2664
2665
2666
2667
2668
2669
2670
2671
2672
2673
2674
2675
2676
2677
2678
2679
2680
2681
2682
2683
2684
2685
2686
2687
2688
2689
2690
2691
2692
2693
2694
2695
2696
2697
2698
2699
2700
2701
2702
2703
2704
2705
2706
2707
2708
2709
2710
2711
2712
2713
2714
2715
2716
2717
2718
2719
2720
2721
2722
2723
2724
2725
2726
2727
2728
2729
2730
2731
2732
2733
2734
2735
2736
2737
2738
2739
2740
2741
2742
2743
2744
2745
2746
2747
2748
2749
2750
2751
2752
2753
2754
2755
2756
2757
2758
2759
2760
2761
2762
2763
2764
2765
2766
2767
2768
2769
2770
2771
2772
2773
2774
2775
2776
2777
2778
2779
2780
2781
2782
2783
2784
2785
2786
2787
2788
2789
2790
2791
2792
2793
2794
2795
2796
2797
2798
2799
2800
2801
2802
2803
2804
2805
2806
2807
2808
2809
2810
2811
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821
2822
2823
2824
2825
2826
2827
2828
2829
2830
2831
2832
2833
2834
2835
2836
2837
2838
2839
2840
2841
2842
2843
2844
2845
2846
2847
2848
2849
2850
2851
2852
2853
2854
2855
2856
2857
2858
2859
2860
2861
2862
2863
2864
2865
2866
2867
2868
2869
2870
2871
2872
2873
2874
2875
2876
2877
2878
2879
2880
2881
2882
2883
2884
2885
2886
2887
2888
2889
2890
2891
2892
2893
2894
2895
2896
2897
2898
2899
2900
2901
2902
2903
2904
2905
2906
2907
2908
2909
2910
2911
2912
2913
2914
2915
2916
2917
2918
2919
2920
2921
2922
2923
2924
2925
2926
2927
2928
2929
2930
2931
2932
2933
2934
2935
2936
2937
2938
2939
2940
2941
2942
2943
2944
2945
2946
2947
2948
2949
2950
2951
2952
2953
2954
2955
2956
2957
2958
2959
2960
2961
2962
2963
2964
2965
2966
2967
2968
2969
2970
2971
2972
2973
2974
2975
2976
2977
2978
2979
2980
2981
2982
2983
2984
2985
2986
2987
2988
2989
2990
2991
2992
2993
2994
2995
2996
2997
2998
2999
3000
3001
3002
3003
3004
3005
3006
3007
3008
3009
3010
3011
3012
3013
3014
3015
3016
3017
3018
3019
3020
3021
3022
3023
3024
3025
3026
3027
3028
3029
3030
3031
3032
3033
3034
3035
3036
3037
3038
3039
3040
3041
3042
3043
3044
3045
3046
3047
3048
3049
3050
3051
3052
3053
3054
3055
3056
3057
3058
3059
3060
3061
3062
3063
3064
3065
3066
3067
3068
3069
3070
3071
3072
3073
3074
3075
3076
3077
3078
3079
3080
3081
3082
3083
3084
3085
3086
3087
3088
3089
3090
3091
3092
3093
3094
3095
3096
3097
3098
3099
3100
3101
3102
3103
3104
3105
3106
3107
3108
3109
3110
3111
3112
3113
3114
3115
3116
3117
3118
3119
3120
3121
3122
3123
3124
3125
3126
3127
3128
3129
3130
3131
3132
3133
3134
3135
3136
3137
3138
3139
3140
3141
3142
3143
3144
3145
3146
3147
3148
3149
3150
3151
3152
3153
3154
3155
3156
3157
3158
3159
3160
3161
3162
3163
3164
3165
3166
3167
3168
3169
3170
3171
3172
3173
3174
3175
3176
3177
3178
3179
3180
3181
3182
3183
3184
3185
3186
3187
3188
3189
3190
3191
3192
3193
3194
3195
3196
3197
3198
3199
3200
3201
3202
3203
3204
3205
3206
3207
3208
3209
3210
3211
3212
3213
3214
3215
3216
3217
3218
3219
3220
3221
3222
3223
3224
3225
3226
3227
3228
3229
3230
3231
3232
3233
3234
3235
3236
3237
3238
3239
3240
3241
3242
3243
3244
3245
3246
3247
3248
3249
3250
3251
3252
3253
3254
3255
3256
3257
3258
3259
3260
3261
3262
3263
3264
3265
3266
3267
3268
3269
3270
3271
3272
3273
3274
3275
3276
3277
3278
3279
3280
3281
3282
3283
3284
3285
3286
3287
3288
3289
3290
3291
3292
3293
3294
3295
3296
3297
3298
3299
3300
3301
3302
3303
3304
3305
3306
3307
3308
3309
3310
3311
3312
3313
3314
3315
3316
3317
3318
3319
3320
3321
3322
3323
3324
3325
3326
3327
3328
3329
3330
3331
3332
3333
3334
3335
3336
3337
3338
3339
3340
3341
3342
3343
3344
3345
3346
3347
3348
3349
3350
3351
3352
3353
3354
3355
3356
3357
3358
3359
3360
3361
3362
3363
3364
3365
3366
3367
3368
3369
3370
3371
3372
3373
3374
3375
3376
3377
3378
3379
3380
3381
3382
3383
3384
3385
3386
3387
3388
3389
3390
3391
3392
3393
3394
3395
3396
3397
3398
3399
3400
3401
3402
3403
3404
3405
3406
3407
3408
3409
3410
3411
3412
3413
3414
3415
3416
3417
3418
3419
3420
3421
3422
3423
3424
3425
3426
3427
3428
3429
3430
3431
3432
3433
3434
3435
3436
3437
3438
3439
3440
3441
3442
3443
3444
3445
3446
3447
3448
3449
3450
3451
3452
3453
3454
/******************************************************************************
* Copyright (c) 2012 Texas Instruments Incorporated - http://www.ti.com
* 
*  Redistribution and use in source and binary forms, with or without 
*  modification, are permitted provided that the following conditions 
*
*  are met:
*
*    Redistributions of source code must retain the above copyright 
*    notice, this list of conditions and the following disclaimer.
*
*
*    Redistributions in binary form must reproduce the above copyright
*    notice, this list of conditions and the following disclaimer in the     
*    documentation and/or other materials provided with the   
*
*    distribution.
*
*
*    Neither the name of Texas Instruments Incorporated nor the names of
*    its contributors may be used to endorse or promote products derived
*    from this software without specific prior written permission.
*
*
*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* 
*****************************************************************************
*
 ---------------------------------------------------------------------------*/

#define GEL_VERSION         1.3

// Timeout definitions
int _GEL_Global_Timeout1 = 0;

#define TIMEOUT_ID 10
// Global timeout value
#define GTIMEOUT 2000
//*****************************************************
// Power definitions
#define PSC_BASE            0x02350000
#define PSC_PTCMD           *( unsigned int* )( PSC_BASE+0x120 )
#define PSC_PTSTAT          *( unsigned int* )( PSC_BASE+0x128 )
#define PSC_PDCTL_BASE      ( PSC_BASE+0x300 )
#define PSC_MDSTAT_BASE     ( PSC_BASE+0x800 )
#define PSC_MDCTL_BASE      ( PSC_BASE+0xA00 )

// Modules on power domain 0
// Always on

// Modules on power domain 1
#define LPSC_DEBUG     (5)
#define LPSC_TETB      (6)

// Modules on power domain 2
#define LPSC_PA        (7)
#define LPSC_SGMII     (8)
#define LPSC_SA        (9)

// Modules on power domain 3
#define LPSC_PCIE      (10)

// Modules on power domain 4
#define LPSC_SRIO      (11)

// Modules on power domain 5
#define LPSC_HYPERLINK_0     (12)

// Modules on power domain 6
#define LPSC_SR     (13)

// Modules on power domain 7
#define LPSC_MSMCRAM   (14)

// Modules on power domain 8
#define LPSC_GEM_0   (15)

// Modules on power domain 9
#define LPSC_GEM_1   (16)

// Modules on power domain 10
#define LPSC_GEM_2   (17)

// Modules on power domain 11
#define LPSC_GEM_3   (18)

// Modules on power domain 12
#define LPSC_GEM_4   (19)

// Modules on power domain 13
#define LPSC_GEM_5   (20)

// Modules on power domain 14
#define LPSC_GEM_6   (21)

// Modules on power domain 15
#define LPSC_GEM_7   (22)

// Modules on power domain 16
#define LPSC_DDR3_0      (23)
#define LPSC_DDR3_1      (24)

// Modules on power domain 17
#define LPSC_TAC       (25)
#define LPSC_RAC_01       (26)

// Modules on power domain 18
#define LPSC_RAC_23       (27)

// Modules on power domain 19
#define LPSC_FFTCA_FFTC_0 (28)
#define LPSC_FFTCA_FFTC_1 (29)

// Modules on power domain 20
#define LPSC_FFTCA_FFTC_2 (30)
#define LPSC_FFTCA_FFTC_3 (31)
#define LPSC_FFTCA_FFTC_4 (32)
#define LPSC_FFTCA_FFTC_5 (33)

// Modules on power domain 21
#define LPSC_AIF      (34)

// Modules on power domain 22
#define LPSC_TCP3D_0      (35)
#define LPSC_TCP3D_1      (36)

// Modules on power domain 23
#define LPSC_TCP3D_2      (37)
#define LPSC_TCP3D_3      (38)

// Modules on power domain 24
#define LPSC_VCP_0      (39)
#define LPSC_VCP_1      (40)
#define LPSC_VCP_2      (41)
#define LPSC_VCP_3      (42)

// Modules on power domain 25
#define LPSC_VCP_4      (43)
#define LPSC_VCP_5      (44)
#define LPSC_VCP_6      (45)
#define LPSC_VCP_7      (46)

// Modules on power domain 26
#define LPSC_BCP     (47)

// Modules on power domain 27
#define LPSC_DXB     (48)

// Modules on power domain 28
#define LPSC_HYPERLINK_1     (49)

// Modules on power domain 29
#define LPSC_XGE     (50)

// Modules on power domain 31
#define LPSC_ARM    (52)


// Power domains definitions
#define PD0         (0)     // Power Domain-0
#define PD1         (1)     // Power Domain-1
#define PD2         (2)     // Power Domain-2
#define PD3         (3)     // Power Domain-3
#define PD4         (4)     // Power Domain-4
#define PD5         (5)     // Power Domain-5
#define PD6         (6)     // Power Domain-6
#define PD7         (7)     // Power Domain-7
#define PD8         (8)     // Power Domain-8
#define PD9         (9)     // Power Domain-9
#define PD10        (10)    // Power Domain-10
#define PD11        (11)    // Power Domain-11
#define PD12        (12)    // Power Domain-12
#define PD13        (13)    // Power Domain-13
#define PD14        (14)    // Power Domain-14
#define PD15        (15)    // Power Domain-15
#define PD16        (16)    // Power Domain-16
#define PD17        (17)    // Power Domain-17
#define PD18        (18)    // Power Domain-18
#define PD19        (19)    // Power Domain-19
#define PD20        (20)    // Power Domain-20
#define PD21        (21)    // Power Domain-21
#define PD22        (22)    // Power Domain-22
#define PD23        (23)    // Power Domain-23
#define PD24        (24)    // Power Domain-24
#define PD25        (25)    // Power Domain-25
#define PD26        (26)    // Power Domain-26
#define PD27        (27)    // Power Domain-27
#define PD28        (28)    // Power Domain-28
#define PD29        (29)    // Power Domain-29
#define PD30        (30)    // Power Domain-30
#define PD31        (31)    // Power Domain-31

#define PSC_SYNCRESET (0x1)
#define PSC_DISABLE   (0x2)
#define PSC_ENABLE    (0x3)

#define CHIP_LEVEL_REG              0x02620000

/******************* PLL registers **********************************/
/*Boot cfg registers*/
#define KICK0                       *(unsigned int*)(CHIP_LEVEL_REG + 0x0038)
#define KICK1                       *(unsigned int*)(CHIP_LEVEL_REG + 0x003C)
#define KICK0_UNLOCK                (0x83E70B13)
#define KICK1_UNLOCK                (0x95A4F1E0)
#define KICK_LOCK                   0
#define TINPSEL                     *(unsigned int*)(CHIP_LEVEL_REG + 0x0300)
#define TOUTPSEL                    *(unsigned int*)(CHIP_LEVEL_REG + 0x0304)
#define MAINPLLCTL0                 *(unsigned int*)(CHIP_LEVEL_REG + 0x0350) //0x0328)
#define MAINPLLCTL1                 *(unsigned int*)(CHIP_LEVEL_REG + 0x0354) //0x032C)
#define MAIN_PLLD_OFFSET            0
#define MAIN_PLLD_MASK              0xFFFFFFC0
#define MAIN_PLLM_OFFSET            12
#define MAIN_PLLM_MASK              0xFFF80FFF
#define MAIN_BWADJ0_OFFSET          24
#define MAIN_BWADJ0_MASK            0x00FFFFFF
#define MAIN_ENSAT_OFFSET           6
#define MAIN_ENSAT_MASK             0xFFFFFFBF
#define MAIN_BWADJ1_OFFSET          0
#define MAIN_BWADJ1_MASK            0xFFFFFFF0

#define OBSCLKCTL                   *(unsigned int*)(CHIP_LEVEL_REG + 0x0C80)

/* PA PLL Registers */
#define BYPASS_BIT_SHIFT 23
#define CLKF_BIT_SHIFT   6
#define CLKD_BIT_SHIFT   0
#define DEVSTAT    (*((unsigned int *) 0x02620020))
#define PAPLLCTL0                 *(unsigned int*)(CHIP_LEVEL_REG + 0x0358) 
#define PAPLLCTL1                 *(unsigned int*)(CHIP_LEVEL_REG + 0x035C) 
#define PASSCLKSEL_MASK    (1 << 17)    /* Tells the configuration of the PASSCLKSEL pin */
#define PA_PLL_BYPASS_MASK (1 << BYPASS_BIT_SHIFT)    /* Tells whether the PA PLL is in BYPASS mode or not */
#define PA_PLL_CLKOD_MASK  (0x00780000) /* Tells the output divider value for the PA PLL */
#define PA_PLL_CLKF_MASK   (0x0007FFC0) /* Tells the multiplier value for the PA PLL */
#define PA_PLL_CLKR_MASK   (0x0000003F) /* Tells the divider value for the PA PLL */
#define PA_PLL_RESET_MASK  (0x00004000)


#define CHIP_MISC1                  *(unsigned int*)(CHIP_LEVEL_REG + 0x0C7C)
#define ARMPLL_ENABLE_OFFSET        13


#define DDR3APLLCTL0  			*(unsigned int*)(CHIP_LEVEL_REG + 0x0360)
#define DDR3APLLCTL1  			*(unsigned int*)(CHIP_LEVEL_REG + 0x0364)
#define DDR3BPLLCTL0  			*(unsigned int*)(CHIP_LEVEL_REG + 0x0368)
#define DDR3BPLLCTL1  			*(unsigned int*)(CHIP_LEVEL_REG + 0x036C)

//******************************************************
// PLL 1 definitions (DSP and ARM clock and subsystems)
#define PLL1_BASE                   0x02310000
#define PLL1_PLLCTL                 (*(unsigned int*)(PLL1_BASE + 0x100))   // PLL1 Control
#define PLL1_SECCTL                 (*(unsigned int*)(PLL1_BASE + 0x108))   // PLL1 Secondary Control
#define PLL1_PLLM                   (*(unsigned int*)(PLL1_BASE + 0x110))   // PLL1 Multiplier
#define PLL1_DIV1                   (*(unsigned int*)(PLL1_BASE + 0x118))   // DIV1 divider
#define PLL1_DIV2                   (*(unsigned int*)(PLL1_BASE + 0x11C))   // DIV2 divider
#define PLL1_DIV3                   (*(unsigned int*)(PLL1_BASE + 0x120))   // DIV3 divider
#define PLL1_CMD                    (*(unsigned int*)(PLL1_BASE + 0x138))   // CMD control
#define PLL1_STAT                   (*(unsigned int*)(PLL1_BASE + 0x13C))   // STAT control
#define PLL1_ALNCTL                 (*(unsigned int*)(PLL1_BASE + 0x140))   // ALNCTL control
#define PLL1_DCHANGE                (*(unsigned int*)(PLL1_BASE + 0x144))   // DCHANGE status
#define PLL1_CKEN                   (*(unsigned int*)(PLL1_BASE + 0x148))   // CKEN control
#define PLL1_CKSTAT                 (*(unsigned int*)(PLL1_BASE + 0x14C))   // CKSTAT status
#define PLL1_SYSTAT                 (*(unsigned int*)(PLL1_BASE + 0x150))   // SYSTAT status
#define PLL1_DIV4                   (*(unsigned int*)(PLL1_BASE + 0x160))   // DIV4 divider
#define PLL1_DIV5                   (*(unsigned int*)(PLL1_BASE + 0x164))   // DIV5 divider
#define PLL1_DIV6                   (*(unsigned int*)(PLL1_BASE + 0x168))   // DIV6 divider
#define PLL1_DIV7                   (*(unsigned int*)(PLL1_BASE + 0x16C))   // DIV7 divider
#define PLL1_DIV8                   (*(unsigned int*)(PLL1_BASE + 0x170))   // DIV8 divider
#define PLL1_DIV9                   (*(unsigned int*)(PLL1_BASE + 0x174))   // DIV9 divider
#define PLL1_DIV10                  (*(unsigned int*)(PLL1_BASE + 0x178))   // DIV10 divider
#define PLL1_DIV11                  (*(unsigned int*)(PLL1_BASE + 0x17C))   // DIV11 divider
#define PLL1_DIV12                  (*(unsigned int*)(PLL1_BASE + 0x180))   // DIV12 divider
#define PLL1_DIV13                  (*(unsigned int*)(PLL1_BASE + 0x184))   // DIV13 divider
#define PLL1_DIV14                  (*(unsigned int*)(PLL1_BASE + 0x188))   // DIV14 divider
#define PLL1_DIV15                  (*(unsigned int*)(PLL1_BASE + 0x18C))   // DIV15 divider
#define PLL1_DIV16                  (*(unsigned int*)(PLL1_BASE + 0x190))   // DIV16 divider
#define PLLPWRDN_OFFSET             1
#define PLLPWRDN_MASK               0xFFFFFFFD
#define PLLRST_OFFSET               3
#define PLLRST_MASK                 0xFFFFFFF7
#define PLLENSRC_OFFSET             5
#define PLLENSRC_MASK               0xFFFFFFDF
#define PLLEN_OFFSET                0
#define PLLEN_MASK                  0xFFFFFFFE
#define OUTPUT_DIVIDE_OFFSET        19
#define OUTPUT_DIVIDE_MASK          0xFF87FFFF    
#define BYPASS_OFFSET               23
#define BYPASS_MASK                 0xFF7FFFFF
#define PLLM_OFFSET                 0
#define PLLM_MASK                   0xFFFFFFC0
#define GOSET_OFFSET                0
#define GOSET_MASK                  0xFFFFFFFE
#define GOSTAT_OFFSET               0
#define GOSTAT_MASK                 0xFFFFFFFE

#define OUTPUT_DIVIDE_OFFSET        19
#define OUTPUT_DIVIDE_MASK          0xFF87FFFF   

// ARMPLL definitions
#define SEC_PLLCTL0_PLLM_OFFSET     6
#define SEC_PLLCTL0_PLLM_MASK       0xFFFF003F
#define SEC_PLLCTL0_BWADJ_OFFSET    24
#define SEC_PLLCTL0_BWADJ_MASK      0x00FFFFFF
#define SEC_PLLCTL0_OD_OFFSET       19
#define SEC_PLLCTL0_OD_MASK         0xFF87FFFF
#define SEC_PLLCTL0_BYPASS_OFFSET   23
#define SEC_PLLCTL0_BYPASS_MASK     0xFF7FFFFF
#define SEC_PLLCTL1_RESET_OFFSET    14
#define SEC_PLLCTL1_RESET_MASK      0xFFFFBFFF
#define SEC_PLLCTL1_PWRDWN_OFFSET   15
#define SEC_PLLCTL1_PWRDWN_MASK     0xFFFF7FFF
#define SEC_PLLCTL1_ENSTAT_OFFSET   6
#define SEC_PLLCTL1_ENSTAT_MASK     0xFFFFFFBF

/*----------------DDR3A Register definition---------------------*/

#define DDR3A_BASE_ADDR (0x21010000)
#define DDR3A_STATUS   (*(int*)(DDR3A_BASE_ADDR + 0x00000004))
#define DDR3A_SDCFG    (*(int*)(DDR3A_BASE_ADDR + 0x00000008))
#define DDR3A_SDRFC    (*(int*)(DDR3A_BASE_ADDR + 0x00000010))
#define DDR3A_SDTIM1   (*(int*)(DDR3A_BASE_ADDR + 0x00000018))
#define DDR3A_SDTIM2   (*(int*)(DDR3A_BASE_ADDR + 0x0000001C))
#define DDR3A_SDTIM3   (*(int*)(DDR3A_BASE_ADDR + 0x00000020))
#define DDR3A_SDTIM4   (*(int*)(DDR3A_BASE_ADDR + 0x00000028))
#define DDR3A_ZQCFG    (*(int*)(DDR3A_BASE_ADDR + 0x000000C8))
#define DDR3A_TMPALRT  (*(int*)(DDR3A_BASE_ADDR + 0x000000CC))
#define DDR3A_DDRPHYC  (*(int*)(DDR3A_BASE_ADDR + 0x000000E4))

#define DDR3A_PHY_CFG_BASE (0x02329000)
#define DDR3A_PIR    (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000004))
#define DDR3A_PGCR0  (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000008))
#define DDR3A_PGCR1  (*(int*)(DDR3A_PHY_CFG_BASE + 0x0000000C))
#define DDR3A_PGCR2  (*(int*)(DDR3A_PHY_CFG_BASE + 0x0000008C))
#define DDR3A_PGSR0  (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000010))
#define DDR3A_PGSR1  (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000014))
#define DDR3A_PLLCR  (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000018))
#define DDR3A_PTR0   (*(int*)(DDR3A_PHY_CFG_BASE + 0x0000001C))
#define DDR3A_PTR1   (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000020))
#define DDR3A_PTR2   (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000024))
#define DDR3A_PTR3   (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000028))
#define DDR3A_PTR4   (*(int*)(DDR3A_PHY_CFG_BASE + 0x0000002C))
#define DDR3A_DSGCR  (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000040))
#define DDR3A_DCR    (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000044))
#define DDR3A_MR0    (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000054))
#define DDR3A_MR1    (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000058))
#define DDR3A_MR2    (*(int*)(DDR3A_PHY_CFG_BASE + 0x0000005C))
#define DDR3A_DTCR   (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000068))
#define DDR3A_DTPR0  (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000048))
#define DDR3A_DTPR1  (*(int*)(DDR3A_PHY_CFG_BASE + 0x0000004C))
#define DDR3A_DTPR2  (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000050))

#define DDR3A_ZQ0CR1  (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000184))
#define DDR3A_ZQ1CR1  (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000194))
#define DDR3A_ZQ2CR1  (*(int*)(DDR3A_PHY_CFG_BASE + 0x000001A4))
#define DDR3A_ZQ3CR1  (*(int*)(DDR3A_PHY_CFG_BASE + 0x000001B4))

#define DDR3A_DATX8_8 (*(int*)(DDR3A_PHY_CFG_BASE + 0x000003C0))


#define DDR3_TEST_START_ADDRESS (*(int*)(0x80000000))

#define IODDRM_MASK            0x00000180  
#define ZCKSEL_MASK            0x01800000
#define CL_MASK				   0x00000072
#define WR_MASK				   0x00000E00
#define BL_MASK				   0x00000003
#define RRMODE_MASK            0x00040000
#define UDIMM_MASK             0x20000000
#define BYTEMASK_MASK          0x0000FC00
#define MPRDQ_MASK             0x00000080
#define PDQ_MASK               0x00000070
#define NOSRA_MASK             0x08000000
#define ECC_MASK               0x00000001
#define RRMODE_MASK            0x00040000

#define DDR3A_DX0GSR0 (*(int*)(DDR3A_PHY_CFG_BASE + 0x000001C4)) //0x71
#define DDR3A_DX1GSR0 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000204)) //0x81
#define DDR3A_DX2GSR0 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000244)) //0x91
#define DDR3A_DX3GSR0 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000284)) //0xA1
#define DDR3A_DX4GSR0 (*(int*)(DDR3A_PHY_CFG_BASE + 0x000002C4)) //0xB1
#define DDR3A_DX5GSR0 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000304)) //0xC1
#define DDR3A_DX6GSR0 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000344)) //0xD1
#define DDR3A_DX7GSR0 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000384)) //0xE1
#define DDR3A_DX8GSR0 (*(int*)(DDR3A_PHY_CFG_BASE + 0x000003C4)) //0xF1

#define DDR3A_TEST_START_ADDRESS (0x80000000)

#define DDR3A_TEST_END_ADDRESS   (DDR3A_TEST_START_ADDRESS + (4 * 100))
#define DDR3A_BASE_ADDRESS        0x80000000


#define DDR3B_BASE_ADDR (0x21020000)
#define DDR3B_STATUS   (*(int*)(DDR3B_BASE_ADDR + 0x00000004))
#define DDR3B_SDCFG    (*(int*)(DDR3B_BASE_ADDR + 0x00000008))
#define DDR3B_SDRFC    (*(int*)(DDR3B_BASE_ADDR + 0x00000010))
#define DDR3B_SDTIM1   (*(int*)(DDR3B_BASE_ADDR + 0x00000018))
#define DDR3B_SDTIM2   (*(int*)(DDR3B_BASE_ADDR + 0x0000001C))
#define DDR3B_SDTIM3   (*(int*)(DDR3B_BASE_ADDR + 0x00000020))
#define DDR3B_SDTIM4   (*(int*)(DDR3B_BASE_ADDR + 0x00000028))
#define DDR3B_ZQCFG    (*(int*)(DDR3B_BASE_ADDR + 0x000000C8))
#define DDR3B_TMPALRT  (*(int*)(DDR3B_BASE_ADDR + 0x000000CC))
#define DDR3B_DDRPHYC  (*(int*)(DDR3B_BASE_ADDR + 0x000000E4))


#define DDR3B_PHY_CFG_BASE (0x02328000)
#define DDR3B_PIR    (*(int*)(DDR3B_PHY_CFG_BASE + 0x00000004))
#define DDR3B_PGCR0  (*(int*)(DDR3B_PHY_CFG_BASE + 0x00000008))
#define DDR3B_PGCR1  (*(int*)(DDR3B_PHY_CFG_BASE + 0x0000000C))
#define DDR3B_PGCR2  (*(int*)(DDR3B_PHY_CFG_BASE + 0x0000008C))
#define DDR3B_PGSR0  (*(int*)(DDR3B_PHY_CFG_BASE + 0x00000010))
#define DDR3B_PGSR1  (*(int*)(DDR3B_PHY_CFG_BASE + 0x00000014))
#define DDR3B_PTR0   (*(int*)(DDR3B_PHY_CFG_BASE + 0x0000001C))
#define DDR3B_PTR1   (*(int*)(DDR3B_PHY_CFG_BASE + 0x00000020))
#define DDR3B_PTR2   (*(int*)(DDR3B_PHY_CFG_BASE + 0x00000024))
#define DDR3B_PTR3   (*(int*)(DDR3B_PHY_CFG_BASE + 0x00000028))
#define DDR3B_PTR4   (*(int*)(DDR3B_PHY_CFG_BASE + 0x0000002C))
#define DDR3B_DSGCR  (*(int*)(DDR3B_PHY_CFG_BASE + 0x00000040))
#define DDR3B_DCR    (*(int*)(DDR3B_PHY_CFG_BASE + 0x00000044))
#define DDR3B_MR0    (*(int*)(DDR3B_PHY_CFG_BASE + 0x00000054))
#define DDR3B_MR1    (*(int*)(DDR3B_PHY_CFG_BASE + 0x00000058))
#define DDR3B_MR2    (*(int*)(DDR3B_PHY_CFG_BASE + 0x0000005C))
#define DDR3B_DTCR   (*(int*)(DDR3B_PHY_CFG_BASE + 0x00000068))
#define DDR3B_DTPR0  (*(int*)(DDR3B_PHY_CFG_BASE + 0x00000048))
#define DDR3B_DTPR1  (*(int*)(DDR3B_PHY_CFG_BASE + 0x0000004C))
#define DDR3B_DTPR2  (*(int*)(DDR3B_PHY_CFG_BASE + 0x00000050))
#define DDR3B_PLLCR  (*(int*)(DDR3B_PHY_CFG_BASE + 0x00000018))

#define DDR3B_ZQ0CR1  (*(int*)(DDR3B_PHY_CFG_BASE + 0x00000184))
#define DDR3B_ZQ1CR1  (*(int*)(DDR3B_PHY_CFG_BASE + 0x00000194))
#define DDR3B_ZQ2CR1  (*(int*)(DDR3B_PHY_CFG_BASE + 0x000001A4))
#define DDR3B_ZQ3CR1  (*(int*)(DDR3B_PHY_CFG_BASE + 0x000001B4))

#define DDR3B_TEST_START_ADDRESS (0x60000000)

#define DDR3B_TEST_END_ADDRESS   (DDR3B_TEST_START_ADDRESS + (4 * 100))

#define DDR3B_BASE_ADDRESS            0x60000000



#define TETRIS_BASE                 0x01E80000

#define TETRIS_CPU0_PTCMD           *(unsigned int*)(TETRIS_BASE + 0x0400)
#define TETRIS_CPU0_PDSTAT          *(unsigned int*)(TETRIS_BASE + 0x0404)
#define TETRIS_CPU0_PDCTL           *(unsigned int*)(TETRIS_BASE + 0x0408)

#define TETRIS_CPU1_PTCMD           *(unsigned int*)(TETRIS_BASE + 0x040C)
#define TETRIS_CPU1_PDSTAT          *(unsigned int*)(TETRIS_BASE + 0x0410)
#define TETRIS_CPU1_PDCTL           *(unsigned int*)(TETRIS_BASE + 0x0414)

#define TETRIS_CPU2_PTCMD           *(unsigned int*)(TETRIS_BASE + 0x0418)
#define TETRIS_CPU2_PDSTAT          *(unsigned int*)(TETRIS_BASE + 0x041C)
#define TETRIS_CPU2_PDCTL           *(unsigned int*)(TETRIS_BASE + 0x0420)

#define TETRIS_CPU3_PTCMD           *(unsigned int*)(TETRIS_BASE + 0x0424)
#define TETRIS_CPU3_PDSTAT          *(unsigned int*)(TETRIS_BASE + 0x0428)
#define TETRIS_CPU3_PDCTL           *(unsigned int*)(TETRIS_BASE + 0x042C)

#define SECPLLCTL0                  *(unsigned int*)(CHIP_LEVEL_REG + 0x0370)
#define SECPLLCTL1                  *(unsigned int*)(CHIP_LEVEL_REG + 0x0374)
unsigned int read_val;

/****************************************************************************
 *
 * NAME
 *      OnTargetConnect
 *
 * PURPOSE:
 *      Setup almost everything ready for a new debug session:
 *      DSP modules and EVM board modules, at target connection.
 *      Do nothing if target is in realtime mode.
 *      This routine is called when you connect to the target board.
 *
 *      IMPORTANT: this routine won't attempt to connect to the target
 *      if the target is not in real-time mode and that the dsp boot
 *      mode switches are not set in emulation boot mode.
 *
 * USAGE
 *      This routine is a callback routine and called by CCS only.
 *
 * RETURN VALUE
 *      NONE
 *
 * REFERENCE
 *
 ****************************************************************************/
OnTargetConnect()
{
    /*------------------------------------------------------*/
    /* GEL_Reset() is used to deal with the worst case      */
    /* senario of unknown target state.  If for some reason */
    /* a reset is not desired upon target connection,       */
    /* GEL_Reset() may be removed and replaced with         */
    /* something "less brutal" like a cache initialization  */
    /* function.                                            */
    /*------------------------------------------------------*/
    //GEL_Reset();
    //xmc_setup();
    //ddr3_setup();
    
    GEL_TextOut("\nConnecting Target...\n");
    
    // Check if target is not in real-time mode. If it is in stop mode,
    // initialize everything. In real-time mode, do nothing to connect
    // unobtrusively...
    if (!GEL_IsInRealtimeMode())
    {
        // Validates if emulation boot mode
        if (DEVSTAT & 0x0000000E)
        {
            GEL_TextOut("No initialization performed since bootmode = %x \n",,,,,(DEVSTAT >> 1 ) & 0xF);
            GEL_TextOut("You can manually initialize with GlobalDefaultSetup\n");
        }
        else
        {
            // Comment the following line at production application test
            // when the application need to initialize everything, but not the
            // GEL file.
            Global_Default_Setup_Silent();
        }
    } else {
        GEL_TextOut("No initialization performed in real time mode\n");
    }
}

/*--------------------------------------------------------------*/
/* OnReset()                                                    */
/* This function is called by CCS when you do Debug->Resest.    */
/* The goal is to put the C6x into a known good state with      */
/* respect to cache, edma and interrupts.                       */
/*--------------------------------------------------------------*/
OnReset( int nErrorCode )
{
}

/*--------------------------------------------------------------*/
/* xmc_setup()                                                  */
/* XMC MPAX register setting to access DDR3 config space        */
/*--------------------------------------------------------------*/

#define XMC_BASE_ADDR (0x08000000)
#define XMPAX2_L     (*(int*)(XMC_BASE_ADDR + 0x00000010))
#define XMPAX2_H     (*(int*)(XMC_BASE_ADDR + 0x00000014))

xmc_setup()
{
  /* mapping for ddr emif registers XMPAX*2 */

    XMPAX2_L =  0x121010FF;  /* replacement addr + perm */
    XMPAX2_H =  0x2101000B;    /* base addr + seg size (64KB)*/	//"1B"-->"B" by xj
    GEL_TextOut("XMC setup complete.\n");
}

/****************************************************************************
 *
 * NAME
 *      Global_Default_Setup_Silent
 *
 * PURPOSE:
 *      Setup almost everything ready for a new debug session:
 *      DSP modules and EVM board modules.
 *
 * USAGE
 *      This routine can be called as:
 *
 *      Global_Default_Setup_Silent()
 *
 * RETURN VALUE
 *      NONE
 *
 * REFERENCE
 *
 ****************************************************************************/
Global_Default_Setup_Silent()
{
    float gel_ver = GEL_VERSION;
    
    // Set DSP cache to pre defined values...
    GEL_TextOut( "TCI6638K2K GEL file Ver is %f \n",,,,, (float) (gel_ver/1.0));
    
    //Set_DSP_Cache();
    
    // Only core 0 can set these
    if (DNUM == 0)
    {
        // Setup main PLL DSP @ 983 MHz
        Set_Pll1(3); // call Set_Pll1 with index = 3 -> 122.88 MHz to 983.04 MHz operation
        
        // Setup all Power Domains on
        Set_Psc_All_On();
        
        // Setup PA PLL
        PaPllConfig();
        
        GEL_TextOut("DDR begin\n");
        xmc_setup();
        ddr3A_32bit_DDR1333_setup();
        ddr3B_64bit_DDR1600_setup();
        GEL_TextOut("DDR done\n");
    }
}

/****************************************************************************
 *
 * NAME
 *      Set_PSC_State
 *
 * PURPOSE:
 *      Set a new power state for the specified domain id in a power controler
 *      domain. Wait for the power transition to complete.
 *
 * USAGE
 *      This routine can be called as:
 *
 *      Set_PSC_State(unsigned int pd,unsigned int id,unsigned int state)
 *
 *      pd    - (i) power domain.
 *
 *      id    - (i) module id to use for module in the specified power domain
 *
 *      state - (i) new state value to set
 *                  0 = RESET
 *                  1 = SYNC RESET
 *                  2 = DISABLE
 *                  3 = ENABLE
 *
 * RETURN VALUE
 *      0 if ok, !=0 for error
 *
 * REFERENCE
 *
 ****************************************************************************/
Set_PSC_State(unsigned int pd,unsigned int id,unsigned int state)
{
    unsigned int* mdctl;
    unsigned int* mdstat;
    unsigned int* pdctl;
    int ret=0;

    // Only core0 can set PSC
    if (DNUM == 0)
    {
        mdctl = ( unsigned int* )(PSC_MDCTL_BASE + ( 4 * id ));
        mdstat = ( unsigned int* )( PSC_MDSTAT_BASE + ( 4 * id ));
        pdctl = ( unsigned int* )(PSC_PDCTL_BASE + ( 4 * pd ));
    
        // If state is already set, do nothing
        if ( ( *mdstat & 0x1f ) == state )
        {
            return(0);
        }
    
        // Wait for GOSTAT to clear
        Set_Timeout(GTIMEOUT);
        while( Get_Timeout() && (PSC_PTSTAT & (0x1 << pd)) != 0 );
    
        // Check if we got timeout error while waiting
        if (!Get_Timeout())
        {
            GEL_TextOut( "Set_PSC_State... Timeout Error #01 pd=%d, md=%d!\n",,2,,,pd,id);
            ret=1;
        }
        else
        {
            // Set power domain control
            *pdctl = (*pdctl) | 0x00000001;
            
            // Set MDCTL NEXT to new state
            *mdctl = ((*mdctl) & ~(0x1f)) | state;
    
            // Start power transition by setting PTCMD GO to 1
            PSC_PTCMD = (PSC_PTCMD) | (0x1<<pd);
    
            // Wait for PTSTAT GOSTAT to clear
            Set_Timeout(GTIMEOUT);
            while( Get_Timeout() && (PSC_PTSTAT & (0x1 << pd)) != 0 );
    
            // Check if we got timeout error while waiting
            if (!Get_Timeout())
            {
                GEL_TextOut( "Set_PSC_State... Timeout Error #02 pd=%d, md=%d!\n",,2,,,pd,id);
                ret=2;
            }
            else
            {
                // Verify state changed
                Set_Timeout(GTIMEOUT);
                while(Get_Timeout() && ( *mdstat & 0x1f ) != state );
    
                // Check if we got timeout error while waiting
                if (!Get_Timeout())
                {
                    GEL_TextOut( "Set_PSC_State... Timeout Error #03 pd=%d, md=%d!\n",,2,,,pd,id);
                    ret=3;
                }
            }
        }
    
        // Kill the currently running timeout
        Kill_Timeout();
    }
    else
    {
        GEL_TextOut("DSP core #%d cannot set PSC.\n",,2,,,DNUM);
    }

    return(ret);
}

/****************************************************************************
 *
 * NAME
 *      Set_Timeout
 *
 * PURPOSE:
 *      Starts a timeout period of msec. The running timeout period can be
 *      query with Get_Timeout. To kill a running timeout before the end,
 *      call Kill_Timeout. Only one timeout period can be used at any time.
 *      A timeout period can be used to measure a period of time while doing
 *      anything else. Not accurate, sets timer at least as big as desired.
 *
 * USAGE
 *      This routine can be called as:
 *
 *      Set_Timeout(msec)
 *
 *      msec - (i) timeout period in msec (not very precise < sec range)
 *
 * RETURN VALUE
 *      NONE
 *
 * REFERENCE
 *
 ****************************************************************************/
Set_Timeout(msec)
{
    // Cancel the current timer if not already expired
    GEL_CancelTimer(TIMEOUT_ID);

    // Starts the timeout period
    _GEL_Global_Timeout1=1;

    // Setup a callback routine with specified timeout
    GEL_SetTimer(msec, TIMEOUT_ID, "_Timeout_Callback()");
}

/****************************************************************************
 *
 * NAME
 *      Get_Timeout
 *
 * PURPOSE:
 *      Query the running state of a timeout period started by Set_Timeout.
 *      (see Set_Timeout for more info).
 *
 * USAGE
 *      This routine can be called as:
 *
 *      Get_Timeout()
 *
 * RETURN VALUE
 *      0:expired, 1:running
 *
 * REFERENCE
 *
 ****************************************************************************/
Get_Timeout()
{
    if (!_GEL_Global_Timeout1)
    {
        // Cancel the current timer
        GEL_CancelTimer(TIMEOUT_ID);
    }

    // Return the global timeout status 1=running, 0=expired
    return _GEL_Global_Timeout1;
}

/****************************************************************************
 *
 * NAME
 *      Kill_Timeout
 *
 * PURPOSE:
 *      Cancel a running timeout period before it expires
 *      (see Set_Timeout for more info).
 *
 * USAGE
 *      This routine can be called as:
 *
 *      Kill_Timeout()
 *
 * RETURN VALUE
 *      NONE
 *
 * REFERENCE
 *
 ****************************************************************************/
Kill_Timeout()
{
    // Cancel the current timer
    GEL_CancelTimer(TIMEOUT_ID);

    // The timeout period is expired
    _GEL_Global_Timeout1=0;
}

/****************************************************************************
 *
 * NAME
 *      _Timeout_Callback
 *
 * PURPOSE:
 *      Internal Callback function used by Set_timeout
 *      (see Set_Timeout for more info).
 *
 * USAGE
 *      This routine must not be called by itself.
 *
 * RETURN VALUE
 *      NONE
 *
 * REFERENCE
 *
 ****************************************************************************/
_Timeout_Callback()
{
    // The timeout period is expired
    _GEL_Global_Timeout1=0;
}


/****************************************************************************
 *
 * NAME
 *      Set_Psc_All_On
 *
 * PURPOSE:
 *      Enable all PSC modules and DSP power domains on ALWAYSON, and wait
 *      for these power transitions to complete.
 *
 * USAGE
 *      This routine can be called as:
 *
 *      Set_Psc_All_On()
 *
 * RETURN VALUE
 *      NONE
 *
 * REFERENCE
 *
 ****************************************************************************/
hotmenu Set_Psc_All_On( )
{
    unsigned int i=0;

   // Only core0 can set PSC
    if (DNUM == 0)
    {
        GEL_TextOut( "Power on all PSC modules and DSP domains... \n");
    
		Set_PSC_State(PD1, LPSC_DEBUG, PSC_ENABLE);
		Set_PSC_State(PD1, LPSC_TETB, PSC_ENABLE);
		Set_PSC_State(PD2, LPSC_PA, PSC_ENABLE);
		Set_PSC_State(PD2, LPSC_SGMII, PSC_ENABLE);
//  Removed unwanted power up of modules	
//		Set_PSC_State(PD2, LPSC_SA, PSC_ENABLE);
//		Set_PSC_State(PD3, LPSC_PCIE, PSC_ENABLE);
//		Set_PSC_State(PD4, LPSC_SRIO, PSC_ENABLE);
//		Set_PSC_State(PD5, LPSC_HYPERLINK_0, PSC_ENABLE);
		Set_PSC_State(PD6, LPSC_SR, PSC_ENABLE);
		Set_PSC_State(PD7, LPSC_MSMCRAM, PSC_ENABLE);
		Set_PSC_State(PD8, LPSC_GEM_0, PSC_ENABLE);
		Set_PSC_State(PD9, LPSC_GEM_1, PSC_ENABLE);
		Set_PSC_State(PD10, LPSC_GEM_2, PSC_ENABLE);
		Set_PSC_State(PD11, LPSC_GEM_3, PSC_ENABLE);
		Set_PSC_State(PD12, LPSC_GEM_4, PSC_ENABLE);
		Set_PSC_State(PD13, LPSC_GEM_5, PSC_ENABLE);
		Set_PSC_State(PD14, LPSC_GEM_6, PSC_ENABLE);
		Set_PSC_State(PD15, LPSC_GEM_7, PSC_ENABLE);
		Set_PSC_State(PD16, LPSC_DDR3_0, PSC_ENABLE);
		Set_PSC_State(PD16, LPSC_DDR3_1, PSC_ENABLE);
//		Set_PSC_State(PD17, LPSC_TAC, PSC_ENABLE);
//		Set_PSC_State(PD17, LPSC_RAC_01, PSC_ENABLE);
//		Set_PSC_State(PD18, LPSC_RAC_23, PSC_ENABLE);
//		Set_PSC_State(PD19, LPSC_FFTCA_FFTC_0, PSC_ENABLE);
//		Set_PSC_State(PD19, LPSC_FFTCA_FFTC_1, PSC_ENABLE);
//		Set_PSC_State(PD20, LPSC_FFTCA_FFTC_2, PSC_ENABLE);
//		Set_PSC_State(PD20, LPSC_FFTCA_FFTC_3, PSC_ENABLE);
//		Set_PSC_State(PD20, LPSC_FFTCA_FFTC_4, PSC_ENABLE);
//		Set_PSC_State(PD20, LPSC_FFTCA_FFTC_5, PSC_ENABLE);
//		Set_PSC_State(PD21, LPSC_AIF, PSC_ENABLE);
//		Set_PSC_State(PD22, LPSC_TCP3D_0, PSC_ENABLE);
//		Set_PSC_State(PD22, LPSC_TCP3D_1, PSC_ENABLE);
//		Set_PSC_State(PD23, LPSC_TCP3D_2, PSC_ENABLE);
//		Set_PSC_State(PD23, LPSC_TCP3D_3, PSC_ENABLE);
//		Set_PSC_State(PD24, LPSC_VCP_0, PSC_ENABLE);
//		Set_PSC_State(PD24, LPSC_VCP_1, PSC_ENABLE);
//		Set_PSC_State(PD24, LPSC_VCP_2, PSC_ENABLE);
//		Set_PSC_State(PD24, LPSC_VCP_3, PSC_ENABLE);
//		Set_PSC_State(PD25, LPSC_VCP_4, PSC_ENABLE);
//		Set_PSC_State(PD25, LPSC_VCP_5, PSC_ENABLE);
//		Set_PSC_State(PD25, LPSC_VCP_6, PSC_ENABLE);
//		Set_PSC_State(PD25, LPSC_VCP_7, PSC_ENABLE);
//		Set_PSC_State(PD26, LPSC_BCP, PSC_ENABLE);
//		Set_PSC_State(PD27, LPSC_DXB, PSC_ENABLE);
//		Set_PSC_State(PD28, LPSC_HYPERLINK_1, PSC_ENABLE);
		Set_PSC_State(PD29, LPSC_XGE, PSC_ENABLE);
		Set_PSC_State(PD31, LPSC_ARM, PSC_ENABLE);
   
        GEL_TextOut( "Power on all PSC modules and DSP domains... Done.\n" );
    }
    else
    {
        GEL_TextOut("DSP core #%d cannot set PSC.\n",,2,,,DNUM);
    }
}


//********************************************************************************************************************************
//********************************************************************************************************************************
/*
   Set_Pll1() - This function executes the main PLL initialization 
   sequence needed to get the main PLL up after coming out of an initial power up 
   before it is locked or after it is already locked.

   Index value determines multiplier, divier used and clock reference assumed for 
   output display. 
 */
Set_Pll1(int index)
{
    int i, TEMP;
    unsigned int BYPASS_val;     
    unsigned int BWADJ_val;     
    unsigned int OD_val;            

    float CLKIN_val;
    unsigned int PLLM_val;
    unsigned int PLLD_val;
    unsigned int PLLDIV3_val; //example value for SYSCLK2 (from 6614 spec) Default /2 - Fast Peripherals, (L2, MSMC, DDR3 EMIF, EDMA0...)
    unsigned int PLLDIV4_val; //example value for SYSCLK3 (from 6614 spec) Default /3 - Switch Fabric
    unsigned int PLLDIV7_val; //example value for SYSCLK6 (from 6614 spec) Defualt /6 - Slow Peripherals (UART, SPI, I2C, GPIO...)

    unsigned int debug_info_on;
    unsigned int delay;

	if(index == 1){            // 122.88 MHz -> 614.4 MHz
        CLKIN_val   = 122.88;       // setup CLKIN to 122.88 MHz
        PLLM_val    = 10;           // setup PLLM (PLL multiplier) to x10
        PLLD_val    = 1;            // setup PLLD (reference divider) to /1
        OD_val      = 2;            // setup OD to a fixed /2
		}
	else if(index == 2){            // 122.88MHz -> 737.28 MHz
        CLKIN_val   = 122.88;       // setup CLKIN to 122.88 MHz
        PLLM_val    = 12;           // setup PLLM (PLL multiplier) to x12
        PLLD_val    = 1;            // setup PLLD (reference divider) to /1
        OD_val      = 2;            // setup OD to a fixed /2
    }
	
	else if(index == 3){            // 122.88MHz -> 983.04 MHz
        CLKIN_val   = 122.88;       // setup CLKIN to 122.88 MHz
        PLLM_val    = 16;           // setup PLLM (PLL multiplier) to x12
        PLLD_val    = 1;            // setup PLLD (reference divider) to /1
        OD_val      = 2;            // setup OD to a fixed /2
    }
	
	else if(index == 4){            // 122.88 MHz -> 1.2 GHz
        CLKIN_val   = 122.88;          // setup CLKIN to 122.88 MHz
        PLLM_val    = 20;           // setup PLLM (PLL multiplier) to x20
        PLLD_val    = 1;            // setup PLLD (reference divider) to /1
        OD_val      = 2;            // setup OD to a fixed /2
    }
    else if(index == 5){            // 122.88 MHz -> 1.35 GHz
        CLKIN_val   = 122.88;          // setup CLKIN to 122.88 MHz
        PLLM_val    = 22;           // setup PLLM (PLL multiplier) to x22
        PLLD_val    = 1;            // setup PLLD (reference divider) to /1
        OD_val      = 2;            // setup OD to a fixed /2
    }
    
	 
	 
    
    PLLDIV3_val = 3;            // setup PLL output divider 3 to /3
    PLLDIV4_val = 5;            // setup PLL output divider 4 to /3
    PLLDIV7_val = 6;            // setup PLL output divider 7 to /6

    BYPASS_val      = PLL1_SECCTL & ~BYPASS_MASK;   // get value of the BYPASS field
    BWADJ_val       = (PLLM_val) >> 1;              // setup BWADJ to be 1/2 the value of PLLM
    OD_val          = 2;                            // setup OD to a fixed /2

    debug_info_on   = 1;
    delay           = 1000; // fix this!

    /* Step 1: Unlock Boot Config Registers */
    KICK0 = KICK0_UNLOCK;
    KICK1 = KICK1_UNLOCK;

    /* Step 2: Check if SECCTL bypass is low or high indicating what state the Main PLL is currently in. if 
       the Main PLL is in bypass still (not yet setup) execute the following steps.  */

    if(BYPASS_val != 0x00000000){ // PLL bypass enabled - Execute PLL setup for PLL fresh out of power on reset
        if(debug_info_on){
            GEL_TextOut("Detected PLL bypass enabled: SECCTL[BYPASS] = %x\n",,,,, BYPASS_val);
        }
        /* Step 2a: Set MAINPLLCTL1[ENSAT] = 1 - This enables proper biasing of PLL analog circuitry */            
        MAINPLLCTL1 |= (1 << MAIN_ENSAT_OFFSET); 
        if(debug_info_on){
            GEL_TextOut("(2a) MAINPLLCTL1 = %x\n",,,,, MAINPLLCTL1);
        }        

        /* Step 2b: Set PLLCTL[PLLEN] = 0 This enables bypass in PLL controller MUX */        
        PLL1_PLLCTL &= ~(1 << PLLEN_OFFSET);        
        if(debug_info_on){    
            GEL_TextOut("(2b) PLLCTL = %x\n",,,,, PLL1_PLLCTL);
        }    

        /* Step 2c: Set PLLCTL[PLLENSRC] = 0 - This enables PLLEN to control PLL controller MUX */    
        PLL1_PLLCTL &= ~(1 << PLLENSRC_OFFSET);
        if(debug_info_on){    
            GEL_TextOut("(2c) PLLCTL = %x\n",,,,, PLL1_PLLCTL);
        }    

        /* Step 2d: Wait 4 reference clock cycles (slowest of ALTCORE or SYSCLK) to make sure 
           that the PLL controller MUX switches properly to bypass. */
        if(debug_info_on){    
            GEL_TextOut("(2d) Delay...\n",,,,,);
        }        
        for(i = 0; i < delay; i++); // this delay is much more than required         

        /* Step 2e: Set SECCTL[BYPASS] = 1 - enables bypass in PLL MUX */    
        PLL1_SECCTL |= (1 << BYPASS_OFFSET);        
        if(debug_info_on){    
            GEL_TextOut("(2e) SECCTL = %x\n",,,,, PLL1_SECCTL);
        }    

        /* Step 2f: Set PLLCTL[PLLPWRDN] = 1 - power down the PLL */        
        PLL1_PLLCTL |= (1 << PLLPWRDN_OFFSET);
        if(debug_info_on){    
            GEL_TextOut("(2f) PLLCTL = %x\n",,,,, PLL1_PLLCTL);
        }    

        /* Step 2g: Wait for at least 5us for the PLL to power down */
        if(debug_info_on){    
            GEL_TextOut("(2g) Delay...\n",,,,,);
        }    
        for(i = 0; i < delay; i++); // this delay is much more than required 

        /* Step 2h: Set PLLCTL[PLLPWRDN] = 0 - Power the PLL back up */    
        PLL1_PLLCTL &= ~(1 << PLLPWRDN_OFFSET);
        if(debug_info_on){    
            GEL_TextOut("(2h) PLLCTL = %x\n",,,,, PLL1_PLLCTL);
        }            

    }
    else{ // PLL bypass disabled - Execute PLL setup for PLL that has previously been locked (skip to Step 3)
        if(debug_info_on){    
            GEL_TextOut("Detected PLL bypass disabled: SECCTL[BYPASS] = %x\n",,,,, BYPASS_val);
        }

        /* Step 3a: Set PLLCTL[PLLEN] = 0 This enables bypass in PLL controller MUX */        
        PLL1_PLLCTL &= ~(1 << PLLEN_OFFSET);        
        if(debug_info_on){    
            GEL_TextOut("(3a) PLLCTL = %x\n",,,,, PLL1_PLLCTL);
        }    

        /* Step 3b: Set PLLCTL[PLLENSRC] = 0 - This enables PLLEN to control PLL controller MUX */    
        PLL1_PLLCTL &= ~(1 << PLLENSRC_OFFSET);
        if(debug_info_on){    
            GEL_TextOut("(3b) PLLCTL = %x\n",,,,, PLL1_PLLCTL);
        }

        /* Step 3c: Wait 4 reference clock cycles (slowest of ALTCORE or SYSCLK) to make sure 
           that the PLL controller MUX switches properly to bypass. */
        if(debug_info_on){    
            GEL_TextOut("(3c) Delay...\n",,,,,);
        }        
        for(i = 0; i < delay; i++); // this delay is much more than required       

    }


    /* Step 4: Programming PLLM[5:0] in the PLLM register of the PLL controller and
       programming PLLM[12:6] in the MAINPLLCTL0 register */        
    PLL1_PLLM &= PLLM_MASK;             // clear the PLLM[5:0] bit field
    PLL1_PLLM |= ~PLLM_MASK & (PLLM_val - 1);   // set the PLLM[5:0] bit field to the 6 LSB of PLLM_val

    if(debug_info_on){
        GEL_TextOut("(4)PLLM[PLLM] = %x\n",,,,, PLL1_PLLM);
    }    

    MAINPLLCTL0 &= MAIN_PLLM_MASK;      // clear the PLLM[12:6] bit field
    MAINPLLCTL0 |= ~MAIN_PLLM_MASK & (( (PLLM_val - 1) >> 6) << MAIN_PLLM_OFFSET);  // set the PLLM[12:6] bit field to the 7 MSB of PLL_val

    if(debug_info_on){
        GEL_TextOut("MAINPLLCTL0 = %x\n",,,,, MAINPLLCTL0);
    }

    /* Step 5: Programming BWADJ[7:0] in the MAINPLLCTL0 register and BWADJ[11:8] in MAINPLLCTL1 register */            
    MAINPLLCTL0 &= MAIN_BWADJ0_MASK;    // clear the MAIN_BWADJ0 bit field
    MAINPLLCTL0 |= ~MAIN_BWADJ0_MASK & ((BWADJ_val - 1) << MAIN_BWADJ0_OFFSET); // set the MAIN_BWADJ[7:0] bit field to the 8 LSB of BWADJ_val

    if(debug_info_on){
        GEL_TextOut("(5) MAINPLLCTL0 = %x\n",,,,, MAINPLLCTL0);
    }

    MAINPLLCTL1 &= MAIN_BWADJ1_MASK;    // clear the MAIN_BWADJ1 bit field
    MAINPLLCTL1 |= ~MAIN_BWADJ1_MASK & (( (BWADJ_val - 1) >> 8) << MAIN_BWADJ1_OFFSET); // set the MAIN_BWADJ[11:8] bit field to the 4 MSB of BWADJ_val

    if(debug_info_on){
        GEL_TextOut("(5) MAINPLLCTL1 = %x\n",,,,, MAINPLLCTL1);
    }

    /* Step 6: Programming PLLD[5:0] in the MAINPLLCTL0 register */            
    MAINPLLCTL0 &= MAIN_PLLD_MASK;      // clear the PLLD bit field
    MAINPLLCTL0 |= ~MAIN_PLLD_MASK & (PLLD_val - 1);    // set the PLLD[5:0] bit field of PLLD to PLLD_val

    if(debug_info_on){
        GEL_TextOut("(6) MAINPLLCTL0 = %x\n",,,,, MAINPLLCTL0);
    }

    /* Step 7: Programming OD[3:0] in the SECCTL register */            
    PLL1_SECCTL &= OUTPUT_DIVIDE_MASK;  // clear the OD bit field
    PLL1_SECCTL |= ~OUTPUT_DIVIDE_MASK & (OD_val - 1) << OUTPUT_DIVIDE_OFFSET;  // set the OD[3:0] bit field of PLLD to OD_val    

    if(debug_info_on){
        GEL_TextOut("(7) SECCTL = %x\n",,,,, PLL1_SECCTL);
    }

    /* Step 8: Following steps are needed to change the default output dividers */            

    /* Step 8a: Check that the GOSTAT bit in PLLSTAT is cleared to show that no GO
       operation is currently in progress*/
    if(debug_info_on){    
        GEL_TextOut("(8a) Delay...\n",,,,,);
    }    
    while((PLL1_STAT) & 0x00000001);

    /* Step 8b: Program the RATIO field in PLLDIVn to the desired new divide-down rate.
       If RATIO field is changed, the PLL controller will flag the change in the
       corresponding bit of DCHANGE*/
    PLL1_DIV3 = (PLLDIV3_val-1) | 0x8000;  //Set PLLDIV3
    PLL1_DIV4 = (PLLDIV4_val-1) | 0x8000;  //Set PLLDIV4
    PLL1_DIV7 = (PLLDIV7_val-1) | 0x8000;  //Set PLLDIV7

    if(debug_info_on){
        GEL_TextOut("PLL1_DIV3 = %x\n",,,,, PLL1_DIV3);
        GEL_TextOut("PLL1_DIV4 = %x\n",,,,, PLL1_DIV4);
        GEL_TextOut("PLL1_DIV7 = %x\n",,,,, PLL1_DIV7);
    }

    /* Step 8c: Set GOSET bit in PLLCMD to initiate the GO operation to change the divide
       values and align the SYSCLKs as programmed */
    PLL1_CMD |= 0x00000001;

    /*Step 8d/e: Read the GOSTAT bit in PLLSTAT to make sure the bit returns to 0 to
      indicate that the GO operation has completed */
    if(debug_info_on){    
        GEL_TextOut("(8d/e) Delay...\n",,,,,);
    }    
    while((PLL1_STAT) & 0x00000001);
    
    /* Step 9: Set PLLCTL[PLLRST] = 1 - Assert PLL reset (Previously Step 3)*/        
    PLL1_PLLCTL |= (1 << PLLRST_OFFSET);

    /* Step 10: Wait for the at least 7us for the PLL reset properly (128 CLKIN1 cycles) */        
    if(debug_info_on){    
        GEL_TextOut("(10) Delay...\n",,,,,);
    }    
    for(i=0;i<delay;i++);

    /* Step 11: Set PLLCTL[PLLRST] = 0 - De-Assert PLL reset */        
    PLL1_PLLCTL &= ~(1 << PLLRST_OFFSET);

    /* Step 12: Wait for PLL to lock (2000 CLKIN1 cycles) */
    if(debug_info_on){    
        GEL_TextOut("(12) Delay...\n",,,,,);
    }    
    for(i=0;i<delay;i++);

    /* Step 13: In SECCTL, write BYPASS = 0 (enable PLL mux to switch to PLL mode) */
    PLL1_SECCTL &= ~(1 << BYPASS_OFFSET);        
    if(debug_info_on){    
        GEL_TextOut("(13) SECCTL = %x\n",,,,, PLL1_SECCTL);
    }    
	 if(debug_info_on){    
        GEL_TextOut("(Delay...\n",,,,,);
    }    
	 for(i=0;i<delay;i++);
	 if(debug_info_on){    
        GEL_TextOut("(Delay...\n",,,,,);
    }    
	 for(i=0;i<delay;i++);

    /* Step 14: In PLLCTL, write PLLEN = 1 to enable PLL mode */
    PLL1_PLLCTL |= (1 << PLLEN_OFFSET);        
    if(debug_info_on){    
        GEL_TextOut("(14) PLLCTL = %x\n",,,,, PLL1_PLLCTL);
    }    

    /* Step 15: Lock Boot Config Registers */
    KICK0 = 0x00000000;
    KICK1 = 0x00000000;

    GEL_TextOut("PLL has been configured (CLKIN * PLLM / PLLD / PLLOD = PLLOUT):\n",,,,,);
    GEL_TextOut("PLL has been configured (%f MHz * %d / %d / 2 = %f MHz)\n",,,,, CLKIN_val, PLLM_val, PLLD_val, (CLKIN_val * PLLM_val / PLLD_val / 2) );

}



Set_Tetris_Pll(int index)
{

    unsigned int BWADJ_val;     
    unsigned int OD_val;            
    unsigned int PLLM_val;
    float CLKIN_val;
    int i;

    GEL_TextOut("Switching on ARM Core 0\n",,,,,);
    TETRIS_CPU0_PDCTL   = 0x00000000;
    TETRIS_CPU0_PTCMD   = 0x00000001;    

    GEL_TextOut("Switching on ARM Core 1\n",,,,,);
    TETRIS_CPU1_PDCTL   = 0x00000000;
    TETRIS_CPU1_PTCMD   = 0x00000001;    
    
    GEL_TextOut("Switching on ARM Core 2\n",,,,,);
    TETRIS_CPU2_PDCTL   = 0x00000000;
    TETRIS_CPU2_PTCMD   = 0x00000001;    
    
    GEL_TextOut("Switching on ARM Core 3\n",,,,,);
    TETRIS_CPU3_PDCTL   = 0x00000000;
    TETRIS_CPU3_PTCMD   = 0x00000001;

       if(index == 1){              // 100 MHz -> 1.0 GHz
        CLKIN_val   = 125;          // setup CLKIN to 125 MHz
        PLLM_val    = 16;           // setup PLLM (PLL multiplier) to x20
        OD_val      = 2;            // setup OD to a fixed /2
    }
    else if(index == 2){            // 100 MHz -> 1.4 GHz
        CLKIN_val   = 125;          // setup CLKIN to 125 MHz
        PLLM_val    = 22;           // setup PLLM (PLL multiplier) to x28
        OD_val      = 2;            // setup OD to a fixed /2
    }
    else if(index == 3){            // 174.825MHz -> 1.4 GHz

        CLKIN_val   = 174.825;      // setup CLKIN to 174.825 MHz
        PLLM_val    = 16;           // setup PLLM (PLL multiplier) to x16
        OD_val      = 2;            // setup OD to a fixed /2
    }

    BWADJ_val       = (PLLM_val-1) >> 1;            // setup BWADJ to be 1/2 the value of PLLM
    OD_val          = 2;                            // setup OD to a fixed /2

    /* Step 1: Unlock Boot Config Registers */
    KICK0 = KICK0_UNLOCK;
    KICK1 = KICK1_UNLOCK;

    //Step 1 : Assert SEC PLL Reset
    SECPLLCTL1 = ((1 << SEC_PLLCTL1_RESET_OFFSET) | (1 << SEC_PLLCTL1_ENSTAT_OFFSET));

    //Step 2 : Change CLKF/OD/BWADJ etc. for SEC PLL
    SECPLLCTL0 = ((BWADJ_val << SEC_PLLCTL0_BWADJ_OFFSET) |
                  ((OD_val-1) << SEC_PLLCTL0_OD_OFFSET)|
                  ((PLLM_val-1) << SEC_PLLCTL0_PLLM_OFFSET));

    //Step 3 : Make sure the resets are held for 5us
    for(i = 0; i < 200000; i++);

    //Step 4 : Remove SEC PLL reset
    SECPLLCTL1 = (1 << SEC_PLLCTL1_ENSTAT_OFFSET);

    //Step 5 : Wait for PLL to lock (4000 CLKIN1 cycles)
    for(i = 0; i < 4000; i++);

    //Step 6 : Get the PLL out of Bypass
    //SECPLLCTL0 &= ~(1 << SEC_PLLCTL0_BYPASS_OFFSET);
    CHIP_MISC1 |= (1 << ARMPLL_ENABLE_OFFSET); 
   

    //Step 6 : Lock Boot Config Registers
    KICK0 = 0x00000000;
    KICK1 = 0x00000000;
    
    GEL_TextOut("ARM PLL has been configured (%f MHz * %d / %d = %f MHz)\n",,,,, CLKIN_val, PLLM_val, OD_val, (CLKIN_val * PLLM_val)/OD_val);

}


/* Set the desired PA PLL configuration */
PaPllConfig()
{
    unsigned int passclksel = (DEVSTAT & PASSCLKSEL_MASK);
    unsigned int papllctl0val_orig = PAPLLCTL0;
    unsigned int papllctl1val_orig = PAPLLCTL1;
    unsigned int papllctl0val_final;
    unsigned int papllctl1val_final;
    unsigned int papllclkf = 16; //204; // 204; 20 (if PASSREFCLK == 100mhz) Multiply by clkf + 1
	unsigned int papllclkd = 0;  //11;  // 11;   1 (if PASSREFCLK == 100mhz) Divide by clkd + 1
    unsigned int i = 0;

    if (passclksel != PASSCLKSEL_MASK) GEL_TextOut("WARNING: SYSCLK is the input to the PA PLL.\n");

    /* Unlock Chip Level Registers */
    KICK0 = KICK0_UNLOCK;
    KICK1 = KICK1_UNLOCK;

   // PAPLLCTL1 = PAPLLCTL1 | 0x00000040; //Set ENSAT = 1; Set PLL Select to 0 (for SYCLK0 as input of PASS)
    PAPLLCTL1 = PAPLLCTL1 | 0x00002040; //Set ENSAT = 1; Set PLL Select to 1 (for PA PLL as input of PASS)  
        
    /*in PAPLLCTL0, clear bypass bit to set the PA PLL in Bypass Mode*/
    //PAPLLCTL0 &= ~(1<<BYPASS_BIT_SHIFT); // Not setting Bypass bit
    PAPLLCTL0 |=  (1<<BYPASS_BIT_SHIFT); // Actually setting bypass bit

    /*Wait 4 cycles for the slowest of PLLOUT or reference clock source (CLKIN)*/
    for(i=0;i<100;i++);
    
    /*In PAPLLCTL1, write PLL reset bit to put the PLL in reset*/
    PAPLLCTL1 |= PA_PLL_RESET_MASK;

    /* Program the multiplier value */
    PAPLLCTL0 &= (~PA_PLL_CLKF_MASK);          //clear multiplier value
    PAPLLCTL0 &= (~PA_PLL_CLKR_MASK);          //clear divider value
    PAPLLCTL0 |= (papllclkf<<CLKF_BIT_SHIFT);  // set PLLM
	PAPLLCTL0 |= (papllclkd<<CLKD_BIT_SHIFT);  // set PLLD
    
    
    PAPLLCTL0 &= 0x00FFFFFF;
    PAPLLCTL0 |= ((((papllclkf + 1)>>1)-1)<<24);
    
    //PAPLLCTL1 = PAPLLCTL1 | 0x00002000;
    
    /*Wait for PLL to properly reset (128 CLKIN1 cycles) */
    for(i=0;i<1000;i++);
    
    /* take the PA PLL out of reset */
    PAPLLCTL1 &= (~PA_PLL_RESET_MASK);
    
    /*Wait for PLL to lock (2000 CLKIN1 cycles) */
    for(i=0;i<5000;i++);

    /* enable PLL mode */
    PAPLLCTL0 &= ~(1<<BYPASS_BIT_SHIFT); // actually setting PLL MODE

    for(i=0;i<4000;i++);

    /* Lock Chip Level Registers */
    KICK0 = KICK_LOCK;
    KICK1 = KICK_LOCK;

    papllctl0val_final = PAPLLCTL0;
    papllctl1val_final = PAPLLCTL1;

    GEL_TextOut("Completed PA PLL Setup\n");
    GEL_TextOut("PAPLLCTL0 - before: 0x%x\t after: 0x%x\n",,,,, papllctl0val_orig, papllctl0val_final);
    GEL_TextOut("PAPLLCTL1 - before: 0x%x\t after: 0x%x\n",,,,, papllctl1val_orig, papllctl1val_final);

    if ((papllctl0val_final != 0x09080500) || (papllctl1val_final != 0x00002040))
    {
    	return 1;
    }

    return 0;

}

//*************************************************************************************************
//*************************************************************************************************
//*************************************************************************************************
//*************************************************************************************************
//*************************************************************************************************
//*************************************************************************************************

//--------DDR3A Memory test----------------------

ddr3A_memory_test ()
{
    unsigned int index, value;

    GEL_TextOut( "DDR3A memory test... Started\n" );

    /* Write a pattern */
    for (index = DDR3A_TEST_START_ADDRESS; index < DDR3A_TEST_END_ADDRESS; index += 4) {
        *index = index;
    }

    /* Read and check the pattern */
    for (index = DDR3A_TEST_START_ADDRESS; index < DDR3A_TEST_END_ADDRESS; index += 4) {

        value = *index;

        if (value  != index) {
            GEL_TextOut( "DDR3A memory test... Failed\n" );
            return -1;
        }
    }

    /* Write a pattern for complementary values */
    for (index = DDR3A_TEST_START_ADDRESS; index < DDR3A_TEST_END_ADDRESS; index += 4) {
        *index = ~index;
    }

    /* Read and check the pattern */
    for (index = DDR3A_TEST_START_ADDRESS; index < DDR3A_TEST_END_ADDRESS; index += 4) {

        value = *index;

        if (value  != ~index) {
            GEL_TextOut( "DDR3A memory test... Failed\n" );
            return -1;
        }
    }

    GEL_TextOut( "DDR3A memory test... Passed\n" );
    return 0;
	
}
	
//---------------------------------------------------	
	
//--------DDR3B Memory test----------------------

ddr3B_memory_test ()
{
    unsigned int index, value;

    GEL_TextOut( "DDR3B memory test... Started\n" );

    /* Write a pattern */
    for (index = DDR3B_TEST_START_ADDRESS; index < DDR3B_TEST_END_ADDRESS; index += 4) {
        *index = index;
    }

    /* Read and check the pattern */
    for (index = DDR3B_TEST_START_ADDRESS; index < DDR3B_TEST_END_ADDRESS; index += 4) {

        value = *index;

        if (value  != index) {
            GEL_TextOut( "DDR3B memory test... Failed\n" );
            return -1;
        }
    }

    /* Write a pattern for complementary values */
    for (index = DDR3B_TEST_START_ADDRESS; index < DDR3B_TEST_END_ADDRESS; index += 4) {
        *index = ~index;
    }

    /* Read and check the pattern */
    for (index = DDR3B_TEST_START_ADDRESS; index < DDR3B_TEST_END_ADDRESS; index += 4) {

        value = *index;

        if (value  != ~index) {
            GEL_TextOut( "DDR3B memory test... Failed\n" );
            return -1;
        }
    }

    GEL_TextOut( "DDR3B memory test... Passed\n" );
    return 0;
	
}
	
//-------------------------------------------------------------------------

	
/****************************************************************************
 *
 * NAME
 *      Setup_Memory_Map
 *
 * PURPOSE:
 *      Setup the Memory Map for EVMC6678L.
 *      Defined memory location avoid debugger access outside these locations.
 *
 * USAGE
 *      This routine can be called as:
 *
 *      Setup_Memory_Map()
 *
 * RETURN VALUE
 *      NONE
 *
 * REFERENCE
 *      Based on TMS320C6678 datasheet.
 *
 ****************************************************************************/
hotmenu Setup_Memory_Map( )
{
    GEL_TextOut("Setup_Memory_Map...\n",,);

    GEL_MapOn( );
    GEL_MapReset( );

    GEL_MapAddStr( 0x00000000, 0, 0x21400000, "R|W|AS4", 0 );   // 
    GEL_MapAddStr( 0x21400000,0, 0x00000080, "R|W|AS4", 0 );   // Hyperlink Config (remote)	
    //GEL_MapAddStr( 0x21400080,0, 0x00000080, "R|W|AS4", 0 );   // Hyperlink Config (remote)
	GEL_MapAddStr( 0x21400200, 0, 0xdebffe00, "R|W|AS4", 0 );   // 
	GEL_TextOut( "Setup_Memory_Map... Done.\n" );
}

/*----------------------------------------------------- DDR3A : DDR800, 32bit--------------------------------------------------------------------------*/
ddr3A_32bit_DDR800_setup()
{
unsigned int multiplier = 15;
	unsigned int divider = 0;
	int temp;
	unsigned int OD_val = 8;
    KICK0 = 0x83E70B13;
    KICK1 = 0x95A4F1E0;
	 
	
//1.	Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010).
	 do { 
    read_val = DDR3A_PGSR0;
    } while ((read_val&0x00000001) != 0x00000001);
	
//4.	Clocks are enabled and frequency is stable---------------------------------------
//DDR3A PLL setup	
   GEL_TextOut ( "DDR3 PLL (PLL2) Setup ... \n");
    //DDR3APLLCTL0 = DDR3APLLCTL0 & 0xFF7FFFFF;
	//	Set ENSAT = 1
		DDR3APLLCTL1 |= 0x00000040;
	// Put the PLL in PLL Mode  
		DDR3APLLCTL0 |= 0x00800000;
	// In PLL Controller, reset the PLL (bit 13 in DDR3APLLCTL1 register) 
		DDR3APLLCTL1 |= 0x00002000;
	// Program the necessary multipliers/dividers and BW adjustments            
     // Set the divider values 
		DDR3APLLCTL0 &= ~(0x0000003F);
        DDR3APLLCTL0 |= (divider & 0x0000003F);
 /* Step 7: Programming OD[3:0] in the SECCTL register */            
    DDR3APLLCTL0 &= OUTPUT_DIVIDE_MASK;  // clear the OD bit field
    DDR3APLLCTL0 |= ~OUTPUT_DIVIDE_MASK & (OD_val - 1) << OUTPUT_DIVIDE_OFFSET;  // set the OD[3:0] bit field of PLLD to OD_val    

		 /* Set the Multipler values */
        DDR3APLLCTL0 &= ~(0x0007FFC0);
        DDR3APLLCTL0 |= ((multiplier << 6) & 0x0007FFC0 );
	   temp = ((multiplier + 1) >> 1) - 1;
        DDR3APLLCTL0 &= ~(0xFF000000); 
        DDR3APLLCTL0 |= ((temp << 24) & 0xFF000000);
        DDR3APLLCTL1 &= ~(0x0000000F);
        DDR3APLLCTL1 |= ((temp >> 8) & 0x0000000F);
	//In DDR3PLLCTL1, write PLLRST = 0 to bring PLL out of reset 
        DDR3APLLCTL1 &= ~(0x00002000);
	// Put the PLL in PLL Mode  
		DDR3APLLCTL0 &= ~(0x00800000); // ReSet the Bit 23
		GEL_TextOut( "DDR3 PLL Setup complete, DDR3A clock now running at 400MHz.\n" );
//DDR3A PLL setup complete ---------------------------------------
	
/*------------------------- Start PHY Configuration -------------------------------*/

 //DDR3A_PGCR1 = 0x0280C487;
 
 //5.a	Program FRQSEL in the PLL Control Register (address offset 0x018).
 DDR3A_PLLCR = 0xDC000; //Set FRQSEL=11, for ctl_clk between 166-275MHz
 
 //5.b.	Program WLSTEP=1, IODDRM=1, and ZCKSEL in the PHY General Configuration Register 1 (address offset 0x00C). 
 DDR3A_PGCR1 |= (1 << 2); //WLSTEP = 1
 
 DDR3A_PGCR1 &= ~(IODDRM_MASK);
 DDR3A_PGCR1 |= (( 1 << 7) & IODDRM_MASK);
 
 
 DDR3A_PGCR1 &= ~(ZCKSEL_MASK);
 DDR3A_PGCR1 |= (( 1 << 23) & ZCKSEL_MASK);
 
    
 //5.c.	Program PHY Timing Parameters Register 0-4 (address offset 0x01C - 0x02C).

	DDR3A_PTR0 = 0x42C21590;
	
	DDR3A_PTR1 = 0xD05612C0;	
	
// Maintaining default values of Phy Timing Parameters Register 2 in PUB
	
	DDR3A_PTR3 = 0x06C30D40;//0x18061A80; 

	DDR3A_PTR4 = 0x06413880;//0x0AAE7100;
	
//5.d.	Program PDQ, MPRDQ, and BYTEMASK in the DRAM Configuration Register (address offset 0x044). 
//		All other fields must be left at their default values.
 
  DDR3A_DCR &= ~(PDQ_MASK); //PDQ = 0
  DDR3A_DCR &= ~(MPRDQ_MASK); //MPRDQ = 0
  
  DDR3A_DCR &= ~(BYTEMASK_MASK);
  DDR3A_DCR |= (( 1 << 10) & BYTEMASK_MASK);
 
 
DDR3A_DCR &= ~(NOSRA_MASK);
DDR3A_DCR |= (( 1 << 27) & NOSRA_MASK);
 
 
  DDR3A_DCR &= ~(UDIMM_MASK);
 DDR3A_DCR |= (( 1 << 29) & UDIMM_MASK);
  
	
//5.e.	Program DRAM Timing Parameters Register 0-2 (address offset 0x048 - 0x050). 

	DDR3A_DTPR0 = 0x50CF6644; //0x50CE6644;
	DDR3A_DTPR1 = 0x12834180;
	DDR3A_DTPR2 = 0x50022A00;

//5.f.	Program BL=0, CL, WR, and PD=1 in the Mode Register 0 (address offset 0x054). 
		//All other fields must be left at their default values.

DDR3A_MR0 = 0x00001420;
	
	
//5.g.	Program DIC, RTT, and TDQS in the Mode Register 1 (address offset 0x058). 
		//All other fields must be left at their default values.

DDR3A_MR1 = 0x00000006;


//---------------------------------------------------------------------------------------------------------					

//5.h.	Program Mode Register 2 (address offset 0x05C).
	// Maintaining default values of Program Mode Register 2
	//	DDR3A_MR2 = 0x00000018;

//5.i.	Program DTMPR=1, DTEXD, DTEXG, RANKEN=1 or 3, and RFSHDT=7 in the Data Training Configuration Register (address offset 0x068). 
		//All other fields must be left at their default values.
		DDR3A_DTCR = 0x710035C7; //0x710035C7;
		
//5.j.	Program tREFPRD=(5*tREFI/ddr_clk_period) in the PHY General Configuration Register 2 (address offset 0x08C). 
		//All other fields must be left at their default values.
	
	DDR3A_PGCR2 = 0x00F03D09; //NOBUB = 0, FXDLAT = 0 	
//DDR3A_PGCR2 = 0x00F83D09; //NOBUB = 0, FXDLAT = 1 
	
//Set Impedence Register	
DDR3A_ZQ0CR1 = 0x0000005D; 
DDR3A_ZQ1CR1 = 0x0000005B;
DDR3A_ZQ2CR1 = 0x0000005B;
	
	
//6.	Re-trigger PHY initialization in DDR PHY through the VBUSP interface.
//6.a.	Program 0x00000033 to the PHY Initialization Register (address offset 0x004) to re-trigger PLL, ZCAL, and DCAL initialization.

	DDR3A_PIR = 0x00000033;
	
//6.b.	Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010).
     do { 
    read_val = DDR3A_PGSR0;
    } while ((read_val&0x00000001) != 0x00000001);

//---------------------------------------------------------------------------------------------------------					

	
  
// 7.	Trigger DDR3 initialization and leveling/training in DDR PHY through the VBUSP interface.
// a.	If using a 16-bit wide DDR interface, program DXEN=0 in the DATX8 2-7 General Configuration Registers (address offsets 0x240, 0x280, 0x2C0, 0x300, 0x340, and 0x380) to disable the leveling/training for the upper byte lanes.
// b.	If using a 32-bit wide DDR interface, program DXEN=0 in the DATX8 4-7 General Configuration Registers (address offsets 0x2C0, 0x300, 0x340, and 0x380) to disable the leveling/training for the upper byte lanes.
// c.	If ECC is not required, program DXEN=0 in the DATX8 8 General Configuration Register (address offset 0x3C0) to disable the leveling/training for the ECC byte lane.
// NOTE: Setup supports 64-bit by default,  ECC enable by default.
 
//7.d.	Program 0x0000XF81 to the PHY Initialization Register (address offset 0x004) to trigger DDR3 initialization and leveling/training sequences 
 	
	DDR3A_PIR = 0x00000F81; //WLADJ - ON
	 //DDR3A_PIR = 0x00000781;  //WLADJ - OFF

//---------------------------------------------------------------------------------------------------------					
			
//7.e.	Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010).
	do {              
		read_val = DDR3A_PGSR0;
	   } while ((read_val&0x00000001) != 0x00000001);
	   

	/* End PHY Configuration */		
//---------------------------------------------------------------------------------------------------------					
/* START EMIF INITIALIZATION
  ++++++++++++++++++SDCFG Register Calculation+++++++++++++++++++
  | 31 - 29  | 28 |27 - 25 | 24   | 23 - 22| 21 - 17 |
  |SDRAM_TYPE|Rsvd|DDR_TERM| DDQS | DYN_ODT|  Rsvd   |
  |  0x011   |  0 | 0x011  | 0x1  |   0x00 |   0x0   |

  | 16-14 |13 - 12 |  11 - 8 |  7   |6 - 5 |  4  |  3  |  2  |  1 - 0  |
  |   CWL | NM     |   CL    | Rsvd |IBANK | Rsvd|EBANK| Rsvd|PAGE_SIZE|
  |  0x11 | 0x00   |  0x1110 |  0x0 | 0x11 | 0x0 |  0  |  0  |   0x10  |
  SDCFG = 0x0110 0011 0010 0010 0011 0011 1011 0010
  SDCFG = 0x6700486A;//0x63223332

  SDRAM_TYPE = 3
  DDR_TERM = 3 (RZQ/4 = 1; RZQ/6=3)
  DDQS = 1 
  DYN_ODT = 0 
  
  CWL = 3 (CWL5=0; CWL6=1; CWL7=2; CWL8=3)
  NM = 0 (64-bit=0, 32-bit=1, 16-bit=2)
  CL = 14 (CL5=2; CL6=4; CL7=6; CL8=8; CL9=10; CL10=12; CL11=14)
  IBANK = 3 (8bank)
  EBANK = 0 (0 - pad_cs_o_n[0] , 1 - pad_cs_o_n[1:0])
  PAGE_SIZE = 2 (1024page-size=2; 2048page-size=3)
*/
/* Start DDR3A EMIF Configuration */
//8.	Configure the EMIF through the VBUSM interface.
//8.a.	Program all EMIF MMR’s.
	DDR3A_SDCFG    = 0x62001462	; //0x6200046A

    DDR3A_SDTIM1   = 0x0A384C23;
    DDR3A_SDTIM2   = 0x00001CA5;
    DDR3A_SDTIM3   = 0x21ADFF32;
	DDR3A_SDTIM4   = 0x533F067F;

	DDR3A_ZQCFG    = 0xF0073200; 	
//8.b.	Program reg_initref_dis=0 in the SDRAM Refresh Control Register (address offset 0x10).
    DDR3A_SDRFC = 0x00000C34;
      
	GEL_TextOut("DDR3A initialization complete \n");
	   /* End  DDR3A EMIF Configuration */

	}	


/*----------------------------------------------------- DDR3A : DDR1066, 32bit--------------------------------------------------------------------------*/
ddr3A_32bit_DDR1066_setup()
{

unsigned int multiplier = 15;
	unsigned int divider = 0;
	int temp;
	unsigned int OD_val = 6;
    KICK0 = 0x83E70B13;
    KICK1 = 0x95A4F1E0;
	 
	
//1.	Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010).
	 do { 
    read_val = DDR3A_PGSR0;
    } while ((read_val&0x00000001) != 0x00000001);
	
//4.	Clocks are enabled and frequency is stable---------------------------------------
//DDR3A PLL setup	
   GEL_TextOut ( "DDR3 PLL (PLL2) Setup ... \n");
    //DDR3APLLCTL0 = DDR3APLLCTL0 & 0xFF7FFFFF;
	//	Set ENSAT = 1
		DDR3APLLCTL1 |= 0x00000040;
	// Put the PLL in PLL Mode  
		DDR3APLLCTL0 |= 0x00800000;
	// In PLL Controller, reset the PLL (bit 13 in DDR3APLLCTL1 register) 
		DDR3APLLCTL1 |= 0x00002000;
	// Program the necessary multipliers/dividers and BW adjustments            
     // Set the divider values 
		DDR3APLLCTL0 &= ~(0x0000003F);
        DDR3APLLCTL0 |= (divider & 0x0000003F);
 /* Step 7: Programming OD[3:0] in the SECCTL register */            
    DDR3APLLCTL0 &= OUTPUT_DIVIDE_MASK;  // clear the OD bit field
    DDR3APLLCTL0 |= ~OUTPUT_DIVIDE_MASK & (OD_val - 1) << OUTPUT_DIVIDE_OFFSET;  // set the OD[3:0] bit field of PLLD to OD_val    

		 /* Set the Multipler values */
        DDR3APLLCTL0 &= ~(0x0007FFC0);
        DDR3APLLCTL0 |= ((multiplier << 6) & 0x0007FFC0 );
	   temp = ((multiplier + 1) >> 1) - 1;
        DDR3APLLCTL0 &= ~(0xFF000000); 
        DDR3APLLCTL0 |= ((temp << 24) & 0xFF000000);
        DDR3APLLCTL1 &= ~(0x0000000F);
        DDR3APLLCTL1 |= ((temp >> 8) & 0x0000000F);
	//In DDR3PLLCTL1, write PLLRST = 0 to bring PLL out of reset 
        DDR3APLLCTL1 &= ~(0x00002000);
	// Put the PLL in PLL Mode  
		DDR3APLLCTL0 &= ~(0x00800000); // ReSet the Bit 23
		GEL_TextOut( "DDR3 PLL Setup complete, DDR3A clock now running at 533MHz.\n" );
//DDR3A PLL setup complete ---------------------------------------
	
/*------------------------- Start PHY Configuration -------------------------------*/

 //DDR3A_PGCR1 = 0x0280C487;
 
 //5.a	Program FRQSEL in the PLL Control Register (address offset 0x018).
 DDR3A_PLLCR = 0xDC000; //Set FRQSEL=11, for ctl_clk between 166-275MHz
 
 //5.b.	Program WLSTEP=1, IODDRM=1, and ZCKSEL in the PHY General Configuration Register 1 (address offset 0x00C). 
 DDR3A_PGCR1 |= (1 << 2); //WLSTEP = 1
 
 DDR3A_PGCR1 &= ~(IODDRM_MASK);
 DDR3A_PGCR1 |= (( 1 << 7) & IODDRM_MASK);
 
 
 DDR3A_PGCR1 &= ~(ZCKSEL_MASK);
 DDR3A_PGCR1 |= (( 1 << 23) & ZCKSEL_MASK);
 
    
 //5.c.	Program PHY Timing Parameters Register 0-4 (address offset 0x01C - 0x02C).

	DDR3A_PTR0 = 0x42C21590;
	
	DDR3A_PTR1 = 0xD05612C0;	
	
// Maintaining default values of Phy Timing Parameters Register 2 in PUB
	
	DDR3A_PTR3 = 0x05B41104;//0x09041104;//0x18061A80; 

	DDR3A_PTR4 = 0x0855A068;//0x0AAE7100;
	
//5.d.	Program PDQ, MPRDQ, and BYTEMASK in the DRAM Configuration Register (address offset 0x044). 
//		All other fields must be left at their default values.
 
  DDR3A_DCR &= ~(PDQ_MASK); //PDQ = 0

  DDR3A_DCR &= ~(MPRDQ_MASK); //MPRDQ = 0
  
  DDR3A_DCR &= ~(BYTEMASK_MASK);
  DDR3A_DCR |= (( 1 << 10) & BYTEMASK_MASK);
 
 
DDR3A_DCR &= ~(NOSRA_MASK);
DDR3A_DCR |= (( 1 << 27) & NOSRA_MASK);
 
//DDR3A_DCR &= ~(UDIMM_MASK);
//DDR3A_DCR |= (( 1 << 29) & UDIMM_MASK);

//RRMODE
 //DDR3A_DSGCR &= ~(RRMODE_MASK); //RR_MODE = 0

//DDR3A_DSGCR &= ~(RRMODE_MASK); //RR_MODE = 1
 //DDR3A_DSGCR |= (( 1 << 18) & RRMODE_MASK);
  
	
//5.e.	Program DRAM Timing Parameters Register 0-2 (address offset 0x048 - 0x050). 

	DDR3A_DTPR0 = 0x6D147764;//0x6D148844;     //0x6D148844; 0x69137764 ---changed in rev 1.3

	DDR3A_DTPR1 = 0x1282B200;//0x12845A00;
	DDR3A_DTPR2 = 0x50023600;

//5.f.	Program BL=0, CL, WR, and PD=1 in the Mode Register 0 (address offset 0x054). 
		//All other fields must be left at their default values.

DDR3A_MR0 = 0x00001830;    //0x00001870; 
	
	
//5.g.	Program DIC, RTT, and TDQS in the Mode Register 1 (address offset 0x058). 
		//All other fields must be left at their default values.

DDR3A_MR1 =  0x00000006; //0x00000044;  ---changed in rev 1.3


//---------------------------------------------------------------------------------------------------------					

//5.h.	Program Mode Register 2 (address offset 0x05C).
	// Maintaining default values of Program Mode Register 2
		DDR3A_MR2 = 0x00000008;  //18   ---changed in rev 1.3


//5.i.	Program DTMPR=1, DTEXD, DTEXG, RANKEN=1 or 3, and RFSHDT=7 in the Data Training Configuration Register (address offset 0x068). 
		//All other fields must be left at their default values.
		DDR3A_DTCR = 0x710035C7; //0x730035C7;
		
//5.j.	Program tREFPRD=(5*tREFI/ddr_clk_period) in the PHY General Configuration Register 2 (address offset 0x08C). 
		//All other fields must be left at their default values.
	
	DDR3A_PGCR2 = 0x00F05159; //NOBUB = 0, FXDLAT = 0 	
//DDR3A_PGCR2 = 0x00F83D09; //NOBUB = 0, FXDLAT = 1 


//Set Impedence Register	
DDR3A_ZQ0CR1 = 0x0000005D; 
DDR3A_ZQ1CR1 = 0x0000005B;
DDR3A_ZQ2CR1 = 0x0000005B;
	
	
	
//6.	Re-trigger PHY initialization in DDR PHY through the VBUSP interface.
//6.a.	Program 0x00000033 to the PHY Initialization Register (address offset 0x004) to re-trigger PLL, ZCAL, and DCAL initialization.

	DDR3A_PIR = 0x00000033;
	
//6.b.	Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010).
     do { 
    read_val = DDR3A_PGSR0;
    } while ((read_val&0x00000001) != 0x00000001);

//---------------------------------------------------------------------------------------------------------					

	
  
// 7.	Trigger DDR3 initialization and leveling/training in DDR PHY through the VBUSP interface.
// a.	If using a 16-bit wide DDR interface, program DXEN=0 in the DATX8 2-7 General Configuration Registers (address offsets 0x240, 0x280, 0x2C0, 0x300, 0x340, and 0x380) to disable the leveling/training for the upper byte lanes.
// b.	If using a 32-bit wide DDR interface, program DXEN=0 in the DATX8 4-7 General Configuration Registers (address offsets 0x2C0, 0x300, 0x340, and 0x380) to disable the leveling/training for the upper byte lanes.
// c.	If ECC is not required, program DXEN=0 in the DATX8 8 General Configuration Register (address offset 0x3C0) to disable the leveling/training for the ECC byte lane.
// NOTE: Setup supports 64-bit by default,  ECC enable by default.
 
//7.d.	Program 0x0000XF81 to the PHY Initialization Register (address offset 0x004) to trigger DDR3 initialization and leveling/training sequences 
 	
	DDR3A_PIR = 0x00000F81; //WLADJ - ON
	 //DDR3A_PIR = 0x00000781;  //WLADJ - OFF


//---------------------------------------------------------------------------------------------------------					
			
//7.e.	Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010).
	do {              
		read_val = DDR3A_PGSR0;
	   } while ((read_val&0x00000001) != 0x00000001);
	   

	/* End PHY Configuration */		
//---------------------------------------------------------------------------------------------------------					
/* START EMIF INITIALIZATION
  ++++++++++++++++++SDCFG Register Calculation+++++++++++++++++++
  | 31 - 29  | 28 |27 - 25 | 24   | 23 - 22| 21 - 17 |
  |SDRAM_TYPE|Rsvd|DDR_TERM| DDQS | DYN_ODT|  Rsvd   |
  |  0x011   |  0 | 0x011  | 0x1  |   0x00 |   0x0   |

  | 16-14 |13 - 12 |  11 - 8 |  7   |6 - 5 |  4  |  3  |  2  |  1 - 0  |
  |   CWL | NM     |   CL    | Rsvd |IBANK | Rsvd|EBANK| Rsvd|PAGE_SIZE|
  |  0x11 | 0x00   |  0x1110 |  0x0 | 0x11 | 0x0 |  0  |  0  |   0x10  |
  SDCFG = 0x0110 0011 0010 0010 0011 0011 1011 0010
  SDCFG = 0x6700486A;//0x63223332

  SDRAM_TYPE = 3
  DDR_TERM = 3 (RZQ/4 = 1; RZQ/6=3)
  DDQS = 1 
  DYN_ODT = 0 
  
  CWL = 3 (CWL5=0; CWL6=1; CWL7=2; CWL8=3)
  NM = 0 (64-bit=0, 32-bit=1, 16-bit=2)
  CL = 14 (CL5=2; CL6=4; CL7=6; CL8=8; CL9=10; CL10=12; CL11=14)
  IBANK = 3 (8bank)
  EBANK = 0 (0 - pad_cs_o_n[0] , 1 - pad_cs_o_n[1:0])
  PAGE_SIZE = 2 (1024page-size=2; 2048page-size=3)
*/
/* Start DDR3A EMIF Configuration */
//8.	Configure the EMIF through the VBUSM interface.
//8.a.	Program all EMIF MMR’s.
	DDR3A_SDCFG    = 0x62005662; //0x62005662;
    DDR3A_SDTIM1   = 0x0E4C6835; //0x0E4C6833;//0x0E4C6833;
    DDR3A_SDTIM2   = 0x00001CC6;  //0x00001CE7;
    DDR3A_SDTIM3   = 0x3169FF32; //0x323DFF32;
	DDR3A_SDTIM4   = 0x533F055F; //0x533F08AF;

	DDR3A_ZQCFG    = 0x70073200;//0xF0073200; 	
//8.b.	Program reg_initref_dis=0 in the SDRAM Refresh Control Register (address offset 0x10).
    DDR3A_SDRFC = 0x00001044;
      
	GEL_TextOut("DDR3A initialization complete \n");
	   /* End  DDR3A EMIF Configuration */

	}



/*----------------------------------------------------- DDR3A : DDR1333, 32bit--------------------------------------------------------------------------*/

ddr3A_32bit_DDR1333_setup()	
{
unsigned int multiplier = 19;
	unsigned int divider = 0;
	int temp;
	unsigned int OD_val = 6;
    KICK0 = 0x83E70B13;
    KICK1 = 0x95A4F1E0;
	 
	
//1.	Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010).
	 do { 
    read_val = DDR3A_PGSR0;
    } while ((read_val&0x00000001) != 0x00000001);
	
//4.	Clocks are enabled and frequency is stable---------------------------------------
//DDR3A PLL setup	
   GEL_TextOut ( "DDR3 PLL (PLL2) Setup ... \n");
    //DDR3APLLCTL0 = DDR3APLLCTL0 & 0xFF7FFFFF;
	//	Set ENSAT = 1
		DDR3APLLCTL1 |= 0x00000040;
	// Put the PLL in PLL Mode  
		DDR3APLLCTL0 |= 0x00800000;
	// In PLL Controller, reset the PLL (bit 13 in DDR3APLLCTL1 register) 
		DDR3APLLCTL1 |= 0x00002000;
	// Program the necessary multipliers/dividers and BW adjustments            
     // Set the divider values 
		DDR3APLLCTL0 &= ~(0x0000003F);
        DDR3APLLCTL0 |= (divider & 0x0000003F);
 /* Step 7: Programming OD[3:0] in the SECCTL register */            
    DDR3APLLCTL0 &= OUTPUT_DIVIDE_MASK;  // clear the OD bit field
    DDR3APLLCTL0 |= ~OUTPUT_DIVIDE_MASK & (OD_val - 1) << OUTPUT_DIVIDE_OFFSET;  // set the OD[3:0] bit field of PLLD to OD_val    

		 /* Set the Multipler values */
        DDR3APLLCTL0 &= ~(0x0007FFC0);
        DDR3APLLCTL0 |= ((multiplier << 6) & 0x0007FFC0 );
	   temp = ((multiplier + 1) >> 1) - 1;
        DDR3APLLCTL0 &= ~(0xFF000000); 
        DDR3APLLCTL0 |= ((temp << 24) & 0xFF000000);
        DDR3APLLCTL1 &= ~(0x0000000F);
        DDR3APLLCTL1 |= ((temp >> 8) & 0x0000000F);
	//In DDR3PLLCTL1, write PLLRST = 0 to bring PLL out of reset 
        DDR3APLLCTL1 &= ~(0x00002000);
	// Put the PLL in PLL Mode  
		DDR3APLLCTL0 &= ~(0x00800000); // ReSet the Bit 23
		GEL_TextOut( "DDR3 PLL Setup complete, DDR3A clock now running at 666 MHz.\n" );
//DDR3A PLL setup complete ---------------------------------------
	
/*------------------------- Start PHY Configuration -------------------------------*/

 //DDR3A_PGCR1 = 0x0280C487;
 
 //5.a	Program FRQSEL in the PLL Control Register (address offset 0x018).
 DDR3A_PLLCR = 0x5C000; //Set FRQSEL=11, for ctl_clk between 166-275MHz
 
 //5.b.	Program WLSTEP=1, IODDRM=1, and ZCKSEL in the PHY General Configuration Register 1 (address offset 0x00C). 
 DDR3A_PGCR1 |= (1 << 2); //WLSTEP = 1
 
 DDR3A_PGCR1 &= ~(IODDRM_MASK);
 DDR3A_PGCR1 |= (( 1 << 7) & IODDRM_MASK);
 
 
 DDR3A_PGCR1 &= ~(ZCKSEL_MASK);
 DDR3A_PGCR1 |= (( 1 << 23) & ZCKSEL_MASK);
 
    
 //5.c.	Program PHY Timing Parameters Register 0-4 (address offset 0x01C - 0x02C).

	DDR3A_PTR0 = 0x42C21590;
	
	DDR3A_PTR1 = 0xD05612C0;	
	
// Maintaining default values of Phy Timing Parameters Register 2 in PUB
	
	DDR3A_PTR3 = 0x0B4515C2;//0x072515C2; //0x0B4515C2;//0x18061A80; 

	DDR3A_PTR4 = 0x0A6E08B4;//0x0AAE7100;
	
//5.d.	Program PDQ, MPRDQ, and BYTEMASK in the DRAM Configuration Register (address offset 0x044). 
//		All other fields must be left at their default values.
 
  DDR3A_DCR &= ~(PDQ_MASK); //PDQ = 0

  DDR3A_DCR &= ~(MPRDQ_MASK); //MPRDQ = 0
  
  DDR3A_DCR &= ~(BYTEMASK_MASK);
  DDR3A_DCR |= (( 1 << 10) & BYTEMASK_MASK);
 
 
DDR3A_DCR &= ~(NOSRA_MASK);
 DDR3A_DCR |= (( 1 << 27) & NOSRA_MASK);
 
 
  //DDR3A_DCR &= ~(UDIMM_MASK);
  //DDR3A_DCR |= (( 1 << 29) & UDIMM_MASK);
  
	
//5.e.	Program DRAM Timing Parameters Register 0-2 (address offset 0x048 - 0x050). 

	DDR3A_DTPR0 = 0x8558AA75;//0x85589975;//0x8558AA55;
	DDR3A_DTPR1 = 0x12857280;//0x12835A80;//0x12857280;
	DDR3A_DTPR2 = 0x5002C200;

//5.f.	Program BL=0, CL, WR, and PD=1 in the Mode Register 0 (address offset 0x054). 
		//All other fields must be left at their default values.

DDR3A_MR0 = 0x00001A60; //50
	
	
//5.g.	Program DIC, RTT, and TDQS in the Mode Register 1 (address offset 0x058). 
		//All other fields must be left at their default values.

DDR3A_MR1 = 0x00000006;


//---------------------------------------------------------------------------------------------------------					

//5.h.	Program Mode Register 2 (address offset 0x05C).
	// Maintaining default values of Program Mode Register 2
	DDR3A_MR2 = 0x00000010;

//5.i.	Program DTMPR=1, DTEXD, DTEXG, RANKEN=1 or 3, and RFSHDT=7 in the Data Training Configuration Register (address offset 0x068). 
		//All other fields must be left at their default values.
		DDR3A_DTCR = 0x710035C7; //0x730035C7;
		
//5.j.	Program tREFPRD=(5*tREFI/ddr_clk_period) in the PHY General Configuration Register 2 (address offset 0x08C). 
		//All other fields must be left at their default values.
	
	DDR3A_PGCR2 = 0x00F065B8; //NOBUB = 0, FXDLAT = 0 	
//DDR3A_PGCR2 = 0x00F83D09; //NOBUB = 0, FXDLAT = 1 
	
//Set Impedence Register	
DDR3A_ZQ0CR1 = 0x0000005D; 
DDR3A_ZQ1CR1 = 0x0000005B;
DDR3A_ZQ2CR1 = 0x0000005B;
//DDR3A_ZQ3CR1 = 0x0000005D;
	
//6.	Re-trigger PHY initialization in DDR PHY through the VBUSP interface.
//6.a.	Program 0x00000033 to the PHY Initialization Register (address offset 0x004) to re-trigger PLL, ZCAL, and DCAL initialization.

	DDR3A_PIR = 0x00000033;
	
//6.b.	Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010).
     do { 
    read_val = DDR3A_PGSR0;
    } while ((read_val&0x00000001) != 0x00000001);

//---------------------------------------------------------------------------------------------------------					

	
  
// 7.	Trigger DDR3 initialization and leveling/training in DDR PHY through the VBUSP interface.
// a.	If using a 16-bit wide DDR interface, program DXEN=0 in the DATX8 2-7 General Configuration Registers (address offsets 0x240, 0x280, 0x2C0, 0x300, 0x340, and 0x380) to disable the leveling/training for the upper byte lanes.
// b.	If using a 32-bit wide DDR interface, program DXEN=0 in the DATX8 4-7 General Configuration Registers (address offsets 0x2C0, 0x300, 0x340, and 0x380) to disable the leveling/training for the upper byte lanes.
// c.	If ECC is not required, program DXEN=0 in the DATX8 8 General Configuration Register (address offset 0x3C0) to disable the leveling/training for the ECC byte lane.
// NOTE: Setup supports 64-bit by default,  ECC enable by default.
 
//7.d.	Program 0x0000XF81 to the PHY Initialization Register (address offset 0x004) to trigger DDR3 initialization and leveling/training sequences 
 	
	DDR3A_PIR = 0x0000FF81; //WLADJ - ON
	 //DDR3A_PIR = 0x00000781;  //WLADJ - OFF


//---------------------------------------------------------------------------------------------------------					
			
//7.e.	Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010).
	do {              
		read_val = DDR3A_PGSR0;
	   } while ((read_val&0x00000001) != 0x00000001);
	   

	/* End PHY Configuration */		
//---------------------------------------------------------------------------------------------------------					
/* START EMIF INITIALIZATION
  ++++++++++++++++++SDCFG Register Calculation+++++++++++++++++++
  | 31 - 29  | 28 |27 - 25 | 24   | 23 - 22| 21 - 17 |
  |SDRAM_TYPE|Rsvd|DDR_TERM| DDQS | DYN_ODT|  Rsvd   |
  |  0x011   |  0 | 0x011  | 0x1  |   0x00 |   0x0   |

  | 16-14 |13 - 12 |  11 - 8 |  7   |6 - 5 |  4  |  3  |  2  |  1 - 0  |
  |   CWL | NM     |   CL    | Rsvd |IBANK | Rsvd|EBANK| Rsvd|PAGE_SIZE|
  |  0x11 | 0x00   |  0x1110 |  0x0 | 0x11 | 0x0 |  0  |  0  |   0x10  |
  SDCFG = 0x0110 0011 0010 0010 0011 0011 1011 0010
  SDCFG = 0x6700486A;//0x63223332

  SDRAM_TYPE = 3
  DDR_TERM = 3 (RZQ/4 = 1; RZQ/6=3)
  DDQS = 1 
  DYN_ODT = 0 
  
  CWL = 3 (CWL5=0; CWL6=1; CWL7=2; CWL8=3)
  NM = 0 (64-bit=0, 32-bit=1, 16-bit=2)
  CL = 14 (CL5=2; CL6=4; CL7=6; CL8=8; CL9=10; CL10=12; CL11=14)
  IBANK = 3 (8bank)
  EBANK = 0 (0 - pad_cs_o_n[0] , 1 - pad_cs_o_n[1:0])
  PAGE_SIZE = 2 (1024page-size=2; 2048page-size=3)
*/
/* Start DDR3A EMIF Configuration */
//8.	Configure the EMIF through the VBUSM interface.
//8.a.	Program all EMIF MMR’s.
	DDR3A_SDCFG    = 0x62009C62; // 9A62//0x62008C62	;//0x6600CE62=single rank,0x6600CE6A=dual rank

    DDR3A_SDTIM1   = 0x125C8044;
    DDR3A_SDTIM2   = 0x00001D29;
    DDR3A_SDTIM3   = 0x32CDFF43;
	DDR3A_SDTIM4   = 0x543F0ADF;

	DDR3A_ZQCFG    = 0x70073200; 	
//8.b.	Program reg_initref_dis=0 in the SDRAM Refresh Control Register (address offset 0x10).
    DDR3A_SDRFC = 0x00001457;
      
	GEL_TextOut("DDR3A initialization complete \n");
	   /* End  DDR3A EMIF Configuration */
}


/*----------------------------------------------------- DDR3B : DDR800, 64bit--------------------------------------------------------------------------*/
ddr3B_64bit_DDR800_setup()
{
unsigned int multiplier = 15;
	unsigned int divider = 0;
	int temp;
	unsigned int OD_val = 8;
    KICK0 = 0x83E70B13;
    KICK1 = 0x95A4F1E0;
	 
	
//1.	Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010).
	 do { 
    read_val = DDR3B_PGSR0;
    } while ((read_val&0x00000001) != 0x00000001);
	
//4.	Clocks are enabled and frequency is stable---------------------------------------
//DDR3B PLL setup	
   GEL_TextOut ( "DDR3 PLL (PLL2) Setup ... \n");
    //DDR3BPLLCTL0 = DDR3BPLLCTL0 & 0xFF7FFFFF;
	//	Set ENSAT = 1
		DDR3BPLLCTL1 |= 0x00000040;
	// Put the PLL in PLL Mode  
		DDR3BPLLCTL0 |= 0x00800000;
	// In PLL Controller, reset the PLL (bit 13 in DDR3BPLLCTL1 register) 
		DDR3BPLLCTL1 |= 0x00002000;
	// Program the necessary multipliers/dividers and BW adjustments            
     // Set the divider values 
		DDR3BPLLCTL0 &= ~(0x0000003F);
        DDR3BPLLCTL0 |= (divider & 0x0000003F);
 /* Step 7: Programming OD[3:0] in the SECCTL register */            
    DDR3BPLLCTL0 &= OUTPUT_DIVIDE_MASK;  // clear the OD bit field
    DDR3BPLLCTL0 |= ~OUTPUT_DIVIDE_MASK & (OD_val - 1) << OUTPUT_DIVIDE_OFFSET;  // set the OD[3:0] bit field of PLLD to OD_val    

		 /* Set the Multipler values */
        DDR3BPLLCTL0 &= ~(0x0007FFC0);
        DDR3BPLLCTL0 |= ((multiplier << 6) & 0x0007FFC0 );
	   temp = ((multiplier + 1) >> 1) - 1;
        DDR3BPLLCTL0 &= ~(0xFF000000); 
        DDR3BPLLCTL0 |= ((temp << 24) & 0xFF000000);
        DDR3BPLLCTL1 &= ~(0x0000000F);
        DDR3BPLLCTL1 |= ((temp >> 8) & 0x0000000F);
	//In DDR3PLLCTL1, write PLLRST = 0 to bring PLL out of reset 
        DDR3BPLLCTL1 &= ~(0x00002000);
	// Put the PLL in PLL Mode  
		DDR3BPLLCTL0 &= ~(0x00800000); // ReSet the Bit 23
		GEL_TextOut( "DDR3 PLL Setup complete, DDR3B clock now running at 400MHz.\n" );
//DDR3B PLL setup complete ---------------------------------------
	
/*------------------------- Start PHY Configuration -------------------------------*/

 //DDR3B_PGCR1 = 0x0280C487;
 
 //5.a	Program FRQSEL in the PLL Control Register (address offset 0x018).
 DDR3B_PLLCR = 0xDC000; //Set FRQSEL=11, for ctl_clk between 166-275MHz
 
 //5.b.	Program WLSTEP=1, IODDRM=1, and ZCKSEL in the PHY General Configuration Register 1 (address offset 0x00C). 
 DDR3B_PGCR1 |= (1 << 2); //WLSTEP = 1
 
 DDR3B_PGCR1 &= ~(IODDRM_MASK);
 DDR3B_PGCR1 |= (( 1 << 7) & IODDRM_MASK);
 
 
 DDR3B_PGCR1 &= ~(ZCKSEL_MASK);
 DDR3B_PGCR1 |= (( 1 << 23) & ZCKSEL_MASK);
 
   //RRMODE
 //DDR3B_DSGCR &= ~(RRMODE_MASK); //RR_MODE = 0

//DDR3B_DSGCR &= ~(RRMODE_MASK); //RR_MODE = 1
 //DDR3B_DSGCR |= (( 1 << 18) & RRMODE_MASK);
 
    
 //5.c.	Program PHY Timing Parameters Register 0-4 (address offset 0x01C - 0x02C).

	DDR3B_PTR0 = 0x42C21590;
	
	DDR3B_PTR1 = 0xD05612C0;	
	
// Maintaining default values of Phy Timing Parameters Register 2 in PUB
	
	DDR3B_PTR3 = 0x06C30D40;//0x18061A80; 

	DDR3B_PTR4 = 0x6413880;//0x0AAE7100;
	
//5.d.	Program PDQ, MPRDQ, and BYTEMASK in the DRAM Configuration Register (address offset 0x044). 
//		All other fields must be left at their default values.
 
  DDR3B_DCR &= ~(PDQ_MASK); //PDQ = 0
  DDR3B_DCR &= ~(MPRDQ_MASK); //MPRDQ = 0
  
  DDR3B_DCR &= ~(BYTEMASK_MASK);
  DDR3B_DCR |= (( 1 << 10) & BYTEMASK_MASK);
 
 
DDR3B_DCR &= ~(NOSRA_MASK);
DDR3B_DCR |= (( 1 << 27) & NOSRA_MASK);
 
 
  //DDR3B_DCR &= ~(UDIMM_MASK);
 //DDR3B_DCR |= (( 1 << 29) & UDIMM_MASK);
  
	
//5.e.	Program DRAM Timing Parameters Register 0-2 (address offset 0x048 - 0x050). 

	DDR3B_DTPR0 = 0x50CE6644;
	DDR3B_DTPR1 = 0x12834180;
	DDR3B_DTPR2 = 0x50022A00;

//5.f.	Program BL=0, CL, WR, and PD=1 in the Mode Register 0 (address offset 0x054). 
		//All other fields must be left at their default values.

DDR3B_MR0 = 0x00001420;
	
	
//5.g.	Program DIC, RTT, and TDQS in the Mode Register 1 (address offset 0x058). 
		//All other fields must be left at their default values.

DDR3B_MR1 = 0x00000006;


//---------------------------------------------------------------------------------------------------------					

//5.h.	Program Mode Register 2 (address offset 0x05C).
	// Maintaining default values of Program Mode Register 2
	//	DDR3B_MR2 = 0x00000018;

//5.i.	Program DTMPR=1, DTEXD, DTEXG, RANKEN=1 or 3, and RFSHDT=7 in the Data Training Configuration Register (address offset 0x068). 
		//All other fields must be left at their default values.
		DDR3B_DTCR = 0x710035C7; //0x710035C7;
		
//5.j.	Program tREFPRD=(5*tREFI/ddr_clk_period) in the PHY General Configuration Register 2 (address offset 0x08C). 
		//All other fields must be left at their default values.
	
	DDR3B_PGCR2 = 0x00F03D09; //NOBUB = 0, FXDLAT = 0 	
//DDR3B_PGCR2 = 0x00F83D09; //NOBUB = 0, FXDLAT = 1 
	
//Set Impedence Register	
DDR3B_ZQ0CR1 = 0x0000005D; 
DDR3B_ZQ1CR1 = 0x0000005B;
DDR3B_ZQ2CR1 = 0x0000005B;
	
	
//6.	Re-trigger PHY initialization in DDR PHY through the VBUSP interface.
//6.a.	Program 0x00000033 to the PHY Initialization Register (address offset 0x004) to re-trigger PLL, ZCAL, and DCAL initialization.

	DDR3B_PIR = 0x00000033;
	
//6.b.	Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010).
     do { 
    read_val = DDR3B_PGSR0;
    } while ((read_val&0x00000001) != 0x00000001);

//---------------------------------------------------------------------------------------------------------					

	
  
// 7.	Trigger DDR3 initialization and leveling/training in DDR PHY through the VBUSP interface.
// a.	If using a 16-bit wide DDR interface, program DXEN=0 in the DATX8 2-7 General Configuration Registers (address offsets 0x240, 0x280, 0x2C0, 0x300, 0x340, and 0x380) to disable the leveling/training for the upper byte lanes.
// b.	If using a 32-bit wide DDR interface, program DXEN=0 in the DATX8 4-7 General Configuration Registers (address offsets 0x2C0, 0x300, 0x340, and 0x380) to disable the leveling/training for the upper byte lanes.
// c.	If ECC is not required, program DXEN=0 in the DATX8 8 General Configuration Register (address offset 0x3C0) to disable the leveling/training for the ECC byte lane.
// NOTE: Setup supports 64-bit by default,  ECC enable by default.
 
//7.d.	Program 0x0000XF81 to the PHY Initialization Register (address offset 0x004) to trigger DDR3 initialization and leveling/training sequences 
 	
	DDR3B_PIR = 0x00000F81; //WLADJ - ON
	 //DDR3B_PIR = 0x00000781;  //WLADJ - OFF

//---------------------------------------------------------------------------------------------------------					
			
//7.e.	Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010).
	do {              
		read_val = DDR3B_PGSR0;
	   } while ((read_val&0x00000001) != 0x00000001);
	   

	/* End PHY Configuration */		
//---------------------------------------------------------------------------------------------------------					
/* START EMIF INITIALIZATION
  ++++++++++++++++++SDCFG Register Calculation+++++++++++++++++++
  | 31 - 29  | 28 |27 - 25 | 24   | 23 - 22| 21 - 17 |
  |SDRAM_TYPE|Rsvd|DDR_TERM| DDQS | DYN_ODT|  Rsvd   |
  |  0x011   |  0 | 0x011  | 0x1  |   0x00 |   0x0   |

  | 16-14 |13 - 12 |  11 - 8 |  7   |6 - 5 |  4  |  3  |  2  |  1 - 0  |
  |   CWL | NM     |   CL    | Rsvd |IBANK | Rsvd|EBANK| Rsvd|PAGE_SIZE|
  |  0x11 | 0x00   |  0x1110 |  0x0 | 0x11 | 0x0 |  0  |  0  |   0x10  |
  SDCFG = 0x0110 0011 0010 0010 0011 0011 1011 0010
  SDCFG = 0x6700486A;//0x63223332

  SDRAM_TYPE = 3
  DDR_TERM = 3 (RZQ/4 = 1; RZQ/6=3)
  DDQS = 1 
  DYN_ODT = 0 
  
  CWL = 3 (CWL5=0; CWL6=1; CWL7=2; CWL8=3)
  NM = 0 (64-bit=0, 32-bit=1, 16-bit=2)
  CL = 14 (CL5=2; CL6=4; CL7=6; CL8=8; CL9=10; CL10=12; CL11=14)
  IBANK = 3 (8bank)
  EBANK = 0 (0 - pad_cs_o_n[0] , 1 - pad_cs_o_n[1:0])
  PAGE_SIZE = 2 (1024page-size=2; 2048page-size=3)
*/
/* Start DDR3B EMIF Configuration */
//8.	Configure the EMIF through the VBUSM interface.
//8.a.	Program all EMIF MMR’s.
	DDR3B_SDCFG    = 0x62000462	;

    DDR3B_SDTIM1   = 0x0A384C23;
    DDR3B_SDTIM2   = 0x00001CA5;
    DDR3B_SDTIM3   = 0x21ADFF32;
	DDR3B_SDTIM4   = 0x533F067F;

	DDR3B_ZQCFG    = 0xF0073200; 	
//8.b.	Program reg_initref_dis=0 in the SDRAM Refresh Control Register (address offset 0x10).
    DDR3B_SDRFC = 0x00000C34;
      
	GEL_TextOut("DDR3B initialization complete \n");
	   /* End  DDR3B EMIF Configuration */

}

/*----------------------------------------------------- DDR3B : DDR1066, 64bit--------------------------------------------------------------------------*/
ddr3B_64bit_DDR1066_setup()
{
unsigned int multiplier = 15;
	unsigned int divider = 0;
	int temp;
	unsigned int OD_val = 6;
    KICK0 = 0x83E70B13;
    KICK1 = 0x95A4F1E0;
	 
	
//1.	Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010).
	 do { 
    read_val = DDR3B_PGSR0;
    } while ((read_val&0x00000001) != 0x00000001);
	
//4.	Clocks are enabled and frequency is stable---------------------------------------
//DDR3B PLL setup	
   GEL_TextOut ( "DDR3 PLL (PLL2) Setup ... \n");
    //DDR3BPLLCTL0 = DDR3BPLLCTL0 & 0xFF7FFFFF;
	//	Set ENSAT = 1
		DDR3BPLLCTL1 |= 0x00000040;
	// Put the PLL in PLL Mode  
		DDR3BPLLCTL0 |= 0x00800000;
	// In PLL Controller, reset the PLL (bit 13 in DDR3BPLLCTL1 register) 
		DDR3BPLLCTL1 |= 0x00002000;
	// Program the necessary multipliers/dividers and BW adjustments            
     // Set the divider values 
		DDR3BPLLCTL0 &= ~(0x0000003F);
        DDR3BPLLCTL0 |= (divider & 0x0000003F);
 /* Step 7: Programming OD[3:0] in the SECCTL register */            
    DDR3BPLLCTL0 &= OUTPUT_DIVIDE_MASK;  // clear the OD bit field
    DDR3BPLLCTL0 |= ~OUTPUT_DIVIDE_MASK & (OD_val - 1) << OUTPUT_DIVIDE_OFFSET;  // set the OD[3:0] bit field of PLLD to OD_val    

		 /* Set the Multipler values */
        DDR3BPLLCTL0 &= ~(0x0007FFC0);
        DDR3BPLLCTL0 |= ((multiplier << 6) & 0x0007FFC0 );
	   temp = ((multiplier + 1) >> 1) - 1;
        DDR3BPLLCTL0 &= ~(0xFF000000); 
        DDR3BPLLCTL0 |= ((temp << 24) & 0xFF000000);
        DDR3BPLLCTL1 &= ~(0x0000000F);
        DDR3BPLLCTL1 |= ((temp >> 8) & 0x0000000F);
	//In DDR3PLLCTL1, write PLLRST = 0 to bring PLL out of reset 
        DDR3BPLLCTL1 &= ~(0x00002000);
	// Put the PLL in PLL Mode  
		DDR3BPLLCTL0 &= ~(0x00800000); // ReSet the Bit 23
		GEL_TextOut( "DDR3 PLL Setup complete, DDR3B clock now running at 533MHz.\n" );
//DDR3B PLL setup complete ---------------------------------------
	
/*------------------------- Start PHY Configuration -------------------------------*/

 //DDR3B_PGCR1 = 0x0280C487;
 
 //5.a	Program FRQSEL in the PLL Control Register (address offset 0x018).
 DDR3B_PLLCR = 0xDC000; //Set FRQSEL=11, for ctl_clk between 166-275MHz
 
 //5.b.	Program WLSTEP=1, IODDRM=1, and ZCKSEL in the PHY General Configuration Register 1 (address offset 0x00C). 
 DDR3B_PGCR1 |= (1 << 2); //WLSTEP = 1
 
 DDR3B_PGCR1 &= ~(IODDRM_MASK);
 DDR3B_PGCR1 |= (( 1 << 7) & IODDRM_MASK);
 
 
 DDR3B_PGCR1 &= ~(ZCKSEL_MASK);
 DDR3B_PGCR1 |= (( 1 << 23) & ZCKSEL_MASK);
 
    
 //5.c.	Program PHY Timing Parameters Register 0-4 (address offset 0x01C - 0x02C).

	DDR3B_PTR0 = 0x42C21590;
	
	DDR3B_PTR1 = 0xD05612C0;	
	
// Maintaining default values of Phy Timing Parameters Register 2 in PUB
	
	DDR3B_PTR3 = 0x09041104;//0x18061A80; 

	DDR3B_PTR4 = 0x0855A068;//0x0AAE7100;
	
//5.d.	Program PDQ, MPRDQ, and BYTEMASK in the DRAM Configuration Register (address offset 0x044). 
//		All other fields must be left at their default values.
 
  DDR3B_DCR &= ~(PDQ_MASK); //PDQ = 0

  DDR3B_DCR &= ~(MPRDQ_MASK); //MPRDQ = 0
  
  DDR3B_DCR &= ~(BYTEMASK_MASK);
  DDR3B_DCR |= (( 1 << 10) & BYTEMASK_MASK);
 
 
DDR3B_DCR &= ~(NOSRA_MASK);
DDR3B_DCR |= (( 1 << 27) & NOSRA_MASK);
 
//DDR3B_DCR &= ~(UDIMM_MASK);
//DDR3B_DCR |= (( 1 << 29) & UDIMM_MASK);
  
	
//5.e.	Program DRAM Timing Parameters Register 0-2 (address offset 0x048 - 0x050). 

	DDR3B_DTPR0 = 0x6D148844;
	DDR3B_DTPR1 = 0x12845A00;
	DDR3B_DTPR2 = 0x50023600;

//5.f.	Program BL=0, CL, WR, and PD=1 in the Mode Register 0 (address offset 0x054). 
		//All other fields must be left at their default values.

DDR3B_MR0 = 0x00001830; //0x00001870
	
	
//5.g.	Program DIC, RTT, and TDQS in the Mode Register 1 (address offset 0x058). 
		//All other fields must be left at their default values.

DDR3B_MR1 = 0x00000006;


//---------------------------------------------------------------------------------------------------------					

//5.h.	Program Mode Register 2 (address offset 0x05C).
	// Maintaining default values of Program Mode Register 2
		DDR3B_MR2 = 0x00000008;

//5.i.	Program DTMPR=1, DTEXD, DTEXG, RANKEN=1 or 3, and RFSHDT=7 in the Data Training Configuration Register (address offset 0x068). 
		//All other fields must be left at their default values.
		DDR3B_DTCR = 0x710035C7; //0x730035C7;
		
//5.j.	Program tREFPRD=(5*tREFI/ddr_clk_period) in the PHY General Configuration Register 2 (address offset 0x08C). 
		//All other fields must be left at their default values.
	
	DDR3B_PGCR2 = 0x00F05159; //NOBUB = 0, FXDLAT = 0 	
//DDR3B_PGCR2 = 0x00F83D09; //NOBUB = 0, FXDLAT = 1 

//Set Impedence Register	
DDR3B_ZQ0CR1 = 0x0000005D; 
DDR3B_ZQ1CR1 = 0x0000005B;
DDR3B_ZQ2CR1 = 0x0000005B;
	
	
//6.	Re-trigger PHY initialization in DDR PHY through the VBUSP interface.
//6.a.	Program 0x00000033 to the PHY Initialization Register (address offset 0x004) to re-trigger PLL, ZCAL, and DCAL initialization.

	DDR3B_PIR = 0x00000033;
	
//6.b.	Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010).
     do { 
    read_val = DDR3B_PGSR0;
    } while ((read_val&0x00000001) != 0x00000001);

//---------------------------------------------------------------------------------------------------------					

	
  
// 7.	Trigger DDR3 initialization and leveling/training in DDR PHY through the VBUSP interface.
// a.	If using a 16-bit wide DDR interface, program DXEN=0 in the DATX8 2-7 General Configuration Registers (address offsets 0x240, 0x280, 0x2C0, 0x300, 0x340, and 0x380) to disable the leveling/training for the upper byte lanes.
// b.	If using a 32-bit wide DDR interface, program DXEN=0 in the DATX8 4-7 General Configuration Registers (address offsets 0x2C0, 0x300, 0x340, and 0x380) to disable the leveling/training for the upper byte lanes.
// c.	If ECC is not required, program DXEN=0 in the DATX8 8 General Configuration Register (address offset 0x3C0) to disable the leveling/training for the ECC byte lane.
// NOTE: Setup supports 64-bit by default,  ECC enable by default.
 
//7.d.	Program 0x0000XF81 to the PHY Initialization Register (address offset 0x004) to trigger DDR3 initialization and leveling/training sequences 
 	
	DDR3B_PIR = 0x00000F81; //WLADJ - ON
	 //DDR3B_PIR = 0x00000781;  //WLADJ - OFF


//---------------------------------------------------------------------------------------------------------					
			
//7.e.	Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010).
	do {              
		read_val = DDR3B_PGSR0;
	   } while ((read_val&0x00000001) != 0x00000001);
	   

	/* End PHY Configuration */		
//---------------------------------------------------------------------------------------------------------					
/* START EMIF INITIALIZATION
  ++++++++++++++++++SDCFG Register Calculation+++++++++++++++++++
  | 31 - 29  | 28 |27 - 25 | 24   | 23 - 22| 21 - 17 |
  |SDRAM_TYPE|Rsvd|DDR_TERM| DDQS | DYN_ODT|  Rsvd   |
  |  0x011   |  0 | 0x011  | 0x1  |   0x00 |   0x0   |

  | 16-14 |13 - 12 |  11 - 8 |  7   |6 - 5 |  4  |  3  |  2  |  1 - 0  |
  |   CWL | NM     |   CL    | Rsvd |IBANK | Rsvd|EBANK| Rsvd|PAGE_SIZE|
  |  0x11 | 0x00   |  0x1110 |  0x0 | 0x11 | 0x0 |  0  |  0  |   0x10  |
  SDCFG = 0x0110 0011 0010 0010 0011 0011 1011 0010
  SDCFG = 0x6700486A;//0x63223332

  SDRAM_TYPE = 3
  DDR_TERM = 3 (RZQ/4 = 1; RZQ/6=3)
  DDQS = 1 
  DYN_ODT = 0 
  
  CWL = 3 (CWL5=0; CWL6=1; CWL7=2; CWL8=3)
  NM = 0 (64-bit=0, 32-bit=1, 16-bit=2)
  CL = 14 (CL5=2; CL6=4; CL7=6; CL8=8; CL9=10; CL10=12; CL11=14)
  IBANK = 3 (8bank)
  EBANK = 0 (0 - pad_cs_o_n[0] , 1 - pad_cs_o_n[1:0])
  PAGE_SIZE = 2 (1024page-size=2; 2048page-size=3)
*/
/* Start DDR3B EMIF Configuration */
//8.	Configure the EMIF through the VBUSM interface.
//8.a.	Program all EMIF MMR’s.
	DDR3B_SDCFG    = 0x62004662; //0x6600CE62=single rank, 0x6600CE6A=dual rank
    DDR3B_SDTIM1   = 0x0E4C6833;
    DDR3B_SDTIM2   = 0x00001CE7;
    DDR3B_SDTIM3   = 0x323DFF32;
	DDR3B_SDTIM4   = 0x533F08AF;

	DDR3B_ZQCFG    = 0xF0073200; 	
//8.b.	Program reg_initref_dis=0 in the SDRAM Refresh Control Register (address offset 0x10).
    DDR3B_SDRFC = 0x00001044;
      
	GEL_TextOut("DDR3B initialization complete \n");
	   /* End  DDR3B EMIF Configuration */
}

/*----------------------------------------------------- DDR3B : DDR1333, 64bit--------------------------------------------------------------------------*/
ddr3B_64bit_DDR1333_setup()
{
unsigned int multiplier = 19;
	unsigned int divider = 0;
	int temp;
	unsigned int OD_val = 6;
    KICK0 = 0x83E70B13;
    KICK1 = 0x95A4F1E0;
	 
	
//1.	Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010).
	 do { 
    read_val = DDR3B_PGSR0;
    } while ((read_val&0x00000001) != 0x00000001);
	
//4.	Clocks are enabled and frequency is stable---------------------------------------
//DDR3B PLL setup	
   GEL_TextOut ( "DDR3 PLL (PLL2) Setup ... \n");
    //DDR3BPLLCTL0 = DDR3BPLLCTL0 & 0xFF7FFFFF;
	//	Set ENSAT = 1
		DDR3BPLLCTL1 |= 0x00000040;
	// Put the PLL in PLL Mode  
		DDR3BPLLCTL0 |= 0x00800000;
	// In PLL Controller, reset the PLL (bit 13 in DDR3BPLLCTL1 register) 
		DDR3BPLLCTL1 |= 0x00002000;
	// Program the necessary multipliers/dividers and BW adjustments            
     // Set the divider values 
		DDR3BPLLCTL0 &= ~(0x0000003F);
        DDR3BPLLCTL0 |= (divider & 0x0000003F);
 /* Step 7: Programming OD[3:0] in the SECCTL register */            
    DDR3BPLLCTL0 &= OUTPUT_DIVIDE_MASK;  // clear the OD bit field
    DDR3BPLLCTL0 |= ~OUTPUT_DIVIDE_MASK & (OD_val - 1) << OUTPUT_DIVIDE_OFFSET;  // set the OD[3:0] bit field of PLLD to OD_val    

		 /* Set the Multipler values */
        DDR3BPLLCTL0 &= ~(0x0007FFC0);
        DDR3BPLLCTL0 |= ((multiplier << 6) & 0x0007FFC0 );
	   temp = ((multiplier + 1) >> 1) - 1;
        DDR3BPLLCTL0 &= ~(0xFF000000); 
        DDR3BPLLCTL0 |= ((temp << 24) & 0xFF000000);
        DDR3BPLLCTL1 &= ~(0x0000000F);
        DDR3BPLLCTL1 |= ((temp >> 8) & 0x0000000F);
	//In DDR3PLLCTL1, write PLLRST = 0 to bring PLL out of reset 
        DDR3BPLLCTL1 &= ~(0x00002000);
	// Put the PLL in PLL Mode  
		DDR3BPLLCTL0 &= ~(0x00800000); // ReSet the Bit 23
		GEL_TextOut( "DDR3 PLL Setup complete, DDR3B clock now running at 666 MHz.\n" );
//DDR3B PLL setup complete ---------------------------------------
	
/*------------------------- Start PHY Configuration -------------------------------*/

 //DDR3B_PGCR1 = 0x0280C487;
 
 //5.a	Program FRQSEL in the PLL Control Register (address offset 0x018).
 DDR3B_PLLCR = 0x5C000; //Set FRQSEL=11, for ctl_clk between 166-275MHz
 
 //5.b.	Program WLSTEP=1, IODDRM=1, and ZCKSEL in the PHY General Configuration Register 1 (address offset 0x00C). 
 DDR3B_PGCR1 |= (1 << 2); //WLSTEP = 1
 
 DDR3B_PGCR1 &= ~(IODDRM_MASK);
 DDR3B_PGCR1 |= (( 1 << 7) & IODDRM_MASK);
 
 
 DDR3B_PGCR1 &= ~(ZCKSEL_MASK);
 DDR3B_PGCR1 |= (( 1 << 23) & ZCKSEL_MASK);
 
    
 //5.c.	Program PHY Timing Parameters Register 0-4 (address offset 0x01C - 0x02C).

	DDR3B_PTR0 = 0x42C21590;
	
	DDR3B_PTR1 = 0xD05612C0;	
	
// Maintaining default values of Phy Timing Parameters Register 2 in PUB
	
	DDR3B_PTR3 = 0x0B4515C2;//0x18061A80; 

	DDR3B_PTR4 = 0x0A6E08B4;//0x0AAE7100;
	
//5.d.	Program PDQ, MPRDQ, and BYTEMASK in the DRAM Configuration Register (address offset 0x044). 
//		All other fields must be left at their default values.
 
  DDR3B_DCR &= ~(PDQ_MASK); //PDQ = 0

  DDR3B_DCR &= ~(MPRDQ_MASK); //MPRDQ = 0
  
  DDR3B_DCR &= ~(BYTEMASK_MASK);
  DDR3B_DCR |= (( 1 << 10) & BYTEMASK_MASK);
 
 
 DDR3B_DCR &= ~(NOSRA_MASK);
 DDR3B_DCR |= (( 1 << 27) & NOSRA_MASK);
 
 
 // DDR3B_DCR &= ~(UDIMM_MASK);
 // DDR3B_DCR |= (( 1 << 29) & UDIMM_MASK);
  
	
//5.e.	Program DRAM Timing Parameters Register 0-2 (address offset 0x048 - 0x050). 

	DDR3B_DTPR0 = 0x8558AA55;
	DDR3B_DTPR1 = 0x12857280;
	DDR3B_DTPR2 = 0x5002C200;

//5.f.	Program BL=0, CL, WR, and PD=1 in the Mode Register 0 (address offset 0x054). 
		//All other fields must be left at their default values.

DDR3B_MR0 = 0x00001A60;
	
	
//5.g.	Program DIC, RTT, and TDQS in the Mode Register 1 (address offset 0x058). 
		//All other fields must be left at their default values.

DDR3B_MR1 = 0x00000006;


//---------------------------------------------------------------------------------------------------------					

//5.h.	Program Mode Register 2 (address offset 0x05C).
	// Maintaining default values of Program Mode Register 2
	DDR3B_MR2 = 0x00000010;

//5.i.	Program DTMPR=1, DTEXD, DTEXG, RANKEN=1 or 3, and RFSHDT=7 in the Data Training Configuration Register (address offset 0x068). 
		//All other fields must be left at their default values.
		DDR3B_DTCR = 0x710035C7; //0x730035C7;
		
//5.j.	Program tREFPRD=(5*tREFI/ddr_clk_period) in the PHY General Configuration Register 2 (address offset 0x08C). 
		//All other fields must be left at their default values.
	
	DDR3B_PGCR2 = 0x00F065B8; //NOBUB = 0, FXDLAT = 0 	
//DDR3B_PGCR2 = 0x00F83D09; //NOBUB = 0, FXDLAT = 1 
	
//Set Impedence Register	
DDR3B_ZQ0CR1 = 0x0000005D; 
DDR3B_ZQ1CR1 = 0x0000005B;
DDR3B_ZQ2CR1 = 0x0000005B;
//DDR3B_ZQ3CR1 = 0x0000005D;
	
//6.	Re-trigger PHY initialization in DDR PHY through the VBUSP interface.
//6.a.	Program 0x00000033 to the PHY Initialization Register (address offset 0x004) to re-trigger PLL, ZCAL, and DCAL initialization.

	DDR3B_PIR = 0x00000033;
	
//6.b.	Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010).
     do { 
    read_val = DDR3B_PGSR0;
    } while ((read_val&0x00000001) != 0x00000001);

//---------------------------------------------------------------------------------------------------------					

	
  
// 7.	Trigger DDR3 initialization and leveling/training in DDR PHY through the VBUSP interface.
// a.	If using a 16-bit wide DDR interface, program DXEN=0 in the DATX8 2-7 General Configuration Registers (address offsets 0x240, 0x280, 0x2C0, 0x300, 0x340, and 0x380) to disable the leveling/training for the upper byte lanes.
// b.	If using a 32-bit wide DDR interface, program DXEN=0 in the DATX8 4-7 General Configuration Registers (address offsets 0x2C0, 0x300, 0x340, and 0x380) to disable the leveling/training for the upper byte lanes.
// c.	If ECC is not required, program DXEN=0 in the DATX8 8 General Configuration Register (address offset 0x3C0) to disable the leveling/training for the ECC byte lane.
// NOTE: Setup supports 64-bit by default,  ECC enable by default.
 
//7.d.	Program 0x0000XF81 to the PHY Initialization Register (address offset 0x004) to trigger DDR3 initialization and leveling/training sequences 
 	
	DDR3B_PIR = 0x0000FF81; //WLADJ - ON
	 //DDR3B_PIR = 0x00000781;  //WLADJ - OFF


//---------------------------------------------------------------------------------------------------------					
			
//7.e.	Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010).
	do {              
		read_val = DDR3B_PGSR0;
	   } while ((read_val&0x00000001) != 0x00000001);
	   

	/* End PHY Configuration */		
//---------------------------------------------------------------------------------------------------------					
/* START EMIF INITIALIZATION
  ++++++++++++++++++SDCFG Register Calculation+++++++++++++++++++
  | 31 - 29  | 28 |27 - 25 | 24   | 23 - 22| 21 - 17 |
  |SDRAM_TYPE|Rsvd|DDR_TERM| DDQS | DYN_ODT|  Rsvd   |
  |  0x011   |  0 | 0x011  | 0x1  |   0x00 |   0x0   |

  | 16-14 |13 - 12 |  11 - 8 |  7   |6 - 5 |  4  |  3  |  2  |  1 - 0  |
  |   CWL | NM     |   CL    | Rsvd |IBANK | Rsvd|EBANK| Rsvd|PAGE_SIZE|
  |  0x11 | 0x00   |  0x1110 |  0x0 | 0x11 | 0x0 |  0  |  0  |   0x10  |
  SDCFG = 0x0110 0011 0010 0010 0011 0011 1011 0010
  SDCFG = 0x6700486A;//0x63223332

  SDRAM_TYPE = 3
  DDR_TERM = 3 (RZQ/4 = 1; RZQ/6=3)
  DDQS = 1 
  DYN_ODT = 0 
  
  CWL = 3 (CWL5=0; CWL6=1; CWL7=2; CWL8=3)
  NM = 0 (64-bit=0, 32-bit=1, 16-bit=2)
  CL = 14 (CL5=2; CL6=4; CL7=6; CL8=8; CL9=10; CL10=12; CL11=14)
  IBANK = 3 (8bank)
  EBANK = 0 (0 - pad_cs_o_n[0] , 1 - pad_cs_o_n[1:0])
  PAGE_SIZE = 2 (1024page-size=2; 2048page-size=3)
*/
/* Start DDR3B EMIF Configuration */
//8.	Configure the EMIF through the VBUSM interface.
//8.a.	Program all EMIF MMR’s.
	DDR3B_SDCFG    = 0x62008C62	;//0x6600CE62=single rank,0x6600CE6A=dual rank

    DDR3B_SDTIM1   = 0x125C8044;
    DDR3B_SDTIM2   = 0x00001D29;
    DDR3B_SDTIM3   = 0x32CDFF43;
	DDR3B_SDTIM4   = 0x543F0ADF;

	DDR3B_ZQCFG    = 0xF0073200; 	
//8.b.	Program reg_initref_dis=0 in the SDRAM Refresh Control Register (address offset 0x10).
    DDR3B_SDRFC = 0x00001457;
      
	GEL_TextOut("DDR3B initialization complete \n");
	   /* End  DDR3B EMIF Configuration */
	   
}

/*----------------------------------------------------- DDR3B : DDR1600, 64bit--------------------------------------------------------------------------*/
ddr3B_64bit_DDR1600_setup()
{
unsigned int multiplier = 15;
	unsigned int divider = 0;
	int temp;
	unsigned int OD_val = 4;
    KICK0 = 0x83E70B13;
    KICK1 = 0x95A4F1E0;
	 
	
//1.	Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010).
	 do { 
    read_val = DDR3B_PGSR0;
    } while ((read_val&0x00000001) != 0x00000001);
	
//4.	Clocks are enabled and frequency is stable---------------------------------------
//DDR3B PLL setup	
   GEL_TextOut ( "DDR3 PLL Setup ... \n");
    //DDR3BPLLCTL0 = DDR3BPLLCTL0 & 0xFF7FFFFF;
	//	Set ENSAT = 1
		DDR3BPLLCTL1 |= 0x00000040;
	// Put the PLL in PLL Mode  
		DDR3BPLLCTL0 |= 0x00800000;
	// In PLL Controller, reset the PLL (bit 13 in DDR3BPLLCTL1 register) 
		DDR3BPLLCTL1 |= 0x00002000;
	// Program the necessary multipliers/dividers and BW adjustments            
     // Set the divider values 
		DDR3BPLLCTL0 &= ~(0x0000003F);
        DDR3BPLLCTL0 |= (divider & 0x0000003F);
 /* Step 7: Programming OD[3:0] in the SECCTL register */            
    DDR3BPLLCTL0 &= OUTPUT_DIVIDE_MASK;  // clear the OD bit field
    DDR3BPLLCTL0 |= ~OUTPUT_DIVIDE_MASK & (OD_val - 1) << OUTPUT_DIVIDE_OFFSET;  // set the OD[3:0] bit field of PLLD to OD_val    
	
	//DDR3BPLLCTL0 &= ~(0x00780000);
	   //DDR3BPLLCTL0 |= ((OD_val << 19)& 0x00780000);

		 /* Set the Multipler values */
        DDR3BPLLCTL0 &= ~(0x0007FFC0);
        DDR3BPLLCTL0 |= ((multiplier << 6) & 0x0007FFC0 );
	   temp = ((multiplier + 1) >> 1) - 1;
        DDR3BPLLCTL0 &= ~(0xFF000000); 
        DDR3BPLLCTL0 |= ((temp << 24) & 0xFF000000);
        DDR3BPLLCTL1 &= ~(0x0000000F);
        DDR3BPLLCTL1 |= ((temp >> 8) & 0x0000000F);
	//In DDR3PLLCTL1, write PLLRST = 0 to bring PLL out of reset 
        DDR3BPLLCTL1 &= ~(0x00002000);
	// Put the PLL in PLL Mode  
		DDR3BPLLCTL0 &= ~(0x00800000); // ReSet the Bit 23
		GEL_TextOut( "DDR3 PLL Setup complete, DDR3B clock now running at 800MHz.\n" );
//DDR3B PLL setup complete ---------------------------------------
	
/*------------------------- Start PHY Configuration -------------------------------*/

 //DDR3B_PGCR1 = 0x0280C487;
 
 //5.a	Program FRQSEL in the PLL Control Register (address offset 0x018).
 DDR3B_PLLCR = 0x1C000; //Set FRQSEL=11, for ctl_clk between 166-275MHz
 
 //5.b.	Program WLSTEP=1, IODDRM=1, and ZCKSEL in the PHY General Configuration Register 1 (address offset 0x00C). 
 DDR3B_PGCR1 |= (1 << 2); //WLSTEP = 1
 
 DDR3B_PGCR1 &= ~(IODDRM_MASK);
 DDR3B_PGCR1 |= (( 1 << 7) & IODDRM_MASK);
 
 
 DDR3B_PGCR1 &= ~(ZCKSEL_MASK);
 DDR3B_PGCR1 |= (( 1 << 23) & ZCKSEL_MASK);
 
    
 //5.c.	Program PHY Timing Parameters Register 0-4 (address offset 0x01C - 0x02C).

	DDR3B_PTR0 = 0x42C21590;
	
	DDR3B_PTR1 = 0xD05612C0;	
	
// Maintaining default values of Phy Timing Parameters Register 2 in PUB
	
	DDR3B_PTR3 = 0x0D861A80;//

	DDR3B_PTR4 = 0x0C827100;
	
//5.d.	Program PDQ, MPRDQ, and BYTEMASK in the DRAM Configuration Register (address offset 0x044). 
//		All other fields must be left at their default values.
 
  DDR3B_DCR &= ~(PDQ_MASK); //PDQ = 0

  DDR3B_DCR &= ~(MPRDQ_MASK); //MPRDQ = 0
  
  DDR3B_DCR &= ~(BYTEMASK_MASK);
  DDR3B_DCR |= (( 1 << 10) & BYTEMASK_MASK);
 
 
  DDR3B_DCR &= ~(NOSRA_MASK);
  DDR3B_DCR |= (( 1 << 27) & NOSRA_MASK);
 
 
  //DDR3B_DCR &= ~(UDIMM_MASK);
  //DDR3B_DCR |= (( 1 << 29) & UDIMM_MASK);
  
	
//5.e.	Program DRAM Timing Parameters Register 0-2 (address offset 0x048 - 0x050). 

	DDR3B_DTPR0 = 0xA19DBB66;
	DDR3B_DTPR1 = 0x12868300;
	DDR3B_DTPR2 = 0x50035200;

//5.f.	Program BL=0, CL, WR, and PD=1 in the Mode Register 0 (address offset 0x054). 
		//All other fields must be left at their default values.

DDR3B_MR0 = 0x00001C70; //-CL - 11, CWL -8
	
	
//5.g.	Program DIC, RTT, and TDQS in the Mode Register 1 (address offset 0x058). 
		//All other fields must be left at their default values.

DDR3B_MR1 = 0x00000006;


//---------------------------------------------------------------------------------------------------------					

//5.h.	Program Mode Register 2 (address offset 0x05C).
	// Maintaining default values of Program Mode Register 2
	//	DDR3B_MR2 = 0x00000018;
	
	DDR3B_MR2 = 0x00000018;

//5.i.	Program DTMPR=1, DTEXD, DTEXG, RANKEN=1 or 3, and RFSHDT=7 in the Data Training Configuration Register (address offset 0x068). 
		//All other fields must be left at their default values.
		DDR3B_DTCR = 0x710035C7; //0x730035C7;
		
//5.j.	Program tREFPRD=(5*tREFI/ddr_clk_period) in the PHY General Configuration Register 2 (address offset 0x08C). 
		//All other fields must be left at their default values.
	
	DDR3B_PGCR2 = 0x00F07A12; //NOBUB = 0, FXDLAT = 0 	
//DDR3B_PGCR2 = 0x00F83D09; //NOBUB = 0, FXDLAT = 1 
	
//Set Impedence Register	
DDR3B_ZQ0CR1 = 0x0000005D; 
DDR3B_ZQ1CR1 = 0x0000005B;
DDR3B_ZQ2CR1 = 0x0000005B;
//DDR3B_ZQ3CR1 = 0x0000005D;

//DDR3B_DATX8_8  &= ~(ECC_MASK);

//6.	Re-trigger PHY initialization in DDR PHY through the VBUSP interface.
//6.a.	Program 0x00000033 to the PHY Initialization Register (address offset 0x004) to re-trigger PLL, ZCAL, and DCAL initialization.

	DDR3B_PIR = 0x00000033;
	
//6.b.	Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010).
     do { 
    read_val = DDR3B_PGSR0;
    } while ((read_val&0x00000001) != 0x00000001);

//---------------------------------------------------------------------------------------------------------					

	
  
// 7.	Trigger DDR3 initialization and leveling/training in DDR PHY through the VBUSP interface.
// a.	If using a 16-bit wide DDR interface, program DXEN=0 in the DATX8 2-7 General Configuration Registers (address offsets 0x240, 0x280, 0x2C0, 0x300, 0x340, and 0x380) to disable the leveling/training for the upper byte lanes.
// b.	If using a 32-bit wide DDR interface, program DXEN=0 in the DATX8 4-7 General Configuration Registers (address offsets 0x2C0, 0x300, 0x340, and 0x380) to disable the leveling/training for the upper byte lanes.
// c.	If ECC is not required, program DXEN=0 in the DATX8 8 General Configuration Register (address offset 0x3C0) to disable the leveling/training for the ECC byte lane.
// NOTE: Setup supports 64-bit by default,  ECC enable by default.
 
//7.d.	Program 0x0000XF81 to the PHY Initialization Register (address offset 0x004) to trigger DDR3 initialization and leveling/training sequences 
 	
	DDR3B_PIR = 0x0000FF81; //WLADJ - ON
	 //DDR3B_PIR = 0x00000781;  //WLADJ - OFF


//---------------------------------------------------------------------------------------------------------					
			
//7.e.	Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010).
	do {              
		read_val = DDR3B_PGSR0;
	   } while ((read_val&0x00000001) != 0x00000001);
	   

	/* End PHY Configuration */		
//---------------------------------------------------------------------------------------------------------					
/* START EMIF INITIALIZATION
  ++++++++++++++++++SDCFG Register Calculation+++++++++++++++++++
  | 31 - 29  | 28 |27 - 25 | 24   | 23 - 22| 21 - 17 |
  |SDRAM_TYPE|Rsvd|DDR_TERM| DDQS | DYN_ODT|  Rsvd   |
  |  0x011   |  0 | 0x011  | 0x1  |   0x00 |   0x0   |

  | 16-14 |13 - 12 |  11 - 8 |  7   |6 - 5 |  4  |  3  |  2  |  1 - 0  |
  |   CWL | NM     |   CL    | Rsvd |IBANK | Rsvd|EBANK| Rsvd|PAGE_SIZE|
  |  0x11 | 0x00   |  0x1110 |  0x0 | 0x11 | 0x0 |  0  |  0  |   0x10  |
  SDCFG = 0x0110 0011 0010 0010 0011 0011 1011 0010
  SDCFG = 0x6700486A;//0x63223332

  SDRAM_TYPE = 3
  DDR_TERM = 3 (RZQ/4 = 1; RZQ/6=3)
  DDQS = 1 
  DYN_ODT = 0 
  
  CWL = 3 (CWL5=0; CWL6=1; CWL7=2; CWL8=3)
  NM = 0 (64-bit=0, 32-bit=1, 16-bit=2)
  CL = 14 (CL5=2; CL6=4; CL7=6; CL8=8; CL9=10; CL10=12; CL11=14)
  IBANK = 3 (8bank)
  EBANK = 0 (0 - pad_cs_o_n[0] , 1 - pad_cs_o_n[1:0])
  PAGE_SIZE = 2 (1024page-size=2; 2048page-size=3)
*/
/* Start DDR3B EMIF Configuration */
//8.	Configure the EMIF through the VBUSM interface.
//8.a.	Program all EMIF MMR’s.
	DDR3B_SDCFG    = 0x6200CE62	;//0x66004862=single rank, 0x6600486A=dual rank   CL- 11

    DDR3B_SDTIM1   = 0x16709C55;
    DDR3B_SDTIM2   = 0x00001D4A;
    DDR3B_SDTIM3   = 0x435DFF54;
	DDR3B_SDTIM4   = 0x553F0CFF;

	DDR3B_ZQCFG    = 0xF0073200; 	
//8.b.	Program reg_initref_dis=0 in the SDRAM Refresh Control Register (address offset 0x10).
    DDR3B_SDRFC = 0x00001869;
      
	GEL_TextOut("DDR3B initialization complete \n");
	   /* End  DDR3B EMIF Configuration */
	   
}




/*--------------------------------------------------------------*/
/* TCI66x MENU                                              */
/*--------------------------------------------------------------*/

menuitem "TCI66x Functions";

/****************************************************************************
 *
 * NAME
 *      Global_Default_Setup
 *
 * PURPOSE:
 *      Setup almost everything ready for a new debug session:
 *      DSP modules and EVM board modules.
 *
 * USAGE
 *      This routine can be called as:
 *
 *      Global_Default_Setup()
 *
 * RETURN VALUE
 *      NONE
 *
 * REFERENCE
 *
 ****************************************************************************/
hotmenu Global_Default_Setup()
{
    GEL_TextOut( "Global Default Setup...\n" );
    Global_Default_Setup_Silent();
    GEL_TextOut( "Global Default Setup... Done.\n" );
}

hotmenu Reset()
{
    GEL_Reset();
}

hotmenu InitXMC()
{
    xmc_setup();
}

hotmenu CORE_PLL_INIT_122_88MHZ_to_614_4MHz()
{
    Set_Pll1(1); // call Set_Pll1 with index = 1 -> 122.88 MHz to 614.4 MHz operation 
}

hotmenu CORE_PLL_INIT_122_88MHZ_to_737_28MHz()
{
    Set_Pll1(2); // call Set_Pll1 with index = 2 -> 122.88 MHz to 737.28 MHz operation 
}

hotmenu CORE_PLL_INIT_122_88MHZ_to_983_04MHz()
{
    Set_Pll1(3); // call Set_Pll1 with index = 3 -> 122.88 MHz to 983.04 MHz operation 
}

hotmenu CORE_PLL_INIT_122_88MHZ_to_1_2GHz()
{
    Set_Pll1(4); // call Set_Pll1 with index = 4 -> 122.88 MHz  to 1.2 GHz operation 
}


hotmenu CORE_PLL_INIT_122_88MHZ_to_1_3Gz()
{
    Set_Pll1(5); // call Set_Pll1 with index = 4 -> 122.88 MHz  to 1.2 GHz operation 
}

hotmenu TETRIS_POWERUP_AND_PLL_INIT_100MHZ_to_1000MHz()
{
    Set_Tetris_Pll(1); // 100 MHz to 1.0 GHz operation 
}

hotmenu TETRIS_POWERUP_AND_PLL_INIT_100MHZ_to_1400MHz()
{
    Set_Tetris_Pll(2); // 100 MHz to 1.4 GHz operation 
}

hotmenu TETRIS_POWERUP_AND_PLL_INIT_175MHZ_to_1400MHz()
{
    Set_Tetris_Pll(3); // 175 MHz to 1.4 GHz operation 
}


hotmenu PA_PLL_COnfig()
{
      PaPllConfig();
}

hotmenu InitDDR3A_32bit_DDR800()
{
      ddr3A_32bit_DDR800_setup();
}   

hotmenu InitDDR3A_32bit_DDR1066()
{
      ddr3A_32bit_DDR1066_setup();
} 

hotmenu InitDDR3A_32bit_DDR1333()
{
      ddr3A_32bit_DDR1333_setup();
} 


hotmenu InitDDR3B_64bit_DDR800()
{
      ddr3B_64bit_DDR800_setup();
}   


hotmenu InitDDR3B_64bit_DDR1066()
{
      ddr3B_64bit_DDR1066_setup();
} 

hotmenu InitDDR3B_64bit_DDR1333()
{
      ddr3B_64bit_DDR1333_setup();
} 

hotmenu InitDDR3B_64bit_DDR1600()
{
      ddr3B_64bit_DDR1600_setup();
} 


///* Function to enable CORE PLL observation clock for PLL output *///
hotmenu ENABLE_CORE_PLL_OBSCLK()
{
    /* Unlock Chip Level Registers */
    KICK0 = KICK0_UNLOCK;
    KICK1 = KICK1_UNLOCK;

    /* set bit 1 to enable power to the CORE PLL observation clock, clear bit 0 to view the CORE PLL observation (output) clock */
    OBSCLKCTL |= (1 << 1);  /* set bit 1 to enable power to the observation clock */
    OBSCLKCTL &= ~(1 << 0); /* clear bit 0 to view the CORE PLL clock */ 

    /* Lock Chip Level Registers */
    KICK0 = 0x00000000;
    KICK1 = 0x00000000;

    GEL_TextOut("CORE PLL observation clock enabled and configured to show CORE PLL output\n");
}

/* Function to enable DDR PLL observation clock for PLL output */
hotmenu ENABLE_DDR_PLL_OBSCLK ()
{
    /* Unlock Chip Level Registers */
    KICK0 = KICK0_UNLOCK;
    KICK1 = KICK1_UNLOCK;

    /* set bit 1 to enable power to the CORE PLL observation clock, clear bit 0 to view the CORE PLL observation (output) clock */
    OBSCLKCTL |= (1 << 3);  /* set bit 3 to enable power to the observation clock */
    OBSCLKCTL |= (1 << 2);  /* set bit 2 to view the DDR PLL clock */ 

    /* Lock Chip Level Registers */
    //KICK0 = 0x00000000;
   // KICK1 = 0x00000000;

    GEL_TextOut("DDR PLL observation clock enabled and configured to show DDR PLL output\n");
}

hotmenu ENABLE_ARM_PLL_OBSCLK ()
{
    /* Unlock Chip Level Registers */
    KICK0 = KICK0_UNLOCK;
    KICK1 = KICK1_UNLOCK;

    /* set bit 1 to enable power to the CORE PLL observation clock, clear bit 0 to view the CORE PLL observation (output) clock */
    //OBSCLKCTL |= (1 << 3);  /* set bit 3 to enable power to the observation clock */
    OBSCLKCTL |= (1 << 6);  /* set bit 2 to view the DDR PLL clock */ 

    /* Lock Chip Level Registers */
    KICK0 = 0x00000000;
    KICK1 = 0x00000000;

    GEL_TextOut("DDR PLL observation clock enabled and configured to show DDR PLL output\n");
}

hotmenu ENABLE_PA_PLL_OBSCLK ()
{
    /* Unlock Chip Level Registers */
    KICK0 = KICK0_UNLOCK;
    KICK1 = KICK1_UNLOCK;

    /* set bit 1 to enable power to the CORE PLL observation clock, clear bit 0 to view the CORE PLL observation (output) clock */
    OBSCLKCTL |= (1 << 4);  /* set bit 3 to enable power to the observation clock */
    OBSCLKCTL |= (1 << 5);  /* set bit 2 to view the DDR PLL clock */ 

    /* Lock Chip Level Registers */
    KICK0 = 0x00000000;
    KICK1 = 0x00000000;

    GEL_TextOut("DDR PLL observation clock enabled and configured to show DDR PLL output\n");
}

hotmenu ddr3A_write_read_test()
{
//int data_set[4];
    //= {0xAAAAAAAA, 0x55555555, 0xFFFFFFFF, 0x00000000};
    unsigned int write_data = 0xAAAAAAAA;
    unsigned int read_data = 0x0;
    unsigned int errors = 0;
    int dw;
    unsigned int i, mem_start, mem_size, mem_location;
    mem_start = DDR3A_BASE_ADDRESS + (DNUM * 0x01000000);
    mem_size = 0x100;
    for(dw=0;dw<4;dw++)
    {
        if (dw == 0) write_data = 0xAAAAAAAA;
        if (dw == 1) write_data = 0x55555555;
        if (dw == 2) write_data = 0xFFFFFFFF;
        if (dw == 3) write_data = 0x00000000;
        mem_location = mem_start;
        GEL_TextOut( "Memory Test Write Core: %d, Mem Start: 0x%x, Mem Size: 0x%x, value: 0x%x ...\n",,2,,,DNUM,mem_start,mem_size,write_data);
        for(i=0;i<mem_size;i++)
        {
            *( unsigned int* )(mem_location) = write_data;
            mem_location += 4;
        }
        mem_location = mem_start;
        GEL_TextOut( "Memory Test Read Core: %d, Mem Start: 0x%x, Mem Size: 0x%x ...\n",,2,,,DNUM,mem_start,mem_size);
        for (i=0;i<mem_size;i++)
        {
            read_data = *( unsigned int* )(mem_location);
            if (read_data != write_data)
            {
                GEL_TextOut("DDR3 Data Error: DSP Core: %d, Mem Addr: 0x%x, read: 0x%x, expected: 0x%x \n",,2,,,DNUM,(DDR3_BASE_ADDRESS + (i * 4)),read_data,write_data);
                errors++;
            }
            mem_location += 4;
        }
        if (errors == 0)
        {
            GEL_TextOut( "Memory Test Done, no errors found.\n" );
        }
        else
        {
            GEL_TextOut("Memory Test Done, %d errors were encounterd. \n",,2,,,errors);
        }
    }
    GEL_TextOut( "All Memory Test Completed on core: %d with %d errors.\n",,2,,,DNUM,errors);

}


hotmenu ddr3B_write_read_test()
{
//int data_set[4];
    //= {0xAAAAAAAA, 0x55555555, 0xFFFFFFFF, 0x00000000};
    unsigned int write_data = 0xAAAAAAAA;
    unsigned int read_data = 0x0;
    unsigned int errors = 0;
    int dw;
    unsigned int i, mem_start, mem_size, mem_location;
    mem_start = DDR3B_BASE_ADDRESS + (DNUM * 0x01000000);
    mem_size = 0x100;
    for(dw=0;dw<4;dw++)
    {
        if (dw == 0) write_data = 0xAAAAAAAA;
        if (dw == 1) write_data = 0x55555555;
        if (dw == 2) write_data = 0xFFFFFFFF;
        if (dw == 3) write_data = 0x00000000;
        mem_location = mem_start;
        GEL_TextOut( "Memory Test Write Core: %d, Mem Start: 0x%x, Mem Size: 0x%x, value: 0x%x ...\n",,2,,,DNUM,mem_start,mem_size,write_data);
        for(i=0;i<mem_size;i++)
        {
            *( unsigned int* )(mem_location) = write_data;
            mem_location += 4;
        }
        mem_location = mem_start;
        GEL_TextOut( "Memory Test Read Core: %d, Mem Start: 0x%x, Mem Size: 0x%x ...\n",,2,,,DNUM,mem_start,mem_size);
        for (i=0;i<mem_size;i++)
        {
            read_data = *( unsigned int* )(mem_location);
            if (read_data != write_data)
            {
                GEL_TextOut("DDR3 Data Error: DSP Core: %d, Mem Addr: 0x%x, read: 0x%x, expected: 0x%x \n",,2,,,DNUM,(DDR3_BASE_ADDRESS + (i * 4)),read_data,write_data);
                errors++;
            }
            mem_location += 4;
        }
        if (errors == 0)
        {
            GEL_TextOut( "Memory Test Done, no errors found.\n" );
        }
        else
        {
            GEL_TextOut("Memory Test Done, %d errors were encounterd. \n",,2,,,errors);
        }
    }
    GEL_TextOut( "All Memory Test Completed on core: %d with %d errors.\n",,2,,,DNUM,errors);
}

menuitem "DSP CLOCK Estimation";

#define TIMER_TSC             (1)    // The timer used for polling TSCH/TSCL  
#define TIMER_TSC_POLL_PERIOD (10)   // Every 10 seconds
unsigned int gPollPeriod = TIMER_TISC_POLL_PERIOD;
unsigned int gTSCL = 0;
unsigned int gTSCH = 0;              // Global var for holding previous read of TSCL/H
unsigned int gNumberPoll=0;          // Number of pulling */
unsigned int gLoopCount=0;



hotmenu dspEnableTsc()
{
  //GEL_TextOut( "dspEnableTsc - write a value to TSCL to enable it\n" );
  if( GEL_IsHalted() ) {
    TSCL = 0;  // A write to TSCL will enable TSC (timestamp counter)
    GEL_Run();
  } else {
    GEL_Halt();
    TSCL = 0;
    GEL_Run();
  }
}
  
  
hotmenu dspDumpTsc()
{
  unsigned int tscl, tsch;
  tscl = TSCL;  /* note: need to read TSCL first */
  tsch = TSCH;
  GEL_TextOut( "dspEnableTsc - TSCH=%x, TSCL=%x\n",,,,, tscl, tsch );
}
  
  
dspPollTsc()
{
  unsigned int tscl, tsch;
  unsigned long long tsc1, tsc2;
  
  if( gLoopCount <= gNumberPoll) { 
    //GEL_EnableRealtime();
    GEL_Halt();
    tscl = TSCL;            /* The read time can be considered as variations */
    tsch = TSCH;            /* The read won't cause variation */
    //GEL_DisableRealtime();
    GEL_Run();
    tsc2  = (((unsigned long long) tsch)<<32) +  tscl;
    tsc1  = (((unsigned long long)gTSCH)<<32) + gTSCL;
    gTSCL = tscl;
    gTSCH = tsch;
  
    //tsc1 = (tsc2-tsc1)/TIMER_TSC_POLL_PERIOD;
    tsc1 = (tsc2-tsc1)/gPollPeriod;
    
    GEL_TextOut( "dspPollTsc - [TSCH,TSCL] = [%x, %x], freq=%dhz, i=%d\n",,,,,
          gTSCH, gTSCL, (tsc1), gLoopCount);
  }
  
  if( gLoopCount>=gNumberPoll ) {
    dspCancelTscTimer();
  } else {  
    gLoopCount++;
  }
}


//
// To cancel the Timer - TIMER_TSC, after using it. Otherwise, it will continue running.
//
hotmenu dspCancelTscTimer()
{
  GEL_TextOut( "dspCancelTscTimer\n");
  GEL_CancelTimer( TIMER_TSC );
}


//
// To poll the DSP clock.
//
dialog dspPollDSPClockFreq(
	pollPeriod   "Polling period (sec) - the longer, the more accurate!",
	numberOfPoll "Number of Polls" )
{
  gPollPeriod = pollPeriod;
  
  GEL_TextOut( "dspPollDSPClockFreq with - pollPeriod=%dsec, numberOfPoll=%d\n"
         ,,,,, gPollPeriod, numberOfPoll);
         
  gNumberPoll = numberOfPoll-1;
  gLoopCount  = 0;
  dspEnableTsc();
  
  // Get the initial value of TSC
  //GEL_EnableRealtime();
  GEL_Halt();
  gTSCL = TSCL;            /* The read time can be considered as variations */
  gTSCH = TSCH;            /* The read won't cause variation */
  //GEL_DisableRealtime();
  GEL_Run();
 
  GEL_SetTimer( gPollPeriod*1000, TIMER_TSC, "dspPollTsc()");
  
}