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authorMing Wei2019-03-25 11:28:27 -0500
committerMing Wei2019-03-25 11:28:27 -0500
commit365c74ca8e1154a6ef28e7c6ef2cca7220a041b6 (patch)
treed1263f60ef218146f5a92651f1aeb484f508cc5c
parentf57cf90ba4c7dff6a016f60f2e343d777f20e06e (diff)
downloadosal-REL.PDK.J7.00.08.00.10.tar.gz
osal-REL.PDK.J7.00.08.00.10.tar.xz
osal-REL.PDK.J7.00.08.00.10.zip
Signed-off-by: Ming Wei <mwei@ti.com>
-rw-r--r--src/nonos/timer/v1/TimerP_nonos.c4
-rw-r--r--test/src/OSAL_board.h2
-rw-r--r--test/src/main_osal_test.c65
3 files changed, 61 insertions, 10 deletions
diff --git a/src/nonos/timer/v1/TimerP_nonos.c b/src/nonos/timer/v1/TimerP_nonos.c
index ee29668..3efd5aa 100644
--- a/src/nonos/timer/v1/TimerP_nonos.c
+++ b/src/nonos/timer/v1/TimerP_nonos.c
@@ -840,9 +840,6 @@ TimerP_Status TimerP_setPeriodMicroSecs(TimerP_Handle handle, uint32_t microsecs
840 } 840 }
841} 841}
842 842
843#if defined (SOC_J721E)
844/* Below API is not supported for SOC_J721E SoCs for bare metal */
845#else
846/* Get time in micro seconds */ 843/* Get time in micro seconds */
847uint64_t TimerP_getTimeInUsecs(void) 844uint64_t TimerP_getTimeInUsecs(void)
848{ 845{
@@ -861,5 +858,4 @@ uint64_t TimerP_getTimeInUsecs(void)
861 858
862 return ((cur_ts*1000u)/freq); 859 return ((cur_ts*1000u)/freq);
863} 860}
864#endif
865/* This file implements the DM timer osal functions on AM devices */ 861/* This file implements the DM timer osal functions on AM devices */
diff --git a/test/src/OSAL_board.h b/test/src/OSAL_board.h
index 4c50bdc..5b37d75 100644
--- a/test/src/OSAL_board.h
+++ b/test/src/OSAL_board.h
@@ -52,7 +52,7 @@ extern "C" {
52#undef OSAL_TEST_CPU_FREQ_KHZ 52#undef OSAL_TEST_CPU_FREQ_KHZ
53 53
54/* AM65XX Core CPU frequency */ 54/* AM65XX Core CPU frequency */
55#if defined (SOC_AM65XX) 55#if defined (SOC_AM65XX) || defined (SOC_J721E)
56#if defined (BUILD_MCU1_0) || defined(BUILD_MCU1_1) 56#if defined (BUILD_MCU1_0) || defined(BUILD_MCU1_1)
57 #define OSAL_TEST_CPU_FREQ_KHZ (400000) 57 #define OSAL_TEST_CPU_FREQ_KHZ (400000)
58#else 58#else
diff --git a/test/src/main_osal_test.c b/test/src/main_osal_test.c
index f681b58..4580dd3 100644
--- a/test/src/main_osal_test.c
+++ b/test/src/main_osal_test.c
@@ -88,7 +88,7 @@ void ErrorHandler(Error_Block *eb)
88 88
89 89
90#undef ENABLE_GET_TIME_TEST 90#undef ENABLE_GET_TIME_TEST
91#if defined(SOC_AM65XX) || defined(SOC_AM572x) || defined(SOC_K2G) || defined(SOC_AM335x) || defined(SOC_AM437x) 91#if defined(SOC_AM65XX) || defined(SOC_J721E) || defined(SOC_AM572x) || defined(SOC_K2G) || defined(SOC_AM335x) || defined(SOC_AM437x)
92#define ENABLE_GET_TIME_TEST 1 92#define ENABLE_GET_TIME_TEST 1
93#endif 93#endif
94 94
@@ -130,7 +130,7 @@ void Board_initOSAL(void)
130 */ 130 */
131volatile uint64_t gTestlocalTimeout = 0x300000U; 131volatile uint64_t gTestlocalTimeout = 0x300000U;
132 132
133#if defined (SOC_AM65XX) || defined (SOC_J721E) 133#if defined (SOC_AM65XX) || (defined(SOC_J721E)&&(!defined(BUILD_C66X_1))&&(!defined(BUILD_C66X_2))&&(!defined(BUILD_C7X_1)))
134#define INT_NUM_IRQ 32 134#define INT_NUM_IRQ 32
135#define LOOP_CNT 100 135#define LOOP_CNT 100
136volatile uint64_t gFlagIRQ = 0; 136volatile uint64_t gFlagIRQ = 0;
@@ -208,7 +208,7 @@ bool OSAL_core_hwi_test()
208 208
209bool OSAL_hwi_test() 209bool OSAL_hwi_test()
210{ 210{
211#if defined (SOC_AM65XX) || defined (SOC_J721E) 211#if defined (SOC_AM65XX) || (defined(SOC_J721E)&&(!defined(BUILD_C66X_1))&&(!defined(BUILD_C66X_2))&&(!defined(BUILD_C7X_1)))
212 OSAL_core_hwi_test(); 212 OSAL_core_hwi_test();
213#endif 213#endif
214 return true; 214 return true;
@@ -392,7 +392,11 @@ bool OSAL_timer_test()
392 TimerP_Status timerStatus; 392 TimerP_Status timerStatus;
393 Osal_HwAttrs hwAttrs; 393 Osal_HwAttrs hwAttrs;
394 394
395#ifdef BARE_METAL
396 int32_t id = OSAL_TEST_TIMER_ID;
397#else
395 int32_t id = TimerP_ANY; 398 int32_t id = TimerP_ANY;
399#endif
396 400
397#if defined(SOC_AM437x) 401#if defined(SOC_AM437x)
398 /* We can't use Timer_ANY for Sys BIOS as it allocates Timer0 which is 402 /* We can't use Timer_ANY for Sys BIOS as it allocates Timer0 which is
@@ -929,7 +933,7 @@ bool OSAL_semaphore_test()
929 933
930 934
931#ifndef BARE_METAL 935#ifndef BARE_METAL
932#if defined(SOC_AM65XX) || defined (SOC_J721E) 936#if (defined(SOC_AM65XX)||defined(SOC_J721E)) && defined (__aarch64__)
933#include <ti/sysbios/family/arm/v8a/Mmu.h> 937#include <ti/sysbios/family/arm/v8a/Mmu.h>
934 938
935volatile int emuwait_mmu=1; 939volatile int emuwait_mmu=1;
@@ -955,13 +959,35 @@ void InitMmu()
955 { 959 {
956 goto mmu_exit; 960 goto mmu_exit;
957 } 961 }
962 mapIdx++;
963 retVal = Mmu_map(0x00A80000, 0x00A80000, 0x000080000, &attrs); /* GTC registers */
964 if(retVal == FALSE) {
965 goto mmu_exit;
966 }
958 967
968#if defined(SOC_J721E)
969 mapIdx++;
970 retVal = Mmu_map(0x01800000, 0x01800000, 0x00200000, &attrs); /* gicv3 */
971 if (retVal == FALSE)
972 {
973 goto mmu_exit;
974 }
975
976 /* SCICLIENT UDMA */
977 mapIdx++;
978 retVal = Mmu_map(0x20000000ul, 0x20000000ul, 0x10000000ul, &attrs);
979 if (retVal == FALSE)
980 {
981 goto mmu_exit;
982 }
983#else
959 mapIdx++; 984 mapIdx++;
960 retVal = Mmu_map(0x01800000, 0x01800000, 0x00100000, &attrs); /* gicv3 */ 985 retVal = Mmu_map(0x01800000, 0x01800000, 0x00100000, &attrs); /* gicv3 */
961 if (retVal == FALSE) 986 if (retVal == FALSE)
962 { 987 {
963 goto mmu_exit; 988 goto mmu_exit;
964 } 989 }
990#endif
965 991
966 mapIdx++; 992 mapIdx++;
967 retVal = Mmu_map(0x02400000, 0x02400000, 0x000c0000, &attrs); /* dmtimer */ 993 retVal = Mmu_map(0x02400000, 0x02400000, 0x000c0000, &attrs); /* dmtimer */
@@ -1034,7 +1060,7 @@ void InitMmu()
1034 } 1060 }
1035 1061
1036 mapIdx++; 1062 mapIdx++;
1037 retVal = Mmu_map(0x30000000ul, 0x30000000ul, 0x0F000000ul, &attrs); /* ctrcontrol0 */ 1063 retVal = Mmu_map(0x30000000ul, 0x30000000ul, 0x10000000ul, &attrs); /* ctrcontrol0 */
1038 if (retVal == FALSE) 1064 if (retVal == FALSE)
1039 { 1065 {
1040 goto mmu_exit; 1066 goto mmu_exit;
@@ -1050,6 +1076,35 @@ void InitMmu()
1050 goto mmu_exit; 1076 goto mmu_exit;
1051 } 1077 }
1052 1078
1079 mapIdx++;
1080 retVal = Mmu_map(0x40f90000, 0x40f90000, 0x00001000, &attrs); /* RAT CFG */
1081 if(retVal == FALSE)
1082 {
1083 goto mmu_exit;
1084 }
1085
1086 mapIdx++;
1087 retVal = Mmu_map(0x47000000, 0x47000000, 0x00100000, &attrs); /* FSS0 cfg */
1088 if(retVal == FALSE)
1089 {
1090 goto mmu_exit;
1091 }
1092
1093 mapIdx++;
1094 retVal = Mmu_map(0x400000000, 0x400000000, 0x400000000, &attrs); /* FSS0 data */
1095 if(retVal == FALSE)
1096 {
1097 goto mmu_exit;
1098 }
1099
1100 attrs.attrIndx = 7;
1101 mapIdx++;
1102 retVal = Mmu_map(0x80000000, 0x80000000, 0x03000000, &attrs); /* ddr */
1103 if (retVal == FALSE)
1104 {
1105 goto mmu_exit;
1106 }
1107
1053 attrs.attrIndx = Mmu_AttrIndx_MAIR7; 1108 attrs.attrIndx = Mmu_AttrIndx_MAIR7;
1054 mapIdx++; 1109 mapIdx++;
1055 retVal = Mmu_map(0x70000000, 0x70000000, 0x04000000, &attrs); /* msmc */ 1110 retVal = Mmu_map(0x70000000, 0x70000000, 0x04000000, &attrs); /* msmc */