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authorAravind Batni2019-01-09 17:12:33 -0600
committerAravind Batni2019-02-24 13:28:28 -0600
commit9af2a40529e5d4d6c3f5c6915d0640eb9c6477c6 (patch)
tree2de07d0b73283528c3fd1e3de0c9e19d7dc23708
parent446907fbb18f48d6d5d7869b698ea226e72639a1 (diff)
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PRSDK-5246: support SMP mode for application so that appropriate cache includes are done from Sys Bios
Signed-off-by: Aravind Batni <aravindbr@ti.com>
-rw-r--r--package.xs1
-rw-r--r--src/tirtos/CacheP_tirtos.c20
2 files changed, 1 insertions, 20 deletions
diff --git a/package.xs b/package.xs
index 9a3ca1c..09c57a6 100644
--- a/package.xs
+++ b/package.xs
@@ -128,6 +128,7 @@ function getLibs(prog)
128 128
129function init() { 129function init() {
130 xdc.loadPackage("ti.csl"); 130 xdc.loadPackage("ti.csl");
131 xdc.loadPackage("ti.sysbios");
131} 132}
132 133
133/* 134/*
diff --git a/src/tirtos/CacheP_tirtos.c b/src/tirtos/CacheP_tirtos.c
index 26a1c87..5282386 100644
--- a/src/tirtos/CacheP_tirtos.c
+++ b/src/tirtos/CacheP_tirtos.c
@@ -35,27 +35,7 @@
35 35
36#include <ti/osal/CacheP.h> 36#include <ti/osal/CacheP.h>
37#include <ti/sysbios/BIOS.h> 37#include <ti/sysbios/BIOS.h>
38
39#if defined (SOC_AM335x)
40#include <ti/sysbios/family/arm/a8/Cache.h>
41#elif defined (SOC_AM437x)
42#include <ti/sysbios/family/arm/a9/Cache.h>
43#elif defined (__ARM_ARCH_7A__)
44#include <ti/sysbios/family/arm/a15/Cache.h>
45#elif defined (__TI_ARM_V7M4__)
46#include <ti/sysbios/hal/unicache/Cache.h>
47#elif defined (__TI_ARM_V7R4__)
48#include <ti/sysbios/family/arm/v7r/Cache.h>
49#elif defined (__TI_ARM_V5__)
50#include <ti/sysbios/family/arm/arm9/Cache.h>
51#elif defined (_TMS320C6X) && !(defined (SOC_OMAPL137) || defined (SOC_OMAPL138))
52#include <ti/sysbios/family/c66/Cache.h>
53#elif defined(__aarch64__)
54#include <ti/sysbios/family/arm/v8a/Cache.h>
55#else
56#include <ti/sysbios/hal/Cache.h> 38#include <ti/sysbios/hal/Cache.h>
57#endif
58
59 39
60void CacheP_wb(const void * addr, int32_t size) 40void CacheP_wb(const void * addr, int32_t size)
61{ 41{