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author | Ming Wei | 2019-07-02 14:38:23 -0500 |
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committer | Sivaraj R | 2019-07-07 19:55:14 -0500 |
commit | 056c290aa925c80358343a3e822f19452bb3d5cd (patch) | |
tree | cd6acfa79fcb9827535f78c4e95e6e2111312f14 | |
parent | f72d0cebeaa3e3e7ee7c448bb52cc2ef7a413ebb (diff) | |
download | osal-REL.PDK.J7.00.09.00.06.tar.gz osal-REL.PDK.J7.00.09.00.06.tar.xz osal-REL.PDK.J7.00.09.00.06.zip |
add calling Osal_appC7xPreInit()REL.PDK.J7.00.09.00.06
Signed-off-by: Ming Wei <mwei@ti.com>
-rwxr-xr-x | osal_component.mk | 2 | ||||
-rwxr-xr-x | test/src/main_osal_test.c | 40 |
2 files changed, 37 insertions, 5 deletions
diff --git a/osal_component.mk b/osal_component.mk index bc6889d..7e0e024 100755 --- a/osal_component.mk +++ b/osal_component.mk | |||
@@ -330,7 +330,7 @@ ifeq ($(SOC),$(filter $(SOC), am65xx)) | |||
330 | endif | 330 | endif |
331 | 331 | ||
332 | ifeq ($(SOC),$(filter $(SOC), j721e)) | 332 | ifeq ($(SOC),$(filter $(SOC), j721e)) |
333 | OSAL_TestApp_$(SOC)_CORELIST = mpu1_0 mcu1_0 mcu2_0 mcu3_0 c66xdsp_1 c7x | 333 | OSAL_TestApp_$(SOC)_CORELIST = mpu1_0 mcu1_0 mcu2_0 mcu3_0 c66xdsp_1 c7x_1 |
334 | OSAL_Baremetal_TestApp_$(SOC)_CORELIST = mpu1_0 mcu1_0 mcu2_0 mcu3_0 | 334 | OSAL_Baremetal_TestApp_$(SOC)_CORELIST = mpu1_0 mcu1_0 mcu2_0 mcu3_0 |
335 | endif | 335 | endif |
336 | 336 | ||
diff --git a/test/src/main_osal_test.c b/test/src/main_osal_test.c index 7f071a2..a0eb3f2 100755 --- a/test/src/main_osal_test.c +++ b/test/src/main_osal_test.c | |||
@@ -74,6 +74,12 @@ | |||
74 | #define TWO_TIMER_INTERRUPT_TEST 0 | 74 | #define TWO_TIMER_INTERRUPT_TEST 0 |
75 | #include <ti/csl/soc.h> | 75 | #include <ti/csl/soc.h> |
76 | 76 | ||
77 | #include <ti/csl/csl_clec.h> | ||
78 | |||
79 | #if defined (__C7100__) | ||
80 | #include <ti/csl/arch/csl_arch.h> | ||
81 | #endif | ||
82 | |||
77 | #ifdef BARE_METAL | 83 | #ifdef BARE_METAL |
78 | #include <ti/csl/csl_timer.h> | 84 | #include <ti/csl/csl_timer.h> |
79 | #include <ti/csl/arch/csl_arch.h> | 85 | #include <ti/csl/arch/csl_arch.h> |
@@ -91,6 +97,7 @@ void ErrorHandler(Error_Block *eb) | |||
91 | } | 97 | } |
92 | #endif | 98 | #endif |
93 | 99 | ||
100 | void Osal_appC7xPreInit(void); | ||
94 | 101 | ||
95 | #undef ENABLE_GET_TIME_TEST | 102 | #undef ENABLE_GET_TIME_TEST |
96 | #if defined(SOC_AM65XX) || defined(SOC_J721E) || defined(SOC_AM572x) || defined(SOC_K2G) || defined(SOC_AM335x) || defined(SOC_AM437x) | 103 | #if defined(SOC_AM65XX) || defined(SOC_J721E) || defined(SOC_AM572x) || defined(SOC_K2G) || defined(SOC_AM335x) || defined(SOC_AM437x) |
@@ -1243,8 +1250,6 @@ void C7x_ConfigureTimerOutput() | |||
1243 | cfgClec.c7xEvtNum = corepackEvent; | 1250 | cfgClec.c7xEvtNum = corepackEvent; |
1244 | CSL_clecConfigEvent(clecBaseAddr, input, &cfgClec); | 1251 | CSL_clecConfigEvent(clecBaseAddr, input, &cfgClec); |
1245 | 1252 | ||
1246 | Hwi_setPriority(14, 1); | ||
1247 | |||
1248 | input = CSLR_COMPUTE_CLUSTER0_GIC_SPI_TIMER1_INTR_PEND_0 + 992; /* Used for Timer Interrupt */ | 1253 | input = CSLR_COMPUTE_CLUSTER0_GIC_SPI_TIMER1_INTR_PEND_0 + 992; /* Used for Timer Interrupt */ |
1249 | corepackEvent = 15; | 1254 | corepackEvent = 15; |
1250 | 1255 | ||
@@ -1255,8 +1260,6 @@ void C7x_ConfigureTimerOutput() | |||
1255 | cfgClec.extEvtNum = 0; | 1260 | cfgClec.extEvtNum = 0; |
1256 | cfgClec.c7xEvtNum = corepackEvent; | 1261 | cfgClec.c7xEvtNum = corepackEvent; |
1257 | CSL_clecConfigEvent(clecBaseAddr, input, &cfgClec); | 1262 | CSL_clecConfigEvent(clecBaseAddr, input, &cfgClec); |
1258 | |||
1259 | Hwi_setPriority(15, 1); | ||
1260 | } | 1263 | } |
1261 | 1264 | ||
1262 | #endif | 1265 | #endif |
@@ -1343,6 +1346,8 @@ int main(void) | |||
1343 | C66xTimerInterruptInit(); | 1346 | C66xTimerInterruptInit(); |
1344 | #endif | 1347 | #endif |
1345 | 1348 | ||
1349 | Osal_appC7xPreInit(); | ||
1350 | |||
1346 | #ifdef BUILD_C7X_1 | 1351 | #ifdef BUILD_C7X_1 |
1347 | C7x_ConfigureTimerOutput(); | 1352 | C7x_ConfigureTimerOutput(); |
1348 | #endif | 1353 | #endif |
@@ -1378,3 +1383,30 @@ void InitMmu(void) | |||
1378 | Osal_initMmuDefault(); | 1383 | Osal_initMmuDefault(); |
1379 | } | 1384 | } |
1380 | #endif | 1385 | #endif |
1386 | |||
1387 | void Osal_appC7xPreInit(void) | ||
1388 | { | ||
1389 | #if defined (__C7100__) | ||
1390 | CSL_ClecEventConfig cfgClec; | ||
1391 | CSL_CLEC_EVTRegs *clecBaseAddr = (CSL_CLEC_EVTRegs*) CSL_COMPUTE_CLUSTER0_CLEC_BASE; | ||
1392 | uint32_t i, maxInputs = 2048U; | ||
1393 | |||
1394 | /* make secure claim bit to FALSE so that after we switch to non-secure mode | ||
1395 | * we can program the CLEC MMRs | ||
1396 | */ | ||
1397 | cfgClec.secureClaimEnable = FALSE; | ||
1398 | cfgClec.evtSendEnable = FALSE; | ||
1399 | cfgClec.rtMap = CSL_CLEC_RTMAP_DISABLE; | ||
1400 | cfgClec.extEvtNum = 0U; | ||
1401 | cfgClec.c7xEvtNum = 0U; | ||
1402 | for(i = 0U; i < maxInputs; i++) | ||
1403 | { | ||
1404 | CSL_clecConfigEvent(clecBaseAddr, i, &cfgClec); | ||
1405 | } | ||
1406 | |||
1407 | /* Switch now */ | ||
1408 | CSL_c7xSecSupv2NonSecSupv(); | ||
1409 | #endif | ||
1410 | |||
1411 | return; | ||
1412 | } | ||