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authorMahesh Radhakrishnan2019-09-12 17:16:13 -0500
committerMahesh Radhakrishnan2019-09-18 14:33:29 -0500
commit2c69b3c5e1dd04bff8283e9e4089cb08c7ebe258 (patch)
tree973a3f81975e6192fa2d8818e3be321ba69f89cc
parentc7c81c753408be9dec3bfd9830ff861d9bff13a7 (diff)
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PRSDK-6302: MISRA-C fixes
-rw-r--r--EventCombinerP.h4
-rw-r--r--HwiP.h2
-rw-r--r--Queue.h6
-rw-r--r--RegisterIntr.h2
-rw-r--r--SemaphoreP.h2
-rw-r--r--SwiP.h2
-rw-r--r--TaskP.h6
-rw-r--r--TimerP.h2
-rw-r--r--arch/core/Core_utils.c3
-rw-r--r--arch/core/a15/Arch_util.c37
-rw-r--r--arch/core/a53/Arch_util.c107
-rw-r--r--arch/core/a53/CacheP_nonos.c10
-rw-r--r--arch/core/a8/Arch_util.c19
-rw-r--r--arch/core/a9/Arch_util.c22
-rw-r--r--arch/core/a9/osalgic.c11
-rw-r--r--arch/core/arm9/Arch_util.c17
-rw-r--r--arch/core/c6x/Arch_util.c143
-rw-r--r--arch/core/c6x/CacheP_nonos.c36
-rw-r--r--arch/core/c7x/Arch_util.c31
-rw-r--r--arch/core/m4/Arch_util.c19
-rwxr-xr-xarch/core/r5/Arch_util.c97
-rw-r--r--osal.h31
-rwxr-xr-xsoc/j721e/TimerP_default.c224
-rw-r--r--soc/j721e/bios_mmu.c24
-rw-r--r--soc/j721e/osal_soc.h13
-rw-r--r--src/linux/HwiP_linux.c5
-rw-r--r--src/linux/SemaphoreP_linux.c2
-rw-r--r--src/linux/TimerP_linux.c2
-rw-r--r--src/linux/Utils_linux.c4
-rw-r--r--src/nonos/EventCombinerP_nonos.c31
-rw-r--r--src/nonos/HwiP_nonos.c28
-rwxr-xr-xsrc/nonos/Nonos_config.h31
-rwxr-xr-xsrc/nonos/RegisterIntr_nonos.c65
-rw-r--r--src/nonos/SemaphoreP_nonos.c146
-rw-r--r--src/nonos/SwiP_nonos.c6
-rw-r--r--src/nonos/Utils_nonos.c44
-rw-r--r--src/nonos/delay/v3/delay.c6
-rw-r--r--src/nonos/delay/v4/delay.c2
-rw-r--r--src/nonos/timer/v0/TimerP_nonos.c66
-rw-r--r--src/nonos/timer/v1/TimerP_nonos.c394
-rw-r--r--src/tirtos/EventCombinerP_tirtos.c43
-rw-r--r--src/tirtos/EventP_tirtos.c3
-rw-r--r--src/tirtos/HwiP_tirtos.c87
-rw-r--r--src/tirtos/Queue_tirtos.c14
-rwxr-xr-xsrc/tirtos/RegisterIntr_tirtos.c78
-rw-r--r--src/tirtos/SemaphoreP_tirtos.c78
-rwxr-xr-xsrc/tirtos/SwiP_tirtos.c12
-rw-r--r--src/tirtos/TaskP_tirtos.c28
-rw-r--r--src/tirtos/TimerP_tirtos.c117
-rwxr-xr-xsrc/tirtos/Utils_tirtos.c45
-rw-r--r--src/tirtos/tirtos_config.h8
-rw-r--r--test/am437x/armv7/nonos/mmu_arm.c3
-rwxr-xr-xtest/src/main_osal_test.c28
53 files changed, 1207 insertions, 1039 deletions
diff --git a/EventCombinerP.h b/EventCombinerP.h
index 62f0b2f..bdd1051 100644
--- a/EventCombinerP.h
+++ b/EventCombinerP.h
@@ -77,7 +77,7 @@ int32_t EventCombinerP_enableEvent(uint32_t eventId);
77 * 77 *
78 * @param unmask Unmask the event 78 * @param unmask Unmask the event
79 */ 79 */
80int32_t EventCombinerP_dispatchPlug(uint32_t eventId, void (*eventIsrRoutine)(uint32_t),uintptr_t arg,bool unmask ); 80int32_t EventCombinerP_dispatchPlug(uint32_t eventId, void (*eventIsrRoutine)(uint32_t arg),uintptr_t arg,bool unmask );
81 81
82/*! 82/*!
83 * @brief Function to return the Hwi Handle corresponding to an event combiner group number 83 * @brief Function to return the Hwi Handle corresponding to an event combiner group number
@@ -95,7 +95,7 @@ HwiP_Handle EventCombinerP_getHwi(uint32_t groupNum);
95 * @param groupNum The event combiner group id (0-3) 95 * @param groupNum The event combiner group id (0-3)
96 * 96 *
97 */ 97 */
98int32_t EventCombinerP_getIntNum(uint32_t groupNum); 98int32_t EventCombinerP_getIntNum(int32_t groupNum);
99 99
100/*! 100/*!
101 * @brief Function to register single event combiner group to a vector number 101 * @brief Function to register single event combiner group to a vector number
diff --git a/HwiP.h b/HwiP.h
index 43fd9c8..fd5d773 100644
--- a/HwiP.h
+++ b/HwiP.h
@@ -162,7 +162,7 @@ extern void HwiP_clearInterrupt(int32_t interruptNum);
162 * @return 162 * @return
163 */ 163 */
164extern HwiP_Handle HwiP_create(int32_t interruptNum, HwiP_Fxn hwiFxn, 164extern HwiP_Handle HwiP_create(int32_t interruptNum, HwiP_Fxn hwiFxn,
165 HwiP_Params *params); 165 const HwiP_Params *params);
166 166
167/*! 167/*!
168 * @brief Function to delete an interrupt on CortexM devices 168 * @brief Function to delete an interrupt on CortexM devices
diff --git a/Queue.h b/Queue.h
index 96b809d..e0642d6 100644
--- a/Queue.h
+++ b/Queue.h
@@ -54,7 +54,7 @@ extern "C" {
54 * @param size size (in bytes) of the memory to be written back and invalidate 54 * @param size size (in bytes) of the memory to be written back and invalidate
55 * 55 *
56 */ 56 */
57typedef struct Osal_Queue_Elem { 57typedef struct {
58 struct Osal_QueueElem *next; 58 struct Osal_QueueElem *next;
59 struct Osal_QueueElem *prev; 59 struct Osal_QueueElem *prev;
60} Osal_Queue_Elem; 60} Osal_Queue_Elem;
@@ -73,7 +73,7 @@ typedef void *Osal_Queue_Handle;
73 * @param params queue parameters 73 * @param params queue parameters
74 * 74 *
75 */ 75 */
76void Osal_Queue_construct(void * structPtr, void * params); 76void Osal_Queue_construct(void * structPtr, const void * params);
77/*! 77/*!
78 * @brief Function to return the queue handle from the structure 78 * @brief Function to return the queue handle from the structure
79 * 79 *
@@ -106,7 +106,7 @@ void * Osal_Queue_get(Osal_Queue_Handle handle);
106 * 106 *
107 * @param Ptr Pointer to the queue element 107 * @param Ptr Pointer to the queue element
108 */ 108 */
109void Osal_Queue_put(Osal_Queue_Handle handle,Osal_Queue_Elem *Ptr); 109void Osal_Queue_put(Osal_Queue_Handle handle,Osal_Queue_Elem *ptr);
110 110
111#ifdef __cplusplus 111#ifdef __cplusplus
112} 112}
diff --git a/RegisterIntr.h b/RegisterIntr.h
index 4e86d44..e824618 100644
--- a/RegisterIntr.h
+++ b/RegisterIntr.h
@@ -59,7 +59,7 @@ typedef struct {
59 char *name; /* Name of the instance for debugging purposes, could be set to NULL */ 59 char *name; /* Name of the instance for debugging purposes, could be set to NULL */
60 int32_t corepacEventNum; /* Event number going in to the corepac */ 60 int32_t corepacEventNum; /* Event number going in to the corepac */
61 int32_t intVecNum; /* Interrupt vector */ 61 int32_t intVecNum; /* Interrupt vector */
62 void (*isrRoutine)(uintptr_t); /* The ISR routine to hook the corepacEventNum to */ 62 void (*isrRoutine)(uintptr_t arg); /* The ISR routine to hook the corepacEventNum to */
63 uintptr_t arg; /* Argument to the ISR routine */ 63 uintptr_t arg; /* Argument to the ISR routine */
64 uint32_t priority; 64 uint32_t priority;
65 uint32_t triggerSensitivity; 65 uint32_t triggerSensitivity;
diff --git a/SemaphoreP.h b/SemaphoreP.h
index 6bf45e9..0e9fd7e 100644
--- a/SemaphoreP.h
+++ b/SemaphoreP.h
@@ -144,7 +144,7 @@ typedef struct SemaphoreP_Params_s {
144 * @return A SemaphoreP_Handle on success or a NULL on an error 144 * @return A SemaphoreP_Handle on success or a NULL on an error
145 */ 145 */
146extern SemaphoreP_Handle SemaphoreP_create(uint32_t count, 146extern SemaphoreP_Handle SemaphoreP_create(uint32_t count,
147 SemaphoreP_Params *params); 147 const SemaphoreP_Params *params);
148 148
149/*! 149/*!
150 * @brief Function to delete a semaphore. 150 * @brief Function to delete a semaphore.
diff --git a/SwiP.h b/SwiP.h
index 027a1ff..118f1e5 100644
--- a/SwiP.h
+++ b/SwiP.h
@@ -94,7 +94,7 @@ typedef struct SwiP_Params_s {
94 * 94 *
95 * @return SwiP_Handle 95 * @return SwiP_Handle
96 */ 96 */
97extern SwiP_Handle SwiP_create(SwiP_Fxn swiFxn, SwiP_Params *params); 97extern SwiP_Handle SwiP_create(SwiP_Fxn swiFxn, const SwiP_Params *params);
98 98
99/*! 99/*!
100 * @brief Function to delete an interrupt on CortexM devices 100 * @brief Function to delete an interrupt on CortexM devices
diff --git a/TaskP.h b/TaskP.h
index 387fb39..3301cc1 100644
--- a/TaskP.h
+++ b/TaskP.h
@@ -100,7 +100,7 @@ typedef struct TaskP_Params_s
100 * @return A TaskP_Handle on success or a NULL on an error 100 * @return A TaskP_Handle on success or a NULL on an error
101 */ 101 */
102extern TaskP_Handle TaskP_create(void *taskfxn, 102extern TaskP_Handle TaskP_create(void *taskfxn,
103 TaskP_Params *params); 103 const TaskP_Params *params);
104 104
105/*! 105/*!
106 * @brief Function to delete a task. 106 * @brief Function to delete a task.
@@ -147,13 +147,13 @@ extern void TaskP_setPrio(TaskP_Handle handle, uint32_t priority);
147 * @brief Function returns the Task handle of current task 147 * @brief Function returns the Task handle of current task
148 * 148 *
149 */ 149 */
150extern TaskP_Handle TaskP_self(); 150extern TaskP_Handle TaskP_self(void);
151 151
152/*! 152/*!
153 * @brief Function returns the Task handle of current task.This is an inline function 153 * @brief Function returns the Task handle of current task.This is an inline function
154 * 154 *
155 */ 155 */
156extern TaskP_Handle TaskP_selfmacro(); 156extern TaskP_Handle TaskP_selfmacro(void);
157 157
158/*! 158/*!
159 * @brief Function Yield processor to equal priority task 159 * @brief Function Yield processor to equal priority task
diff --git a/TimerP.h b/TimerP.h
index 05ac30f..3a435d5 100644
--- a/TimerP.h
+++ b/TimerP.h
@@ -201,7 +201,7 @@ typedef struct TimerP_Params_s {
201 */ 201 */
202extern TimerP_Handle TimerP_create(int32_t id, 202extern TimerP_Handle TimerP_create(int32_t id,
203 TimerP_Fxn tickFxn, 203 TimerP_Fxn tickFxn,
204 TimerP_Params *params); 204 const TimerP_Params *params);
205 205
206/*! 206/*!
207 * @brief Function to delete a timer. 207 * @brief Function to delete a timer.
diff --git a/arch/core/Core_utils.c b/arch/core/Core_utils.c
index 5464297..58e16ae 100644
--- a/arch/core/Core_utils.c
+++ b/arch/core/Core_utils.c
@@ -37,12 +37,13 @@
37#include <stdbool.h> 37#include <stdbool.h>
38#include <stdlib.h> 38#include <stdlib.h>
39#include <string.h> 39#include <string.h>
40#include <ti/osal/osal.h>
40 41
41#if defined(gnu_targets_arm_A15F) 42#if defined(gnu_targets_arm_A15F)
42#include <ti/csl/arch/a15/V0/csl_a15.h> 43#include <ti/csl/arch/a15/V0/csl_a15.h>
43#endif 44#endif
44 45
45int32_t Osal_getCoreId() 46int32_t Osal_getCoreId(void)
46{ 47{
47#if defined(gnu_targets_arm_A15F) 48#if defined(gnu_targets_arm_A15F)
48 return ((int32_t)CSL_a15ReadCoreId()); 49 return ((int32_t)CSL_a15ReadCoreId());
diff --git a/arch/core/a15/Arch_util.c b/arch/core/a15/Arch_util.c
index f64f49f..8e8f9a3 100644
--- a/arch/core/a15/Arch_util.c
+++ b/arch/core/a15/Arch_util.c
@@ -39,7 +39,7 @@
39#include <stdlib.h> 39#include <stdlib.h>
40#include <ti/csl/arch/a15/csl_a15_startup.h> 40#include <ti/csl/arch/a15/csl_a15_startup.h>
41#include <ti/osal/src/nonos/Nonos_config.h> 41#include <ti/osal/src/nonos/Nonos_config.h>
42 42#include <ti/csl/tistdtypes.h>
43/* Local structure definition */ 43/* Local structure definition */
44typedef struct HwiP_nonOs_s { 44typedef struct HwiP_nonOs_s {
45 Bool used; 45 Bool used;
@@ -72,7 +72,7 @@ void OsalArch_compileTime_SizeChk(void)
72/* TI compiler */ 72/* TI compiler */
73#pragma diag_suppress 179 73#pragma diag_suppress 179
74#endif 74#endif
75 OSAL_COMPILE_TIME_SIZE_CHECK (sizeof(HwiP_nonOs) < OSAL_NONOS_HWIP_SIZE_BYTES); 75 OSAL_COMPILE_TIME_SIZE_CHECK (sizeof(HwiP_nonOs),OSAL_NONOS_HWIP_SIZE_BYTES);
76#if defined(__GNUC__) && !defined(__ti__) 76#if defined(__GNUC__) && !defined(__ti__)
77#pragma GCC diagnostic pop 77#pragma GCC diagnostic pop
78#endif 78#endif
@@ -98,8 +98,8 @@ void OsalArch_gicInit(void)
98 gCpuIntrf->gicDist->distBasePtr = (void *)SOC_INTC_MPU_DISTRIBUTOR_BASE; 98 gCpuIntrf->gicDist->distBasePtr = (void *)SOC_INTC_MPU_DISTRIBUTOR_BASE;
99 gCpuIntrf->initStatus = (Uint32)FALSE; 99 gCpuIntrf->initStatus = (Uint32)FALSE;
100 gCpuIntrf->gicDist->initStatus = (Uint32)FALSE; 100 gCpuIntrf->gicDist->initStatus = (Uint32)FALSE;
101 gCpuIntrf->pDefaultIntrHandlers = NULL; 101 gCpuIntrf->pDefaultIntrHandlers = NULL_PTR;
102 gCpuIntrf->pDefaultUserParameter = NULL; 102 gCpuIntrf->pDefaultUserParameter = NULL_PTR;
103 CSL_armGicInit(gCpuIntrf); 103 CSL_armGicInit(gCpuIntrf);
104 } 104 }
105 else { 105 else {
@@ -144,9 +144,9 @@ void OsalArch_globalRestoreInterrupt (uintptr_t restoreValue)
144 144
145/* Below function registers the interrupt for a given ISR */ 145/* Below function registers the interrupt for a given ISR */
146HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn, 146HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn,
147 HwiP_Params *params) 147 const HwiP_Params *params)
148{ 148{
149 Hwi_Struct *hwi_handle = (Hwi_Struct *) NULL; 149 Hwi_Struct *hwi_handle = (Hwi_Struct *) NULL_PTR;
150 150
151 uint32_t i; 151 uint32_t i;
152 uintptr_t key; 152 uintptr_t key;
@@ -159,7 +159,7 @@ HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn,
159 /* Check if user has specified any memory block to be used, which gets 159 /* Check if user has specified any memory block to be used, which gets
160 * the precedence over the internal static memory block 160 * the precedence over the internal static memory block
161 */ 161 */
162 if (gOsal_HwAttrs.extHwiPBlock.base != (uintptr_t)NULL) 162 if (gOsal_HwAttrs.extHwiPBlock.base != (uintptr_t)NULL_PTR)
163 { 163 {
164 /* pick up the external memory block configured */ 164 /* pick up the external memory block configured */
165 hwiPool = (HwiP_nonOs *) gOsal_HwAttrs.extHwiPBlock.base; 165 hwiPool = (HwiP_nonOs *) gOsal_HwAttrs.extHwiPBlock.base;
@@ -173,9 +173,9 @@ HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn,
173 maxHwi = OSAL_NONOS_CONFIGNUM_HWI; 173 maxHwi = OSAL_NONOS_CONFIGNUM_HWI;
174 } 174 }
175 175
176 if (params == NULL) 176 if (params == NULL_PTR)
177 { 177 {
178 return (NULL); 178 return (NULL_PTR);
179 } 179 }
180 180
181 key = OsalArch_globalDisableInterrupt(); 181 key = OsalArch_globalDisableInterrupt();
@@ -194,10 +194,10 @@ HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn,
194 } 194 }
195 else 195 else
196 { 196 {
197 retHandle = (HwiP_Handle)(NULL); 197 retHandle = (HwiP_Handle)(NULL_PTR);
198 } 198 }
199 199
200 if (hwi_handle != (Hwi_Struct *) NULL) 200 if (hwi_handle != (Hwi_Struct *) NULL_PTR)
201 { 201 {
202 /* Initialize User parameters */ 202 /* Initialize User parameters */
203 hwi_handle->gicParams.pUserParam = (void *) params->arg; 203 hwi_handle->gicParams.pUserParam = (void *) params->arg;
@@ -239,7 +239,7 @@ HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn,
239/* Below function deletes the hwi created */ 239/* Below function deletes the hwi created */
240HwiP_Status OsalArch_HwiPDelete(HwiP_Handle handle) 240HwiP_Status OsalArch_HwiPDelete(HwiP_Handle handle)
241{ 241{
242 CSL_Status status = CSL_SOK; 242
243 HwiP_nonOs *hwi_hnd = (HwiP_nonOs*) handle; 243 HwiP_nonOs *hwi_hnd = (HwiP_nonOs*) handle;
244 uintptr_t key; 244 uintptr_t key;
245 HwiP_Status ret_val; 245 HwiP_Status ret_val;
@@ -249,14 +249,7 @@ HwiP_Status OsalArch_HwiPDelete(HwiP_Handle handle)
249 hwi_hnd->used = FALSE; 249 hwi_hnd->used = FALSE;
250 OsalArch_globalRestoreInterrupt(key); 250 OsalArch_globalRestoreInterrupt(key);
251 251
252 if (status == CSL_SOK) 252 ret_val = HwiP_OK;
253 {
254 ret_val = (HwiP_OK);
255 }
256 else
257 {
258 ret_val = (HwiP_FAILURE);
259 }
260 return (ret_val); 253 return (ret_val);
261} 254}
262 255
@@ -288,7 +281,7 @@ void osalArch_TimestampInit(void)
288 timerParams.period = 1000000u; 281 timerParams.period = 1000000u;
289 timerHandle = TimerP_create(TimerP_ANY, (TimerP_Fxn)&osalArch_TimestampCcntAutoRefresh, &timerParams); 282 timerHandle = TimerP_create(TimerP_ANY, (TimerP_Fxn)&osalArch_TimestampCcntAutoRefresh, &timerParams);
290 283
291 if ( timerHandle != (TimerP_Handle) NULL) 284 if ( timerHandle != (TimerP_Handle) NULL_PTR)
292 { 285 {
293 /* start the timer */ 286 /* start the timer */
294 TimerP_start(timerHandle); 287 TimerP_start(timerHandle);
@@ -304,7 +297,7 @@ void osalArch_TimestampGet64(TimeStamp_Struct *tStamp)
304 uint32_t lo, ovsrStatus; 297 uint32_t lo, ovsrStatus;
305 uintptr_t key; 298 uintptr_t key;
306 299
307 if (tStamp != (TimeStamp_Struct *) NULL) 300 if (tStamp != (TimeStamp_Struct *) NULL_PTR)
308 { 301 {
309 key = HwiP_disable(); 302 key = HwiP_disable();
310 /* Make sure init is done, if not done already */ 303 /* Make sure init is done, if not done already */
diff --git a/arch/core/a53/Arch_util.c b/arch/core/a53/Arch_util.c
index 2f99e49..21f6572 100644
--- a/arch/core/a53/Arch_util.c
+++ b/arch/core/a53/Arch_util.c
@@ -33,13 +33,14 @@
33 * ======== HwiP_tirtos.c ======== 33 * ======== HwiP_tirtos.c ========
34 */ 34 */
35 35
36 36#include <string.h>
37#include <stdint.h> 37#include <stdint.h>
38#include <stdbool.h> 38#include <stdbool.h>
39#include <stdlib.h> 39#include <stdlib.h>
40#include <ti/osal/src/nonos/Nonos_config.h> 40#include <ti/osal/src/nonos/Nonos_config.h>
41#include <ti/csl/src/ip/arm_gic/V2/csl_gic.h> 41#include <ti/csl/src/ip/arm_gic/V2/csl_gic.h>
42#include <ti/csl/soc.h> 42#include <ti/csl/soc.h>
43#include <ti/csl/tistdtypes.h>
43 44
44/* Local define */ 45/* Local define */
45#define HWIP_A53_DEFAULT_PRIORITY ((uint32_t) 0xE0U) 46#define HWIP_A53_DEFAULT_PRIORITY ((uint32_t) 0xE0U)
@@ -47,14 +48,14 @@
47/* Local hwi structures */ 48/* Local hwi structures */
48 49
49typedef struct HwiP_nonOs_s { 50typedef struct HwiP_nonOs_s {
50 Bool used; 51 bool used;
51 Hwi_Struct hwi; 52 Hwi_Struct hwi;
52} HwiP_nonOs; 53} HwiP_nonOs;
53 54
54/* Local hwi structures */ 55/* Local hwi structures */
55static HwiP_nonOs hwiStructs[OSAL_NONOS_CONFIGNUM_HWI] = {{0}}; 56static HwiP_nonOs hwiStructs[OSAL_NONOS_CONFIGNUM_HWI];
56static bool gTimestampFirstTime = TRUE; 57static bool gTimestampFirstTime = (bool)true;
57 58static bool gHwiInitialized = (bool)false;
58 59
59/* 60/*
60 * Dummy function to check size during compile time 61 * Dummy function to check size during compile time
@@ -70,7 +71,7 @@ void OsalArch_compileTime_SizeChk(void)
70/* TI compiler */ 71/* TI compiler */
71#pragma diag_suppress 179 72#pragma diag_suppress 179
72#endif 73#endif
73 OSAL_COMPILE_TIME_SIZE_CHECK (sizeof(HwiP_nonOs) < OSAL_NONOS_HWIP_SIZE_BYTES); 74 OSAL_COMPILE_TIME_SIZE_CHECK ((uint32_t)sizeof(HwiP_nonOs), OSAL_NONOS_HWIP_SIZE_BYTES);
74#if defined(__GNUC__) && !defined(__ti__) 75#if defined(__GNUC__) && !defined(__ti__)
75#pragma GCC diagnostic pop 76#pragma GCC diagnostic pop
76#endif 77#endif
@@ -108,14 +109,14 @@ void OsalArch_gicInit(void)
108/* This function enables the interrupt for a given interrupt number */ 109/* This function enables the interrupt for a given interrupt number */
109void OsalArch_enableInterrupt(uint32_t intNum) 110void OsalArch_enableInterrupt(uint32_t intNum)
110{ 111{
111 Intc_SystemEnable((uint16_t)intNum); 112 (void)Intc_SystemEnable((uint16_t)intNum);
112 return; 113 return;
113} 114}
114 115
115/* This function disables the interrupt for a given interrupt number */ 116/* This function disables the interrupt for a given interrupt number */
116void OsalArch_disableInterrupt(uint32_t intNum) 117void OsalArch_disableInterrupt(uint32_t intNum)
117{ 118{
118 Intc_SystemDisable((uint16_t)intNum); 119 (void)Intc_SystemDisable((uint16_t)intNum);
119 return; 120 return;
120} 121}
121 122
@@ -129,17 +130,19 @@ void OsalArch_clearInterrupt(uint32_t intNum)
129int32_t OsalArch_postInterrupt(uint32_t intrNum) 130int32_t OsalArch_postInterrupt(uint32_t intrNum)
130{ 131{
131 CSL_gic500_gicdRegs *gicdRegs = (CSL_gic500_gicdRegs *)(GIC_BASE_ADDR); 132 CSL_gic500_gicdRegs *gicdRegs = (CSL_gic500_gicdRegs *)(GIC_BASE_ADDR);
132 CSL_gic500_gicrRegs *gicrRegs = (CSL_gic500_gicrRegs *) ( GIC_BASE_ADDR + CSL_GIC500_GICR_CORE_CONTROL_CTLR(0)); 133 CSL_gic500_gicrRegs *gicrRegs = (CSL_gic500_gicrRegs *) ( GIC_BASE_ADDR + CSL_GIC500_GICR_CORE_CONTROL_CTLR(0U));
133 uint64_t cpuId = CSL_a53GetCpuId(); 134 uint64_t cpuId = CSL_a53GetCpuId();
134 uint8_t coreId = cpuId &= 0xFFU; 135 uint8_t coreId;
136 cpuId &= 0xFFU;
137 coreId = (uint8_t)cpuId;
135 138
136 if (intrNum < 32) 139 if (intrNum < 32U)
137 { 140 {
138 CSL_gicSetPendingSgiPpiIntr(gicrRegs, coreId, intrNum); 141 (void)CSL_gicSetPendingSgiPpiIntr(gicrRegs, coreId, intrNum);
139 } 142 }
140 else if (intrNum < 960) 143 else if (intrNum < 960U)
141 { 144 {
142 CSL_gicSetPendingSpiIntr(gicdRegs, intrNum); 145 (void)CSL_gicSetPendingSpiIntr(gicdRegs, intrNum);
143 } 146 }
144 else 147 else
145 { 148 {
@@ -167,24 +170,24 @@ void OsalArch_globalRestoreInterrupt (uintptr_t restoreValue)
167 170
168/* Below function registers the interrupt for a given ISR */ 171/* Below function registers the interrupt for a given ISR */
169HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn, 172HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn,
170 HwiP_Params *params) 173 const HwiP_Params *params)
171{ 174{
172 Hwi_Struct *hwi_handle = (Hwi_Struct *) NULL; 175 Hwi_Struct *hwi_handle = NULL_PTR;
173 176
174 uint32_t i; 177 uint32_t i;
175 uintptr_t key; 178 uintptr_t key;
176 179 uint16_t priority;
177 uintptr_t temp; 180 uintptr_t temp;
178 HwiP_nonOs *hwiPool; 181 HwiP_nonOs *hwiPool;
179 uint32_t maxHwi; 182 uint32_t maxHwi;
180 HwiP_Handle retHandle; 183 HwiP_Handle retHandle = NULL_PTR;
181 uint64_t cpuId; 184 uint64_t cpuId;
182 uint8_t coreId; 185 uint8_t coreId;
183 186
184 /* Check if user has specified any memory block to be used, which gets 187 /* Check if user has specified any memory block to be used, which gets
185 * the precedence over the internal static memory block 188 * the precedence over the internal static memory block
186 */ 189 */
187 if (gOsal_HwAttrs.extHwiPBlock.base != (uintptr_t)NULL) 190 if (gOsal_HwAttrs.extHwiPBlock.base != 0U)
188 { 191 {
189 /* pick up the external memory block configured */ 192 /* pick up the external memory block configured */
190 hwiPool = (HwiP_nonOs *) gOsal_HwAttrs.extHwiPBlock.base; 193 hwiPool = (HwiP_nonOs *) gOsal_HwAttrs.extHwiPBlock.base;
@@ -196,19 +199,24 @@ HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn,
196 /* Pick up the internal static memory block */ 199 /* Pick up the internal static memory block */
197 hwiPool = (HwiP_nonOs *) &hwiStructs[0]; 200 hwiPool = (HwiP_nonOs *) &hwiStructs[0];
198 maxHwi = OSAL_NONOS_CONFIGNUM_HWI; 201 maxHwi = OSAL_NONOS_CONFIGNUM_HWI;
202
203 if(gHwiInitialized==(bool)false)
204 {
205 /* Initializing the first time */
206 (void)memset((void *)hwiStructs,0,sizeof(hwiStructs));
207 gHwiInitialized = true;
208 }
199 } 209 }
200 210
201 if (params == NULL) 211 if (params != NULL_PTR)
202 { 212 {
203 return (NULL);
204 }
205 213
206 cpuId = CSL_a53GetCpuId(); 214 cpuId = CSL_a53GetCpuId();
207 coreId = (uint8_t)(cpuId) & (uint8_t)0xFF; 215 coreId = (uint8_t)(cpuId) & (uint8_t)0xFF;
208 key = OsalArch_globalDisableInterrupt(); 216 key = OsalArch_globalDisableInterrupt();
209 for (i = 0u; i < maxHwi; i++) { 217 for (i = 0u; i < maxHwi; i++) {
210 if (hwiPool[i].used == FALSE) { 218 if (hwiPool[i].used == false) {
211 hwiPool[i].used = TRUE; 219 hwiPool[i].used = true;
212 break; 220 break;
213 } 221 }
214 } 222 }
@@ -221,49 +229,54 @@ HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn,
221 } 229 }
222 else 230 else
223 { 231 {
224 retHandle = (HwiP_Handle)(NULL); 232 retHandle = NULL_PTR;
225 } 233 }
226 234 }
227 if (hwi_handle != (Hwi_Struct *) NULL) 235
236 if (hwi_handle != NULL_PTR)
228 { 237 {
229 /* Registering the Interrupt Service Routine(ISR). */ 238 /* Registering the Interrupt Service Routine(ISR). */
230 Intc_IntRegister((uint16_t)interruptNum, (IntrFuncPtr) hwiFxn, (void *)params->arg); 239 Intc_IntRegister((uint16_t)interruptNum, (IntrFuncPtr) hwiFxn, (void *)params->arg);
231 240
232 /* Set the priority to default priority if priority is set un-initialized */ 241 /* Set the priority to default priority if priority is set un-initialized */
242
233 if (params->priority == HWIP_USE_DEFAULT_PRIORITY) 243 if (params->priority == HWIP_USE_DEFAULT_PRIORITY)
234 { 244 {
235 params->priority = HWIP_A53_DEFAULT_PRIORITY; 245 priority = (uint16_t)HWIP_A53_DEFAULT_PRIORITY;
236 } 246 } else
247 {
248 priority = (uint16_t)params->priority;
249 }
237 250
238 /* Setting the priority for the interrupts in INTC. */ 251 /* Setting the priority for the interrupts in INTC. */
239 Intc_IntPrioritySet((uint16_t)interruptNum, params->priority, coreId); 252 Intc_IntPrioritySet((uint16_t)interruptNum, priority,coreId);
240 253
241 /* Set the trigger type */ 254 /* Set the trigger type */
242 if ((params->triggerSensitivity == OSAL_ARM_GIC_TRIG_TYPE_HIGH_LEVEL) || 255 if ((params->triggerSensitivity == (uint32_t)OSAL_ARM_GIC_TRIG_TYPE_HIGH_LEVEL) ||
243 (params->triggerSensitivity == OSAL_ARM_GIC_TRIG_TYPE_LEVEL) || 256 (params->triggerSensitivity == (uint32_t)OSAL_ARM_GIC_TRIG_TYPE_LEVEL) ||
244 (params->triggerSensitivity == OSAL_ARM_GIC_TRIG_TYPE_LOW_LEVEL)) 257 (params->triggerSensitivity == (uint32_t)OSAL_ARM_GIC_TRIG_TYPE_LOW_LEVEL))
245 { 258 {
246 Intc_IntAssignLevelIntType(interruptNum); 259 (void)Intc_IntAssignLevelIntType((uint16_t)interruptNum);
247 } 260 }
248 261
249 if ((params->triggerSensitivity == OSAL_ARM_GIC_TRIG_TYPE_RISING_EDGE) || 262 if ((params->triggerSensitivity == (uint32_t)OSAL_ARM_GIC_TRIG_TYPE_RISING_EDGE) ||
250 (params->triggerSensitivity == OSAL_ARM_GIC_TRIG_TYPE_EDGE) || 263 (params->triggerSensitivity == (uint32_t)OSAL_ARM_GIC_TRIG_TYPE_EDGE) ||
251 (params->triggerSensitivity == OSAL_ARM_GIC_TRIG_TYPE_FALLING_EDGE)) 264 (params->triggerSensitivity == (uint32_t)OSAL_ARM_GIC_TRIG_TYPE_FALLING_EDGE))
252 { 265 {
253 Intc_IntAssignEdgeIntType(interruptNum); 266 (void)Intc_IntAssignEdgeIntType((uint16_t)interruptNum);
254 } 267 }
255 268
256 /* Return Non Zero value for the handle for A15 target */ 269 /* Return Non Zero value for the handle for A15 target */
257 hwi_handle->intNum = interruptNum; 270 hwi_handle->intNum = (uint32_t)interruptNum;
258 271
259 /* Enabling the interrupt if configured */ 272 /* Enabling the interrupt if configured */
260 if (params->enableIntr == TRUE) 273 if (params->enableIntr == 1U)
261 { 274 {
262 OsalArch_enableInterrupt(interruptNum); 275 OsalArch_enableInterrupt((uint32_t)interruptNum);
263 } 276 }
264 else 277 else
265 { 278 {
266 OsalArch_disableInterrupt(interruptNum); 279 OsalArch_disableInterrupt((uint32_t)interruptNum);
267 } 280 }
268 } 281 }
269 return ((HwiP_Handle) (retHandle) ); 282 return ((HwiP_Handle) (retHandle) );
@@ -278,8 +291,8 @@ HwiP_Status OsalArch_HwiPDelete(HwiP_Handle handle)
278 291
279 /* mark that handle as free */ 292 /* mark that handle as free */
280 key = OsalArch_globalDisableInterrupt(); 293 key = OsalArch_globalDisableInterrupt();
281 hwi_hnd->used = FALSE; 294 hwi_hnd->used = (bool)false;
282 Intc_IntUnregister(hwi_hnd->hwi.intNum ); 295 Intc_IntUnregister((uint16_t)(hwi_hnd->hwi.intNum));
283 OsalArch_globalRestoreInterrupt(key); 296 OsalArch_globalRestoreInterrupt(key);
284 return (HwiP_OK); 297 return (HwiP_OK);
285} 298}
@@ -287,10 +300,10 @@ HwiP_Status OsalArch_HwiPDelete(HwiP_Handle handle)
287/* Initialize the time stamp module */ 300/* Initialize the time stamp module */
288void osalArch_TimestampInit(void) 301void osalArch_TimestampInit(void)
289{ 302{
290 if (gTimestampFirstTime == TRUE) 303 if (gTimestampFirstTime == (bool)true)
291 { 304 {
292 CSL_initGTC(); 305 CSL_initGTC();
293 gTimestampFirstTime = FALSE; 306 gTimestampFirstTime = (bool)false;
294 } 307 }
295 return; 308 return;
296} 309}
diff --git a/arch/core/a53/CacheP_nonos.c b/arch/core/a53/CacheP_nonos.c
index fe1ffef..63de18f 100644
--- a/arch/core/a53/CacheP_nonos.c
+++ b/arch/core/a53/CacheP_nonos.c
@@ -50,9 +50,9 @@ static uint32_t CacheP_getCacheSize(void)
50 cacheLineSize = CSL_a53v8GetCurrentCacheSize(); 50 cacheLineSize = CSL_a53v8GetCurrentCacheSize();
51 /* Indicates the (log2 (number of words in cache line)) - 2 */ 51 /* Indicates the (log2 (number of words in cache line)) - 2 */
52 cacheLineSize &= (uint32_t) 7U; 52 cacheLineSize &= (uint32_t) 7U;
53 cacheLineSize += 2; 53 cacheLineSize += 2U;
54 /* Now get the actual size by left shift operation */ 54 /* Now get the actual size by left shift operation */
55 cacheLineSize = (1U << cacheLineSize); 55 cacheLineSize = ((uint32_t)1U << cacheLineSize);
56 return (cacheLineSize); 56 return (cacheLineSize);
57} 57}
58 58
@@ -63,7 +63,7 @@ void CacheP_wb(const void * addr, int32_t size)
63 uint32_t cacheLineSize = CacheP_getCacheSize(); 63 uint32_t cacheLineSize = CacheP_getCacheSize();
64 64
65 /* Calculate the last address */ 65 /* Calculate the last address */
66 lastAddr = (uintptr_t) addr + size; 66 lastAddr = (uintptr_t) addr + (uint32_t)size;
67 67
68 /* find the first address for cache Wb */ 68 /* find the first address for cache Wb */
69 firstAddr = (uintptr_t ) addr & ~(cacheLineSize -1U); 69 firstAddr = (uintptr_t ) addr & ~(cacheLineSize -1U);
@@ -82,7 +82,7 @@ void CacheP_wbInv(const void * addr, int32_t size)
82 uint32_t cacheLineSize = CacheP_getCacheSize(); 82 uint32_t cacheLineSize = CacheP_getCacheSize();
83 83
84 /* Calculate the last address */ 84 /* Calculate the last address */
85 lastAddr = (uintptr_t) addr + size; 85 lastAddr = (uintptr_t) addr + (uint32_t)size;
86 86
87 /* find the first address for cache Wb */ 87 /* find the first address for cache Wb */
88 firstAddr = (uintptr_t ) addr & ~(cacheLineSize -1U); 88 firstAddr = (uintptr_t ) addr & ~(cacheLineSize -1U);
@@ -102,7 +102,7 @@ void CacheP_Inv(const void * addr, int32_t size)
102 uint32_t cacheLineSize = CacheP_getCacheSize(); 102 uint32_t cacheLineSize = CacheP_getCacheSize();
103 103
104 /* Calculate the last address */ 104 /* Calculate the last address */
105 lastAddr = (uintptr_t) addr + size; 105 lastAddr = (uintptr_t) addr + (uint32_t)size;
106 106
107 /* find the first address for cache Wb */ 107 /* find the first address for cache Wb */
108 firstAddr = (uintptr_t ) addr & ~(cacheLineSize -1U); 108 firstAddr = (uintptr_t ) addr & ~(cacheLineSize -1U);
diff --git a/arch/core/a8/Arch_util.c b/arch/core/a8/Arch_util.c
index 79e9c34..aecf1d5 100644
--- a/arch/core/a8/Arch_util.c
+++ b/arch/core/a8/Arch_util.c
@@ -38,6 +38,7 @@
38#include <stdbool.h> 38#include <stdbool.h>
39#include <stdlib.h> 39#include <stdlib.h>
40#include <ti/osal/src/nonos/Nonos_config.h> 40#include <ti/osal/src/nonos/Nonos_config.h>
41#include <ti/csl/tistdtypes.h>
41#include "interrupt.h" 42#include "interrupt.h"
42 43
43 44
@@ -126,9 +127,9 @@ void OsalArch_globalRestoreInterrupt (uintptr_t restoreValue)
126 127
127/* Below function registers the interrupt for a given ISR */ 128/* Below function registers the interrupt for a given ISR */
128HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn, 129HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn,
129 HwiP_Params *params) 130 const HwiP_Params *params)
130{ 131{
131 Hwi_Struct *hwi_handle = (Hwi_Struct *) NULL; 132 Hwi_Struct *hwi_handle = (Hwi_Struct *) NULL_PTR;
132 intcIntrParams_t intrParams; 133 intcIntrParams_t intrParams;
133 uint32_t i; 134 uint32_t i;
134 uintptr_t key; 135 uintptr_t key;
@@ -141,7 +142,7 @@ HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn,
141 /* Check if user has specified any memory block to be used, which gets 142 /* Check if user has specified any memory block to be used, which gets
142 * the precedence over the internal static memory block 143 * the precedence over the internal static memory block
143 */ 144 */
144 if (gOsal_HwAttrs.extHwiPBlock.base != (uintptr_t)NULL) 145 if (gOsal_HwAttrs.extHwiPBlock.base != (uintptr_t)NULL_PTR)
145 { 146 {
146 /* pick up the external memory block configured */ 147 /* pick up the external memory block configured */
147 hwiPool = (HwiP_nonOs *) gOsal_HwAttrs.extHwiPBlock.base; 148 hwiPool = (HwiP_nonOs *) gOsal_HwAttrs.extHwiPBlock.base;
@@ -155,9 +156,9 @@ HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn,
155 maxHwi = OSAL_NONOS_CONFIGNUM_HWI; 156 maxHwi = OSAL_NONOS_CONFIGNUM_HWI;
156 } 157 }
157 158
158 if (params == NULL) 159 if (params == NULL_PTR)
159 { 160 {
160 return (NULL); 161 return (NULL_PTR);
161 } 162 }
162 163
163 key = OsalArch_globalDisableInterrupt(); 164 key = OsalArch_globalDisableInterrupt();
@@ -176,7 +177,7 @@ HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn,
176 } 177 }
177 else 178 else
178 { 179 {
179 retHandle = (HwiP_Handle)(NULL); 180 retHandle = (HwiP_Handle)(NULL_PTR);
180 } 181 }
181 182
182 183
@@ -202,7 +203,7 @@ HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn,
202 intrParams.triggerType = INTC_TRIG_HIGH_LEVEL; 203 intrParams.triggerType = INTC_TRIG_HIGH_LEVEL;
203 break; 204 break;
204 } 205 }
205 if (hwi_handle != (Hwi_Struct *) NULL) 206 if (hwi_handle != (Hwi_Struct *) NULL_PTR)
206 { 207 {
207 /* Record the hwiFxn and argument */ 208 /* Record the hwiFxn and argument */
208 hwi_handle->arg = (void*) params->arg; 209 hwi_handle->arg = (void*) params->arg;
@@ -273,7 +274,7 @@ void osalArch_TimestampInit(void)
273 timerParams.period = 1000000u; 274 timerParams.period = 1000000u;
274 timerHandle = TimerP_create(TimerP_ANY, (TimerP_Fxn)&osalArch_TimestampCcntAutoRefresh, &timerParams); 275 timerHandle = TimerP_create(TimerP_ANY, (TimerP_Fxn)&osalArch_TimestampCcntAutoRefresh, &timerParams);
275 276
276 if ( timerHandle != (TimerP_Handle) NULL) 277 if ( timerHandle != (TimerP_Handle) NULL_PTR)
277 { 278 {
278 /* start the timer */ 279 /* start the timer */
279 TimerP_start(timerHandle); 280 TimerP_start(timerHandle);
@@ -289,7 +290,7 @@ void osalArch_TimestampGet64(TimeStamp_Struct *tStamp)
289 uint32_t lo, ovsrStatus; 290 uint32_t lo, ovsrStatus;
290 uintptr_t key; 291 uintptr_t key;
291 292
292 if (tStamp != (TimeStamp_Struct *) NULL) 293 if (tStamp != (TimeStamp_Struct *) NULL_PTR)
293 { 294 {
294 key = HwiP_disable(); 295 key = HwiP_disable();
295 /* Make sure init is done, if not done already */ 296 /* Make sure init is done, if not done already */
diff --git a/arch/core/a9/Arch_util.c b/arch/core/a9/Arch_util.c
index c1a352b..58a1469 100644
--- a/arch/core/a9/Arch_util.c
+++ b/arch/core/a9/Arch_util.c
@@ -39,7 +39,7 @@
39#include <stdlib.h> 39#include <stdlib.h>
40#include <ti/osal/src/nonos/Nonos_config.h> 40#include <ti/osal/src/nonos/Nonos_config.h>
41#include "interrupt.h" 41#include "interrupt.h"
42 42#include <ti/csl/tistdtypes.h>
43 43
44#define OSAL_ARCH_UTIL_ZERO ((uint32_t) 0U) 44#define OSAL_ARCH_UTIL_ZERO ((uint32_t) 0U)
45 45
@@ -70,7 +70,7 @@ void OsalArch_compileTime_SizeChk(void)
70/* TI compiler */ 70/* TI compiler */
71#pragma diag_suppress 179 71#pragma diag_suppress 179
72#endif 72#endif
73 OSAL_COMPILE_TIME_SIZE_CHECK (sizeof(HwiP_nonOs) < OSAL_NONOS_HWIP_SIZE_BYTES); 73 OSAL_COMPILE_TIME_SIZE_CHECK (sizeof(HwiP_nonOs),OSAL_NONOS_HWIP_SIZE_BYTES);
74#if defined(__GNUC__) && !defined(__ti__) 74#if defined(__GNUC__) && !defined(__ti__)
75#pragma GCC diagnostic pop 75#pragma GCC diagnostic pop
76#endif 76#endif
@@ -120,9 +120,9 @@ void OsalArch_globalRestoreInterrupt (uintptr_t restoreValue)
120 120
121/* Below function registers the interrupt for a given ISR */ 121/* Below function registers the interrupt for a given ISR */
122HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn, 122HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn,
123 HwiP_Params *params) 123 const HwiP_Params *params)
124{ 124{
125 Hwi_Struct *hwi_handle = (Hwi_Struct *) NULL; 125 Hwi_Struct *hwi_handle = (Hwi_Struct *) NULL_PTR;
126 intcIntrParams_t intrParams; 126 intcIntrParams_t intrParams;
127 uint32_t i; 127 uint32_t i;
128 uintptr_t key; 128 uintptr_t key;
@@ -135,7 +135,7 @@ HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn,
135 /* Check if user has specified any memory block to be used, which gets 135 /* Check if user has specified any memory block to be used, which gets
136 * the precedence over the internal static memory block 136 * the precedence over the internal static memory block
137 */ 137 */
138 if (gOsal_HwAttrs.extHwiPBlock.base != (uintptr_t)NULL) 138 if (gOsal_HwAttrs.extHwiPBlock.base != (uintptr_t)NULL_PTR)
139 { 139 {
140 /* pick up the external memory block configured */ 140 /* pick up the external memory block configured */
141 hwiPool = (HwiP_nonOs *) gOsal_HwAttrs.extHwiPBlock.base; 141 hwiPool = (HwiP_nonOs *) gOsal_HwAttrs.extHwiPBlock.base;
@@ -149,9 +149,9 @@ HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn,
149 maxHwi = OSAL_NONOS_CONFIGNUM_HWI; 149 maxHwi = OSAL_NONOS_CONFIGNUM_HWI;
150 } 150 }
151 151
152 if (params == NULL) 152 if (params == NULL_PTR)
153 { 153 {
154 return (NULL); 154 return (NULL_PTR);
155 } 155 }
156 156
157 key = OsalArch_globalDisableInterrupt(); 157 key = OsalArch_globalDisableInterrupt();
@@ -170,7 +170,7 @@ HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn,
170 } 170 }
171 else 171 else
172 { 172 {
173 retHandle = (HwiP_Handle)(NULL); 173 retHandle = (HwiP_Handle)(NULL_PTR);
174 } 174 }
175 175
176 176
@@ -196,7 +196,7 @@ HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn,
196 intrParams.triggerType = INTC_TRIG_HIGH_LEVEL; 196 intrParams.triggerType = INTC_TRIG_HIGH_LEVEL;
197 break; 197 break;
198 } 198 }
199 if (hwi_handle != (Hwi_Struct *) NULL) 199 if (hwi_handle != (Hwi_Struct *) NULL_PTR)
200 { 200 {
201 /* Record the hwiFxn and argument */ 201 /* Record the hwiFxn and argument */
202 hwi_handle->arg = (void*) params->arg; 202 hwi_handle->arg = (void*) params->arg;
@@ -267,7 +267,7 @@ void osalArch_TimestampInit(void)
267 timerParams.period = 1000000u; 267 timerParams.period = 1000000u;
268 timerHandle = TimerP_create(TimerP_ANY, (TimerP_Fxn)&osalArch_TimestampCcntAutoRefresh, &timerParams); 268 timerHandle = TimerP_create(TimerP_ANY, (TimerP_Fxn)&osalArch_TimestampCcntAutoRefresh, &timerParams);
269 269
270 if ( timerHandle != (TimerP_Handle) NULL) 270 if ( timerHandle != (TimerP_Handle) NULL_PTR)
271 { 271 {
272 /* start the timer */ 272 /* start the timer */
273 TimerP_start(timerHandle); 273 TimerP_start(timerHandle);
@@ -283,7 +283,7 @@ void osalArch_TimestampGet64(TimeStamp_Struct *tStamp)
283 uint32_t lo, ovsrStatus; 283 uint32_t lo, ovsrStatus;
284 uintptr_t key; 284 uintptr_t key;
285 285
286 if (tStamp != (TimeStamp_Struct *) NULL) 286 if (tStamp != (TimeStamp_Struct *) NULL_PTR)
287 { 287 {
288 key = HwiP_disable(); 288 key = HwiP_disable();
289 /* Make sure init is done, if not done already */ 289 /* Make sure init is done, if not done already */
diff --git a/arch/core/a9/osalgic.c b/arch/core/a9/osalgic.c
index cb5f1da..e0bc47a 100644
--- a/arch/core/a9/osalgic.c
+++ b/arch/core/a9/osalgic.c
@@ -73,6 +73,7 @@
73#include "cpu.h" 73#include "cpu.h"
74#include "console_utils.h" 74#include "console_utils.h"
75#include "osalgic.h" 75#include "osalgic.h"
76#include <ti/csl/tistdtypes.h>
76 77
77/* ========================================================================== */ 78/* ========================================================================== */
78/* Macros & Typedefs */ 79/* Macros & Typedefs */
@@ -200,7 +201,7 @@ int32_t INTCConfigIntr(uint32_t intrNum, intcIntrParams_t *pIntrParams,
200 /* Validate the parameters. SGI can't be configured */ 201 /* Validate the parameters. SGI can't be configured */
201 if ((intrNum > GIC_MAX_INTR_NO) || 202 if ((intrNum > GIC_MAX_INTR_NO) ||
202 (pIntrParams->priority > GIC_CPU_INTF_MIN_PRI) || 203 (pIntrParams->priority > GIC_CPU_INTF_MIN_PRI) ||
203 (pIntrParams->pFnIntrHandler == NULL) || 204 (pIntrParams->pFnIntrHandler == NULL_PTR) ||
204 /* Priority value is not given in the levels supported */ 205 /* Priority value is not given in the levels supported */
205 (pIntrParams->priority % gicInst->noPriorityStep != 0)) 206 (pIntrParams->priority % gicInst->noPriorityStep != 0))
206 status = E_INVALID_PARAM; 207 status = E_INVALID_PARAM;
@@ -290,7 +291,7 @@ int32_t INTCConfigIntr(uint32_t intrNum, intcIntrParams_t *pIntrParams,
290 291
291int32_t INTCEnableIntr(uint32_t intrNum) 292int32_t INTCEnableIntr(uint32_t intrNum)
292{ 293{
293 gicData_t *gicInst = NULL; 294 gicData_t *gicInst = NULL_PTR;
294 uint32_t distBaseAddr = 0; 295 uint32_t distBaseAddr = 0;
295 int32_t status = S_PASS; 296 int32_t status = S_PASS;
296 297
@@ -308,7 +309,7 @@ int32_t INTCEnableIntr(uint32_t intrNum)
308 309
309int32_t INTCDisableIntr(uint32_t intrNum) 310int32_t INTCDisableIntr(uint32_t intrNum)
310{ 311{
311 gicData_t *gicInst = NULL; 312 gicData_t *gicInst = NULL_PTR;
312 uint32_t distBaseAddr = 0; 313 uint32_t distBaseAddr = 0;
313 int32_t status = S_PASS; 314 int32_t status = S_PASS;
314 315
@@ -392,7 +393,7 @@ int32_t INTCTriggerIpcIntr(uint32_t intrNum, uint32_t cpuId)
392{ 393{
393 uint32_t sgiVal = 0; 394 uint32_t sgiVal = 0;
394 int32_t status = S_PASS; 395 int32_t status = S_PASS;
395 gicData_t *gicInst = NULL; 396 gicData_t *gicInst = NULL_PTR;
396 uint32_t distBaseAddr = 0; 397 uint32_t distBaseAddr = 0;
397 398
398 /* Valid interrupt numbers are 0-15 */ 399 /* Valid interrupt numbers are 0-15 */
@@ -710,7 +711,7 @@ static void InitGicCpu(uint32_t isCpuSecure)
710 * Note: Make sure the CPU is in secure state when configuring secure 711 * Note: Make sure the CPU is in secure state when configuring secure
711 * registers, otherwise you may get an abort. 712 * registers, otherwise you may get an abort.
712 */ 713 */
713 if ((NULL != secureConfig) && (gicInst->isSecExtnSupp) && isCpuSecure) 714 if ((NULL_PTR != secureConfig) && (gicInst->isSecExtnSupp) && isCpuSecure)
714 { 715 {
715 /* Core interrupt selection (FIQ/IRQ) for secure interrupts */ 716 /* Core interrupt selection (FIQ/IRQ) for secure interrupts */
716 ctrlConfigval = ( 717 ctrlConfigval = (
diff --git a/arch/core/arm9/Arch_util.c b/arch/core/arm9/Arch_util.c
index 3f4b005..9caf263 100644
--- a/arch/core/arm9/Arch_util.c
+++ b/arch/core/arm9/Arch_util.c
@@ -38,10 +38,11 @@
38#include <stdbool.h> 38#include <stdbool.h>
39#include <stdlib.h> 39#include <stdlib.h>
40#include <ti/osal/src/nonos/Nonos_config.h> 40#include <ti/osal/src/nonos/Nonos_config.h>
41#include <ti/csl/tistdtypes.h>
41 42
42/* Local structure definition */ 43/* Local structure definition */
43typedef struct HwiP_nonOs_s { 44typedef struct HwiP_nonOs_s {
44 Bool used; 45 bool used;
45 Hwi_Struct hwi; 46 Hwi_Struct hwi;
46} HwiP_nonOs; 47} HwiP_nonOs;
47 48
@@ -64,7 +65,7 @@ void OsalArch_compileTime_SizeChk(void)
64/* TI compiler */ 65/* TI compiler */
65#pragma diag_suppress 179 66#pragma diag_suppress 179
66#endif 67#endif
67 OSAL_COMPILE_TIME_SIZE_CHECK (sizeof(HwiP_nonOs) < OSAL_NONOS_HWIP_SIZE_BYTES); 68 OSAL_COMPILE_TIME_SIZE_CHECK (sizeof(HwiP_nonOs),OSAL_NONOS_HWIP_SIZE_BYTES);
68#if defined(__GNUC__) && !defined(__ti__) 69#if defined(__GNUC__) && !defined(__ti__)
69#pragma GCC diagnostic pop 70#pragma GCC diagnostic pop
70#endif 71#endif
@@ -106,7 +107,7 @@ void OsalArch_globalRestoreInterrupt (uintptr_t restoreValue)
106 107
107/* Below function registers the interrupt for a given ISR */ 108/* Below function registers the interrupt for a given ISR */
108HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn, 109HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn,
109 HwiP_Params *params) 110 const HwiP_Params *params)
110{ 111{
111 uint32_t i; 112 uint32_t i;
112 uint32_t channelNo; 113 uint32_t channelNo;
@@ -120,7 +121,7 @@ HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn,
120 /* Check if user has specified any memory block to be used, which gets 121 /* Check if user has specified any memory block to be used, which gets
121 * the precedence over the internal static memory block 122 * the precedence over the internal static memory block
122 */ 123 */
123 if (gOsal_HwAttrs.extHwiPBlock.base != (uintptr_t)NULL) 124 if (gOsal_HwAttrs.extHwiPBlock.base != (uintptr_t)NULL_PTR)
124 { 125 {
125 /* pick up the external memory block configured */ 126 /* pick up the external memory block configured */
126 hwiPool = (HwiP_nonOs *) gOsal_HwAttrs.extHwiPBlock.base; 127 hwiPool = (HwiP_nonOs *) gOsal_HwAttrs.extHwiPBlock.base;
@@ -134,9 +135,9 @@ HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn,
134 maxHwi = OSAL_NONOS_CONFIGNUM_HWI; 135 maxHwi = OSAL_NONOS_CONFIGNUM_HWI;
135 } 136 }
136 137
137 if (params == NULL) 138 if (params == NULL_PTR)
138 { 139 {
139 return (NULL); 140 return (NULL_PTR);
140 } 141 }
141 142
142 key = OsalArch_globalDisableInterrupt(); 143 key = OsalArch_globalDisableInterrupt();
@@ -154,10 +155,10 @@ HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn,
154 } 155 }
155 else 156 else
156 { 157 {
157 retHandle = (HwiP_Handle)(NULL); 158 retHandle = (HwiP_Handle)(NULL_PTR);
158 } 159 }
159 160
160 if (retHandle != (HwiP_Handle) NULL) 161 if (retHandle != (HwiP_Handle) NULL_PTR)
161 { 162 {
162 Intc_Init(); 163 Intc_Init();
163 164
diff --git a/arch/core/c6x/Arch_util.c b/arch/core/c6x/Arch_util.c
index 5300250..931b0e0 100644
--- a/arch/core/c6x/Arch_util.c
+++ b/arch/core/c6x/Arch_util.c
@@ -33,21 +33,24 @@
33 * ======== HwiP_tirtos.c ======== 33 * ======== HwiP_tirtos.c ========
34 */ 34 */
35 35
36#include <c6x.h>
36 37
37#include <stdint.h> 38#include <stdint.h>
38#include <stdbool.h> 39#include <stdbool.h>
39#include <stdlib.h> 40#include <stdlib.h>
41#include <string.h>
40#include <ti/csl/csl_tsc.h> 42#include <ti/csl/csl_tsc.h>
41#include <ti/osal/src/nonos/Nonos_config.h> 43#include <ti/osal/src/nonos/Nonos_config.h>
44#include <ti/csl/tistdtypes.h>
42 45
43/* Local structure definition */ 46/* Local structure definition */
44typedef struct HwiP_nonOs_s { 47typedef struct HwiP_nonOs_s {
45 Bool used; 48 bool used;
46 Hwi_Struct hwi; 49 Hwi_Struct hwi;
47} HwiP_nonOs; 50} HwiP_nonOs;
48 51
49/* Local hwi structures */ 52/* Local hwi structures */
50static HwiP_nonOs hwiStructs[OSAL_NONOS_CONFIGNUM_HWI] = {{0}}; 53static HwiP_nonOs hwiStructs[OSAL_NONOS_CONFIGNUM_HWI];
51 54
52 55
53/* 56/*
@@ -58,25 +61,25 @@ static HwiP_nonOs hwiStructs[OSAL_NONOS_CONFIGNUM_HWI] = {{0}};
58void OsalArch_compileTime_SizeChk(void) 61void OsalArch_compileTime_SizeChk(void)
59{ 62{
60 #pragma diag_suppress 179 63 #pragma diag_suppress 179
61 OSAL_COMPILE_TIME_SIZE_CHECK (sizeof(HwiP_nonOs) < OSAL_NONOS_HWIP_SIZE_BYTES); 64 OSAL_COMPILE_TIME_SIZE_CHECK ((uint32_t)sizeof(HwiP_nonOs),OSAL_NONOS_HWIP_SIZE_BYTES);
62} 65}
63 66
64static bool gFirstTime = FALSE; 67static bool gFirstTime = (bool)false;
65static CSL_IntcContext gContext; 68static CSL_IntcContext gContext;
66static CSL_IntcEventHandlerRecord gEventRecord[OSAL_NONOS_CONFIGNUM_HWI]; 69static CSL_IntcEventHandlerRecord gEventRecord[OSAL_NONOS_CONFIGNUM_HWI];
67static bool gTimestampFirstTime = TRUE; 70static bool gTimestampFirstTime = (bool)true;
68 71static bool gHwiInitialized = (bool)false;
69/* This function enables the interrupt for a given interrupt number */ 72/* This function enables the interrupt for a given interrupt number */
70void OsalArch_enableInterrupt(uint32_t intNum) 73void OsalArch_enableInterrupt(uint32_t intNum)
71{ 74{
72 CSL_intcInterruptEnable((CSL_IntcVectId)intNum); 75 (void)CSL_intcInterruptEnable((CSL_IntcVectId)intNum);
73 return; 76 return;
74} 77}
75 78
76/* This function disables the interrupt for a given interrupt number */ 79/* This function disables the interrupt for a given interrupt number */
77void OsalArch_disableInterrupt(uint32_t intNum) 80void OsalArch_disableInterrupt(uint32_t intNum)
78{ 81{
79 CSL_intcInterruptDisable((CSL_IntcVectId)intNum); 82 (void)CSL_intcInterruptDisable((CSL_IntcVectId)intNum);
80 return; 83 return;
81} 84}
82 85
@@ -95,14 +98,14 @@ uintptr_t OsalArch_globalDisableInterrupt(void)
95/* Below function globally restore interrupt in the chip level */ 98/* Below function globally restore interrupt in the chip level */
96void OsalArch_globalRestoreInterrupt (uintptr_t restoreValue) 99void OsalArch_globalRestoreInterrupt (uintptr_t restoreValue)
97{ 100{
98 _restore_interrupts(restoreValue); 101 (void)_restore_interrupts(restoreValue);
99} 102}
100 103
101/* Below function registers the interrupt for a given ISR */ 104/* Below function registers the interrupt for a given ISR */
102HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn, 105HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn,
103 HwiP_Params *params) 106 const HwiP_Params *params)
104{ 107{
105 Hwi_Struct *hwi_handle = (Hwi_Struct *) NULL; 108 Hwi_Struct *hwi_handle = NULL_PTR;
106 CSL_IntcParam vectId; 109 CSL_IntcParam vectId;
107 110
108 uint32_t i; 111 uint32_t i;
@@ -116,7 +119,7 @@ HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn,
116 /* Check if user has specified any memory block to be used, which gets 119 /* Check if user has specified any memory block to be used, which gets
117 * the precedence over the internal static memory block 120 * the precedence over the internal static memory block
118 */ 121 */
119 if (gOsal_HwAttrs.extHwiPBlock.base != (uintptr_t)NULL) 122 if (gOsal_HwAttrs.extHwiPBlock.base != 0U)
120 { 123 {
121 /* pick up the external memory block configured */ 124 /* pick up the external memory block configured */
122 hwiPool = (HwiP_nonOs *) gOsal_HwAttrs.extHwiPBlock.base; 125 hwiPool = (HwiP_nonOs *) gOsal_HwAttrs.extHwiPBlock.base;
@@ -128,75 +131,85 @@ HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn,
128 /* Pick up the internal static memory block */ 131 /* Pick up the internal static memory block */
129 hwiPool = (HwiP_nonOs *) &hwiStructs[0]; 132 hwiPool = (HwiP_nonOs *) &hwiStructs[0];
130 maxHwi = OSAL_NONOS_CONFIGNUM_HWI; 133 maxHwi = OSAL_NONOS_CONFIGNUM_HWI;
131 } 134
132 135 if(gHwiInitialized==(bool)false)
133 if (params == NULL) 136 {
134 { 137 /* Initializing the first time */
135 return (NULL); 138 (void)memset((void *)hwiStructs,0,sizeof(hwiStructs));
136 } 139 gHwiInitialized = (bool)true;
137
138 key = OsalArch_globalDisableInterrupt();
139 for (i = 0u; i < maxHwi; i++) {
140 if (hwiPool[i].used == FALSE) {
141 hwiPool[i].used = TRUE;
142 break;
143 } 140 }
144 } 141 }
145 OsalArch_globalRestoreInterrupt(key);
146 142
147 if (i != maxHwi) 143 if (params == NULL_PTR)
148 { 144 {
149 hwi_handle = &(hwiPool[i].hwi); 145 retHandle = NULL_PTR;
150 retHandle = (HwiP_Handle)&hwiPool[i];
151 } 146 }
152 else 147 else
153 { 148 {
154 retHandle = (HwiP_Handle)(NULL); 149
155 } 150 key = OsalArch_globalDisableInterrupt();
156 151 for (i = 0u; i < maxHwi; i++)
157 if (hwi_handle != (Hwi_Struct *) NULL) 152 {
153 if (hwiPool[i].used == (bool)false) {
154 hwiPool[i].used = (bool)true;
155 break;
156 }
157 }
158 OsalArch_globalRestoreInterrupt(key);
159
160 if (i != maxHwi)
161 {
162 hwi_handle = &(hwiPool[i].hwi);
163 retHandle = (HwiP_Handle)&hwiPool[i];
164 }
165 else
166 {
167 retHandle = NULL_PTR;
168 }
169 }
170 if (hwi_handle != NULL_PTR)
158 { 171 {
159 if (gFirstTime == FALSE) { 172 if (gFirstTime == (bool)false) {
160 /* record the index in the handle */ 173 /* record the index in the handle */
161 gContext.numEvtEntries = OSAL_NONOS_CONFIGNUM_HWI; 174 gContext.numEvtEntries = (Uint16)OSAL_NONOS_CONFIGNUM_HWI;
162 gContext.eventhandlerRecord = gEventRecord; 175 gContext.eventhandlerRecord = gEventRecord;
163 CSL_intcInit(&gContext); 176 (void)CSL_intcInit(&gContext);
164 gFirstTime = TRUE; 177 gFirstTime = (bool)true;
165 } 178 }
166 179
167 CSL_intcGlobalNmiEnable(); 180 (void)CSL_intcGlobalNmiEnable();
168 CSL_intcGlobalEnable(NULL); 181 (void)CSL_intcGlobalEnable(NULL_PTR);
169 182
170 vectId = (CSL_IntcParam)interruptNum; 183 vectId = (CSL_IntcParam)interruptNum;
171 hwi_handle->handle = CSL_intcOpen (&hwi_handle->intcObj, params->evtId, &vectId, NULL); 184 hwi_handle->handle = CSL_intcOpen (&hwi_handle->intcObj, (CSL_IntcEventId)params->evtId, &vectId, NULL_PTR);
172 185
173 if(hwi_handle->handle != NULL) 186 if(hwi_handle->handle != NULL_PTR)
174 { 187 {
175 CSL_IntcEventHandlerRecord evtHandler; 188 CSL_IntcEventHandlerRecord evtHandler;
176 evtHandler.handler = (CSL_IntcEventHandler)hwiFxn; 189 evtHandler.handler = (CSL_IntcEventHandler)hwiFxn;
177 evtHandler.arg = (void *) params->arg; 190 evtHandler.arg = (CSL_IntcEventHandler) params->arg;
178 191
179 CSL_intcPlugEventHandler(hwi_handle->handle, &evtHandler); 192 (void)CSL_intcPlugEventHandler(hwi_handle->handle, &evtHandler);
180 CSL_intcHwControl(hwi_handle->handle,CSL_INTC_CMD_EVTCLEAR,NULL); 193 (void)CSL_intcHwControl(hwi_handle->handle,CSL_INTC_CMD_EVTCLEAR,NULL_PTR);
181 CSL_intcHwControl(hwi_handle->handle,CSL_INTC_CMD_EVTENABLE,NULL); 194 (void)CSL_intcHwControl(hwi_handle->handle,CSL_INTC_CMD_EVTENABLE,NULL_PTR);
182 195
183 /* Enabling the interrupt if configured */ 196 /* Enabling the interrupt if configured */
184 if (params->enableIntr == TRUE) 197 if (params->enableIntr == 1U)
185 { 198 {
186 /* Enabling the interrupt in INTC. */ 199 /* Enabling the interrupt in INTC. */
187 OsalArch_enableInterrupt(interruptNum); 200 OsalArch_enableInterrupt((uint32_t)interruptNum);
188 } 201 }
189 else 202 else
190 { 203 {
191 /* Disabling the interrupt in INTC. */ 204 /* Disabling the interrupt in INTC. */
192 OsalArch_disableInterrupt(interruptNum); 205 OsalArch_disableInterrupt((uint32_t)interruptNum);
193 } 206 }
194 } 207 }
195 else 208 else
196 { 209 {
197 /* Free the pool */ 210 /* Free the pool */
198 hwiPool[i].used = FALSE; 211 hwiPool[i].used = (bool)false;
199 retHandle = (HwiP_Handle *) NULL; 212 retHandle = NULL_PTR;
200 } 213 }
201 } 214 }
202 215
@@ -212,7 +225,7 @@ HwiP_Status OsalArch_HwiPDelete(HwiP_Handle handle)
212 225
213 /* mark that handle as free */ 226 /* mark that handle as free */
214 key = OsalArch_globalDisableInterrupt(); 227 key = OsalArch_globalDisableInterrupt();
215 hwi_hnd->used = FALSE; 228 hwi_hnd->used = (bool)false;
216 OsalArch_globalRestoreInterrupt(key); 229 OsalArch_globalRestoreInterrupt(key);
217 status = CSL_intcClose(hwi_hnd->hwi.handle); 230 status = CSL_intcClose(hwi_hnd->hwi.handle);
218 231
@@ -234,12 +247,12 @@ HwiP_Status OsalArch_HwiPDelete(HwiP_Handle handle)
234HwiP_Handle OsalArch_getHandle(int32_t interruptNum) 247HwiP_Handle OsalArch_getHandle(int32_t interruptNum)
235{ 248{
236 uint32_t i; 249 uint32_t i;
237 Hwi_Struct *handle=NULL,*handle_temp; 250 Hwi_Struct *handle=NULL_PTR,*handle_temp;
238 uintptr_t temp; 251 uintptr_t temp;
239 HwiP_nonOs *hwiPool; 252 HwiP_nonOs *hwiPool;
240 uint32_t maxHwi = 0; 253 uint32_t maxHwi = 0;
241 254
242 if (gOsal_HwAttrs.extHwiPBlock.base != (uintptr_t)NULL) 255 if (gOsal_HwAttrs.extHwiPBlock.base != 0U)
243 { 256 {
244 /* pick up the external memory block configured */ 257 /* pick up the external memory block configured */
245 hwiPool = (HwiP_nonOs *) gOsal_HwAttrs.extHwiPBlock.base; 258 hwiPool = (HwiP_nonOs *) gOsal_HwAttrs.extHwiPBlock.base;
@@ -253,15 +266,15 @@ HwiP_Handle OsalArch_getHandle(int32_t interruptNum)
253 maxHwi = OSAL_NONOS_CONFIGNUM_HWI; 266 maxHwi = OSAL_NONOS_CONFIGNUM_HWI;
254 } 267 }
255 268
256 /* Fetch it if it is already allocated, else return NULL */ 269 /* Fetch it if it is already allocated, else return NULL_PTR */
257 /* Go through the list and find out if there is an HWI whose interrupt number matches */ 270 /* Go through the list and find out if there is an HWI whose interrupt number matches */
258 271
259 /* First go through the external memory pool */ 272 /* First go through the external memory pool */
260 for (i = 0; i < maxHwi; i++) 273 for (i = 0; i < maxHwi; i++)
261 { 274 {
262 if(hwiPool[i].used == TRUE) { 275 if(hwiPool[i].used == (bool)true) {
263 handle_temp=&hwiPool[i].hwi; 276 handle_temp=&hwiPool[i].hwi;
264 if(handle_temp->intcObj.vectId==interruptNum) { 277 if(handle_temp->intcObj.vectId==(CSL_IntcVectId)interruptNum) {
265 handle=handle_temp; 278 handle=handle_temp;
266 break; 279 break;
267 } 280 }
@@ -269,12 +282,12 @@ HwiP_Handle OsalArch_getHandle(int32_t interruptNum)
269 } 282 }
270 283
271 /* Now check the internal static pool, if not found already */ 284 /* Now check the internal static pool, if not found already */
272 if (handle != (HwiP_Handle) NULL) 285 if (handle != NULL_PTR)
273 { 286 {
274 for(i=0;i<OSAL_NONOS_CONFIGNUM_HWI;i++) { 287 for(i=0;i<OSAL_NONOS_CONFIGNUM_HWI;i++) {
275 if(hwiStructs[i].used == TRUE) { 288 if(hwiStructs[i].used == (bool)true) {
276 handle_temp=&hwiStructs[i].hwi; 289 handle_temp=&hwiStructs[i].hwi;
277 if(handle_temp->intcObj.vectId==interruptNum) { 290 if(handle_temp->intcObj.vectId==(CSL_IntcVectId)interruptNum) {
278 handle=handle_temp; 291 handle=handle_temp;
279 break; 292 break;
280 } 293 }
@@ -290,14 +303,14 @@ HwiP_Handle OsalArch_getHandle(int32_t interruptNum)
290int32_t OsalArch_getEventId(int32_t interruptNum) 303int32_t OsalArch_getEventId(int32_t interruptNum)
291{ 304{
292 Hwi_Struct *handle; 305 Hwi_Struct *handle;
306 int32_t retVal=-1;
293 /* Find the handle registered to this interrupt number */ 307 /* Find the handle registered to this interrupt number */
294 handle=(Hwi_Struct *)OsalArch_getHandle(interruptNum); 308 handle=(Hwi_Struct *)OsalArch_getHandle(interruptNum);
295 if(handle!=NULL) { 309 if(handle!=NULL_PTR) {
296 return(handle->intcObj.eventId); 310 retVal = handle->intcObj.eventId;
297 } else { 311 }
298 return(-1);
299 }
300 312
313 return(retVal);
301} 314}
302 315
303/* Return the cycle frequency used for timeStamp */ 316/* Return the cycle frequency used for timeStamp */
@@ -310,11 +323,11 @@ int32_t osalArch_TimeStampGetFreqKHz(void)
310/* Initialize the time stamp module */ 323/* Initialize the time stamp module */
311void osalArch_TimestampInit(void) 324void osalArch_TimestampInit(void)
312{ 325{
313 if (gTimestampFirstTime == TRUE) 326 if (gTimestampFirstTime == (bool)true)
314 { 327 {
315 /* Initialize TSCL to 0, for count */ 328 /* Initialize TSCL to 0, for count */
316 CSL_tscEnable(); 329 CSL_tscEnable();
317 gTimestampFirstTime = FALSE; 330 gTimestampFirstTime = (bool)false;
318 } 331 }
319 332
320 return; 333 return;
diff --git a/arch/core/c6x/CacheP_nonos.c b/arch/core/c6x/CacheP_nonos.c
index 2fdfd5b..35b9627 100644
--- a/arch/core/c6x/CacheP_nonos.c
+++ b/arch/core/c6x/CacheP_nonos.c
@@ -42,48 +42,48 @@
42 42
43void CacheP_wb(const void * addr, int32_t size) 43void CacheP_wb(const void * addr, int32_t size)
44{ 44{
45 uint32_t alignedAddr = (uint32_t)addr & ~((uint32_t)0x3u); 45 uintptr_t alignedAddr = (uintptr_t)addr & ~((uintptr_t)0x3u);
46 uint32_t alignedSize = (uint32_t)size + (uint32_t)addr - (uint32_t)alignedAddr; 46 uint32_t alignedSize = (uint32_t)size + (uint32_t)((uintptr_t)addr - (uintptr_t)alignedAddr);
47 uint32_t block_addr=alignedAddr; 47 uintptr_t block_addr=alignedAddr;
48 int32_t size_remaining=alignedSize; 48 int32_t size_remaining=(int32_t)alignedSize;
49 uint32_t bytes_count; 49 uint32_t bytes_count;
50 50
51 while(size_remaining > 0) { 51 while(size_remaining > 0) {
52 bytes_count = (size_remaining > CACHE_L2_LINESIZE )? CACHE_L2_LINESIZE:size_remaining; 52 bytes_count = ((uint32_t)size_remaining > CACHE_L2_LINESIZE )? CACHE_L2_LINESIZE:(uint32_t)size_remaining;
53 CACHE_wbL2((void *)block_addr,bytes_count,CACHE_WAIT); 53 CACHE_wbL2((void *)block_addr,bytes_count,CACHE_WAIT);
54 size_remaining-=CACHE_L2_LINESIZE; 54 size_remaining-=(int32_t)CACHE_L2_LINESIZE;
55 block_addr+=CACHE_L2_LINESIZE; 55 block_addr+=CACHE_L2_LINESIZE;
56 } 56 }
57} 57}
58 58
59void CacheP_wbInv(const void * addr, int32_t size) 59void CacheP_wbInv(const void * addr, int32_t size)
60{ 60{
61 uint32_t alignedAddr = (uint32_t)addr & ~((uint32_t)0x3u); 61 uintptr_t alignedAddr = (uintptr_t)addr & ~((uintptr_t)0x3u);
62 uint32_t alignedSize = (uint32_t)size + (uint32_t)addr - (uint32_t)alignedAddr; 62 uint32_t alignedSize = (uint32_t)size + (uint32_t)((uintptr_t)addr - (uintptr_t)alignedAddr);
63 uint32_t block_addr=alignedAddr; 63 uintptr_t block_addr=alignedAddr;
64 int32_t size_remaining=alignedSize; 64 int32_t size_remaining=(int32_t)alignedSize;
65 uint32_t bytes_count; 65 uint32_t bytes_count;
66 66
67 while(size_remaining > 0) { 67 while(size_remaining > 0) {
68 bytes_count = (size_remaining > CACHE_L2_LINESIZE )? CACHE_L2_LINESIZE:size_remaining; 68 bytes_count = ((uint32_t)size_remaining > CACHE_L2_LINESIZE )? CACHE_L2_LINESIZE:(uint32_t)size_remaining;
69 CACHE_wbInvL2((void *)block_addr,bytes_count,CACHE_WAIT); 69 CACHE_wbInvL2((void *)block_addr,bytes_count,CACHE_WAIT);
70 size_remaining-=CACHE_L2_LINESIZE; 70 size_remaining-=(int32_t)CACHE_L2_LINESIZE;
71 block_addr+=CACHE_L2_LINESIZE; 71 block_addr+=CACHE_L2_LINESIZE;
72 } 72 }
73} 73}
74 74
75void CacheP_Inv(const void * addr, int32_t size) 75void CacheP_Inv(const void * addr, int32_t size)
76{ 76{
77 uint32_t alignedAddr = (uint32_t)addr & ~((uint32_t)0x3u); 77 uintptr_t alignedAddr = (uintptr_t)addr & ~((uintptr_t)0x3u);
78 uint32_t alignedSize = (uint32_t)size + (uint32_t)addr - (uint32_t)alignedAddr; 78 uint32_t alignedSize = (uint32_t)size + (uint32_t)((uintptr_t)addr - (uintptr_t)alignedAddr);
79 uint32_t block_addr=alignedAddr; 79 uintptr_t block_addr=alignedAddr;
80 int32_t size_remaining=alignedSize; 80 int32_t size_remaining=(int32_t)alignedSize;
81 uint32_t bytes_count; 81 uint32_t bytes_count;
82 82
83 while(size_remaining > 0) { 83 while(size_remaining > 0) {
84 bytes_count = (size_remaining > CACHE_L2_LINESIZE )? CACHE_L2_LINESIZE:size_remaining; 84 bytes_count = ((uint32_t)size_remaining > CACHE_L2_LINESIZE )? CACHE_L2_LINESIZE:(uint32_t)size_remaining;
85 CACHE_invL2((void *)block_addr,bytes_count,CACHE_WAIT); 85 CACHE_invL2((void *)block_addr,bytes_count,CACHE_WAIT);
86 size_remaining-=CACHE_L2_LINESIZE; 86 size_remaining-=(int32_t)CACHE_L2_LINESIZE;
87 block_addr+=CACHE_L2_LINESIZE; 87 block_addr+=CACHE_L2_LINESIZE;
88 } 88 }
89} 89}
diff --git a/arch/core/c7x/Arch_util.c b/arch/core/c7x/Arch_util.c
index 55d0e66..b6d0f5f 100644
--- a/arch/core/c7x/Arch_util.c
+++ b/arch/core/c7x/Arch_util.c
@@ -38,6 +38,7 @@
38#include <stdbool.h> 38#include <stdbool.h>
39#include <stdlib.h> 39#include <stdlib.h>
40#include <ti/osal/src/nonos/Nonos_config.h> 40#include <ti/osal/src/nonos/Nonos_config.h>
41#include <ti/csl/tistdtypes.h>
41 42
42/* Local structure definition */ 43/* Local structure definition */
43typedef struct HwiP_nonOs_s { 44typedef struct HwiP_nonOs_s {
@@ -57,7 +58,7 @@ static HwiP_nonOs hwiStructs[OSAL_NONOS_CONFIGNUM_HWI] = {{0}};
57void OsalArch_compileTime_SizeChk(void) 58void OsalArch_compileTime_SizeChk(void)
58{ 59{
59 #pragma diag_suppress 179 60 #pragma diag_suppress 179
60 OSAL_COMPILE_TIME_SIZE_CHECK (sizeof(HwiP_nonOs) < OSAL_NONOS_HWIP_SIZE_BYTES); 61 OSAL_COMPILE_TIME_SIZE_CHECK (sizeof(HwiP_nonOs),OSAL_NONOS_HWIP_SIZE_BYTES);
61} 62}
62 63
63static bool gFirstTime = FALSE; 64static bool gFirstTime = FALSE;
@@ -100,9 +101,9 @@ void OsalArch_globalRestoreInterrupt (uintptr_t restoreValue)
100 101
101/* Below function registers the interrupt for a given ISR */ 102/* Below function registers the interrupt for a given ISR */
102HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn, 103HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn,
103 HwiP_Params *params) 104 const HwiP_Params *params)
104{ 105{
105 Hwi_Struct *hwi_handle = (Hwi_Struct *) NULL; 106 Hwi_Struct *hwi_handle = (Hwi_Struct *) NULL_PTR;
106 //CSL_IntcParam vectId; 107 //CSL_IntcParam vectId;
107 108
108 uint32_t i; 109 uint32_t i;
@@ -116,7 +117,7 @@ HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn,
116 /* Check if user has specified any memory block to be used, which gets 117 /* Check if user has specified any memory block to be used, which gets
117 * the precedence over the internal static memory block 118 * the precedence over the internal static memory block
118 */ 119 */
119 if (gOsal_HwAttrs.extHwiPBlock.base != (uintptr_t)NULL) 120 if (gOsal_HwAttrs.extHwiPBlock.base != (uintptr_t)NULL_PTR)
120 { 121 {
121 /* pick up the external memory block configured */ 122 /* pick up the external memory block configured */
122 hwiPool = (HwiP_nonOs *) gOsal_HwAttrs.extHwiPBlock.base; 123 hwiPool = (HwiP_nonOs *) gOsal_HwAttrs.extHwiPBlock.base;
@@ -130,9 +131,9 @@ HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn,
130 maxHwi = OSAL_NONOS_CONFIGNUM_HWI; 131 maxHwi = OSAL_NONOS_CONFIGNUM_HWI;
131 } 132 }
132 133
133 if (params == NULL) 134 if (params == NULL_PTR)
134 { 135 {
135 return (NULL); 136 return (NULL_PTR);
136 } 137 }
137 138
138 key = OsalArch_globalDisableInterrupt(); 139 key = OsalArch_globalDisableInterrupt();
@@ -151,10 +152,10 @@ HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn,
151 } 152 }
152 else 153 else
153 { 154 {
154 retHandle = (HwiP_Handle)(NULL); 155 retHandle = (HwiP_Handle)(NULL_PTR);
155 } 156 }
156 157
157 if (hwi_handle != (Hwi_Struct *) NULL) 158 if (hwi_handle != (Hwi_Struct *) NULL_PTR)
158 { 159 {
159 //if (gFirstTime == FALSE) { 160 //if (gFirstTime == FALSE) {
160 // /* record the index in the handle */ 161 // /* record the index in the handle */
@@ -167,26 +168,26 @@ HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn,
167 168
168 //TODO: Integrate to CSL once C7x arch is supported 169 //TODO: Integrate to CSL once C7x arch is supported
169 //CSL_intcGlobalNmiEnable(); 170 //CSL_intcGlobalNmiEnable();
170 //CSL_intcGlobalEnable(NULL); 171 //CSL_intcGlobalEnable(NULL_PTR);
171 //vectId = (CSL_IntcParam)interruptNum; 172 //vectId = (CSL_IntcParam)interruptNum;
172 // 173 //
173 //hwi_handle->handle = CSL_intcOpen (&hwi_handle->intcObj, params->evtId, &vectId, NULL); 174 //hwi_handle->handle = CSL_intcOpen (&hwi_handle->intcObj, params->evtId, &vectId, NULL_PTR);
174 // 175 //
175 //if(hwi_handle->handle != NULL) 176 //if(hwi_handle->handle != NULL_PTR)
176 //{ 177 //{
177 // CSL_IntcEventHandlerRecord evtHandler; 178 // CSL_IntcEventHandlerRecord evtHandler;
178 // evtHandler.handler = (CSL_IntcEventHandler)hwiFxn; 179 // evtHandler.handler = (CSL_IntcEventHandler)hwiFxn;
179 // evtHandler.arg = (void *) params->arg; 180 // evtHandler.arg = (void *) params->arg;
180 // 181 //
181 // CSL_intcPlugEventHandler(hwi_handle->handle, &evtHandler); 182 // CSL_intcPlugEventHandler(hwi_handle->handle, &evtHandler);
182 // CSL_intcHwControl(hwi_handle->handle,CSL_INTC_CMD_EVTCLEAR,NULL); 183 // CSL_intcHwControl(hwi_handle->handle,CSL_INTC_CMD_EVTCLEAR,NULL_PTR);
183 // CSL_intcHwControl(hwi_handle->handle,CSL_INTC_CMD_EVTENABLE,NULL); 184 // CSL_intcHwControl(hwi_handle->handle,CSL_INTC_CMD_EVTENABLE,NULL_PTR);
184 //} 185 //}
185 //else 186 //else
186 //{ 187 //{
187 // /* Free the pool */ 188 // /* Free the pool */
188 // hwiPool[i].used = FALSE; 189 // hwiPool[i].used = FALSE;
189 // retHandle = (HwiP_Handle *) NULL; 190 // retHandle = (HwiP_Handle *) NULL_PTR;
190 //} 191 //}
191 } 192 }
192 193
@@ -224,7 +225,7 @@ HwiP_Status OsalArch_HwiPDelete(HwiP_Handle handle)
224 */ 225 */
225HwiP_Handle OsalArch_getHandle(int32_t interruptNum) 226HwiP_Handle OsalArch_getHandle(int32_t interruptNum)
226{ 227{
227 Hwi_Struct *handle=NULL; 228 Hwi_Struct *handle=NULL_PTR;
228 return((HwiP_Handle)handle); 229 return((HwiP_Handle)handle);
229} 230}
230/* 231/*
diff --git a/arch/core/m4/Arch_util.c b/arch/core/m4/Arch_util.c
index b40bd80..25bbce0 100644
--- a/arch/core/m4/Arch_util.c
+++ b/arch/core/m4/Arch_util.c
@@ -39,6 +39,7 @@
39#include <stdlib.h> 39#include <stdlib.h>
40#include <ti/csl/csl_timer.h> 40#include <ti/csl/csl_timer.h>
41#include <ti/osal/src/nonos/Nonos_config.h> 41#include <ti/osal/src/nonos/Nonos_config.h>
42#include <ti/csl/tistdtypes.h>
42 43
43/* Local structure definition */ 44/* Local structure definition */
44typedef struct HwiP_nonOs_s { 45typedef struct HwiP_nonOs_s {
@@ -81,7 +82,7 @@ void OsalArch_compileTime_SizeChk(void)
81/* TI compiler */ 82/* TI compiler */
82#pragma diag_suppress 179 83#pragma diag_suppress 179
83#endif 84#endif
84 OSAL_COMPILE_TIME_SIZE_CHECK (sizeof(HwiP_nonOs) < OSAL_NONOS_HWIP_SIZE_BYTES); 85 OSAL_COMPILE_TIME_SIZE_CHECK (sizeof(HwiP_nonOs),OSAL_NONOS_HWIP_SIZE_BYTES);
85#if defined(__GNUC__) && !defined(__ti__) 86#if defined(__GNUC__) && !defined(__ti__)
86#pragma GCC diagnostic pop 87#pragma GCC diagnostic pop
87#endif 88#endif
@@ -121,7 +122,7 @@ void OsalArch_globalRestoreInterrupt (uintptr_t restoreValue)
121 122
122/* Below function registers the interrupt for a given ISR */ 123/* Below function registers the interrupt for a given ISR */
123HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn, 124HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn,
124 HwiP_Params *params) 125 const HwiP_Params *params)
125{ 126{
126 uint32_t i; 127 uint32_t i;
127 uintptr_t key; 128 uintptr_t key;
@@ -134,7 +135,7 @@ HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn,
134 /* Check if user has specified any memory block to be used, which gets 135 /* Check if user has specified any memory block to be used, which gets
135 * the precedence over the internal static memory block 136 * the precedence over the internal static memory block
136 */ 137 */
137 if (gOsal_HwAttrs.extHwiPBlock.base != (uintptr_t)NULL) 138 if (gOsal_HwAttrs.extHwiPBlock.base != (uintptr_t)NULL_PTR)
138 { 139 {
139 /* pick up the external memory block configured */ 140 /* pick up the external memory block configured */
140 hwiPool = (HwiP_nonOs *) gOsal_HwAttrs.extHwiPBlock.base; 141 hwiPool = (HwiP_nonOs *) gOsal_HwAttrs.extHwiPBlock.base;
@@ -148,9 +149,9 @@ HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn,
148 maxHwi = OSAL_NONOS_CONFIGNUM_HWI; 149 maxHwi = OSAL_NONOS_CONFIGNUM_HWI;
149 } 150 }
150 151
151 if (params == NULL) 152 if (params == NULL_PTR)
152 { 153 {
153 return (NULL); 154 return (NULL_PTR);
154 } 155 }
155 156
156 key = OsalArch_globalDisableInterrupt(); 157 key = OsalArch_globalDisableInterrupt();
@@ -168,10 +169,10 @@ HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn,
168 } 169 }
169 else 170 else
170 { 171 {
171 retHandle = (HwiP_Handle)(NULL); 172 retHandle = (HwiP_Handle)(NULL_PTR);
172 } 173 }
173 174
174 if (retHandle != (HwiP_Handle) NULL) 175 if (retHandle != (HwiP_Handle) NULL_PTR)
175 { 176 {
176 if (gFirstTime == TRUE) { 177 if (gFirstTime == TRUE) {
177 Intc_Init(); 178 Intc_Init();
@@ -251,7 +252,7 @@ void osalArch_TimestampInit(void)
251 timerParams.period = TimerP_MAX_PERIOD-1U; 252 timerParams.period = TimerP_MAX_PERIOD-1U;
252 timerHandle = TimerP_create(TimerP_ANY, (TimerP_Fxn)&osalArch_TimestampCcntAutoRefresh, &timerParams); 253 timerHandle = TimerP_create(TimerP_ANY, (TimerP_Fxn)&osalArch_TimestampCcntAutoRefresh, &timerParams);
253 254
254 if ( timerHandle != (TimerP_Handle) NULL) 255 if ( timerHandle != (TimerP_Handle) NULL_PTR)
255 { 256 {
256 Arch_TimerP_Struct *timer = (Arch_TimerP_Struct *) timerHandle; 257 Arch_TimerP_Struct *timer = (Arch_TimerP_Struct *) timerHandle;
257 gTimerBaseAddr = (uintptr_t)gDmTimerPInfoTbl[timer->timerId].baseAddr; 258 gTimerBaseAddr = (uintptr_t)gDmTimerPInfoTbl[timer->timerId].baseAddr;
@@ -269,7 +270,7 @@ void osalArch_TimestampGet64(TimeStamp_Struct *tStamp)
269{ 270{
270 uintptr_t key; 271 uintptr_t key;
271 272
272 if (tStamp != (TimeStamp_Struct *) NULL) 273 if (tStamp != (TimeStamp_Struct *) NULL_PTR)
273 { 274 {
274 key = HwiP_disable(); 275 key = HwiP_disable();
275 /* Make sure init is done, if not done already */ 276 /* Make sure init is done, if not done already */
diff --git a/arch/core/r5/Arch_util.c b/arch/core/r5/Arch_util.c
index 4980539..d30cb0d 100755
--- a/arch/core/r5/Arch_util.c
+++ b/arch/core/r5/Arch_util.c
@@ -37,6 +37,8 @@
37#include <stdint.h> 37#include <stdint.h>
38#include <stdbool.h> 38#include <stdbool.h>
39#include <stdlib.h> 39#include <stdlib.h>
40#include <string.h>
41#include <ti/csl/tistdtypes.h>
40#include <ti/csl/arch/r5/interrupt.h> 42#include <ti/csl/arch/r5/interrupt.h>
41#include <ti/osal/src/nonos/Nonos_config.h> 43#include <ti/osal/src/nonos/Nonos_config.h>
42 44
@@ -48,12 +50,12 @@
48/* Local hwi structures */ 50/* Local hwi structures */
49 51
50typedef struct HwiP_nonOs_s { 52typedef struct HwiP_nonOs_s {
51 Bool used; 53 bool used;
52 Hwi_Struct hwi; 54 Hwi_Struct hwi;
53} HwiP_nonOs; 55} HwiP_nonOs;
54 56
55/* Local hwi structures */ 57/* Local hwi structures */
56static HwiP_nonOs hwiStructs[OSAL_NONOS_CONFIGNUM_HWI] = {{0}}; 58static HwiP_nonOs hwiStructs[OSAL_NONOS_CONFIGNUM_HWI];
57 59
58/* local function */ 60/* local function */
59static void osalArch_TimestampCcntAutoRefresh(uintptr_t arg); 61static void osalArch_TimestampCcntAutoRefresh(uintptr_t arg);
@@ -72,17 +74,18 @@ void OsalArch_compileTime_SizeChk(void)
72/* TI compiler */ 74/* TI compiler */
73#pragma diag_suppress 179 75#pragma diag_suppress 179
74#endif 76#endif
75 OSAL_COMPILE_TIME_SIZE_CHECK (sizeof(HwiP_nonOs) < OSAL_NONOS_HWIP_SIZE_BYTES); 77 OSAL_COMPILE_TIME_SIZE_CHECK ((uint32_t)sizeof(HwiP_nonOs),OSAL_NONOS_HWIP_SIZE_BYTES);
76#if defined(__GNUC__) && !defined(__ti__) 78#if defined(__GNUC__) && !defined(__ti__)
77#pragma GCC diagnostic pop 79#pragma GCC diagnostic pop
78#endif 80#endif
79} 81}
80 82
81static bool gFirstTime = TRUE; 83static bool gFirstTime = (bool)true;
82static bool gTimestampFirstTime = TRUE; 84static bool gTimestampFirstTime = (bool)true;
85static bool gHwiInitialized = (bool)false;
83static CSL_vimRegs *gVimRegs; 86static CSL_vimRegs *gVimRegs;
84 87
85static TimeStamp_Struct gTimeStamp = {0U}; 88static TimeStamp_Struct gTimeStamp = {NULL,NULL};
86static HwiP_Handle gHwiPHandle; 89static HwiP_Handle gHwiPHandle;
87 90
88/* This function enables the interrupt for a given interrupt number */ 91/* This function enables the interrupt for a given interrupt number */
@@ -126,23 +129,23 @@ void OsalArch_globalRestoreInterrupt (uintptr_t restoreValue)
126 129
127/* Below function registers the interrupt for a given ISR */ 130/* Below function registers the interrupt for a given ISR */
128HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn, 131HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn,
129 HwiP_Params *params) 132 const HwiP_Params *params)
130{ 133{
131 Hwi_Struct *hwi_handle = (Hwi_Struct *) NULL; 134 Hwi_Struct *hwi_handle = NULL;
132 135
133 uint32_t i; 136 uint32_t i;
134 uintptr_t key; 137 uintptr_t key;
135 138 uint16_t priority;
136 uintptr_t temp; 139 uintptr_t temp;
137 HwiP_nonOs *hwiPool; 140 HwiP_nonOs *hwiPool;
138 uint32_t maxHwi; 141 uint32_t maxHwi;
139 HwiP_Handle retHandle; 142 HwiP_Handle retHandle = NULL_PTR;
140 CSL_ArmR5CPUInfo info; 143 CSL_ArmR5CPUInfo info;
141 144
142 /* Check if user has specified any memory block to be used, which gets 145 /* Check if user has specified any memory block to be used, which gets
143 * the precedence over the internal static memory block 146 * the precedence over the internal static memory block
144 */ 147 */
145 if (gOsal_HwAttrs.extHwiPBlock.base != (uintptr_t)NULL) 148 if (gOsal_HwAttrs.extHwiPBlock.base != 0U)
146 { 149 {
147 /* pick up the external memory block configured */ 150 /* pick up the external memory block configured */
148 hwiPool = (HwiP_nonOs *) gOsal_HwAttrs.extHwiPBlock.base; 151 hwiPool = (HwiP_nonOs *) gOsal_HwAttrs.extHwiPBlock.base;
@@ -154,17 +157,22 @@ HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn,
154 /* Pick up the internal static memory block */ 157 /* Pick up the internal static memory block */
155 hwiPool = (HwiP_nonOs *) &hwiStructs[0]; 158 hwiPool = (HwiP_nonOs *) &hwiStructs[0];
156 maxHwi = OSAL_NONOS_CONFIGNUM_HWI; 159 maxHwi = OSAL_NONOS_CONFIGNUM_HWI;
160
161 if(gHwiInitialized==(bool)false)
162 {
163 /* Initializing the first time */
164 (void)memset((void *)hwiStructs,0,sizeof(hwiStructs));
165 gHwiInitialized = (bool)true;
166 }
157 } 167 }
158 168
159 if (params == NULL) 169 if (params != NULL_PTR)
160 { 170 {
161 return (NULL);
162 }
163 171
164 key = OsalArch_globalDisableInterrupt(); 172 key = OsalArch_globalDisableInterrupt();
165 for (i = 0u; i < maxHwi; i++) { 173 for (i = 0u; i < maxHwi; i++) {
166 if (hwiPool[i].used == FALSE) { 174 if (hwiPool[i].used == (bool)false) {
167 hwiPool[i].used = TRUE; 175 hwiPool[i].used = (bool)true;
168 break; 176 break;
169 } 177 }
170 } 178 }
@@ -180,9 +188,9 @@ HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn,
180 retHandle = (HwiP_Handle)(NULL); 188 retHandle = (HwiP_Handle)(NULL);
181 } 189 }
182 190
183 if (hwi_handle != (Hwi_Struct *)NULL) 191 if (hwi_handle != NULL_PTR)
184 { 192 {
185 if (gFirstTime == TRUE) 193 if (gFirstTime == (bool)true)
186 { 194 {
187 Intc_Init(); 195 Intc_Init();
188 CSL_armR5GetCpuID(&info); 196 CSL_armR5GetCpuID(&info);
@@ -196,26 +204,26 @@ HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn,
196 /* MAIN SS Pulsar R5 SS */ 204 /* MAIN SS Pulsar R5 SS */
197 gVimRegs = (CSL_vimRegs *)(uintptr_t)CSL_MAIN_DOMAIN_VIM_BASE_ADDR; 205 gVimRegs = (CSL_vimRegs *)(uintptr_t)CSL_MAIN_DOMAIN_VIM_BASE_ADDR;
198 } 206 }
199 gFirstTime = FALSE; 207 gFirstTime = (bool)false;
200 Intc_SystemEnable(); 208 Intc_SystemEnable();
201 } 209 }
202 210
203 /* Disable the interrupt first */ 211 /* Disable the interrupt first */
204 Intc_IntDisable(interruptNum); 212 Intc_IntDisable((uint16_t)interruptNum);
205 213
206 /* Set the trigger type */ 214 /* Set the trigger type */
207 if ((params->triggerSensitivity == OSAL_ARM_GIC_TRIG_TYPE_HIGH_LEVEL) || 215 if ((params->triggerSensitivity == (uint32_t)OSAL_ARM_GIC_TRIG_TYPE_HIGH_LEVEL) ||
208 (params->triggerSensitivity == OSAL_ARM_GIC_TRIG_TYPE_LEVEL) || 216 (params->triggerSensitivity == (uint32_t)OSAL_ARM_GIC_TRIG_TYPE_LEVEL) ||
209 (params->triggerSensitivity == OSAL_ARM_GIC_TRIG_TYPE_LOW_LEVEL)) 217 (params->triggerSensitivity == (uint32_t)OSAL_ARM_GIC_TRIG_TYPE_LOW_LEVEL))
210 { 218 {
211 Intc_IntSetSrcType(interruptNum, CSL_VIM_INTR_TYPE_LEVEL); 219 Intc_IntSetSrcType((uint16_t)interruptNum, CSL_VIM_INTR_TYPE_LEVEL);
212 } 220 }
213 else 221 else
214 { 222 {
215 Intc_IntSetSrcType(interruptNum, CSL_VIM_INTR_TYPE_PULSE); 223 Intc_IntSetSrcType((uint16_t)interruptNum, CSL_VIM_INTR_TYPE_PULSE);
216 } 224 }
217 225
218 hwi_handle->intNum = interruptNum; 226 hwi_handle->intNum = (uint32_t)interruptNum;
219 227
220 /* Registering the Interrupt Service Routine(ISR). */ 228 /* Registering the Interrupt Service Routine(ISR). */
221 Intc_IntRegister((uint16_t)interruptNum, (IntrFuncPtr) hwiFxn, (void *)params->arg); 229 Intc_IntRegister((uint16_t)interruptNum, (IntrFuncPtr) hwiFxn, (void *)params->arg);
@@ -223,24 +231,29 @@ HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn,
223 /* Set the priority to default priority if priority is set un-initialized */ 231 /* Set the priority to default priority if priority is set un-initialized */
224 if (params->priority == HWIP_USE_DEFAULT_PRIORITY) 232 if (params->priority == HWIP_USE_DEFAULT_PRIORITY)
225 { 233 {
226 params->priority = HWIP_R5F_DEFAULT_PRIORITY; 234 priority = (uint16_t)HWIP_R5F_DEFAULT_PRIORITY;
227 } 235 }
236 else
237 {
238 priority = (uint16_t)params->priority;
239 }
228 240
229 /* Setting the priority for the UART interrupt in INTC. */ 241 /* Setting the priority for the UART interrupt in INTC. */
230 Intc_IntPrioritySet((uint16_t)interruptNum, params->priority, 0); 242 Intc_IntPrioritySet((uint16_t)interruptNum, priority, 0);
231 243
232 /* Enabling the interrupt if configured */ 244 /* Enabling the interrupt if configured */
233 if (params->enableIntr == TRUE) 245 if (params->enableIntr == 1U)
234 { 246 {
235 /* Enabling the interrupt in INTC. */ 247 /* Enabling the interrupt in INTC. */
236 Intc_IntEnable(interruptNum); 248 Intc_IntEnable((uint16_t)interruptNum);
237 } 249 }
238 else 250 else
239 { 251 {
240 /* Disabling the interrupt in INTC. */ 252 /* Disabling the interrupt in INTC. */
241 Intc_IntDisable(interruptNum); 253 Intc_IntDisable((uint16_t)interruptNum);
242 } 254 }
243 } 255 }
256 }
244 return ((HwiP_Handle) (retHandle) ); 257 return ((HwiP_Handle) (retHandle) );
245 258
246} 259}
@@ -252,8 +265,8 @@ HwiP_Status OsalArch_HwiPDelete(HwiP_Handle handle)
252 265
253 /* mark that handle as free */ 266 /* mark that handle as free */
254 key = OsalArch_globalDisableInterrupt(); 267 key = OsalArch_globalDisableInterrupt();
255 hwi_hnd->used = FALSE; 268 hwi_hnd->used = (bool)false;
256 Intc_IntUnregister(hwi_hnd->hwi.intNum ); 269 Intc_IntUnregister((uint16_t)hwi_hnd->hwi.intNum );
257 OsalArch_globalRestoreInterrupt(key); 270 OsalArch_globalRestoreInterrupt(key);
258 return (HwiP_OK); 271 return (HwiP_OK);
259} 272}
@@ -271,23 +284,23 @@ void osalArch_TimestampInit(void)
271 TimerP_Params timerParams; 284 TimerP_Params timerParams;
272 TimerP_Handle timerHandle; 285 TimerP_Handle timerHandle;
273 286
274 if (gTimestampFirstTime == TRUE) 287 if (gTimestampFirstTime == (bool)true)
275 { 288 {
276 osal_TimestampProvider_initCCNT(); 289 osal_TimestampProvider_initCCNT();
277 /* One time initialization is done */ 290 /* One time initialization is done */
278 gTimestampFirstTime = FALSE; 291 gTimestampFirstTime = (bool)false;
279 292
280 /* Initialize the parameters */ 293 /* Initialize the parameters */
281 TimerP_Params_init(&timerParams); 294 TimerP_Params_init(&timerParams);
282 timerParams.startMode = TimerP_StartMode_USER; 295 timerParams.startMode = (uint32_t)TimerP_StartMode_USER;
283 timerParams.periodType = TimerP_PeriodType_MICROSECS; 296 timerParams.periodType = (uint32_t)TimerP_PeriodType_MICROSECS;
284 timerParams.period = 1000000u; 297 timerParams.period = 1000000u;
285 timerHandle = TimerP_create(TimerP_ANY, (TimerP_Fxn)&osalArch_TimestampCcntAutoRefresh, &timerParams); 298 timerHandle = TimerP_create((int32_t)TimerP_ANY, (TimerP_Fxn)&osalArch_TimestampCcntAutoRefresh, &timerParams);
286 299
287 if ( timerHandle != (TimerP_Handle) NULL) 300 if ( timerHandle != NULL_PTR)
288 { 301 {
289 /* start the timer */ 302 /* start the timer */
290 TimerP_start(timerHandle); 303 (void)TimerP_start(timerHandle);
291 } 304 }
292 } 305 }
293 306
@@ -300,7 +313,7 @@ void osalArch_TimestampGet64(TimeStamp_Struct *tStamp)
300 uint32_t lo, ovsrStatus; 313 uint32_t lo, ovsrStatus;
301 uintptr_t key; 314 uintptr_t key;
302 315
303 if (tStamp != (TimeStamp_Struct *) NULL) 316 if (tStamp != NULL_PTR)
304 { 317 {
305 key = HwiP_disable(); 318 key = HwiP_disable();
306 /* Make sure init is done, if not done already */ 319 /* Make sure init is done, if not done already */
diff --git a/osal.h b/osal.h
index f1d01fb..edd382d 100644
--- a/osal.h
+++ b/osal.h
@@ -150,16 +150,8 @@ typedef enum Osal_ThreadType_e {
150 Osal_ThreadType_Main /*!< Current thread is Main */ 150 Osal_ThreadType_Main /*!< Current thread is Main */
151} Osal_ThreadType; 151} Osal_ThreadType;
152 152
153#ifdef __KLOCWORK__
154
155extern void abort(void);
156/* tell klockwork that OSAL_Assert(1) is fatal */
157#define OSAL_Assert(x) if ((x)) { abort(); }
158
159#else
160
161/* Internal function for assert */ 153/* Internal function for assert */
162extern void _DebugP_assert(int32_t expression, const char *file, int32_t line); 154extern void Osal_DebugP_assert(int32_t expression, const char *file, int32_t line);
163/*! 155/*!
164 * @brief Assert checking function 156 * @brief Assert checking function
165 * 157 *
@@ -170,9 +162,8 @@ extern void _DebugP_assert(int32_t expression, const char *file, int32_t line);
170 * @param expression Expression to evaluate 162 * @param expression Expression to evaluate
171 */ 163 */
172/* in real code use TI's version of OSAL_Assert (which is also fatal for OSAL_Assert(1)*/ 164/* in real code use TI's version of OSAL_Assert (which is also fatal for OSAL_Assert(1)*/
173#define OSAL_Assert(expression) (_DebugP_assert((expression), \ 165#define OSAL_Assert(expression) (Osal_DebugP_assert((int32_t)((expression)?1:0),\
174 __FILE__, __LINE__)) 166 __FILE__, __LINE__))
175#endif
176 167
177/*! 168/*!
178 * @brief Function to get the current thread type. 169 * @brief Function to get the current thread type.
@@ -251,32 +242,32 @@ typedef struct Osal_HwAttrs_s
251/*! 242/*!
252 * bit map to set Event combiner interrupt numbers in the Osal_HwAttr 243 * bit map to set Event combiner interrupt numbers in the Osal_HwAttr
253 */ 244 */
254#define OSAL_HWATTR_SET_ECM_INT (0x00000002) 245#define OSAL_HWATTR_SET_ECM_INT (0x00000002U)
255 246
256/*! 247/*!
257 * bit map to set the hardware access type 248 * bit map to set the hardware access type
258 */ 249 */
259#define OSAL_HWATTR_SET_HWACCESS_TYPE (0x00000004) 250#define OSAL_HWATTR_SET_HWACCESS_TYPE (0x00000004U)
260 251
261/*! 252/*!
262 * bit map to set the osal_delay Timer base address 253 * bit map to set the osal_delay Timer base address
263 */ 254 */
264#define OSAL_HWATTR_SET_OSALDELAY_TIMER_BASE (0x00000008) 255#define OSAL_HWATTR_SET_OSALDELAY_TIMER_BASE (0x00000008U)
265 256
266/*! 257/*!
267 * bit map to set the extended SemaphoreP memory block for additional SemaphoreP needs 258 * bit map to set the extended SemaphoreP memory block for additional SemaphoreP needs
268 */ 259 */
269#define OSAL_HWATTR_SET_SEMP_EXT_BASE (0x00000010) 260#define OSAL_HWATTR_SET_SEMP_EXT_BASE (0x00000010U)
270 261
271/*! 262/*!
272 * bit map to set the extended HwiP memory block for additional HwiP needs 263 * bit map to set the extended HwiP memory block for additional HwiP needs
273 */ 264 */
274#define OSAL_HWATTR_SET_HWIP_EXT_BASE (0x00000020) 265#define OSAL_HWATTR_SET_HWIP_EXT_BASE (0x00000020U)
275 266
276/*! 267/*!
277 * bit map to set the CPU frequency 268 * bit map to set the CPU frequency
278 */ 269 */
279#define OSAL_HWATTR_SET_CPU_FREQ (0x00000040) 270#define OSAL_HWATTR_SET_CPU_FREQ (0x00000040U)
280 271
281/*! 272/*!
282 * bit map to set the target processor list to direct interrupts to specific core 273 * bit map to set the target processor list to direct interrupts to specific core
@@ -338,13 +329,13 @@ extern Osal_HwAttrs gOsal_HwAttrs;
338 * allows 0 overhead compile time size check. This "works" when 329 * allows 0 overhead compile time size check. This "works" when
339 * the expression contains sizeof() which otherwise doesn't work 330 * the expression contains sizeof() which otherwise doesn't work
340 * with preprocessor */ 331 * with preprocessor */
341#define OSAL_COMPILE_TIME_SIZE_CHECK(postulate) \ 332#define OSAL_COMPILE_TIME_SIZE_CHECK(x,y) \
342 do { \ 333 do { \
343 struct { \ 334 struct { \
344 uint8_t NegativeSizeIfPostulateFalse[((int)(postulate))*2 - 1];\ 335 uint8_t NegativeSizeIfPostulateFalse[(y) + 1U - (x)]; \
345 } PostulateCheck; \ 336 } PostulateCheck; \
346 } \ 337 } \
347 while (0) 338 while ((bool)false)
348 339
349#ifdef __cplusplus 340#ifdef __cplusplus
350} 341}
diff --git a/soc/j721e/TimerP_default.c b/soc/j721e/TimerP_default.c
index e50e512..658af30 100755
--- a/soc/j721e/TimerP_default.c
+++ b/soc/j721e/TimerP_default.c
@@ -56,20 +56,20 @@ TimerP_dmTimerDefault gDmTimerPInfoTbl[TimerP_numTimerDevices] = {
56 "DMTimer0", /* Timer Name */ 56 "DMTimer0", /* Timer Name */
57#if defined (BUILD_MCU) 57#if defined (BUILD_MCU)
58 /* Default configurations for R5 core */ 58 /* Default configurations for R5 core */
59 CSL_MCU_TIMER0_CFG_BASE, /* MCU domain's DM Timer base address */ 59 (uint32_t)CSL_MCU_TIMER0_CFG_BASE, /* MCU domain's DM Timer base address */
60 CSLR_MCU_R5FSS0_CORE0_INTR_MCU_TIMER0_INTR_PEND_0, /* MCU domain's DM Timer interrupt number */ 60 (int32_t)CSLR_MCU_R5FSS0_CORE0_INTR_MCU_TIMER0_INTR_PEND_0, /* MCU domain's DM Timer interrupt number */
61 TIMERP_EVENT_NOT_AVAILABLE /* Event Id */ 61 TIMERP_EVENT_NOT_AVAILABLE /* Event Id */
62#endif 62#endif
63#if defined (BUILD_MPU) 63#if defined (BUILD_MPU)
64 /* Default configurations for A72 core */ 64 /* Default configurations for A72 core */
65 CSL_TIMER0_CFG_BASE, /* Main domain's DM Timer base address */ 65 (uint32_t)CSL_TIMER0_CFG_BASE, /* Main domain's DM Timer base address */
66 CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER0_INTR_PEND_0, /* Main domain's DM Timer interrupt number */ 66 (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER0_INTR_PEND_0, /* Main domain's DM Timer interrupt number */
67 TIMERP_EVENT_NOT_AVAILABLE /* Event Id */ 67 TIMERP_EVENT_NOT_AVAILABLE /* Event Id */
68#endif 68#endif
69#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2) 69#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
70 /* Default configurations for DSP core */ 70 /* Default configurations for DSP core */
71 CSL_TIMER0_CFG_BASE, /* Main domain's DM Timer base address */ 71 (uint32_t)CSL_TIMER0_CFG_BASE, /* Main domain's DM Timer base address */
72 TIMERP_INTR_USER_CONFIGURE, /* User Confugure */ 72 (int32_t)TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
73 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */ 73 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
74#endif 74#endif
75 }, 75 },
@@ -77,17 +77,17 @@ TimerP_dmTimerDefault gDmTimerPInfoTbl[TimerP_numTimerDevices] = {
77 { 77 {
78 "DMTimer1", 78 "DMTimer1",
79#if defined (BUILD_MCU) 79#if defined (BUILD_MCU)
80 CSL_MCU_TIMER1_CFG_BASE, 80 (uint32_t)CSL_MCU_TIMER1_CFG_BASE,
81 CSLR_MCU_R5FSS0_CORE0_INTR_MCU_TIMER1_INTR_PEND_0, 81 (int32_t)CSLR_MCU_R5FSS0_CORE0_INTR_MCU_TIMER1_INTR_PEND_0,
82 TIMERP_EVENT_NOT_AVAILABLE 82 TIMERP_EVENT_NOT_AVAILABLE
83#endif 83#endif
84#if defined (BUILD_MPU) 84#if defined (BUILD_MPU)
85 CSL_TIMER1_CFG_BASE, 85 (uint32_t)CSL_TIMER1_CFG_BASE,
86 CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER1_INTR_PEND_0, 86 (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER1_INTR_PEND_0,
87 TIMERP_EVENT_NOT_AVAILABLE 87 TIMERP_EVENT_NOT_AVAILABLE
88#endif 88#endif
89#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2) 89#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
90 CSL_TIMER1_CFG_BASE, 90 (uint32_t)CSL_TIMER1_CFG_BASE,
91 TIMERP_INTR_USER_CONFIGURE, /* User Confugure */ 91 TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
92 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */ 92 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
93#endif 93#endif
@@ -96,18 +96,18 @@ TimerP_dmTimerDefault gDmTimerPInfoTbl[TimerP_numTimerDevices] = {
96 { 96 {
97 "DMTimer2", 97 "DMTimer2",
98#if defined (BUILD_MCU) 98#if defined (BUILD_MCU)
99 CSL_MCU_TIMER2_CFG_BASE, 99 (uint32_t)CSL_MCU_TIMER2_CFG_BASE,
100 CSLR_MCU_R5FSS0_CORE0_INTR_MCU_TIMER2_INTR_PEND_0, 100 (int32_t)CSLR_MCU_R5FSS0_CORE0_INTR_MCU_TIMER2_INTR_PEND_0,
101 TIMERP_EVENT_NOT_AVAILABLE 101 TIMERP_EVENT_NOT_AVAILABLE
102#endif 102#endif
103#if defined (BUILD_MPU) 103#if defined (BUILD_MPU)
104 CSL_TIMER2_CFG_BASE, 104 (uint32_t)CSL_TIMER2_CFG_BASE,
105 CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER2_INTR_PEND_0, 105 (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER2_INTR_PEND_0,
106 TIMERP_EVENT_NOT_AVAILABLE 106 TIMERP_EVENT_NOT_AVAILABLE
107#endif 107#endif
108#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2) 108#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
109 CSL_TIMER2_CFG_BASE, 109 (uint32_t)CSL_TIMER2_CFG_BASE,
110 TIMERP_INTR_USER_CONFIGURE, /* User Confugure */ 110 (int32_t)TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
111 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */ 111 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
112#endif 112#endif
113 }, 113 },
@@ -115,18 +115,18 @@ TimerP_dmTimerDefault gDmTimerPInfoTbl[TimerP_numTimerDevices] = {
115 { 115 {
116 "DMTimer3", 116 "DMTimer3",
117#if defined (BUILD_MCU) 117#if defined (BUILD_MCU)
118 CSL_MCU_TIMER3_CFG_BASE, 118 (uint32_t)CSL_MCU_TIMER3_CFG_BASE,
119 CSLR_MCU_R5FSS0_CORE0_INTR_MCU_TIMER3_INTR_PEND_0, 119 (int32_t)CSLR_MCU_R5FSS0_CORE0_INTR_MCU_TIMER3_INTR_PEND_0,
120 TIMERP_EVENT_NOT_AVAILABLE 120 TIMERP_EVENT_NOT_AVAILABLE
121#endif 121#endif
122#if defined (BUILD_MPU) 122#if defined (BUILD_MPU)
123 CSL_TIMER3_CFG_BASE, 123 (uint32_t)CSL_TIMER3_CFG_BASE,
124 CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER3_INTR_PEND_0, 124 (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER3_INTR_PEND_0,
125 TIMERP_EVENT_NOT_AVAILABLE 125 TIMERP_EVENT_NOT_AVAILABLE
126#endif 126#endif
127#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2) 127#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
128 CSL_TIMER3_CFG_BASE, 128 (uint32_t)CSL_TIMER3_CFG_BASE,
129 TIMERP_INTR_USER_CONFIGURE, /* User Confugure */ 129 (int32_t)TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
130 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */ 130 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
131#endif 131#endif
132 }, 132 },
@@ -134,18 +134,18 @@ TimerP_dmTimerDefault gDmTimerPInfoTbl[TimerP_numTimerDevices] = {
134 { 134 {
135 "DMTimer4", 135 "DMTimer4",
136#if defined (BUILD_MCU) 136#if defined (BUILD_MCU)
137 CSL_MCU_TIMER4_CFG_BASE, 137 (uint32_t)CSL_MCU_TIMER4_CFG_BASE,
138 CSLR_MCU_R5FSS0_CORE0_INTR_MCU_TIMER4_INTR_PEND_0, 138 (int32_t)CSLR_MCU_R5FSS0_CORE0_INTR_MCU_TIMER4_INTR_PEND_0,
139 TIMERP_EVENT_NOT_AVAILABLE 139 TIMERP_EVENT_NOT_AVAILABLE
140#endif 140#endif
141#if defined (BUILD_MPU) 141#if defined (BUILD_MPU)
142 CSL_TIMER4_CFG_BASE, 142 (uint32_t)CSL_TIMER4_CFG_BASE,
143 CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER4_INTR_PEND_0, 143 (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER4_INTR_PEND_0,
144 TIMERP_EVENT_NOT_AVAILABLE 144 TIMERP_EVENT_NOT_AVAILABLE
145#endif 145#endif
146#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2) 146#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
147 CSL_TIMER4_CFG_BASE, 147 (uint32_t)CSL_TIMER4_CFG_BASE,
148 TIMERP_INTR_USER_CONFIGURE, /* User Confugure */ 148 (int32_t)TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
149 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */ 149 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
150#endif 150#endif
151 }, 151 },
@@ -153,18 +153,18 @@ TimerP_dmTimerDefault gDmTimerPInfoTbl[TimerP_numTimerDevices] = {
153 { 153 {
154 "DMTimer5", 154 "DMTimer5",
155#if defined (BUILD_MCU) 155#if defined (BUILD_MCU)
156 CSL_MCU_TIMER5_CFG_BASE, 156 (uint32_t)CSL_MCU_TIMER5_CFG_BASE,
157 CSLR_MCU_R5FSS0_CORE0_INTR_MCU_TIMER5_INTR_PEND_0, 157 (int32_t)CSLR_MCU_R5FSS0_CORE0_INTR_MCU_TIMER5_INTR_PEND_0,
158 TIMERP_EVENT_NOT_AVAILABLE 158 TIMERP_EVENT_NOT_AVAILABLE
159#endif 159#endif
160#if defined (BUILD_MPU) 160#if defined (BUILD_MPU)
161 CSL_TIMER5_CFG_BASE, 161 (uint32_t)CSL_TIMER5_CFG_BASE,
162 CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER5_INTR_PEND_0, 162 (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER5_INTR_PEND_0,
163 TIMERP_EVENT_NOT_AVAILABLE 163 TIMERP_EVENT_NOT_AVAILABLE
164#endif 164#endif
165#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2) 165#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
166 CSL_TIMER5_CFG_BASE, 166 (uint32_t)CSL_TIMER5_CFG_BASE,
167 TIMERP_INTR_USER_CONFIGURE, /* User Confugure */ 167 (int32_t)TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
168 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */ 168 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
169#endif 169#endif
170 }, 170 },
@@ -172,18 +172,18 @@ TimerP_dmTimerDefault gDmTimerPInfoTbl[TimerP_numTimerDevices] = {
172 { 172 {
173 "DMTimer6", 173 "DMTimer6",
174#if defined (BUILD_MCU) 174#if defined (BUILD_MCU)
175 CSL_MCU_TIMER6_CFG_BASE, 175 (uint32_t)CSL_MCU_TIMER6_CFG_BASE,
176 CSLR_MCU_R5FSS0_CORE0_INTR_MCU_TIMER6_INTR_PEND_0, 176 (int32_t)CSLR_MCU_R5FSS0_CORE0_INTR_MCU_TIMER6_INTR_PEND_0,
177 TIMERP_EVENT_NOT_AVAILABLE 177 TIMERP_EVENT_NOT_AVAILABLE
178#endif 178#endif
179#if defined (BUILD_MPU) 179#if defined (BUILD_MPU)
180 CSL_TIMER6_CFG_BASE, 180 (uint32_t)CSL_TIMER6_CFG_BASE,
181 CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER6_INTR_PEND_0, 181 (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER6_INTR_PEND_0,
182 TIMERP_EVENT_NOT_AVAILABLE 182 TIMERP_EVENT_NOT_AVAILABLE
183#endif 183#endif
184#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2) 184#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
185 CSL_TIMER6_CFG_BASE, 185 (uint32_t)CSL_TIMER6_CFG_BASE,
186 TIMERP_INTR_USER_CONFIGURE, /* User Confugure */ 186 (int32_t)TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
187 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */ 187 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
188#endif 188#endif
189 }, 189 },
@@ -191,18 +191,18 @@ TimerP_dmTimerDefault gDmTimerPInfoTbl[TimerP_numTimerDevices] = {
191 { 191 {
192 "DMTimer7", 192 "DMTimer7",
193#if defined (BUILD_MCU) 193#if defined (BUILD_MCU)
194 CSL_MCU_TIMER7_CFG_BASE, 194 (uint32_t)CSL_MCU_TIMER7_CFG_BASE,
195 CSLR_MCU_R5FSS0_CORE0_INTR_MCU_TIMER7_INTR_PEND_0, 195 (int32_t)CSLR_MCU_R5FSS0_CORE0_INTR_MCU_TIMER7_INTR_PEND_0,
196 TIMERP_EVENT_NOT_AVAILABLE 196 TIMERP_EVENT_NOT_AVAILABLE
197#endif 197#endif
198#if defined (BUILD_MPU) 198#if defined (BUILD_MPU)
199 CSL_TIMER7_CFG_BASE, 199 (uint32_t)CSL_TIMER7_CFG_BASE,
200 CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER7_INTR_PEND_0, 200 (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER7_INTR_PEND_0,
201 TIMERP_EVENT_NOT_AVAILABLE 201 TIMERP_EVENT_NOT_AVAILABLE
202#endif 202#endif
203#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2) 203#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
204 CSL_TIMER7_CFG_BASE, 204 (uint32_t)CSL_TIMER7_CFG_BASE,
205 TIMERP_INTR_USER_CONFIGURE, /* User Confugure */ 205 (int32_t)TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
206 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */ 206 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
207#endif 207#endif
208 }, 208 },
@@ -210,18 +210,18 @@ TimerP_dmTimerDefault gDmTimerPInfoTbl[TimerP_numTimerDevices] = {
210 { 210 {
211 "DMTimer8", 211 "DMTimer8",
212#if defined (BUILD_MCU) 212#if defined (BUILD_MCU)
213 CSL_MCU_TIMER8_CFG_BASE, 213 (uint32_t)CSL_MCU_TIMER8_CFG_BASE,
214 CSLR_MCU_R5FSS0_CORE0_INTR_MCU_TIMER8_INTR_PEND_0, 214 (int32_t)CSLR_MCU_R5FSS0_CORE0_INTR_MCU_TIMER8_INTR_PEND_0,
215 TIMERP_EVENT_NOT_AVAILABLE 215 TIMERP_EVENT_NOT_AVAILABLE
216#endif 216#endif
217#if defined (BUILD_MPU) 217#if defined (BUILD_MPU)
218 CSL_TIMER8_CFG_BASE, 218 (uint32_t)CSL_TIMER8_CFG_BASE,
219 CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER8_INTR_PEND_0, 219 (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER8_INTR_PEND_0,
220 TIMERP_EVENT_NOT_AVAILABLE 220 TIMERP_EVENT_NOT_AVAILABLE
221#endif 221#endif
222#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2) 222#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
223 CSL_TIMER8_CFG_BASE, 223 (uint32_t)CSL_TIMER8_CFG_BASE,
224 TIMERP_INTR_USER_CONFIGURE, /* User Confugure */ 224 (int32_t)TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
225 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */ 225 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
226#endif 226#endif
227 }, 227 },
@@ -229,18 +229,18 @@ TimerP_dmTimerDefault gDmTimerPInfoTbl[TimerP_numTimerDevices] = {
229 { 229 {
230 "DMTimer9", 230 "DMTimer9",
231#if defined (BUILD_MCU) 231#if defined (BUILD_MCU)
232 CSL_MCU_TIMER9_CFG_BASE, 232 (uint32_t)CSL_MCU_TIMER9_CFG_BASE,
233 CSLR_MCU_R5FSS0_CORE0_INTR_MCU_TIMER9_INTR_PEND_0, 233 (int32_t)CSLR_MCU_R5FSS0_CORE0_INTR_MCU_TIMER9_INTR_PEND_0,
234 TIMERP_EVENT_NOT_AVAILABLE 234 TIMERP_EVENT_NOT_AVAILABLE
235#endif 235#endif
236#if defined (BUILD_MPU) 236#if defined (BUILD_MPU)
237 CSL_TIMER9_CFG_BASE, 237 (uint32_t)CSL_TIMER9_CFG_BASE,
238 CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER9_INTR_PEND_0, 238 (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER9_INTR_PEND_0,
239 TIMERP_EVENT_NOT_AVAILABLE 239 TIMERP_EVENT_NOT_AVAILABLE
240#endif 240#endif
241#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2) 241#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
242 CSL_TIMER9_CFG_BASE, 242 (uint32_t)CSL_TIMER9_CFG_BASE,
243 TIMERP_INTR_USER_CONFIGURE, /* User Confugure */ 243 (int32_t)TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
244 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */ 244 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
245#endif 245#endif
246 }, 246 },
@@ -249,17 +249,17 @@ TimerP_dmTimerDefault gDmTimerPInfoTbl[TimerP_numTimerDevices] = {
249 "DMTimer10", 249 "DMTimer10",
250#if defined (BUILD_MCU) 250#if defined (BUILD_MCU)
251 0U, 251 0U,
252 0U, 252 0,
253 TIMERP_EVENT_NOT_AVAILABLE 253 TIMERP_EVENT_NOT_AVAILABLE
254#endif 254#endif
255#if defined (BUILD_MPU) 255#if defined (BUILD_MPU)
256 CSL_TIMER10_CFG_BASE, 256 (uint32_t)CSL_TIMER10_CFG_BASE,
257 CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER10_INTR_PEND_0, 257 (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER10_INTR_PEND_0,
258 TIMERP_EVENT_NOT_AVAILABLE 258 TIMERP_EVENT_NOT_AVAILABLE
259#endif 259#endif
260#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2) 260#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
261 CSL_TIMER10_CFG_BASE, 261 (uint32_t)CSL_TIMER10_CFG_BASE,
262 TIMERP_INTR_USER_CONFIGURE, /* User Confugure */ 262 (int32_t)TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
263 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */ 263 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
264#endif 264#endif
265 }, 265 },
@@ -268,17 +268,17 @@ TimerP_dmTimerDefault gDmTimerPInfoTbl[TimerP_numTimerDevices] = {
268 "DMTimer11", 268 "DMTimer11",
269#if defined (BUILD_MCU) 269#if defined (BUILD_MCU)
270 0U, 270 0U,
271 0U, 271 0,
272 TIMERP_EVENT_NOT_AVAILABLE 272 TIMERP_EVENT_NOT_AVAILABLE
273#endif 273#endif
274#if defined (BUILD_MPU) 274#if defined (BUILD_MPU)
275 CSL_TIMER11_CFG_BASE, 275 (uint32_t)CSL_TIMER11_CFG_BASE,
276 CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER11_INTR_PEND_0, 276 (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER11_INTR_PEND_0,
277 TIMERP_EVENT_NOT_AVAILABLE 277 TIMERP_EVENT_NOT_AVAILABLE
278#endif 278#endif
279#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2) 279#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
280 CSL_TIMER11_CFG_BASE, 280 (uint32_t)CSL_TIMER11_CFG_BASE,
281 TIMERP_INTR_USER_CONFIGURE, /* User Confugure */ 281 (int32_t)TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
282 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */ 282 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
283#endif 283#endif
284 }, 284 },
@@ -287,17 +287,17 @@ TimerP_dmTimerDefault gDmTimerPInfoTbl[TimerP_numTimerDevices] = {
287 "DMTimer12", 287 "DMTimer12",
288#if defined (BUILD_MCU) 288#if defined (BUILD_MCU)
289 0U, 289 0U,
290 0U, 290 0,
291 TIMERP_EVENT_NOT_AVAILABLE 291 TIMERP_EVENT_NOT_AVAILABLE
292#endif 292#endif
293#if defined (BUILD_MPU) 293#if defined (BUILD_MPU)
294 CSL_TIMER12_CFG_BASE, 294 (uint32_t)CSL_TIMER12_CFG_BASE,
295 CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER12_INTR_PEND_0, 295 (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER12_INTR_PEND_0,
296 TIMERP_EVENT_NOT_AVAILABLE 296 TIMERP_EVENT_NOT_AVAILABLE
297#endif 297#endif
298#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2) 298#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
299 CSL_TIMER12_CFG_BASE, 299 (uint32_t)CSL_TIMER12_CFG_BASE,
300 TIMERP_INTR_USER_CONFIGURE, /* User Confugure */ 300 (int32_t)TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
301 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */ 301 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
302#endif 302#endif
303 }, 303 },
@@ -306,17 +306,17 @@ TimerP_dmTimerDefault gDmTimerPInfoTbl[TimerP_numTimerDevices] = {
306 "DMTimer13", 306 "DMTimer13",
307#if defined (BUILD_MCU) 307#if defined (BUILD_MCU)
308 0U, 308 0U,
309 0U, 309 0,
310 TIMERP_EVENT_NOT_AVAILABLE 310 TIMERP_EVENT_NOT_AVAILABLE
311#endif 311#endif
312#if defined (BUILD_MPU) 312#if defined (BUILD_MPU)
313 CSL_TIMER13_CFG_BASE, 313 (uint32_t)CSL_TIMER13_CFG_BASE,
314 CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER13_INTR_PEND_0, 314 (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER13_INTR_PEND_0,
315 TIMERP_EVENT_NOT_AVAILABLE 315 TIMERP_EVENT_NOT_AVAILABLE
316#endif 316#endif
317#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2) 317#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
318 CSL_TIMER13_CFG_BASE, 318 (uint32_t)CSL_TIMER13_CFG_BASE,
319 TIMERP_INTR_USER_CONFIGURE, /* User Confugure */ 319 (int32_t)TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
320 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */ 320 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
321#endif 321#endif
322 }, 322 },
@@ -325,17 +325,17 @@ TimerP_dmTimerDefault gDmTimerPInfoTbl[TimerP_numTimerDevices] = {
325 "DMTimer14", 325 "DMTimer14",
326#if defined (BUILD_MCU) 326#if defined (BUILD_MCU)
327 0U, 327 0U,
328 0U, 328 0,
329 TIMERP_EVENT_NOT_AVAILABLE 329 TIMERP_EVENT_NOT_AVAILABLE
330#endif 330#endif
331#if defined (BUILD_MPU) 331#if defined (BUILD_MPU)
332 CSL_TIMER14_CFG_BASE, 332 (uint32_t)CSL_TIMER14_CFG_BASE,
333 CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER14_INTR_PEND_0, 333 (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER14_INTR_PEND_0,
334 TIMERP_EVENT_NOT_AVAILABLE 334 TIMERP_EVENT_NOT_AVAILABLE
335#endif 335#endif
336#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2) 336#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
337 CSL_TIMER14_CFG_BASE, 337 (uint32_t)CSL_TIMER14_CFG_BASE,
338 TIMERP_INTR_USER_CONFIGURE, /* User Confugure */ 338 (int32_t)TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
339 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */ 339 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
340#endif 340#endif
341 }, 341 },
@@ -344,17 +344,17 @@ TimerP_dmTimerDefault gDmTimerPInfoTbl[TimerP_numTimerDevices] = {
344 "DMTimer15", 344 "DMTimer15",
345#if defined (BUILD_MCU) 345#if defined (BUILD_MCU)
346 0U, 346 0U,
347 0U, 347 0,
348 TIMERP_EVENT_NOT_AVAILABLE 348 TIMERP_EVENT_NOT_AVAILABLE
349#endif 349#endif
350#if defined (BUILD_MPU) 350#if defined (BUILD_MPU)
351 CSL_TIMER15_CFG_BASE, 351 (uint32_t)CSL_TIMER15_CFG_BASE,
352 CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER15_INTR_PEND_0, 352 (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER15_INTR_PEND_0,
353 TIMERP_EVENT_NOT_AVAILABLE 353 TIMERP_EVENT_NOT_AVAILABLE
354#endif 354#endif
355#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2) 355#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
356 CSL_TIMER15_CFG_BASE, 356 (uint32_t)CSL_TIMER15_CFG_BASE,
357 TIMERP_INTR_USER_CONFIGURE, /* User Confugure */ 357 (int32_t)TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
358 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */ 358 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
359#endif 359#endif
360 }, 360 },
@@ -363,17 +363,17 @@ TimerP_dmTimerDefault gDmTimerPInfoTbl[TimerP_numTimerDevices] = {
363 "DMTimer16", 363 "DMTimer16",
364#if defined (BUILD_MCU) 364#if defined (BUILD_MCU)
365 0U, 365 0U,
366 0U, 366 0,
367 TIMERP_EVENT_NOT_AVAILABLE 367 TIMERP_EVENT_NOT_AVAILABLE
368#endif 368#endif
369#if defined (BUILD_MPU) 369#if defined (BUILD_MPU)
370 CSL_TIMER16_CFG_BASE, 370 (uint32_t)CSL_TIMER16_CFG_BASE,
371 CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER16_INTR_PEND_0, 371 (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER16_INTR_PEND_0,
372 TIMERP_EVENT_NOT_AVAILABLE 372 TIMERP_EVENT_NOT_AVAILABLE
373#endif 373#endif
374#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2) 374#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
375 CSL_TIMER16_CFG_BASE, 375 (uint32_t)CSL_TIMER16_CFG_BASE,
376 TIMERP_INTR_USER_CONFIGURE, /* User Confugure */ 376 (int32_t)TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
377 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */ 377 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
378#endif 378#endif
379 }, 379 },
@@ -382,17 +382,17 @@ TimerP_dmTimerDefault gDmTimerPInfoTbl[TimerP_numTimerDevices] = {
382 "DMTimer17", 382 "DMTimer17",
383#if defined (BUILD_MCU) 383#if defined (BUILD_MCU)
384 0U, 384 0U,
385 0U, 385 0,
386 TIMERP_EVENT_NOT_AVAILABLE 386 TIMERP_EVENT_NOT_AVAILABLE
387#endif 387#endif
388#if defined (BUILD_MPU) 388#if defined (BUILD_MPU)
389 CSL_TIMER17_CFG_BASE, 389 (uint32_t)CSL_TIMER17_CFG_BASE,
390 CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER17_INTR_PEND_0, 390 (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER17_INTR_PEND_0,
391 TIMERP_EVENT_NOT_AVAILABLE 391 TIMERP_EVENT_NOT_AVAILABLE
392#endif 392#endif
393#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2) 393#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
394 CSL_TIMER17_CFG_BASE, 394 (uint32_t)CSL_TIMER17_CFG_BASE,
395 TIMERP_INTR_USER_CONFIGURE, /* User Confugure */ 395 (int32_t)TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
396 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */ 396 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
397#endif 397#endif
398 }, 398 },
@@ -401,17 +401,17 @@ TimerP_dmTimerDefault gDmTimerPInfoTbl[TimerP_numTimerDevices] = {
401 "DMTimer18", 401 "DMTimer18",
402#if defined (BUILD_MCU) 402#if defined (BUILD_MCU)
403 0U, 403 0U,
404 0U, 404 0,
405 TIMERP_EVENT_NOT_AVAILABLE 405 TIMERP_EVENT_NOT_AVAILABLE
406#endif 406#endif
407#if defined (BUILD_MPU) 407#if defined (BUILD_MPU)
408 CSL_TIMER18_CFG_BASE, 408 (uint32_t)CSL_TIMER18_CFG_BASE,
409 CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER18_INTR_PEND_0, 409 (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER18_INTR_PEND_0,
410 TIMERP_EVENT_NOT_AVAILABLE 410 TIMERP_EVENT_NOT_AVAILABLE
411#endif 411#endif
412#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2) 412#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
413 CSL_TIMER18_CFG_BASE, 413 (uint32_t)CSL_TIMER18_CFG_BASE,
414 TIMERP_INTR_USER_CONFIGURE, /* User Confugure */ 414 (int32_t)TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
415 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */ 415 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
416#endif 416#endif
417 }, 417 },
@@ -420,17 +420,17 @@ TimerP_dmTimerDefault gDmTimerPInfoTbl[TimerP_numTimerDevices] = {
420 "DMTimer19", 420 "DMTimer19",
421#if defined (BUILD_MCU) 421#if defined (BUILD_MCU)
422 0U, 422 0U,
423 0U, 423 0,
424 TIMERP_EVENT_NOT_AVAILABLE 424 TIMERP_EVENT_NOT_AVAILABLE
425#endif 425#endif
426#if defined (BUILD_MPU) 426#if defined (BUILD_MPU)
427 CSL_TIMER19_CFG_BASE, 427 (uint32_t)CSL_TIMER19_CFG_BASE,
428 CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER19_INTR_PEND_0, 428 (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER19_INTR_PEND_0,
429 TIMERP_EVENT_NOT_AVAILABLE 429 TIMERP_EVENT_NOT_AVAILABLE
430#endif 430#endif
431#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2) 431#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
432 CSL_TIMER19_CFG_BASE, 432 (uint32_t)CSL_TIMER19_CFG_BASE,
433 TIMERP_INTR_USER_CONFIGURE, /* User Confugure */ 433 (int32_t)TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
434 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */ 434 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
435#endif 435#endif
436 } 436 }
@@ -464,14 +464,14 @@ void TimerP_updateDefaultInfoTbl(void)
464 for (i = 0U; i < TimerP_numTimerDevices; i++) 464 for (i = 0U; i < TimerP_numTimerDevices; i++)
465 { 465 {
466 gDmTimerPInfoTbl[i].baseAddr = ((uint32_t)CSL_TIMER0_CFG_BASE) + \ 466 gDmTimerPInfoTbl[i].baseAddr = ((uint32_t)CSL_TIMER0_CFG_BASE) + \
467 ((uint32_t)0x10000U) * i; 467 (((uint32_t)0x10000U) * i);
468 if (i < 12U) 468 if (i < 12U)
469 { 469 {
470 /* 470 /*
471 * The interrupt events of Main domain's DM Timer instance 0 - 11 are routed 471 * The interrupt events of Main domain's DM Timer instance 0 - 11 are routed
472 * by default through the MAIN_PULSARx Int Routers for connection to the R5 VIMs 472 * by default through the MAIN_PULSARx Int Routers for connection to the R5 VIMs
473 */ 473 */
474 gDmTimerPInfoTbl[i].intNum = CSLR_R5FSS0_INTROUTER0_IN_TIMER0_INTR_PEND_0 + i; 474 gDmTimerPInfoTbl[i].intNum = (int32_t)CSLR_R5FSS0_INTROUTER0_IN_TIMER0_INTR_PEND_0 + (int32_t)i;
475 } 475 }
476 else 476 else
477 { 477 {
@@ -479,7 +479,7 @@ void TimerP_updateDefaultInfoTbl(void)
479 * The interrupt events of Main domain's DM Timer instance 12 - 19 479 * The interrupt events of Main domain's DM Timer instance 12 - 19
480 * are directly connected to the MAIN Pulsar VIMs. 480 * are directly connected to the MAIN Pulsar VIMs.
481 */ 481 */
482 gDmTimerPInfoTbl[i].intNum = CSLR_R5FSS0_CORE0_INTR_TIMER12_INTR_PEND_0 + i - 12U; 482 gDmTimerPInfoTbl[i].intNum = (int32_t)CSLR_R5FSS0_CORE0_INTR_TIMER12_INTR_PEND_0 + (int32_t)i - 12;
483 } 483 }
484 } 484 }
485 } 485 }
diff --git a/soc/j721e/bios_mmu.c b/soc/j721e/bios_mmu.c
index 169939a..784b19b 100644
--- a/soc/j721e/bios_mmu.c
+++ b/soc/j721e/bios_mmu.c
@@ -65,7 +65,7 @@
65/* Function Declarations */ 65/* Function Declarations */
66/* ========================================================================== */ 66/* ========================================================================== */
67 67
68/* None */ 68void Osal_initMmuDefault(void);
69 69
70/* ========================================================================== */ 70/* ========================================================================== */
71/* Global Variables */ 71/* Global Variables */
@@ -86,21 +86,21 @@ void Osal_initMmuDefault(void)
86 attrs.attrIndx = Mmu_AttrIndx_MAIR0; 86 attrs.attrIndx = Mmu_AttrIndx_MAIR0;
87 87
88 /* Register region */ 88 /* Register region */
89 Mmu_map(0x00000000U, 0x00000000U, 0x20000000U, &attrs); 89 (void)Mmu_map(0x00000000U, 0x00000000U, 0x20000000U, &attrs);
90 Mmu_map(0x20000000U, 0x20000000U, 0x20000000U, &attrs); 90 (void)Mmu_map(0x20000000U, 0x20000000U, 0x20000000U, &attrs);
91 Mmu_map(0x40000000U, 0x40000000U, 0x20000000U, &attrs); 91 (void)Mmu_map(0x40000000U, 0x40000000U, 0x20000000U, &attrs);
92 Mmu_map(0x60000000U, 0x60000000U, 0x10000000U, &attrs); 92 (void)Mmu_map(0x60000000U, 0x60000000U, 0x10000000U, &attrs);
93 Mmu_map(0x78000000U, 0x78000000U, 0x08000000U, &attrs); /* CLEC */ 93 (void)Mmu_map(0x78000000U, 0x78000000U, 0x08000000U, &attrs); /* CLEC */
94 94
95#if defined(BUILD_MPU) 95#if defined(BUILD_MPU)
96 Mmu_map(0x400000000U, 0x400000000U, 0x400000000U, &attrs); /* FSS0 data */ 96 (void)Mmu_map(0x400000000U, 0x400000000U, 0x400000000U, &attrs); /* FSS0 data */
97#endif 97#endif
98 98
99 attrs.attrIndx = Mmu_AttrIndx_MAIR7; 99 attrs.attrIndx = Mmu_AttrIndx_MAIR7;
100 Mmu_map(0x80000000U, 0x80000000U, 0x20000000U, &attrs); /* DDR */ 100 (void)Mmu_map(0x80000000U, 0x80000000U, 0x20000000U, &attrs); /* DDR */
101 Mmu_map(0xA0000000U, 0xA0000000U, 0x20000000U, &attrs); /* DDR */ 101 (void)Mmu_map(0xA0000000U, 0xA0000000U, 0x20000000U, &attrs); /* DDR */
102 Mmu_map(0x70000000U, 0x70000000U, 0x00800000U, &attrs); /* MSMC - 8MB */ 102 (void)Mmu_map(0x70000000U, 0x70000000U, 0x00800000U, &attrs); /* MSMC - 8MB */
103 Mmu_map(0x41C00000U, 0x41C00000U, 0x00080000U, &attrs); /* OCMC - 512KB */ 103 (void)Mmu_map(0x41C00000U, 0x41C00000U, 0x00080000U, &attrs); /* OCMC - 512KB */
104 104
105 /* 105 /*
106 * DDR range 0xA0000000 - 0xAA000000 : Used as RAM by multiple 106 * DDR range 0xA0000000 - 0xAA000000 : Used as RAM by multiple
@@ -108,7 +108,7 @@ void Osal_initMmuDefault(void)
108 * IPC VRing Buffer - uncached 108 * IPC VRing Buffer - uncached
109 */ 109 */
110 attrs.attrIndx = Mmu_AttrIndx_MAIR4; 110 attrs.attrIndx = Mmu_AttrIndx_MAIR4;
111 Mmu_map(0xAA000000, 0xAA000000, 0x02000000, &attrs); 111 (void)Mmu_map(0xAA000000U, 0xAA000000U, 0x02000000U, &attrs);
112 112
113 return; 113 return;
114} 114}
diff --git a/soc/j721e/osal_soc.h b/soc/j721e/osal_soc.h
index 88a3e1b..0c8c23e 100644
--- a/soc/j721e/osal_soc.h
+++ b/soc/j721e/osal_soc.h
@@ -45,14 +45,25 @@ extern "C" {
45#endif 45#endif
46#include <ti/osal/osal.h> 46#include <ti/osal/osal.h>
47#include <ti/csl/soc.h> 47#include <ti/csl/soc.h>
48 48#if defined(TimerP_numTimerDevices)
49#undef TimerP_numTimerDevices 49#undef TimerP_numTimerDevices
50#endif
51
52#if defined(TIMERP_ANY_MASK)
50#undef TIMERP_ANY_MASK 53#undef TIMERP_ANY_MASK
54#endif
55
51#define EXTERNAL_CLOCK_KHZ_DEFAULT (24000) 56#define EXTERNAL_CLOCK_KHZ_DEFAULT (24000)
52#define PMU_CLOCK_KHZ_DEFAULT (1000000U) 57#define PMU_CLOCK_KHZ_DEFAULT (1000000U)
53 58
59#if defined(TIMERP_TIMER_FREQ_LO)
54#undef TIMERP_TIMER_FREQ_LO 60#undef TIMERP_TIMER_FREQ_LO
61#endif
62
63#if defined(TIMERP_TIMER_FREQ_HI)
55#undef TIMERP_TIMER_FREQ_HI 64#undef TIMERP_TIMER_FREQ_HI
65#endif
66
56#define TIMERP_TIMER_FREQ_LO ((int32_t) 25000000) 67#define TIMERP_TIMER_FREQ_LO ((int32_t) 25000000)
57#define TIMERP_TIMER_FREQ_HI ((int32_t) 0) 68#define TIMERP_TIMER_FREQ_HI ((int32_t) 0)
58 69
diff --git a/src/linux/HwiP_linux.c b/src/linux/HwiP_linux.c
index 71ba494..64d3095 100644
--- a/src/linux/HwiP_linux.c
+++ b/src/linux/HwiP_linux.c
@@ -36,7 +36,6 @@
36#include <stdint.h> 36#include <stdint.h>
37#include <stdbool.h> 37#include <stdbool.h>
38#include <stdlib.h> 38#include <stdlib.h>
39
40#include <ti/osal/HwiP.h> 39#include <ti/osal/HwiP.h>
41 40
42/* 41/*
@@ -51,10 +50,10 @@ void HwiP_clearInterrupt(int32_t interruptNum)
51 * ======== HwiP_create ======== 50 * ======== HwiP_create ========
52 */ 51 */
53HwiP_Handle HwiP_create(int32_t interruptNum, HwiP_Fxn hwiFxn, 52HwiP_Handle HwiP_create(int32_t interruptNum, HwiP_Fxn hwiFxn,
54 HwiP_Params *params) 53 const HwiP_Params *params)
55{ 54{
56 /* stub */ 55 /* stub */
57 return ((HwiP_Handle)NULL); 56 return ((HwiP_Handle)NULL_PTR);
58} 57}
59 58
60/* 59/*
diff --git a/src/linux/SemaphoreP_linux.c b/src/linux/SemaphoreP_linux.c
index 71fa6ea..c407bce 100644
--- a/src/linux/SemaphoreP_linux.c
+++ b/src/linux/SemaphoreP_linux.c
@@ -49,7 +49,7 @@
49 * ======== SemaphoreP_create ======== 49 * ======== SemaphoreP_create ========
50 */ 50 */
51SemaphoreP_Handle SemaphoreP_create(uint32_t count, 51SemaphoreP_Handle SemaphoreP_create(uint32_t count,
52 SemaphoreP_Params *params) 52 const SemaphoreP_Params *params)
53{ 53{
54 sem_t *handle; 54 sem_t *handle;
55 55
diff --git a/src/linux/TimerP_linux.c b/src/linux/TimerP_linux.c
index b0cbcde..178b9fb 100644
--- a/src/linux/TimerP_linux.c
+++ b/src/linux/TimerP_linux.c
@@ -47,7 +47,7 @@ void TimerP_Params_init(TimerP_Params *params)
47 47
48TimerP_Handle TimerP_create(int32_t id, 48TimerP_Handle TimerP_create(int32_t id,
49 TimerP_Fxn tickFxn, 49 TimerP_Fxn tickFxn,
50 TimerP_Params *params) 50 const TimerP_Params *params)
51{ 51{
52 /* stub */ 52 /* stub */
53 return NULL; 53 return NULL;
diff --git a/src/linux/Utils_linux.c b/src/linux/Utils_linux.c
index 69a7571..0c2d102 100644
--- a/src/linux/Utils_linux.c
+++ b/src/linux/Utils_linux.c
@@ -40,8 +40,8 @@
40/* 40/*
41 * ======== _DebugP_assert ======== 41 * ======== _DebugP_assert ========
42 */ 42 */
43void _DebugP_assert(int32_t expression, const char *file, int32_t line); /*for misra warnings*/ 43void Osal_DebugP_assert(int32_t expression, const char *file, int32_t line); /*for misra warnings*/
44void _DebugP_assert(int32_t expression, const char *file, int32_t line) 44void Osal_DebugP_assert(int32_t expression, const char *file, int32_t line)
45{ 45{
46 if (expression) { 46 if (expression) {
47 while (1) {} 47 while (1) {}
diff --git a/src/nonos/EventCombinerP_nonos.c b/src/nonos/EventCombinerP_nonos.c
index d3f44a2..dcdb9a6 100644
--- a/src/nonos/EventCombinerP_nonos.c
+++ b/src/nonos/EventCombinerP_nonos.c
@@ -41,7 +41,6 @@
41#include <stdint.h> 41#include <stdint.h>
42#include <stdbool.h> 42#include <stdbool.h>
43#include <stdlib.h> 43#include <stdlib.h>
44
45#include <ti/osal/src/nonos/Nonos_config.h> 44#include <ti/osal/src/nonos/Nonos_config.h>
46 45
47#ifdef __cplusplus 46#ifdef __cplusplus
@@ -49,24 +48,24 @@ extern "C" {
49#endif 48#endif
50 49
51/* This is the number of c6x interrupts [0-15] */ 50/* This is the number of c6x interrupts [0-15] */
52#define OSAL_ECM_NUM_INTERRUPTS 16 51#define OSAL_ECM_NUM_INTERRUPTS (16)
53/************************************************************** 52/**************************************************************
54 Description: Returns the Hwi Handle associated with the event group. 53 Description: Returns the Hwi Handle associated with the event group.
55 It returns NULL if the Event combiner is not registered 54 It returns NULL_PTR if the Event combiner is not registered
56 with an interrupt vector (0-15) 55 with an interrupt vector (0-15)
57 Argument: The Event Combiner group Number [0-3] 56 Argument: The Event Combiner group Number [0-3]
58 Returns: The HwiHandle corresponding to the group number. 57 Returns: The HwiHandle corresponding to the group number.
59 NULL if it doesnt registered yet. 58 NULL_PTR if it doesnt registered yet.
60*******************************************************************/ 59*******************************************************************/
61HwiP_Handle EventCombinerP_getHwi(uint32_t groupNum) { 60HwiP_Handle EventCombinerP_getHwi(uint32_t groupNum) {
62 HwiP_Handle handle=NULL; 61 HwiP_Handle handle=NULL_PTR;
63 int32_t event,i; 62 int32_t event,i;
64 63
65 for(i=0;i<OSAL_ECM_NUM_INTERRUPTS;i++) { 64 for(i=0;i<OSAL_ECM_NUM_INTERRUPTS;i++) {
66 /* Find out the event associated with the interrupt vector number */ 65 /* Find out the event associated with the interrupt vector number */
67 event=HwiP_getEventId(i); 66 event=HwiP_getEventId(i);
68 67
69 if(event==groupNum) { 68 if((uint32_t)event==groupNum) {
70 /* If the associated event is the ECM group (0-3), 69 /* If the associated event is the ECM group (0-3),
71 * find out the event associated with the interrupt vector number */ 70 * find out the event associated with the interrupt vector number */
72 handle=HwiP_getHandle(i); 71 handle=HwiP_getHandle(i);
@@ -82,7 +81,7 @@ HwiP_Handle EventCombinerP_getHwi(uint32_t groupNum) {
82 Returns: The interrupt vector id corresponding to a groupNum. 81 Returns: The interrupt vector id corresponding to a groupNum.
83 -1 if the event combiner is not registered 82 -1 if the event combiner is not registered
84*******************************************************************/ 83*******************************************************************/
85int32_t EventCombinerP_getIntNum(uint32_t groupNum) { 84int32_t EventCombinerP_getIntNum(int32_t groupNum) {
86 85
87 int32_t event,i,intNum=-1; 86 int32_t event,i,intNum=-1;
88 87
@@ -144,10 +143,10 @@ int32_t EventCombinerP_enableEvent(uint32_t eventNum)
144{ 143{
145 uint32_t mask,groupId; 144 uint32_t mask,groupId;
146 145
147 groupId = eventNum/32; 146 groupId = eventNum/32U;
148 mask = 1 << (eventNum%32); 147 mask = (uint32_t)1U << (eventNum%32U);
149 /* Get the current mask and clear the bit first */ 148 /* Get the current mask and clear the bit first */
150 CSL_intcCombinedEventEnable(groupId, mask); 149 (void)CSL_intcCombinedEventEnable((CSL_IntcEventId)groupId, (CSL_BitMask32)mask);
151 return OSAL_EVTCOMBINE_GROUPREG_SUCCESS; 150 return OSAL_EVTCOMBINE_GROUPREG_SUCCESS;
152} 151}
153/************************************************************************** 152/**************************************************************************
@@ -162,10 +161,10 @@ int32_t EventCombinerP_disableEvent(uint32_t eventNum)
162{ 161{
163 uint32_t groupId,mask; 162 uint32_t groupId,mask;
164 163
165 groupId = eventNum/32; 164 groupId = eventNum/32U;
166 mask = 1 << (eventNum%32); 165 mask = (uint32_t)1U << (eventNum%32U);
167 166
168 CSL_intcCombinedEventDisable(groupId,mask); 167 (void)CSL_intcCombinedEventDisable((CSL_IntcEventId)groupId,(CSL_BitMask32)mask);
169 return OSAL_EVTCOMBINE_GROUPREG_SUCCESS; 168 return OSAL_EVTCOMBINE_GROUPREG_SUCCESS;
170} 169}
171/************************************************************************** 170/**************************************************************************
@@ -192,11 +191,11 @@ int32_t EventCombinerP_dispatchPlug(uint32_t eventId, void (*eventIsrRoutine)(ui
192 we use this temporary handle (which has ->eventId= corepac eventId) so that 191 we use this temporary handle (which has ->eventId= corepac eventId) so that
193 the CSL_intcPlugEventHandler(handleTemp,..) registers it 192 the CSL_intcPlugEventHandler(handleTemp,..) registers it
194 */ 193 */
195 handleTemp->eventId = eventId; 194 handleTemp->eventId = (CSL_IntcEventId)eventId;
196 evtHandler.handler = (CSL_IntcEventHandler)eventIsrRoutine; 195 evtHandler.handler = (CSL_IntcEventHandler)eventIsrRoutine;
197 evtHandler.arg = (void *)arg; 196 evtHandler.arg = (void *)arg;
198 CSL_intcPlugEventHandler(handleTemp, &evtHandler); 197 (void)CSL_intcPlugEventHandler(handleTemp, &evtHandler);
199 EventCombinerP_disableEvent(eventId); /* Disable event by default */ 198 (void)EventCombinerP_disableEvent(eventId); /* Disable event by default */
200 CSL_rint(); 199 CSL_rint();
201 200
202 /* Nothing to be done, as HwiP_Create() already takes care of this internally, via CSL_intcOpen() */ 201 /* Nothing to be done, as HwiP_Create() already takes care of this internally, via CSL_intcOpen() */
diff --git a/src/nonos/HwiP_nonos.c b/src/nonos/HwiP_nonos.c
index 0391cab..80ac911 100644
--- a/src/nonos/HwiP_nonos.c
+++ b/src/nonos/HwiP_nonos.c
@@ -53,13 +53,13 @@ void HwiP_clearInterrupt(int32_t interruptNum)
53 * ======== HwiP_create ======== 53 * ======== HwiP_create ========
54 */ 54 */
55HwiP_Handle HwiP_create(int32_t interruptNum, HwiP_Fxn hwiFxn, 55HwiP_Handle HwiP_create(int32_t interruptNum, HwiP_Fxn hwiFxn,
56 HwiP_Params *params) 56 const HwiP_Params *params)
57{ 57{
58 HwiP_Handle handle; 58 HwiP_Handle handle;
59 handle = OsalArch_HwiPCreate(interruptNum,hwiFxn,params); 59 handle = OsalArch_HwiPCreate(interruptNum,hwiFxn,params);
60 60
61 /* Update statistics for successful allocation */ 61 /* Update statistics for successful allocation */
62 if (handle != (HwiP_Handle) NULL) 62 if (handle != NULL_PTR)
63 { 63 {
64 gOsalHwiAllocCnt++; 64 gOsalHwiAllocCnt++;
65 if (gOsalHwiAllocCnt > gOsalHwiPeak) 65 if (gOsalHwiAllocCnt > gOsalHwiPeak)
@@ -75,19 +75,25 @@ HwiP_Handle HwiP_create(int32_t interruptNum, HwiP_Fxn hwiFxn,
75 */ 75 */
76HwiP_Status HwiP_delete(HwiP_Handle handle) 76HwiP_Status HwiP_delete(HwiP_Handle handle)
77{ 77{
78 OSAL_Assert((handle == NULL));
79
80 HwiP_Status status; 78 HwiP_Status status;
81 79
82 status = OsalArch_HwiPDelete(handle); 80 OSAL_Assert((handle == NULL_PTR));
83 81
84 if (status == HwiP_OK) 82 if(handle!=NULL_PTR) {
85 { 83 status = OsalArch_HwiPDelete(handle);
84
85 if (status == HwiP_OK)
86 {
86 if (gOsalHwiAllocCnt > 0U) 87 if (gOsalHwiAllocCnt > 0U)
87 { 88 {
88 gOsalHwiAllocCnt--; 89 gOsalHwiAllocCnt--;
89 } 90 }
90 } 91 }
92 }
93 else
94 {
95 status = HwiP_FAILURE;
96 }
91 97
92 return (status); 98 return (status);
93} 99}
@@ -133,17 +139,17 @@ int32_t HwiP_post(uint32_t interruptNum)
133 */ 139 */
134void HwiP_Params_init(HwiP_Params *params) 140void HwiP_Params_init(HwiP_Params *params)
135{ 141{
136 params->name = NULL; 142 params->name = NULL_PTR;
137 params->arg = 0; 143 params->arg = 0;
138 params->priority = HWIP_USE_DEFAULT_PRIORITY; 144 params->priority = HWIP_USE_DEFAULT_PRIORITY;
139 params->evtId = 0; 145 params->evtId = 0;
140 params->enableIntr = TRUE; 146 params->enableIntr = TRUE;
141#if defined (__ARM_ARCH_7A__) || defined(__aarch64__) || defined (__TI_ARM_V7R4__) 147#if defined (__ARM_ARCH_7A__) || defined(__aarch64__) || defined (__TI_ARM_V7R4__)
142 params->triggerSensitivity = OSAL_ARM_GIC_TRIG_TYPE_LEVEL; 148 params->triggerSensitivity = (uint32_t)OSAL_ARM_GIC_TRIG_TYPE_LEVEL;
143#if !defined (SOC_AM437x) && !defined(SOC_AM335x) && !defined (__TI_ARM_V7R4__) 149#if !defined (SOC_AM437x) && !defined(SOC_AM335x) && !defined (__TI_ARM_V7R4__)
144 { 150 {
145 Osal_HwAttrs hwAttrs; 151 Osal_HwAttrs hwAttrs;
146 Osal_getHwAttrs(&hwAttrs); 152 (void)Osal_getHwAttrs(&hwAttrs);
147 if(hwAttrs.hwAccessType==OSAL_HWACCESS_UNRESTRICTED) 153 if(hwAttrs.hwAccessType==OSAL_HWACCESS_UNRESTRICTED)
148 { 154 {
149 /* Do GIC init only in the case of unrestricted hw access */ 155 /* Do GIC init only in the case of unrestricted hw access */
diff --git a/src/nonos/Nonos_config.h b/src/nonos/Nonos_config.h
index 3596892..c9db72e 100755
--- a/src/nonos/Nonos_config.h
+++ b/src/nonos/Nonos_config.h
@@ -46,14 +46,6 @@ extern "C" {
46#include <ti/osal/soc/osal_soc.h> 46#include <ti/osal/soc/osal_soc.h>
47#include <ti/csl/csl_types.h> 47#include <ti/csl/csl_types.h>
48 48
49
50/* TimeStamp Provider structure */
51typedef struct timeStamp_struct
52{
53 uint32_t lo;
54 uint32_t hi;
55}TimeStamp_Struct;
56
57/* Host emulation defines _TMS320C6X which needs to be */ 49/* Host emulation defines _TMS320C6X which needs to be */
58#if defined (HOST_EMULATION) 50#if defined (HOST_EMULATION)
59 #if defined (__C7100__) 51 #if defined (__C7100__)
@@ -119,6 +111,15 @@ typedef struct hwi_struct {
119} Hwi_Struct; 111} Hwi_Struct;
120#endif 112#endif
121 113
114
115/* TimeStamp Provider structure */
116typedef struct timeStamp_struct
117{
118 uint32_t lo;
119 uint32_t hi;
120}TimeStamp_Struct;
121
122
122#define TIMERP_EVENT_NOT_AVAILABLE (-(int32_t) (1u)) 123#define TIMERP_EVENT_NOT_AVAILABLE (-(int32_t) (1u))
123#define TIMERP_INTR_USER_CONFIGURE (-(int32_t) (2u)) 124#define TIMERP_INTR_USER_CONFIGURE (-(int32_t) (2u))
124#define TIMERP_EVENT_USER_CONFIGURE (-(int32_t) (3u)) 125#define TIMERP_EVENT_USER_CONFIGURE (-(int32_t) (3u))
@@ -211,7 +212,7 @@ void OsalArch_globalRestoreInterrupt (uintptr_t restoreValue);
211 212
212/* Below function registers the interrupt for a given ISR */ 213/* Below function registers the interrupt for a given ISR */
213HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn, 214HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn,
214 HwiP_Params *params); 215 const HwiP_Params *params);
215 216
216/* Below function deletes/frees up the HwiP handle created */ 217/* Below function deletes/frees up the HwiP handle created */
217HwiP_Status OsalArch_HwiPDelete(HwiP_Handle handle); 218HwiP_Status OsalArch_HwiPDelete(HwiP_Handle handle);
@@ -240,6 +241,18 @@ int32_t OsalArch_getEventId(int32_t interruptNum);
240 241
241extern Osal_HwAttrs gOsal_HwAttrs; 242extern Osal_HwAttrs gOsal_HwAttrs;
242 243
244
245#ifndef NULL_PTR
246#define NULL_PTR ((void *)0x0)
247#endif
248/*
249 * Dummy function to check size during compile time
250 * ======== HwiP_compileTime_SizeChk ========
251 */
252void OsalArch_compileTime_SizeChk(void);
253void SemaphoreP_compileTime_SizeChk(void);
254void HwiP_compileTime_SizeChk(void);
255
243#ifdef __cplusplus 256#ifdef __cplusplus
244} 257}
245#endif 258#endif
diff --git a/src/nonos/RegisterIntr_nonos.c b/src/nonos/RegisterIntr_nonos.c
index 7266ad2..d881814 100755
--- a/src/nonos/RegisterIntr_nonos.c
+++ b/src/nonos/RegisterIntr_nonos.c
@@ -41,7 +41,6 @@
41#include <ti/osal/src/nonos/Nonos_config.h> 41#include <ti/osal/src/nonos/Nonos_config.h>
42#include <ti/osal/RegisterIntr.h> 42#include <ti/osal/RegisterIntr.h>
43#include <ti/csl/csl.h> 43#include <ti/csl/csl.h>
44#include <ti/csl/tistdtypes.h>
45#ifdef _TMS320C6X 44#ifdef _TMS320C6X
46#include <ti/csl/src/intc/csl_intcAux.h> 45#include <ti/csl/src/intc/csl_intcAux.h>
47#endif 46#endif
@@ -57,24 +56,24 @@ extern "C" {
57 */ 56 */
58void Osal_RegisterInterrupt_initParams(OsalRegisterIntrParams_t *interruptRegParams) 57void Osal_RegisterInterrupt_initParams(OsalRegisterIntrParams_t *interruptRegParams)
59{ 58{
60 if(interruptRegParams!=NULL) { 59 if(interruptRegParams!=NULL_PTR) {
61 /* Corepac config */ 60 /* Corepac config */
62 interruptRegParams->corepacConfig.name=NULL; 61 interruptRegParams->corepacConfig.name=NULL_PTR;
63 interruptRegParams->corepacConfig.corepacEventNum=-1; 62 interruptRegParams->corepacConfig.corepacEventNum=-1;
64 interruptRegParams->corepacConfig.intVecNum=-1; 63 interruptRegParams->corepacConfig.intVecNum=-1;
65 interruptRegParams->corepacConfig.isrRoutine=NULL; 64 interruptRegParams->corepacConfig.isrRoutine=NULL_PTR;
66 interruptRegParams->corepacConfig.arg=(uintptr_t)NULL; 65 interruptRegParams->corepacConfig.arg=(uintptr_t)0U;
67 interruptRegParams->corepacConfig.priority=0x20U; /* Default */ 66 interruptRegParams->corepacConfig.priority=0x20U; /* Default */
68#if defined (__ARM_ARCH_7A__) 67#if defined (__ARM_ARCH_7A__)
69 interruptRegParams->corepacConfig.triggerSensitivity = 0x3; /* interrupt edge triggered */ 68 interruptRegParams->corepacConfig.triggerSensitivity = 0x3; /* interrupt edge triggered */
70#endif 69#endif
71 70
72#if defined(__aarch64__) || defined (__TI_ARM_V7R4__) 71#if defined(__aarch64__) || defined (__TI_ARM_V7R4__)
73 interruptRegParams->corepacConfig.triggerSensitivity = OSAL_ARM_GIC_TRIG_TYPE_LEVEL; /* interrupt level triggered */ 72 interruptRegParams->corepacConfig.triggerSensitivity = (uint32_t)OSAL_ARM_GIC_TRIG_TYPE_LEVEL; /* interrupt level triggered */
74#endif 73#endif
75 /* SOC Mux Config */ 74 /* SOC Mux Config */
76 interruptRegParams->socMuxConfig.muxInParams=NULL; 75 interruptRegParams->socMuxConfig.muxInParams=NULL_PTR;
77 interruptRegParams->socMuxConfig.muxOutParams=NULL; 76 interruptRegParams->socMuxConfig.muxOutParams=NULL_PTR;
78 } 77 }
79 return; 78 return;
80} 79}
@@ -88,11 +87,11 @@ OsalInterruptRetCode_e Osal_RegisterInterrupt(OsalRegisterIntrParams_t *interrup
88{ 87{
89 88
90 OsalInterruptRetCode_e ret=OSAL_INT_SUCCESS; 89 OsalInterruptRetCode_e ret=OSAL_INT_SUCCESS;
91 HwiP_Handle hwiPHandle=NULL; 90 HwiP_Handle hwiPHandle=NULL_PTR;
92 HwiP_Params hwiInputParams; 91 HwiP_Params hwiInputParams;
93 92
94 /* Program the corepac interrupt */ 93 /* Program the corepac interrupt */
95 if( (interruptRegParams->corepacConfig.isrRoutine ==NULL) || 94 if( (interruptRegParams->corepacConfig.isrRoutine ==NULL_PTR) ||
96 (interruptRegParams->corepacConfig.corepacEventNum<0)) { 95 (interruptRegParams->corepacConfig.corepacEventNum<0)) {
97 ret=OSAL_INT_ERR_INVALID_PARAMS; 96 ret=OSAL_INT_ERR_INVALID_PARAMS;
98 } 97 }
@@ -102,7 +101,7 @@ OsalInterruptRetCode_e Osal_RegisterInterrupt(OsalRegisterIntrParams_t *interrup
102 hwiInputParams.name = interruptRegParams->corepacConfig.name; 101 hwiInputParams.name = interruptRegParams->corepacConfig.name;
103 hwiInputParams.arg = (uintptr_t)interruptRegParams->corepacConfig.arg; 102 hwiInputParams.arg = (uintptr_t)interruptRegParams->corepacConfig.arg;
104 hwiInputParams.priority = interruptRegParams->corepacConfig.priority; 103 hwiInputParams.priority = interruptRegParams->corepacConfig.priority;
105 hwiInputParams.evtId = interruptRegParams->corepacConfig.corepacEventNum; 104 hwiInputParams.evtId = (uint32_t)interruptRegParams->corepacConfig.corepacEventNum;
106#if defined (__ARM_ARCH_7A__) || defined (__aarch64__) || defined (__TI_ARM_V7R4__) 105#if defined (__ARM_ARCH_7A__) || defined (__aarch64__) || defined (__TI_ARM_V7R4__)
107 hwiInputParams.triggerSensitivity = interruptRegParams->corepacConfig.triggerSensitivity; 106 hwiInputParams.triggerSensitivity = interruptRegParams->corepacConfig.triggerSensitivity;
108#endif 107#endif
@@ -116,48 +115,46 @@ OsalInterruptRetCode_e Osal_RegisterInterrupt(OsalRegisterIntrParams_t *interrup
116 HwiP_Create(Event_combiner_event,core_intVecNum,Event_dispatcher_plug); 115 HwiP_Create(Event_combiner_event,core_intVecNum,Event_dispatcher_plug);
117*/ 116*/
118 if(interruptRegParams->corepacConfig.intVecNum == OSAL_REGINT_INTVEC_EVENT_COMBINER) { 117 if(interruptRegParams->corepacConfig.intVecNum == OSAL_REGINT_INTVEC_EVENT_COMBINER) {
119 EventCombinerP_dispatchPlug(interruptRegParams->corepacConfig.corepacEventNum, 118 (void)EventCombinerP_dispatchPlug((uint32_t)interruptRegParams->corepacConfig.corepacEventNum,
120 interruptRegParams->corepacConfig.isrRoutine, 119 interruptRegParams->corepacConfig.isrRoutine,
121 interruptRegParams->corepacConfig.arg,TRUE); 120 interruptRegParams->corepacConfig.arg,(bool)true);
122 121
123 EventCombinerP_enableEvent(interruptRegParams->corepacConfig.corepacEventNum); 122 (void)EventCombinerP_enableEvent((uint32_t)interruptRegParams->corepacConfig.corepacEventNum);
124 /* Map to a particular group */ 123 /* Map to a particular group */
125 if(hwiInputParams.evtId > 3) { 124 if(hwiInputParams.evtId > 3U) {
126 /* For C66X the interrupt needs to be grouped to {0,1,2,3} to either of the four 32-bit event registers */ 125 /* For C66X the interrupt needs to be grouped to {0,1,2,3} to either of the four 32-bit event registers */
127 hwiInputParams.evtId= interruptRegParams->corepacConfig.corepacEventNum/32; 126 hwiInputParams.evtId= ((uint32_t)interruptRegParams->corepacConfig.corepacEventNum)/32U;
128 } 127 }
129 /* The dispatch function in the event combiner case is EventCombiner_dispatch */ 128 /* The dispatch function in the event combiner case is EventCombiner_dispatch */
130 129
131 /* Find out if the event combiner is already registered, if so, dont re-register */ 130 /* Find out if the event combiner is already registered, if so, dont re-register */
132 hwiPHandle = EventCombinerP_getHwi(hwiInputParams.evtId); 131 hwiPHandle = EventCombinerP_getHwi(hwiInputParams.evtId);
133 if(hwiPHandle==NULL) { 132 if(hwiPHandle==NULL_PTR) {
134 /* The event hasn't been registered yet. Register it as per the defaults provided by OSAL */ 133 /* The event hasn't been registered yet. Register it as per the defaults provided by OSAL */
135 Osal_HwAttrs hwAttrs; 134 Osal_HwAttrs hwAttrs;
136 135
137 /* Get the default OSAL mapped ones */ 136 /* Get the default OSAL mapped ones */
138 Osal_getHwAttrs(&hwAttrs); 137 (void)Osal_getHwAttrs(&hwAttrs);
139 138
140 /* No need to register seperately in case of baremetal , the HwiP_Create() takes care of it */ 139 /* No need to register seperately in case of baremetal , the HwiP_Create() takes care of it */
141 140
142 hwiPHandle = HwiP_create(hwAttrs.ECM_intNum[hwiInputParams.evtId],interruptRegParams->corepacConfig.isrRoutine, &hwiInputParams); 141 hwiPHandle = HwiP_create(hwAttrs.ECM_intNum[hwiInputParams.evtId],interruptRegParams->corepacConfig.isrRoutine, &hwiInputParams);
143 142
144 if(hwiPHandle==NULL) { 143 if(hwiPHandle==NULL_PTR) {
145 ret=OSAL_INT_ERR_EVENTCOMBINER_REG; 144 ret=OSAL_INT_ERR_EVENTCOMBINER_REG;
146 goto finish_processing;
147 } 145 }
148 } else { 146 } else {
149 /* The Event combiner handle already exists. Now plug the ISR routine in to 147 /* The Event combiner handle already exists. Now plug the ISR routine in to
150 the CSL_intcEventHandlerRecord_p */ 148 the CSL_intcEventHandlerRecord_p */
151 EventCombinerP_dispatchPlug(interruptRegParams->corepacConfig.corepacEventNum, 149 (void)EventCombinerP_dispatchPlug((uint32_t)interruptRegParams->corepacConfig.corepacEventNum,
152 interruptRegParams->corepacConfig.isrRoutine, 150 interruptRegParams->corepacConfig.isrRoutine,
153 interruptRegParams->corepacConfig.arg,TRUE); 151 interruptRegParams->corepacConfig.arg,(bool)true);
154 } 152 }
155 } else { 153 } else {
156 /* Do not use the event combiner. Use the supplied ISR routine */ 154 /* Do not use the event combiner. Use the supplied ISR routine */
157 hwiPHandle = HwiP_create(interruptRegParams->corepacConfig.intVecNum,interruptRegParams->corepacConfig.isrRoutine, &hwiInputParams); 155 hwiPHandle = HwiP_create(interruptRegParams->corepacConfig.intVecNum,interruptRegParams->corepacConfig.isrRoutine, &hwiInputParams);
158 if(hwiPHandle ==NULL) { 156 if(hwiPHandle ==NULL_PTR) {
159 ret=OSAL_INT_ERR_HWICREATE; 157 ret=OSAL_INT_ERR_HWICREATE;
160 goto finish_processing;
161 } 158 }
162 } 159 }
163#else 160#else
@@ -165,7 +162,7 @@ OsalInterruptRetCode_e Osal_RegisterInterrupt(OsalRegisterIntrParams_t *interrup
165#if (defined (__ARM_ARCH_7A__) || defined (__aarch64__)) && !defined (SOC_AM437x) && !defined(SOC_AM335x) 162#if (defined (__ARM_ARCH_7A__) || defined (__aarch64__)) && !defined (SOC_AM437x) && !defined(SOC_AM335x)
166 /* Initialize GIC if not done already */ 163 /* Initialize GIC if not done already */
167 Osal_HwAttrs hwAttrs; 164 Osal_HwAttrs hwAttrs;
168 Osal_getHwAttrs(&hwAttrs); 165 (void)Osal_getHwAttrs(&hwAttrs);
169 if(hwAttrs.hwAccessType==OSAL_HWACCESS_UNRESTRICTED) 166 if(hwAttrs.hwAccessType==OSAL_HWACCESS_UNRESTRICTED)
170 { 167 {
171 /* Do GIC init only in the case of unrestricted hw access */ 168 /* Do GIC init only in the case of unrestricted hw access */
@@ -182,13 +179,11 @@ OsalInterruptRetCode_e Osal_RegisterInterrupt(OsalRegisterIntrParams_t *interrup
182#endif 179#endif
183 180
184 hwiPHandle = HwiP_create(interruptRegParams->corepacConfig.intVecNum,interruptRegParams->corepacConfig.isrRoutine, &hwiInputParams); 181 hwiPHandle = HwiP_create(interruptRegParams->corepacConfig.intVecNum,interruptRegParams->corepacConfig.isrRoutine, &hwiInputParams);
185 if(hwiPHandle ==NULL) { 182 if(hwiPHandle ==NULL_PTR) {
186 ret=OSAL_INT_ERR_HWICREATE; 183 ret=OSAL_INT_ERR_HWICREATE;
187 goto finish_processing;
188 } 184 }
189#endif 185#endif
190 186
191finish_processing:
192 *hwiPHandlePtr=hwiPHandle; 187 *hwiPHandlePtr=hwiPHandle;
193 return ret ; 188 return ret ;
194} 189}
@@ -217,8 +212,8 @@ OsalInterruptRetCode_e Osal_DeleteInterrupt(HwiP_Handle handle,int32_t corepacEv
217 hwi_eventId=(((Hwi_Struct *)handle)->handle)->eventId; 212 hwi_eventId=(((Hwi_Struct *)handle)->handle)->eventId;
218 if( (hwi_eventId > 0) && (hwi_eventId <4)) { 213 if( (hwi_eventId > 0) && (hwi_eventId <4)) {
219 /* This is event combiner, so do not destroy the hwi, but remove the dispatch table entry */ 214 /* This is event combiner, so do not destroy the hwi, but remove the dispatch table entry */
220 EventCombinerP_dispatchPlug(corepacEventNum,NULL,0,FALSE); 215 (void)EventCombinerP_dispatchPlug((uint32_t)corepacEventNum,NULL_PTR,0,(bool)false);
221 EventCombinerP_disableEvent(corepacEventNum); 216 (void)EventCombinerP_disableEvent((uint32_t)corepacEventNum);
222 /* Return Success */ 217 /* Return Success */
223 } else { 218 } else {
224 /* This is not an event dispatcher function, so destruct the HwiP as usual */ 219 /* This is not an event dispatcher function, so destruct the HwiP as usual */
@@ -257,12 +252,12 @@ void Osal_EnableInterrupt(int32_t corepacEvent,int32_t interruptNum)
257 /* If this is called from a module which uses event combiner */ 252 /* If this is called from a module which uses event combiner */
258 /* Just enable the event inside the event combiner and 253 /* Just enable the event inside the event combiner and
259 * not the whole interrupt as it will be used by the event dispatcher */ 254 * not the whole interrupt as it will be used by the event dispatcher */
260 EventCombinerP_enableEvent(corepacEvent); 255 (void)EventCombinerP_enableEvent((uint32_t)corepacEvent);
261 /* Make sure GIE bit in CSR is set for interrupts */ 256 /* Make sure GIE bit in CSR is set for interrupts */
262 csrRegVal = CSL_chipReadCSR(); 257 csrRegVal = CSL_chipReadCSR();
263 if (!(csrRegVal & CSL_CHIP_CSR_GIE_ENABLE)) { 258 if ((csrRegVal & CSL_CHIP_CSR_GIE_ENABLE) == 0U) {
264 csrRegVal |= CSL_CHIP_CSR_GIE_ENABLE; 259 csrRegVal |= CSL_CHIP_CSR_GIE_ENABLE;
265 CSL_chipWriteCSR(csrRegVal); 260 (void)CSL_chipWriteCSR(csrRegVal);
266 } 261 }
267 } else { 262 } else {
268 /* This is not an event combiner based interrupt */ 263 /* This is not an event combiner based interrupt */
@@ -289,7 +284,7 @@ void Osal_DisableInterrupt(int32_t corepacEvent,int32_t interruptNum)
289 /* If this is called from a module which uses event combiner */ 284 /* If this is called from a module which uses event combiner */
290 /* Just enable the event inside the event combiner and 285 /* Just enable the event inside the event combiner and
291 * not the whole interrupt as it will be used by the event dispatcher */ 286 * not the whole interrupt as it will be used by the event dispatcher */
292 EventCombinerP_disableEvent(corepacEvent); 287 (void)EventCombinerP_disableEvent((uint32_t)corepacEvent);
293 } else { 288 } else {
294 /* This is not an event combiner based interrupt */ 289 /* This is not an event combiner based interrupt */
295 HwiP_disableInterrupt(interruptNum); 290 HwiP_disableInterrupt(interruptNum);
@@ -311,7 +306,7 @@ void Osal_ClearInterrupt(int32_t corepacEvent,int32_t interruptNum)
311 int32_t intNum=interruptNum; 306 int32_t intNum=interruptNum;
312#ifdef _TMS320C6X 307#ifdef _TMS320C6X
313 if(interruptNum==OSAL_REGINT_INTVEC_EVENT_COMBINER) { 308 if(interruptNum==OSAL_REGINT_INTVEC_EVENT_COMBINER) {
314 uint32_t groupNum=corepacEvent/32; 309 int32_t groupNum=corepacEvent/32;
315 /* If this is called from a module which uses event combiner, 310 /* If this is called from a module which uses event combiner,
316 * get the corresponding interrupt number for that particular event 311 * get the corresponding interrupt number for that particular event
317 * before proceeding to clear it */ 312 * before proceeding to clear it */
diff --git a/src/nonos/SemaphoreP_nonos.c b/src/nonos/SemaphoreP_nonos.c
index b03effa..d2a7bd7 100644
--- a/src/nonos/SemaphoreP_nonos.c
+++ b/src/nonos/SemaphoreP_nonos.c
@@ -54,18 +54,7 @@ typedef struct Sem_Struct_s {
54 SemaphoreP_Mode mode; 54 SemaphoreP_Mode mode;
55} Sem_Struct; 55} Sem_Struct;
56 56
57Sem_Struct semStructs[OSAL_NONOS_CONFIGNUM_SEMAPHORE] = 57Sem_Struct semStructs[OSAL_NONOS_CONFIGNUM_SEMAPHORE];
58{
59 {false, 0, 0, SemaphoreP_Mode_COUNTING},
60 {false, 1, 0, SemaphoreP_Mode_COUNTING},
61 {false, 2, 0, SemaphoreP_Mode_COUNTING},
62 {false, 3, 0, SemaphoreP_Mode_COUNTING},
63 {false, 4, 0, SemaphoreP_Mode_COUNTING},
64 {false, 5, 0, SemaphoreP_Mode_COUNTING},
65 {false, 6, 0, SemaphoreP_Mode_COUNTING},
66 {false, 7, 0, SemaphoreP_Mode_COUNTING}
67};
68
69/* 58/*
70 * Dummy function to check size during compile time 59 * Dummy function to check size during compile time
71 * ======== SemaphoreP_compileTime_SizeChk ======== 60 * ======== SemaphoreP_compileTime_SizeChk ========
@@ -80,17 +69,30 @@ void SemaphoreP_compileTime_SizeChk(void)
80/* TI compiler */ 69/* TI compiler */
81#pragma diag_suppress 179 70#pragma diag_suppress 179
82#endif 71#endif
83 OSAL_COMPILE_TIME_SIZE_CHECK (sizeof(Sem_Struct) < OSAL_NONOS_SEMAPHOREP_SIZE_BYTES); 72 OSAL_COMPILE_TIME_SIZE_CHECK ((uint32_t)sizeof(Sem_Struct),OSAL_NONOS_SEMAPHOREP_SIZE_BYTES);
84#if defined(__GNUC__) && !defined(__ti__) 73#if defined(__GNUC__) && !defined(__ti__)
85#pragma GCC diagnostic pop 74#pragma GCC diagnostic pop
86#endif 75#endif
87} 76}
77static void semaphoreInit( Sem_Struct *semPool, uint32_t maxSemaphores)
78{
79 uint32_t i;
80 Sem_Struct *semPool_ptr = semPool;
81 for(i=0;i<maxSemaphores;i++)
82 {
83 semPool_ptr->used = (bool)false;
84 semPool_ptr->sem = i;
85 semPool_ptr->count = 0;
86 semPool_ptr->mode = SemaphoreP_Mode_COUNTING;
87 semPool_ptr++;
88 }
88 89
90}
89/* 91/*
90 * ======== SemaphoreP_create ======== 92 * ======== SemaphoreP_create ========
91 */ 93 */
92SemaphoreP_Handle SemaphoreP_create(uint32_t count, 94SemaphoreP_Handle SemaphoreP_create(uint32_t count,
93 SemaphoreP_Params *params) 95 const SemaphoreP_Params *params)
94{ 96{
95 uint32_t i; 97 uint32_t i;
96 uintptr_t key; 98 uintptr_t key;
@@ -104,7 +106,7 @@ SemaphoreP_Handle SemaphoreP_create(uint32_t count,
104 /* Check if user has specified any memory block to be used, which gets 106 /* Check if user has specified any memory block to be used, which gets
105 * the precedence over the internal static memory block 107 * the precedence over the internal static memory block
106 */ 108 */
107 if (gOsal_HwAttrs.extSemaphorePBlock.base != (uintptr_t)NULL) 109 if (gOsal_HwAttrs.extSemaphorePBlock.base != (uintptr_t)0U)
108 { 110 {
109 /* pick up the external memory block configured */ 111 /* pick up the external memory block configured */
110 semPool = (Sem_Struct *) gOsal_HwAttrs.extSemaphorePBlock.base; 112 semPool = (Sem_Struct *) gOsal_HwAttrs.extSemaphorePBlock.base;
@@ -117,12 +119,17 @@ SemaphoreP_Handle SemaphoreP_create(uint32_t count,
117 semPool = (Sem_Struct *) &semStructs[0]; 119 semPool = (Sem_Struct *) &semStructs[0];
118 maxSemaphores = OSAL_NONOS_CONFIGNUM_SEMAPHORE; 120 maxSemaphores = OSAL_NONOS_CONFIGNUM_SEMAPHORE;
119 } 121 }
120 122 /* First time, semaphores are not initialized */
123 if(gOsalSemAllocCnt==0U)
124 {
125 semaphoreInit(semPool,maxSemaphores);
126 }
127
121 for (i = 0; i < maxSemaphores; i++) 128 for (i = 0; i < maxSemaphores; i++)
122 { 129 {
123 if (semPool[i].used == false) 130 if (semPool[i].used == (bool)false)
124 { 131 {
125 semPool[i].used = true; 132 semPool[i].used = (bool)true;
126 133
127 /* Update statistics */ 134 /* Update statistics */
128 gOsalSemAllocCnt++; 135 gOsalSemAllocCnt++;
@@ -133,7 +140,7 @@ SemaphoreP_Handle SemaphoreP_create(uint32_t count,
133 140
134 semPool[i].sem = i; 141 semPool[i].sem = i;
135 semPool[i].count = count; 142 semPool[i].count = count;
136 if (params) 143 if (params != NULL_PTR)
137 { 144 {
138 semPool[i].mode = params->mode; 145 semPool[i].mode = params->mode;
139 } 146 }
@@ -145,7 +152,7 @@ SemaphoreP_Handle SemaphoreP_create(uint32_t count,
145 152
146 if (i == maxSemaphores) 153 if (i == maxSemaphores)
147 { 154 {
148 ret_val = NULL; 155 ret_val = NULL_PTR;
149 } 156 }
150 else 157 else
151 { 158 {
@@ -159,21 +166,29 @@ SemaphoreP_Handle SemaphoreP_create(uint32_t count,
159 */ 166 */
160SemaphoreP_Status SemaphoreP_delete(SemaphoreP_Handle handle) 167SemaphoreP_Status SemaphoreP_delete(SemaphoreP_Handle handle)
161{ 168{
162 OSAL_Assert((handle == NULL)); 169 OSAL_Assert((handle == NULL_PTR));
163 170 SemaphoreP_Status ret = SemaphoreP_OK;
164 uintptr_t key; 171 uintptr_t key;
165 Sem_Struct *semS = (Sem_Struct *)handle; 172 Sem_Struct *semS = (Sem_Struct *)handle;
166 173
167 key = HwiP_disable(); 174 if(semS != NULL_PTR)
168 semS->used = false;
169 /* Found the bsp osal semaphore object to delete */
170 if (gOsalSemAllocCnt > 0U)
171 { 175 {
176 key = HwiP_disable();
177 semS->used = (bool)false;
178 /* Found the bsp osal semaphore object to delete */
179 if (gOsalSemAllocCnt > 0U)
180 {
172 gOsalSemAllocCnt--; 181 gOsalSemAllocCnt--;
182 }
183 HwiP_restore(key);
184 ret = SemaphoreP_OK;
173 } 185 }
174 HwiP_restore(key); 186 else
187 {
188 ret = SemaphoreP_FAILURE;
189 }
175 190
176 return (SemaphoreP_OK); 191 return (ret);
177} 192}
178 193
179/* 194/*
@@ -181,9 +196,11 @@ SemaphoreP_Status SemaphoreP_delete(SemaphoreP_Handle handle)
181 */ 196 */
182void SemaphoreP_Params_init(SemaphoreP_Params *params) 197void SemaphoreP_Params_init(SemaphoreP_Params *params)
183{ 198{
184 OSAL_Assert((params == NULL)); 199 OSAL_Assert((params == NULL_PTR));
185 params->mode = SemaphoreP_Mode_COUNTING; 200 if(params!=NULL_PTR) {
186 params->name = NULL; 201 params->mode = SemaphoreP_Mode_COUNTING;
202 params->name = NULL_PTR;
203 }
187} 204}
188 205
189/* 206/*
@@ -191,17 +208,19 @@ void SemaphoreP_Params_init(SemaphoreP_Params *params)
191 */ 208 */
192SemaphoreP_Status SemaphoreP_pend(SemaphoreP_Handle handle, uint32_t timeout) 209SemaphoreP_Status SemaphoreP_pend(SemaphoreP_Handle handle, uint32_t timeout)
193{ 210{
194 OSAL_Assert((handle == NULL)); 211 OSAL_Assert((handle == NULL_PTR));
195 212
196 uintptr_t key; 213 uintptr_t key;
197 Sem_Struct *semS = (Sem_Struct *)handle; 214 Sem_Struct *semS = (Sem_Struct *)handle;
198 uint32_t semTimeout = timeout; 215 uint32_t semTimeout = timeout;
199 SemaphoreP_Status ret_val = SemaphoreP_OK; 216 SemaphoreP_Status ret_val = SemaphoreP_OK;
200 217 bool iterate = (bool)true;
201 while (ret_val == SemaphoreP_OK) 218
202 { 219 if(semS!=NULL) {
220 while ( (ret_val == SemaphoreP_OK) && (iterate== (bool)true))
221 {
203 key = HwiP_disable(); 222 key = HwiP_disable();
204 if (semS->count > 0) 223 if (semS->count > 0U)
205 { 224 {
206 if (semS->mode == SemaphoreP_Mode_BINARY) 225 if (semS->mode == SemaphoreP_Mode_BINARY)
207 { 226 {
@@ -212,15 +231,15 @@ SemaphoreP_Status SemaphoreP_pend(SemaphoreP_Handle handle, uint32_t timeout)
212 semS->count--; 231 semS->count--;
213 } 232 }
214 HwiP_restore(key); 233 HwiP_restore(key);
215 break; 234 iterate=(bool)false;
216 } 235 }
217 else 236 else
218 { 237 {
219 HwiP_restore(key); 238 HwiP_restore(key);
220 if (semTimeout == SemaphoreP_NO_WAIT) 239 if (semTimeout == SemaphoreP_NO_WAIT)
221 { 240 {
222 ret_val = (SemaphoreP_TIMEOUT); 241 ret_val = (SemaphoreP_TIMEOUT);
223 break; 242 iterate=(bool)false;
224 } 243 }
225 else if (semTimeout == SemaphoreP_WAIT_FOREVER) 244 else if (semTimeout == SemaphoreP_WAIT_FOREVER)
226 { 245 {
@@ -228,11 +247,15 @@ SemaphoreP_Status SemaphoreP_pend(SemaphoreP_Handle handle, uint32_t timeout)
228 } 247 }
229 else /* Timed wait */ 248 else /* Timed wait */
230 { 249 {
231 Osal_delay(1); 250 (void)Osal_delay(1);
232 semTimeout--; 251 semTimeout--;
233 } 252 }
234 } 253 }
235 } 254 }
255 } else
256 {
257 ret_val = SemaphoreP_FAILURE;
258 }
236 259
237 return (ret_val); 260 return (ret_val);
238} 261}
@@ -242,23 +265,31 @@ SemaphoreP_Status SemaphoreP_pend(SemaphoreP_Handle handle, uint32_t timeout)
242 */ 265 */
243SemaphoreP_Status SemaphoreP_post(SemaphoreP_Handle handle) 266SemaphoreP_Status SemaphoreP_post(SemaphoreP_Handle handle)
244{ 267{
245 OSAL_Assert((handle == NULL)); 268 OSAL_Assert((handle == NULL_PTR));
246 269 SemaphoreP_Status ret = SemaphoreP_OK;
247 uintptr_t key; 270 uintptr_t key;
248 Sem_Struct *semS = (Sem_Struct *)handle; 271 Sem_Struct *semS = (Sem_Struct *)handle;
249 272 if(semS != NULL_PTR)
250 key = HwiP_disable();
251 if (semS->mode == SemaphoreP_Mode_BINARY)
252 { 273 {
274
275 key = HwiP_disable();
276 if (semS->mode == SemaphoreP_Mode_BINARY)
277 {
253 semS->count = 1; 278 semS->count = 1;
254 } 279 }
280 else
281 {
282 semS->count++;
283 }
284 HwiP_restore(key);
285 ret = SemaphoreP_OK;
286 }
255 else 287 else
256 { 288 {
257 semS->count++; 289 ret = SemaphoreP_FAILURE;
258 } 290 }
259 HwiP_restore(key);
260 291
261 return (SemaphoreP_OK); 292 return (ret);
262} 293}
263 294
264/* 295/*
@@ -267,10 +298,15 @@ SemaphoreP_Status SemaphoreP_post(SemaphoreP_Handle handle)
267int32_t SemaphoreP_getCount(SemaphoreP_Handle handle) 298int32_t SemaphoreP_getCount(SemaphoreP_Handle handle)
268 299
269{ 300{
270 OSAL_Assert((handle == NULL)); 301 int32_t ret=0;
302 OSAL_Assert((handle == NULL_PTR));
271 Sem_Struct *semS = (Sem_Struct *)handle; 303 Sem_Struct *semS = (Sem_Struct *)handle;
272 304 if(semS !=NULL_PTR) {
273 return (semS->count); 305 ret = (int32_t)semS->count;
306 } else {
307 ret = 0;
308 }
309 return (ret);
274} 310}
275 311
276/* Nothing past this point */ 312/* Nothing past this point */
diff --git a/src/nonos/SwiP_nonos.c b/src/nonos/SwiP_nonos.c
index 3a9b815..c9397f3 100644
--- a/src/nonos/SwiP_nonos.c
+++ b/src/nonos/SwiP_nonos.c
@@ -38,13 +38,13 @@
38#include <stdint.h> 38#include <stdint.h>
39#include <stdbool.h> 39#include <stdbool.h>
40#include <stdlib.h> 40#include <stdlib.h>
41 41#include <ti/osal/src/nonos/Nonos_config.h>
42/* 42/*
43 * ======== SwiP_create ======== 43 * ======== SwiP_create ========
44 */ 44 */
45SwiP_Handle SwiP_create(SwiP_Fxn swiFxn, SwiP_Params *params) 45SwiP_Handle SwiP_create(SwiP_Fxn swiFxn, const SwiP_Params *params)
46{ 46{
47 return (NULL); 47 return (NULL_PTR);
48} 48}
49 49
50/* 50/*
diff --git a/src/nonos/Utils_nonos.c b/src/nonos/Utils_nonos.c
index 6cb3a32..379b4f0 100644
--- a/src/nonos/Utils_nonos.c
+++ b/src/nonos/Utils_nonos.c
@@ -47,7 +47,7 @@
47#endif 47#endif
48 48
49#ifndef OSAL_DELAY_TIMER_ADDR_DEFAULT 49#ifndef OSAL_DELAY_TIMER_ADDR_DEFAULT
50#define OSAL_DELAY_TIMER_ADDR_DEFAULT ((uintptr_t)(NULL)) 50#define OSAL_DELAY_TIMER_ADDR_DEFAULT ((uintptr_t)(0U))
51#endif 51#endif
52 52
53#ifndef OSAL_TARGET_PROC_MASK_DEFAULT 53#ifndef OSAL_TARGET_PROC_MASK_DEFAULT
@@ -62,6 +62,7 @@ uint32_t gOsalHwiAllocCnt = 0U, gOsalHwiPeak = 0U;
62#define OSAL_CPU_FREQ_KHZ_DEFAULT (400000) 62#define OSAL_CPU_FREQ_KHZ_DEFAULT (400000)
63#endif 63#endif
64 64
65volatile bool Osal_DebugP_Assert_Val=(bool)true;
65 66
66/* Global Osal_HwAttr structure */ 67/* Global Osal_HwAttr structure */
67Osal_HwAttrs gOsal_HwAttrs = { 68Osal_HwAttrs gOsal_HwAttrs = {
@@ -87,24 +88,23 @@ Osal_HwAttrs gOsal_HwAttrs = {
87 (uintptr_t) OSAL_DELAY_TIMER_ADDR_DEFAULT, /* Timer Base address for osal delay implementation for AM3/AM4 parts */ 88 (uintptr_t) OSAL_DELAY_TIMER_ADDR_DEFAULT, /* Timer Base address for osal delay implementation for AM3/AM4 parts */
88 /* Default external Semaphore Memory Block */ 89 /* Default external Semaphore Memory Block */
89 { 90 {
90 (uintptr_t) NULL, 91 (uintptr_t) 0U,
91 0U 92 0U
92 }, 93 },
93 /* Default external HwiP Memory Block */ 94 /* Default external HwiP Memory Block */
94 { 95 {
95 (uintptr_t) NULL, 96 (uintptr_t) 0U,
96 0U 97 0U
97 } 98 }
98}; 99};
99 100
100/* 101/*
101 * ======== _DebugP_assert ======== 102 * ======== Osal_DebugP_assert ========
102 */ 103 */
103void _DebugP_assert(int32_t expression, const char *file, int32_t line); /*for misra warnings*/ 104void Osal_DebugP_assert(int32_t expression, const char *file, int32_t line)
104void _DebugP_assert(int32_t expression, const char *file, int32_t line)
105{ 105{
106 if (expression) { 106 if (expression != 0) {
107 while (1) {} 107 while (Osal_DebugP_Assert_Val == (bool)true) {}
108 } 108 }
109} 109}
110 110
@@ -120,26 +120,26 @@ Osal_ThreadType Osal_getThreadType(void)
120int32_t Osal_setHwAttrs(uint32_t ctrlBitMap, const Osal_HwAttrs *hwAttrs) 120int32_t Osal_setHwAttrs(uint32_t ctrlBitMap, const Osal_HwAttrs *hwAttrs)
121{ 121{
122 int32_t ret = osal_FAILURE; 122 int32_t ret = osal_FAILURE;
123 if (hwAttrs != NULL) { 123 if (hwAttrs != NULL_PTR) {
124 if (ctrlBitMap & OSAL_HWATTR_SET_EXT_CLK) { 124 if ((ctrlBitMap & OSAL_HWATTR_SET_EXT_CLK) !=0U) {
125 gOsal_HwAttrs.extClkKHz= hwAttrs->extClkKHz; 125 gOsal_HwAttrs.extClkKHz= hwAttrs->extClkKHz;
126 ret = osal_OK; 126 ret = osal_OK;
127 } 127 }
128#ifdef _TMS320C6X 128#ifdef _TMS320C6X
129 /* Set the Event Combiner Interrupts */ 129 /* Set the Event Combiner Interrupts */
130 if (ctrlBitMap & OSAL_HWATTR_SET_ECM_INT) { 130 if ((ctrlBitMap & OSAL_HWATTR_SET_ECM_INT) !=0U) {
131 memcpy(gOsal_HwAttrs.ECM_intNum,hwAttrs->ECM_intNum,4*sizeof(gOsal_HwAttrs.ECM_intNum[0])); 131 (void)memcpy(gOsal_HwAttrs.ECM_intNum,hwAttrs->ECM_intNum,4U*sizeof(gOsal_HwAttrs.ECM_intNum[0]));
132 ret = osal_OK; 132 ret = osal_OK;
133 } 133 }
134#endif 134#endif
135 /* Set the Hw Access type */ 135 /* Set the Hw Access type */
136 if (ctrlBitMap & OSAL_HWATTR_SET_HWACCESS_TYPE) { 136 if ((ctrlBitMap & OSAL_HWATTR_SET_HWACCESS_TYPE) != 0U) {
137 gOsal_HwAttrs.hwAccessType = hwAttrs->hwAccessType; 137 gOsal_HwAttrs.hwAccessType = hwAttrs->hwAccessType;
138 ret = osal_OK; 138 ret = osal_OK;
139 } 139 }
140 140
141 /* Set the Hw Access type */ 141 /* Set the Hw Access type */
142 if (ctrlBitMap & OSAL_HWATTR_SET_OSALDELAY_TIMER_BASE) { 142 if ((ctrlBitMap & OSAL_HWATTR_SET_OSALDELAY_TIMER_BASE) !=0U) {
143#if defined(SOC_AM437x)|| defined (SOC_AM335x) 143#if defined(SOC_AM437x)|| defined (SOC_AM335x)
144 gOsal_HwAttrs.osalDelayTimerBaseAddr = hwAttrs->osalDelayTimerBaseAddr; 144 gOsal_HwAttrs.osalDelayTimerBaseAddr = hwAttrs->osalDelayTimerBaseAddr;
145 ret = osal_OK; 145 ret = osal_OK;
@@ -149,24 +149,24 @@ int32_t Osal_setHwAttrs(uint32_t ctrlBitMap, const Osal_HwAttrs *hwAttrs)
149 } 149 }
150 150
151 /* Set the extended memmory block for semaphore operations */ 151 /* Set the extended memmory block for semaphore operations */
152 if (ctrlBitMap & OSAL_HWATTR_SET_SEMP_EXT_BASE) 152 if ((ctrlBitMap & OSAL_HWATTR_SET_SEMP_EXT_BASE) !=0U)
153 { 153 {
154 gOsal_HwAttrs.extSemaphorePBlock = hwAttrs->extSemaphorePBlock; 154 gOsal_HwAttrs.extSemaphorePBlock = hwAttrs->extSemaphorePBlock;
155