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authorSinthu Raja M2019-09-11 10:42:50 -0500
committerSinthu Raja M2019-09-13 01:55:45 -0500
commit6d8b57ed1b74242bcb0c3ce6fbc43e230cdd1f44 (patch)
tree46e86327ec4d420289da6dbad5b252de3c9c1948
parent94bd0b8f323f285c053e3618729485df3bc5e888 (diff)
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PRSDK-5851 Addressing review comments
Updated targetProcMask HwAttrs param specific to A15 core only
-rw-r--r--osal.h4
-rw-r--r--src/nonos/Utils_nonos.c2
-rw-r--r--src/tirtos/HwiP_tirtos.c9
-rwxr-xr-xsrc/tirtos/Utils_tirtos.c6
4 files changed, 16 insertions, 5 deletions
diff --git a/osal.h b/osal.h
index d46abc7..ddbdff3 100644
--- a/osal.h
+++ b/osal.h
@@ -224,8 +224,10 @@ typedef struct Osal_HwAttrs_s
224 int32_t cpuFreqKHz; 224 int32_t cpuFreqKHz;
225 /* External Clock value in KHz */ 225 /* External Clock value in KHz */
226 int32_t extClkKHz; 226 int32_t extClkKHz;
227#if defined(gnu_targets_arm_A15F)
227 /* Set Target processor list */ 228 /* Set Target processor list */
228 uint32_t targetProcMask; 229 uint32_t a15TargetProcMask;
230#endif
229#ifdef _TMS320C6X 231#ifdef _TMS320C6X
230 int32_t ECM_intNum[4]; /* Interrupt numbers for Event combiner groups (0-3)*/ 232 int32_t ECM_intNum[4]; /* Interrupt numbers for Event combiner groups (0-3)*/
231#endif 233#endif
diff --git a/src/nonos/Utils_nonos.c b/src/nonos/Utils_nonos.c
index 5a9c698..6cb3a32 100644
--- a/src/nonos/Utils_nonos.c
+++ b/src/nonos/Utils_nonos.c
@@ -67,7 +67,9 @@ uint32_t gOsalHwiAllocCnt = 0U, gOsalHwiPeak = 0U;
67Osal_HwAttrs gOsal_HwAttrs = { 67Osal_HwAttrs gOsal_HwAttrs = {
68 OSAL_CPU_FREQ_KHZ_DEFAULT, 68 OSAL_CPU_FREQ_KHZ_DEFAULT,
69 EXTERNAL_CLOCK_KHZ_DEFAULT, 69 EXTERNAL_CLOCK_KHZ_DEFAULT,
70#if defined(gnu_targets_arm_A15F)
70 OSAL_TARGET_PROC_MASK_DEFAULT, 71 OSAL_TARGET_PROC_MASK_DEFAULT,
72#endif
71#ifdef _TMS320C6X 73#ifdef _TMS320C6X
72 /* ECM_intNum[]: Event combiner interrupts */ 74 /* ECM_intNum[]: Event combiner interrupts */
73 { OSAL_ECM_GROUP0_INT, /* Interrupt[4-15] to use for Event Combiner Group 0 */ 75 { OSAL_ECM_GROUP0_INT, /* Interrupt[4-15] to use for Event Combiner Group 0 */
diff --git a/src/tirtos/HwiP_tirtos.c b/src/tirtos/HwiP_tirtos.c
index b259363..ca03e4b 100644
--- a/src/tirtos/HwiP_tirtos.c
+++ b/src/tirtos/HwiP_tirtos.c
@@ -217,16 +217,19 @@ HwiP_Handle HwiP_create(int32_t interruptNum, HwiP_Fxn hwiFxn,
217 hwiParams.triggerSensitivity = (UInt)params->triggerSensitivity; 217 hwiParams.triggerSensitivity = (UInt)params->triggerSensitivity;
218#endif 218#endif
219#if defined(gnu_targets_arm_A15F) 219#if defined(gnu_targets_arm_A15F)
220 /* Set the target interrupt to the running core */ 220 /*
221 * Set target processor list ID to handle interrupt in all available a15 cores
222 * of any given platform.
223 */
221 if(!BIOS_smpEnabled) 224 if(!BIOS_smpEnabled)
222 { 225 {
223 if(gOsal_HwAttrs.targetProcMask == OSAL_TARGET_PROC_MASK_DEFAULT) 226 if(gOsal_HwAttrs.a15TargetProcMask == OSAL_TARGET_PROC_MASK_DEFAULT)
224 { 227 {
225 hwiParams.targetProcList = 1 << Osal_getCoreId(); 228 hwiParams.targetProcList = 1 << Osal_getCoreId();
226 } 229 }
227 else 230 else
228 { 231 {
229 hwiParams.targetProcList = gOsal_HwAttrs.targetProcMask; 232 hwiParams.targetProcList = gOsal_HwAttrs.a15TargetProcMask;
230 } 233 }
231 234
232 } 235 }
diff --git a/src/tirtos/Utils_tirtos.c b/src/tirtos/Utils_tirtos.c
index 277ab42..641dfd8 100755
--- a/src/tirtos/Utils_tirtos.c
+++ b/src/tirtos/Utils_tirtos.c
@@ -67,7 +67,9 @@ uint32_t gOsalHwiAllocCnt = 0U, gOsalHwiPeak = 0U;
67Osal_HwAttrs gOsal_HwAttrs = { 67Osal_HwAttrs gOsal_HwAttrs = {
68 OSAL_CPU_FREQ_KHZ_DEFAULT, 68 OSAL_CPU_FREQ_KHZ_DEFAULT,
69 EXTERNAL_CLOCK_KHZ_DEFAULT, 69 EXTERNAL_CLOCK_KHZ_DEFAULT,
70#if defined(gnu_targets_arm_A15F)
70 OSAL_TARGET_PROC_MASK_DEFAULT, 71 OSAL_TARGET_PROC_MASK_DEFAULT,
72#endif
71#ifdef _TMS320C6X 73#ifdef _TMS320C6X
72 /* ECM_intNum[]: Event combiner interrupts */ 74 /* ECM_intNum[]: Event combiner interrupts */
73 { OSAL_ECM_GROUP0_INT, /* Interrupt[4-15] to use for Event Combiner Group 0 */ 75 { OSAL_ECM_GROUP0_INT, /* Interrupt[4-15] to use for Event Combiner Group 0 */
@@ -192,12 +194,14 @@ int32_t Osal_setHwAttrs(uint32_t ctrlBitMap, const Osal_HwAttrs *hwAttrs)
192 ret = osal_OK; 194 ret = osal_OK;
193 } 195 }
194 196
197#if defined(gnu_targets_arm_A15F)
195 /* Set the target processor list for routing the interrupt to specific core */ 198 /* Set the target processor list for routing the interrupt to specific core */
196 if (ctrlBitMap & OSAL_HWATTR_SET_TARG_PROC_LIST) 199 if (ctrlBitMap & OSAL_HWATTR_SET_TARG_PROC_LIST)
197 { 200 {
198 gOsal_HwAttrs.targetProcMask = hwAttrs->targetProcMask; 201 gOsal_HwAttrs.a15TargetProcMask = hwAttrs->a15TargetProcMask;
199 ret = osal_OK; 202 ret = osal_OK;
200 } 203 }
204#endif
201 ret = osal_OK; 205 ret = osal_OK;
202 } 206 }
203 return(ret); 207 return(ret);