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author | Sinthu Raja M | 2019-08-13 06:35:20 -0500 |
---|---|---|
committer | Mahesh Radhakrishnan | 2019-09-10 15:00:37 -0500 |
commit | 7df52b9330ee5dccf99544c520d824b8689e738d (patch) | |
tree | 8c50180d68b11b2d9acba8aecd1a63736632e415 | |
parent | 6a686648eeeb62a934604c2782061b06999f5891 (diff) | |
download | osal-7df52b9330ee5dccf99544c520d824b8689e738d.tar.gz osal-7df52b9330ee5dccf99544c520d824b8689e738d.tar.xz osal-7df52b9330ee5dccf99544c520d824b8689e738d.zip |
PRSDK-5851: Update OSAL_hwAttrs structure params
1. Add a params to Osal_HwAttrs structure.
2. Add common get_CoreId API to support all cores in future.
3. Update HwiP_create function to use the get_CoreId API to mask the
target processor interrupt for the running core.
-rw-r--r-- | arch/core/Core_utils.c | 52 | ||||
-rw-r--r-- | osal.h | 13 | ||||
-rw-r--r-- | src/nonos/Utils_nonos.c | 5 | ||||
-rw-r--r-- | src/src_common_tirtos.mk | 6 | ||||
-rw-r--r-- | src/tirtos/HwiP_tirtos.c | 9 | ||||
-rwxr-xr-x | src/tirtos/Utils_tirtos.c | 7 | ||||
-rw-r--r-- | src/tirtos/tirtos_config.h | 4 |
7 files changed, 89 insertions, 7 deletions
diff --git a/arch/core/Core_utils.c b/arch/core/Core_utils.c new file mode 100644 index 0000000..5464297 --- /dev/null +++ b/arch/core/Core_utils.c | |||
@@ -0,0 +1,52 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2019, Texas Instruments Incorporated | ||
3 | * All rights reserved. | ||
4 | * | ||
5 | * Redistribution and use in source and binary forms, with or without | ||
6 | * modification, are permitted provided that the following conditions | ||
7 | * are met: | ||
8 | * | ||
9 | * * Redistributions of source code must retain the above copyright | ||
10 | * notice, this list of conditions and the following disclaimer. | ||
11 | * | ||
12 | * * Redistributions in binary form must reproduce the above copyright | ||
13 | * notice, this list of conditions and the following disclaimer in the | ||
14 | * documentation and/or other materials provided with the distribution. | ||
15 | * | ||
16 | * * Neither the name of Texas Instruments Incorporated nor the names of | ||
17 | * its contributors may be used to endorse or promote products derived | ||
18 | * from this software without specific prior written permission. | ||
19 | * | ||
20 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | ||
21 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, | ||
22 | * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR | ||
23 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR | ||
24 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, | ||
25 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, | ||
26 | * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; | ||
27 | * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, | ||
28 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR | ||
29 | * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, | ||
30 | * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
31 | */ | ||
32 | /* | ||
33 | * ======== Core_utils.c ======== | ||
34 | */ | ||
35 | |||
36 | #include <stdint.h> | ||
37 | #include <stdbool.h> | ||
38 | #include <stdlib.h> | ||
39 | #include <string.h> | ||
40 | |||
41 | #if defined(gnu_targets_arm_A15F) | ||
42 | #include <ti/csl/arch/a15/V0/csl_a15.h> | ||
43 | #endif | ||
44 | |||
45 | int32_t Osal_getCoreId() | ||
46 | { | ||
47 | #if defined(gnu_targets_arm_A15F) | ||
48 | return ((int32_t)CSL_a15ReadCoreId()); | ||
49 | #else | ||
50 | return 0; | ||
51 | #endif | ||
52 | } | ||
@@ -224,6 +224,8 @@ typedef struct Osal_HwAttrs_s | |||
224 | int32_t cpuFreqKHz; | 224 | int32_t cpuFreqKHz; |
225 | /* External Clock value in KHz */ | 225 | /* External Clock value in KHz */ |
226 | int32_t extClkKHz; | 226 | int32_t extClkKHz; |
227 | /* Set Target processor list */ | ||
228 | uint32_t targetProcMask; | ||
227 | #ifdef _TMS320C6X | 229 | #ifdef _TMS320C6X |
228 | int32_t ECM_intNum[4]; /* Interrupt numbers for Event combiner groups (0-3)*/ | 230 | int32_t ECM_intNum[4]; /* Interrupt numbers for Event combiner groups (0-3)*/ |
229 | #endif | 231 | #endif |
@@ -274,6 +276,11 @@ typedef struct Osal_HwAttrs_s | |||
274 | */ | 276 | */ |
275 | #define OSAL_HWATTR_SET_CPU_FREQ (0x00000040) | 277 | #define OSAL_HWATTR_SET_CPU_FREQ (0x00000040) |
276 | 278 | ||
279 | /*! | ||
280 | * bit map to set the target processor list to direct interrupts to specific core | ||
281 | */ | ||
282 | #define OSAL_HWATTR_SET_TARG_PROC_LIST (0x00000080) | ||
283 | |||
277 | 284 | ||
278 | /*! | 285 | /*! |
279 | * @brief Function to set the Hw Attributes | 286 | * @brief Function to set the Hw Attributes |
@@ -312,6 +319,12 @@ extern int32_t Osal_getHwAttrs(Osal_HwAttrs *hwAttrs); | |||
312 | */ | 319 | */ |
313 | extern int32_t Osal_getStaticMemStatus(Osal_StaticMemStatus *pMemStat); | 320 | extern int32_t Osal_getStaticMemStatus(Osal_StaticMemStatus *pMemStat); |
314 | 321 | ||
322 | /*! | ||
323 | * @brief Function to get the core ID of the running Core. | ||
324 | * | ||
325 | * @return core ID of the running core | ||
326 | */ | ||
327 | extern int32_t Osal_getCoreId(void); | ||
315 | 328 | ||
316 | /*! | 329 | /*! |
317 | * @brief external references for Osal Hw Attribute structure | 330 | * @brief external references for Osal Hw Attribute structure |
diff --git a/src/nonos/Utils_nonos.c b/src/nonos/Utils_nonos.c index cf83bc1..5a9c698 100644 --- a/src/nonos/Utils_nonos.c +++ b/src/nonos/Utils_nonos.c | |||
@@ -50,6 +50,10 @@ | |||
50 | #define OSAL_DELAY_TIMER_ADDR_DEFAULT ((uintptr_t)(NULL)) | 50 | #define OSAL_DELAY_TIMER_ADDR_DEFAULT ((uintptr_t)(NULL)) |
51 | #endif | 51 | #endif |
52 | 52 | ||
53 | #ifndef OSAL_TARGET_PROC_MASK_DEFAULT | ||
54 | #define OSAL_TARGET_PROC_MASK_DEFAULT (0xFFFFU) | ||
55 | #endif | ||
56 | |||
53 | /* Global Osal static memory status variables */ | 57 | /* Global Osal static memory status variables */ |
54 | uint32_t gOsalSemAllocCnt = 0U, gOsalSemPeak = 0U; | 58 | uint32_t gOsalSemAllocCnt = 0U, gOsalSemPeak = 0U; |
55 | uint32_t gOsalTimerAllocCnt = 0U, gOsalTimerPeak = 0U; | 59 | uint32_t gOsalTimerAllocCnt = 0U, gOsalTimerPeak = 0U; |
@@ -63,6 +67,7 @@ uint32_t gOsalHwiAllocCnt = 0U, gOsalHwiPeak = 0U; | |||
63 | Osal_HwAttrs gOsal_HwAttrs = { | 67 | Osal_HwAttrs gOsal_HwAttrs = { |
64 | OSAL_CPU_FREQ_KHZ_DEFAULT, | 68 | OSAL_CPU_FREQ_KHZ_DEFAULT, |
65 | EXTERNAL_CLOCK_KHZ_DEFAULT, | 69 | EXTERNAL_CLOCK_KHZ_DEFAULT, |
70 | OSAL_TARGET_PROC_MASK_DEFAULT, | ||
66 | #ifdef _TMS320C6X | 71 | #ifdef _TMS320C6X |
67 | /* ECM_intNum[]: Event combiner interrupts */ | 72 | /* ECM_intNum[]: Event combiner interrupts */ |
68 | { OSAL_ECM_GROUP0_INT, /* Interrupt[4-15] to use for Event Combiner Group 0 */ | 73 | { OSAL_ECM_GROUP0_INT, /* Interrupt[4-15] to use for Event Combiner Group 0 */ |
diff --git a/src/src_common_tirtos.mk b/src/src_common_tirtos.mk index 81f188a..b2abf88 100644 --- a/src/src_common_tirtos.mk +++ b/src/src_common_tirtos.mk | |||
@@ -1,8 +1,8 @@ | |||
1 | 1 | ||
2 | SRCDIR = . src/tirtos | 2 | SRCDIR = . src/tirtos arch/core |
3 | INCDIR = . src/tirtos | 3 | INCDIR = . src/tirtos |
4 | 4 | ||
5 | SRCS_COMMON += SemaphoreP_tirtos.c HwiP_tirtos.c SwiP_tirtos.c Utils_tirtos.c CacheP_tirtos.c RegisterIntr_tirtos.c EventCombinerP_tirtos.c Queue_tirtos.c EventP_tirtos.c TaskP_tirtos.c | 5 | SRCS_COMMON += Core_utils.c SemaphoreP_tirtos.c HwiP_tirtos.c SwiP_tirtos.c Utils_tirtos.c CacheP_tirtos.c RegisterIntr_tirtos.c EventCombinerP_tirtos.c Queue_tirtos.c EventP_tirtos.c TaskP_tirtos.c |
6 | 6 | ||
7 | ifeq ($(SOC),$(filter $(SOC), am574x am572x am571x k2g k2l k2e k2h k2k c6678 c6657 am437x am335x omapl137 omapl138 c6747 am65xx j721e)) | 7 | ifeq ($(SOC),$(filter $(SOC), am574x am572x am571x k2g k2l k2e k2h k2k c6678 c6657 am437x am335x omapl137 omapl138 c6747 am65xx j721e)) |
8 | SRCS_COMMON += TimerP_tirtos.c | 8 | SRCS_COMMON += TimerP_tirtos.c |
@@ -14,7 +14,7 @@ ifeq ($(ISA),$(filter $(ISA), a53 a72 c7x)) | |||
14 | endif | 14 | endif |
15 | 15 | ||
16 | PACKAGE_SRCS_COMMON = makefile HwiP.h SwiP.h MuxIntcP.h osal.h osal_component.mk SemaphoreP.h \ | 16 | PACKAGE_SRCS_COMMON = makefile HwiP.h SwiP.h MuxIntcP.h osal.h osal_component.mk SemaphoreP.h \ |
17 | src/tirtos src/src_common_nonos.mk src/src_common_tirtos.mk \ | 17 | arch/core src/tirtos src/src_common_nonos.mk src/src_common_tirtos.mk \ |
18 | docs/OSAL_SoftwareManifest.html docs/ReleaseNotes_OSAL.pdf \ | 18 | docs/OSAL_SoftwareManifest.html docs/ReleaseNotes_OSAL.pdf \ |
19 | build/makefile_nonos_indp.mk build/makefile_nonos.mk build/makefile_tirtos_indp.mk build/makefile_tirtos.mk | 19 | build/makefile_nonos_indp.mk build/makefile_nonos.mk build/makefile_tirtos_indp.mk build/makefile_tirtos.mk |
20 | 20 | ||
diff --git a/src/tirtos/HwiP_tirtos.c b/src/tirtos/HwiP_tirtos.c index eb45902..56400ab 100644 --- a/src/tirtos/HwiP_tirtos.c +++ b/src/tirtos/HwiP_tirtos.c | |||
@@ -42,13 +42,11 @@ | |||
42 | #include <xdc/std.h> | 42 | #include <xdc/std.h> |
43 | #include <xdc/runtime/Error.h> | 43 | #include <xdc/runtime/Error.h> |
44 | #include <xdc/runtime/Memory.h> | 44 | #include <xdc/runtime/Memory.h> |
45 | #include <ti/sysbios/BIOS.h> | ||
45 | #if defined(__ARM_ARCH_7A__) | 46 | #if defined(__ARM_ARCH_7A__) |
46 | 47 | ||
47 | #if defined(gnu_targets_arm_A15F) || defined(gnu_targets_arm_A9F) | 48 | #if defined(gnu_targets_arm_A15F) || defined(gnu_targets_arm_A9F) |
48 | #include <ti/sysbios/family/arm/gic/Hwi.h> | 49 | #include <ti/sysbios/family/arm/gic/Hwi.h> |
49 | #if defined(gnu_targets_arm_A15F) | ||
50 | #include <ti/csl/arch/a15/V0/csl_a15.h> | ||
51 | #endif | ||
52 | #elif defined(ti_targets_arm_elf_A8F) || \ | 50 | #elif defined(ti_targets_arm_elf_A8F) || \ |
53 | defined(ti_targets_arm_elf_A8Fnv) || \ | 51 | defined(ti_targets_arm_elf_A8Fnv) || \ |
54 | defined(gnu_targets_arm_A8F) | 52 | defined(gnu_targets_arm_A8F) |
@@ -220,7 +218,10 @@ HwiP_Handle HwiP_create(int32_t interruptNum, HwiP_Fxn hwiFxn, | |||
220 | #endif | 218 | #endif |
221 | #if defined(gnu_targets_arm_A15F) | 219 | #if defined(gnu_targets_arm_A15F) |
222 | /* Set the target interrupt to the running core */ | 220 | /* Set the target interrupt to the running core */ |
223 | hwiParams.targetProcList = 1 << CSL_a15ReadCoreId(); | 221 | if(gOsal_HwAttrs.targetProcMask == OSAL_TARGET_PROC_MASK_DEFAULT) |
222 | { | ||
223 | hwiParams.targetProcList = 1 << Osal_getCoreId(); | ||
224 | } | ||
224 | #endif | 225 | #endif |
225 | #endif | 226 | #endif |
226 | #if defined (__TI_ARM_V7R4__) | 227 | #if defined (__TI_ARM_V7R4__) |
diff --git a/src/tirtos/Utils_tirtos.c b/src/tirtos/Utils_tirtos.c index 847d55f..277ab42 100755 --- a/src/tirtos/Utils_tirtos.c +++ b/src/tirtos/Utils_tirtos.c | |||
@@ -67,6 +67,7 @@ uint32_t gOsalHwiAllocCnt = 0U, gOsalHwiPeak = 0U; | |||
67 | Osal_HwAttrs gOsal_HwAttrs = { | 67 | Osal_HwAttrs gOsal_HwAttrs = { |
68 | OSAL_CPU_FREQ_KHZ_DEFAULT, | 68 | OSAL_CPU_FREQ_KHZ_DEFAULT, |
69 | EXTERNAL_CLOCK_KHZ_DEFAULT, | 69 | EXTERNAL_CLOCK_KHZ_DEFAULT, |
70 | OSAL_TARGET_PROC_MASK_DEFAULT, | ||
70 | #ifdef _TMS320C6X | 71 | #ifdef _TMS320C6X |
71 | /* ECM_intNum[]: Event combiner interrupts */ | 72 | /* ECM_intNum[]: Event combiner interrupts */ |
72 | { OSAL_ECM_GROUP0_INT, /* Interrupt[4-15] to use for Event Combiner Group 0 */ | 73 | { OSAL_ECM_GROUP0_INT, /* Interrupt[4-15] to use for Event Combiner Group 0 */ |
@@ -191,6 +192,12 @@ int32_t Osal_setHwAttrs(uint32_t ctrlBitMap, const Osal_HwAttrs *hwAttrs) | |||
191 | ret = osal_OK; | 192 | ret = osal_OK; |
192 | } | 193 | } |
193 | 194 | ||
195 | /* Set the target processor list for routing the interrupt to specific core */ | ||
196 | if (ctrlBitMap & OSAL_HWATTR_SET_TARG_PROC_LIST) | ||
197 | { | ||
198 | gOsal_HwAttrs.targetProcMask = hwAttrs->targetProcMask; | ||
199 | ret = osal_OK; | ||
200 | } | ||
194 | ret = osal_OK; | 201 | ret = osal_OK; |
195 | } | 202 | } |
196 | return(ret); | 203 | return(ret); |
diff --git a/src/tirtos/tirtos_config.h b/src/tirtos/tirtos_config.h index 2c3fb85..63271bd 100644 --- a/src/tirtos/tirtos_config.h +++ b/src/tirtos/tirtos_config.h | |||
@@ -69,6 +69,10 @@ extern "C" { | |||
69 | #endif | 69 | #endif |
70 | #endif /* __ARM_ARCH_7A__ */ | 70 | #endif /* __ARM_ARCH_7A__ */ |
71 | 71 | ||
72 | #ifndef OSAL_TARGET_PROC_MASK_DEFAULT | ||
73 | #define OSAL_TARGET_PROC_MASK_DEFAULT (0xFFFFU) | ||
74 | #endif | ||
75 | |||
72 | extern Osal_HwAttrs gOsal_HwAttrs; | 76 | extern Osal_HwAttrs gOsal_HwAttrs; |
73 | 77 | ||
74 | #ifdef __cplusplus | 78 | #ifdef __cplusplus |