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authorMing Wei2019-06-27 10:55:41 -0500
committerSivaraj R2019-07-07 19:55:14 -0500
commit7c6d30b4dc2da3307b69394285313a40c6857704 (patch)
treea81a1abfe44497a6979774ac0d212f6ad5dd9026
parent276c330ca6df2750371bd274b77911274fc67d38 (diff)
downloadosal-7c6d30b4dc2da3307b69394285313a40c6857704.tar.gz
osal-7c6d30b4dc2da3307b69394285313a40c6857704.tar.xz
osal-7c6d30b4dc2da3307b69394285313a40c6857704.zip
Update the default settings for DMTimers
Signed-off-by: Ming Wei <mwei@ti.com>
-rw-r--r--soc/j721e/TimerP_default.c118
-rw-r--r--src/nonos/Nonos_config.h2
-rw-r--r--src/tirtos/RegisterIntr_tirtos.c2
-rwxr-xr-xtest/src/main_osal_test.c34
-rwxr-xr-xtest/sysbios_unit_test/makefile2
5 files changed, 91 insertions, 67 deletions
diff --git a/soc/j721e/TimerP_default.c b/soc/j721e/TimerP_default.c
index 4d0eb04..5fc1309 100644
--- a/soc/j721e/TimerP_default.c
+++ b/soc/j721e/TimerP_default.c
@@ -69,8 +69,8 @@ TimerP_dmTimerDefault gDmTimerPInfoTbl[TimerP_numTimerDevices] = {
69#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2) 69#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
70 /* Default configurations for DSP core */ 70 /* Default configurations for DSP core */
71 CSL_TIMER0_CFG_BASE, /* Main domain's DM Timer base address */ 71 CSL_TIMER0_CFG_BASE, /* Main domain's DM Timer base address */
72 0U, /* TBD */ 72 TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
73 0U /* TBD */ 73 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
74#endif 74#endif
75 }, 75 },
76 /* Timer ID 1 */ 76 /* Timer ID 1 */
@@ -87,9 +87,9 @@ TimerP_dmTimerDefault gDmTimerPInfoTbl[TimerP_numTimerDevices] = {
87 TIMERP_EVENT_NOT_AVAILABLE 87 TIMERP_EVENT_NOT_AVAILABLE
88#endif 88#endif
89#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2) 89#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
90 CSL_TIMER0_CFG_BASE, 90 CSL_TIMER1_CFG_BASE,
91 0U, /* TBD */ 91 TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
92 0U /* TBD */ 92 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
93#endif 93#endif
94 }, 94 },
95 /* Timer ID 2 */ 95 /* Timer ID 2 */
@@ -106,9 +106,9 @@ TimerP_dmTimerDefault gDmTimerPInfoTbl[TimerP_numTimerDevices] = {
106 TIMERP_EVENT_NOT_AVAILABLE 106 TIMERP_EVENT_NOT_AVAILABLE
107#endif 107#endif
108#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2) 108#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
109 CSL_TIMER0_CFG_BASE, 109 CSL_TIMER2_CFG_BASE,
110 0U, /* TBD */ 110 TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
111 0U /* TBD */ 111 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
112#endif 112#endif
113 }, 113 },
114 /* Timer ID 3 */ 114 /* Timer ID 3 */
@@ -125,9 +125,9 @@ TimerP_dmTimerDefault gDmTimerPInfoTbl[TimerP_numTimerDevices] = {
125 TIMERP_EVENT_NOT_AVAILABLE 125 TIMERP_EVENT_NOT_AVAILABLE
126#endif 126#endif
127#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2) 127#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
128 CSL_TIMER0_CFG_BASE, 128 CSL_TIMER3_CFG_BASE,
129 0U, /* TBD */ 129 TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
130 0U /* TBD */ 130 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
131#endif 131#endif
132 }, 132 },
133 /* Timer ID 4 */ 133 /* Timer ID 4 */
@@ -144,9 +144,9 @@ TimerP_dmTimerDefault gDmTimerPInfoTbl[TimerP_numTimerDevices] = {
144 TIMERP_EVENT_NOT_AVAILABLE 144 TIMERP_EVENT_NOT_AVAILABLE
145#endif 145#endif
146#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2) 146#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
147 CSL_TIMER0_CFG_BASE, 147 CSL_TIMER4_CFG_BASE,
148 0U, /* TBD */ 148 TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
149 0U /* TBD */ 149 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
150#endif 150#endif
151 }, 151 },
152 /* Timer ID 5 */ 152 /* Timer ID 5 */
@@ -163,9 +163,9 @@ TimerP_dmTimerDefault gDmTimerPInfoTbl[TimerP_numTimerDevices] = {
163 TIMERP_EVENT_NOT_AVAILABLE 163 TIMERP_EVENT_NOT_AVAILABLE
164#endif 164#endif
165#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2) 165#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
166 CSL_TIMER0_CFG_BASE, 166 CSL_TIMER5_CFG_BASE,
167 0U, /* TBD */ 167 TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
168 0U /* TBD */ 168 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
169#endif 169#endif
170 }, 170 },
171 /* Timer ID 6 */ 171 /* Timer ID 6 */
@@ -182,9 +182,9 @@ TimerP_dmTimerDefault gDmTimerPInfoTbl[TimerP_numTimerDevices] = {
182 TIMERP_EVENT_NOT_AVAILABLE 182 TIMERP_EVENT_NOT_AVAILABLE
183#endif 183#endif
184#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2) 184#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
185 CSL_TIMER0_CFG_BASE, 185 CSL_TIMER6_CFG_BASE,
186 0U, /* TBD */ 186 TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
187 0U /* TBD */ 187 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
188#endif 188#endif
189 }, 189 },
190 /* Timer ID 7 */ 190 /* Timer ID 7 */
@@ -201,9 +201,9 @@ TimerP_dmTimerDefault gDmTimerPInfoTbl[TimerP_numTimerDevices] = {
201 TIMERP_EVENT_NOT_AVAILABLE 201 TIMERP_EVENT_NOT_AVAILABLE
202#endif 202#endif
203#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2) 203#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
204 CSL_TIMER0_CFG_BASE, 204 CSL_TIMER7_CFG_BASE,
205 0U, /* TBD */ 205 TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
206 0U /* TBD */ 206 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
207#endif 207#endif
208 }, 208 },
209 /* Timer ID 8 */ 209 /* Timer ID 8 */
@@ -220,9 +220,9 @@ TimerP_dmTimerDefault gDmTimerPInfoTbl[TimerP_numTimerDevices] = {
220 TIMERP_EVENT_NOT_AVAILABLE 220 TIMERP_EVENT_NOT_AVAILABLE
221#endif 221#endif
222#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2) 222#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
223 CSL_TIMER0_CFG_BASE, 223 CSL_TIMER8_CFG_BASE,
224 0U, /* TBD */ 224 TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
225 0U /* TBD */ 225 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
226#endif 226#endif
227 }, 227 },
228 /* Timer ID 9 */ 228 /* Timer ID 9 */
@@ -239,9 +239,9 @@ TimerP_dmTimerDefault gDmTimerPInfoTbl[TimerP_numTimerDevices] = {
239 TIMERP_EVENT_NOT_AVAILABLE 239 TIMERP_EVENT_NOT_AVAILABLE
240#endif 240#endif
241#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2) 241#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
242 CSL_TIMER0_CFG_BASE, 242 CSL_TIMER9_CFG_BASE,
243 0U, /* TBD */ 243 TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
244 0U /* TBD */ 244 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
245#endif 245#endif
246 }, 246 },
247 /* Timer ID 10 */ 247 /* Timer ID 10 */
@@ -258,9 +258,9 @@ TimerP_dmTimerDefault gDmTimerPInfoTbl[TimerP_numTimerDevices] = {
258 TIMERP_EVENT_NOT_AVAILABLE 258 TIMERP_EVENT_NOT_AVAILABLE
259#endif 259#endif
260#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2) 260#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
261 CSL_TIMER0_CFG_BASE, 261 CSL_TIMER10_CFG_BASE,
262 0U, /* TBD */ 262 TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
263 0U /* TBD */ 263 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
264#endif 264#endif
265 }, 265 },
266 /* Timer ID 11 */ 266 /* Timer ID 11 */
@@ -277,9 +277,9 @@ TimerP_dmTimerDefault gDmTimerPInfoTbl[TimerP_numTimerDevices] = {
277 TIMERP_EVENT_NOT_AVAILABLE 277 TIMERP_EVENT_NOT_AVAILABLE
278#endif 278#endif
279#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2) 279#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
280 CSL_TIMER0_CFG_BASE, 280 CSL_TIMER11_CFG_BASE,
281 0U, /* TBD */ 281 TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
282 0U /* TBD */ 282 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
283#endif 283#endif
284 }, 284 },
285 /* Timer ID 12 */ 285 /* Timer ID 12 */
@@ -296,9 +296,9 @@ TimerP_dmTimerDefault gDmTimerPInfoTbl[TimerP_numTimerDevices] = {
296 TIMERP_EVENT_NOT_AVAILABLE 296 TIMERP_EVENT_NOT_AVAILABLE
297#endif 297#endif
298#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2) 298#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
299 CSL_TIMER0_CFG_BASE, 299 CSL_TIMER12_CFG_BASE,
300 0U, /* TBD */ 300 TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
301 0U /* TBD */ 301 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
302#endif 302#endif
303 }, 303 },
304 /* Timer ID 13 */ 304 /* Timer ID 13 */
@@ -315,9 +315,9 @@ TimerP_dmTimerDefault gDmTimerPInfoTbl[TimerP_numTimerDevices] = {
315 TIMERP_EVENT_NOT_AVAILABLE 315 TIMERP_EVENT_NOT_AVAILABLE
316#endif 316#endif
317#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2) 317#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
318 CSL_TIMER0_CFG_BASE, 318 CSL_TIMER13_CFG_BASE,
319 0U, /* TBD */ 319 TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
320 0U /* TBD */ 320 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
321#endif 321#endif
322 }, 322 },
323 /* Timer ID 14 */ 323 /* Timer ID 14 */
@@ -334,9 +334,9 @@ TimerP_dmTimerDefault gDmTimerPInfoTbl[TimerP_numTimerDevices] = {
334 TIMERP_EVENT_NOT_AVAILABLE 334 TIMERP_EVENT_NOT_AVAILABLE
335#endif 335#endif
336#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2) 336#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
337 CSL_TIMER0_CFG_BASE, 337 CSL_TIMER14_CFG_BASE,
338 0U, /* TBD */ 338 TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
339 0U /* TBD */ 339 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
340#endif 340#endif
341 }, 341 },
342 /* Timer ID 15 */ 342 /* Timer ID 15 */
@@ -353,9 +353,9 @@ TimerP_dmTimerDefault gDmTimerPInfoTbl[TimerP_numTimerDevices] = {
353 TIMERP_EVENT_NOT_AVAILABLE 353 TIMERP_EVENT_NOT_AVAILABLE
354#endif 354#endif
355#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2) 355#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
356 CSL_TIMER0_CFG_BASE, 356 CSL_TIMER15_CFG_BASE,
357 0U, /* TBD */ 357 TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
358 0U /* TBD */ 358 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
359#endif 359#endif
360 }, 360 },
361 /* Timer ID 16 */ 361 /* Timer ID 16 */
@@ -372,9 +372,9 @@ TimerP_dmTimerDefault gDmTimerPInfoTbl[TimerP_numTimerDevices] = {
372 TIMERP_EVENT_NOT_AVAILABLE 372 TIMERP_EVENT_NOT_AVAILABLE
373#endif 373#endif
374#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2) 374#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
375 CSL_TIMER0_CFG_BASE, 375 CSL_TIMER16_CFG_BASE,
376 0U, /* TBD */ 376 TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
377 0U /* TBD */ 377 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
378#endif 378#endif
379 }, 379 },
380 /* Timer ID 17 */ 380 /* Timer ID 17 */
@@ -391,9 +391,9 @@ TimerP_dmTimerDefault gDmTimerPInfoTbl[TimerP_numTimerDevices] = {
391 TIMERP_EVENT_NOT_AVAILABLE 391 TIMERP_EVENT_NOT_AVAILABLE
392#endif 392#endif
393#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2) 393#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
394 CSL_TIMER0_CFG_BASE, 394 CSL_TIMER17_CFG_BASE,
395 0U, /* TBD */ 395 TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
396 0U /* TBD */ 396 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
397#endif 397#endif
398 }, 398 },
399 /* Timer ID 18 */ 399 /* Timer ID 18 */
@@ -410,9 +410,9 @@ TimerP_dmTimerDefault gDmTimerPInfoTbl[TimerP_numTimerDevices] = {
410 TIMERP_EVENT_NOT_AVAILABLE 410 TIMERP_EVENT_NOT_AVAILABLE
411#endif 411#endif
412#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2) 412#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
413 CSL_TIMER0_CFG_BASE, 413 CSL_TIMER18_CFG_BASE,
414 0U, /* TBD */ 414 TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
415 0U /* TBD */ 415 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
416#endif 416#endif
417 }, 417 },
418 /* Timer ID 19 */ 418 /* Timer ID 19 */
@@ -429,9 +429,9 @@ TimerP_dmTimerDefault gDmTimerPInfoTbl[TimerP_numTimerDevices] = {
429 TIMERP_EVENT_NOT_AVAILABLE 429 TIMERP_EVENT_NOT_AVAILABLE
430#endif 430#endif
431#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2) 431#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
432 CSL_TIMER0_CFG_BASE, 432 CSL_TIMER19_CFG_BASE,
433 0U, /* TBD */ 433 TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
434 0U /* TBD */ 434 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
435#endif 435#endif
436 } 436 }
437}; 437};
diff --git a/src/nonos/Nonos_config.h b/src/nonos/Nonos_config.h
index afb72e2..cb73869 100644
--- a/src/nonos/Nonos_config.h
+++ b/src/nonos/Nonos_config.h
@@ -113,6 +113,8 @@ typedef struct hwi_struct {
113#endif 113#endif
114 114
115#define TIMERP_EVENT_NOT_AVAILABLE (-(int32_t) (1u)) 115#define TIMERP_EVENT_NOT_AVAILABLE (-(int32_t) (1u))
116#define TIMERP_INTR_USER_CONFIGURE (-(int32_t) (2u))
117#define TIMERP_EVENT_USER_CONFIGURE (-(int32_t) (3u))
116 118
117/* 119/*
118 * @brief TimerP Information structure 120 * @brief TimerP Information structure
diff --git a/src/tirtos/RegisterIntr_tirtos.c b/src/tirtos/RegisterIntr_tirtos.c
index 8265bca..5d1da5f 100644
--- a/src/tirtos/RegisterIntr_tirtos.c
+++ b/src/tirtos/RegisterIntr_tirtos.c
@@ -87,7 +87,7 @@ void Osal_RegisterInterrupt_initParams(OsalRegisterIntrParams_t *interruptRegPar
87#ifdef __TI_ARM_V7R4__ 87#ifdef __TI_ARM_V7R4__
88 interruptRegParams->corepacConfig.priority=0x15U; /* Default */ 88 interruptRegParams->corepacConfig.priority=0x15U; /* Default */
89#else 89#else
90#ifdef __C7100__ 90#if defined(__C7100__) || defined(BUILD_DSP_1) || defined(BUILD_DSP_2)
91 interruptRegParams->corepacConfig.priority=0x01U; /* Default */ 91 interruptRegParams->corepacConfig.priority=0x01U; /* Default */
92#else 92#else
93 interruptRegParams->corepacConfig.priority=0x20U; /* Default */ 93 interruptRegParams->corepacConfig.priority=0x20U; /* Default */
diff --git a/test/src/main_osal_test.c b/test/src/main_osal_test.c
index 8143277..47c7ceb 100755
--- a/test/src/main_osal_test.c
+++ b/test/src/main_osal_test.c
@@ -308,8 +308,8 @@ UT_Timer_Type_t timer_type = UT_Timer_TIMER64;
308 #define OSAL_TEST_TIMER_ID2 (3U) 308 #define OSAL_TEST_TIMER_ID2 (3U)
309 #define OSAL_TEST_TIMER_PERIOD (5000U) 309 #define OSAL_TEST_TIMER_PERIOD (5000U)
310 #elif defined (BUILD_C66X_2) 310 #elif defined (BUILD_C66X_2)
311 #define OSAL_TEST_TIMER_ID (1U) 311 #define OSAL_TEST_TIMER_ID (2U)
312 #define OSAL_TEST_TIMER_ID2 (2U) 312 #define OSAL_TEST_TIMER_ID2 (3U)
313 #define OSAL_TEST_TIMER_PERIOD (5000U) 313 #define OSAL_TEST_TIMER_PERIOD (5000U)
314 #elif defined (BUILD_C7X_1) 314 #elif defined (BUILD_C7X_1)
315 #define OSAL_TEST_TIMER_ID (1U) 315 #define OSAL_TEST_TIMER_ID (1U)
@@ -437,7 +437,6 @@ bool OSAL_timer_test()
437#if defined(BUILD_C66X_1) || defined(BUILD_C66X_2) || defined(BUILD_C7X_1) 437#if defined(BUILD_C66X_1) || defined(BUILD_C66X_2) || defined(BUILD_C7X_1)
438 id = OSAL_TEST_TIMER_ID; 438 id = OSAL_TEST_TIMER_ID;
439#endif 439#endif
440
441 volatile int32_t i; 440 volatile int32_t i;
442 uint32_t prevCount, ctrlBitmap = OSAL_HWATTR_SET_OSALDELAY_TIMER_BASE ; 441 uint32_t prevCount, ctrlBitmap = OSAL_HWATTR_SET_OSALDELAY_TIMER_BASE ;
443 bool ret = true; 442 bool ret = true;
@@ -488,18 +487,26 @@ bool OSAL_timer_test()
488 timerParams.periodType = TimerP_PeriodType_MICROSECS; 487 timerParams.periodType = TimerP_PeriodType_MICROSECS;
489 timerParams.period = OSAL_TEST_TIMER_PERIOD; 488 timerParams.period = OSAL_TEST_TIMER_PERIOD;
490 489
490#if defined(SOC_J721E)
491#if defined(BUILD_C66X_1) 491#if defined(BUILD_C66X_1)
492 /* the Eevnt 21 is used for DMTimer0 by SYS/BIOS by default, so we need to use a different one here for DMTimer2 */
493 timerParams.eventId = 22;
494 /* the Interrupt 14 is used for DMTimer0 by SYS/BIOS by default, so we need to use a different one here for DMTimer2 */
492 timerParams.intNum = 15; 495 timerParams.intNum = 15;
493 OSAL_log("\n set intNum=%d, id=%d, \n", timerParams.intNum, id); 496 OSAL_log("\n set intNum=%d, id=%d, \n", timerParams.intNum, id);
494#endif 497#endif
495#if defined(BUILD_C66X_2) 498#if defined(BUILD_C66X_2)
496 timerParams.intNum = 12; 499 /* the Eevnt 20 is used for DMTimer0 by SYS/BIOS by default, so we need to use a different one here for DMTimer2 */
500 timerParams.eventId = 22;
501 /* the Interrupt 14 is used for DMTimer0 by SYS/BIOS by default, so we need to use a different one here for DMTimer2 */
502 timerParams.intNum = 15;
497#endif 503#endif
498 504
499#if defined(BUILD_C7X_1) 505#if defined(BUILD_C7X_1)
500 timerParams.intNum = 15; 506 timerParams.intNum = 15;
501 OSAL_log("\n set intNum=%d, id=%d, \n", timerParams.intNum, id); 507 OSAL_log("\n set intNum=%d, id=%d, \n", timerParams.intNum, id);
502#endif 508#endif
509#endif
503 510
504#if !defined(SOC_J721E) 511#if !defined(SOC_J721E)
505#if defined(_TMS320C6X) 512#if defined(_TMS320C6X)
@@ -1281,14 +1288,29 @@ void C66xTimerInterruptInit(void)
1281 * intr_router[12] corresponds to output event #21, which is what we 1288 * intr_router[12] corresponds to output event #21, which is what we
1282 * set eventId to in .cfg file. 1289 * set eventId to in .cfg file.
1283 * - bit 16 enables the entry 1290 * - bit 16 enables the entry
1284 * - lower bits define input event (#0 for dmtimer #0) 1291 * - lower bits define input event (#1 for dmtimer #0)
1292 * intr_router[13] corresponds to output event #22, which is what we
1293 * set eventId to in this file.
1294 * - bit 16 enables the entry
1295 * - lower bits define input event (#3 for dmtimer #2)
1285 */ 1296 */
1286#ifdef BUILD_C66X_1 1297#ifdef BUILD_C66X_1
1287 intr_router[12] = 0x00010001; 1298 intr_router[12] = 0x00010001;
1288 intr_router[13] = 0x00010003; 1299 intr_router[13] = 0x00010003;
1289#endif 1300#endif
1301 /*
1302 * intr_router[11] corresponds to output event #20, which is what we
1303 * set eventId to in .cfg file.
1304 * - bit 16 enables the entry
1305 * - lower bits define input event (#1 for dmtimer #0)
1306 * intr_router[13] corresponds to output event #22, which is what we
1307 * set eventId to in this file.
1308 * - bit 16 enables the entry
1309 * - lower bits define input event (#3 for dmtimer #2)
1310 */
1290#ifdef BUILD_C66X_2 1311#ifdef BUILD_C66X_2
1291 intr_router[11] = 0x00010002; 1312 intr_router[11] = 0x00010001;
1313 intr_router[13] = 0x00010003;
1292#endif 1314#endif
1293} 1315}
1294 1316
diff --git a/test/sysbios_unit_test/makefile b/test/sysbios_unit_test/makefile
index a27a59a..e497fdc 100755
--- a/test/sysbios_unit_test/makefile
+++ b/test/sysbios_unit_test/makefile
@@ -62,7 +62,7 @@ XDC_CFG_FILE_$(CORE) = $(PDK_INSTALL_PATH)/ti/build/j721e/sysbios_c66.cfg
62EXTERNAL_LNKCMD_FILE = $(PDK_INSTALL_PATH)/ti/build/j721e/linker_c66.lds 62EXTERNAL_LNKCMD_FILE = $(PDK_INSTALL_PATH)/ti/build/j721e/linker_c66.lds
63endif 63endif
64 64
65ifeq ($(CORE),$(filter $(CORE), c7x)) 65ifeq ($(CORE),$(filter $(CORE), c7x_1))
66# Enable XDC build for application by providing XDC CFG File per core 66# Enable XDC build for application by providing XDC CFG File per core
67XDC_CFG_FILE_$(CORE) = $(PDK_INSTALL_PATH)/ti/build/j721e/sysbios_c7x.cfg 67XDC_CFG_FILE_$(CORE) = $(PDK_INSTALL_PATH)/ti/build/j721e/sysbios_c7x.cfg
68EXTERNAL_LNKCMD_FILE = $(PDK_INSTALL_PATH)/ti/build/j721e/linker_c7x.lds 68EXTERNAL_LNKCMD_FILE = $(PDK_INSTALL_PATH)/ti/build/j721e/linker_c7x.lds