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author | Aravind Batni | 2019-07-29 17:26:17 -0500 |
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committer | Aravind Batni | 2019-08-06 10:07:51 -0500 |
commit | 889e0efef3722349443dc1c796a89b96786a52e7 (patch) | |
tree | 0d4adab56a4255861507de351442903f41ce9335 | |
parent | be89db7005d8699bfe4dd07f788e00fb90d1a0ab (diff) | |
download | osal-889e0efef3722349443dc1c796a89b96786a52e7.tar.gz osal-889e0efef3722349443dc1c796a89b96786a52e7.tar.xz osal-889e0efef3722349443dc1c796a89b96786a52e7.zip |
PRSDK-5612: added enable/disable interrupt option during HwiP Create
Signed-off-by: Aravind Batni <aravindbr@ti.com>
-rw-r--r-- | HwiP.h | 2 | ||||
-rw-r--r-- | arch/core/a15/Arch_util.c | 5 | ||||
-rw-r--r-- | arch/core/a53/Arch_util.c | 11 | ||||
-rw-r--r-- | arch/core/a8/Arch_util.c | 15 | ||||
-rw-r--r-- | arch/core/a9/Arch_util.c | 15 | ||||
-rw-r--r-- | arch/core/arm9/Arch_util.c | 15 | ||||
-rw-r--r-- | arch/core/c6x/Arch_util.c | 12 | ||||
-rw-r--r-- | arch/core/m4/Arch_util.c | 15 | ||||
-rwxr-xr-x | arch/core/r5/Arch_util.c | 13 | ||||
-rw-r--r-- | src/nonos/HwiP_nonos.c | 1 | ||||
-rw-r--r-- | src/tirtos/HwiP_tirtos.c | 12 |
11 files changed, 98 insertions, 18 deletions
@@ -130,6 +130,8 @@ typedef struct HwiP_Params_s { | |||
130 | set to NULL if not needed. */ | 130 | set to NULL if not needed. */ |
131 | uintptr_t arg; /*!< Argument passed into the Hwi function. */ | 131 | uintptr_t arg; /*!< Argument passed into the Hwi function. */ |
132 | uint32_t priority; /*!< Device specific priority. */ | 132 | uint32_t priority; /*!< Device specific priority. */ |
133 | uint32_t enableIntr; /*!< When set to TRUE, interrupt is enabled after the create | ||
134 | otherwise interrupt is disabled after HwiP_Create */ | ||
133 | uint32_t evtId; /*!< Event Id associated */ | 135 | uint32_t evtId; /*!< Event Id associated */ |
134 | #if defined (__ARM_ARCH_7A__) || defined(__aarch64__) || defined (__TI_ARM_V7R4__) | 136 | #if defined (__ARM_ARCH_7A__) || defined(__aarch64__) || defined (__TI_ARM_V7R4__) |
135 | uint32_t triggerSensitivity; /*!< Set an interrupt's trigger sensitivity for | 137 | uint32_t triggerSensitivity; /*!< Set an interrupt's trigger sensitivity for |
diff --git a/arch/core/a15/Arch_util.c b/arch/core/a15/Arch_util.c index 68be49a..f64f49f 100644 --- a/arch/core/a15/Arch_util.c +++ b/arch/core/a15/Arch_util.c | |||
@@ -225,6 +225,11 @@ HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn, | |||
225 | 225 | ||
226 | /* Configure the interrupt Controller */ | 226 | /* Configure the interrupt Controller */ |
227 | CSL_armGicConfigIntr(gCpuIntrf, (uint32_t)interruptNum, &hwi_handle->gicParams); | 227 | CSL_armGicConfigIntr(gCpuIntrf, (uint32_t)interruptNum, &hwi_handle->gicParams); |
228 | /* above CSL call enables the IRQ by defaualt, disable it if configured */ | ||
229 | if (params->enableIntr != TRUE) | ||
230 | { | ||
231 | CSL_a15DisableIrq(); | ||
232 | } | ||
228 | } | 233 | } |
229 | /* Return Non Zero value for the handle for A15 target */ | 234 | /* Return Non Zero value for the handle for A15 target */ |
230 | return ((HwiP_Handle) (retHandle) ); | 235 | return ((HwiP_Handle) (retHandle) ); |
diff --git a/arch/core/a53/Arch_util.c b/arch/core/a53/Arch_util.c index afa8ea9..2f99e49 100644 --- a/arch/core/a53/Arch_util.c +++ b/arch/core/a53/Arch_util.c | |||
@@ -256,8 +256,15 @@ HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn, | |||
256 | /* Return Non Zero value for the handle for A15 target */ | 256 | /* Return Non Zero value for the handle for A15 target */ |
257 | hwi_handle->intNum = interruptNum; | 257 | hwi_handle->intNum = interruptNum; |
258 | 258 | ||
259 | /* Enabling the interrupt in INTC. */ | 259 | /* Enabling the interrupt if configured */ |
260 | OsalArch_enableInterrupt(interruptNum); | 260 | if (params->enableIntr == TRUE) |
261 | { | ||
262 | OsalArch_enableInterrupt(interruptNum); | ||
263 | } | ||
264 | else | ||
265 | { | ||
266 | OsalArch_disableInterrupt(interruptNum); | ||
267 | } | ||
261 | } | 268 | } |
262 | return ((HwiP_Handle) (retHandle) ); | 269 | return ((HwiP_Handle) (retHandle) ); |
263 | 270 | ||
diff --git a/arch/core/a8/Arch_util.c b/arch/core/a8/Arch_util.c index 1c719af..79e9c34 100644 --- a/arch/core/a8/Arch_util.c +++ b/arch/core/a8/Arch_util.c | |||
@@ -217,9 +217,18 @@ HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn, | |||
217 | 217 | ||
218 | /* Configure the interrupt Controller */ | 218 | /* Configure the interrupt Controller */ |
219 | INTCConfigIntr(interruptNum,&intrParams, FALSE); | 219 | INTCConfigIntr(interruptNum,&intrParams, FALSE); |
220 | 220 | ||
221 | /* Enabling the interrupt in INTC. */ | 221 | /* Enabling the interrupt if configured */ |
222 | HwiP_enableInterrupt(interruptNum); | 222 | if (params->enableIntr == TRUE) |
223 | { | ||
224 | /* Enabling the interrupt in INTC. */ | ||
225 | OsalArch_enableInterrupt(interruptNum); | ||
226 | } | ||
227 | else | ||
228 | { | ||
229 | /* Disabling the interrupt in INTC. */ | ||
230 | OsalArch_disableInterrupt(interruptNum); | ||
231 | } | ||
223 | } | 232 | } |
224 | return ( (HwiP_Handle) (retHandle) ); | 233 | return ( (HwiP_Handle) (retHandle) ); |
225 | 234 | ||
diff --git a/arch/core/a9/Arch_util.c b/arch/core/a9/Arch_util.c index 068a192..c1a352b 100644 --- a/arch/core/a9/Arch_util.c +++ b/arch/core/a9/Arch_util.c | |||
@@ -211,9 +211,18 @@ HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn, | |||
211 | 211 | ||
212 | /* Configure the interrupt Controller */ | 212 | /* Configure the interrupt Controller */ |
213 | INTCConfigIntr(interruptNum,&intrParams, FALSE); | 213 | INTCConfigIntr(interruptNum,&intrParams, FALSE); |
214 | 214 | ||
215 | /* Enabling the interrupt in INTC. */ | 215 | /* Enabling the interrupt if configured */ |
216 | HwiP_enableInterrupt(interruptNum); | 216 | if (params->enableIntr == TRUE) |
217 | { | ||
218 | /* Enabling the interrupt in INTC. */ | ||
219 | OsalArch_enableInterrupt(interruptNum); | ||
220 | } | ||
221 | else | ||
222 | { | ||
223 | /* Disabling the interrupt in INTC. */ | ||
224 | OsalArch_disableInterrupt(interruptNum); | ||
225 | } | ||
217 | } | 226 | } |
218 | return ( (HwiP_Handle) (retHandle) ); | 227 | return ( (HwiP_Handle) (retHandle) ); |
219 | 228 | ||
diff --git a/arch/core/arm9/Arch_util.c b/arch/core/arm9/Arch_util.c index 9cf25fe..3f4b005 100644 --- a/arch/core/arm9/Arch_util.c +++ b/arch/core/arm9/Arch_util.c | |||
@@ -171,9 +171,18 @@ HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn, | |||
171 | are mapped to FIQ and Channel numbers 2-31 are mapped to IRQ of ARM.*/ | 171 | are mapped to FIQ and Channel numbers 2-31 are mapped to IRQ of ARM.*/ |
172 | channelNo = ((params->priority > 31) || (params->priority < 2)) ? 0x12U : params->priority; | 172 | channelNo = ((params->priority > 31) || (params->priority < 2)) ? 0x12U : params->priority; |
173 | IntChannelSet((uint32_t)interruptNum, channelNo); | 173 | IntChannelSet((uint32_t)interruptNum, channelNo); |
174 | 174 | ||
175 | /* Enabling the UART interrupt in INTC. */ | 175 | /* Enabling the interrupt if configured */ |
176 | OsalArch_enableInterrupt(interruptNum); | 176 | if (params->enableIntr == TRUE) |
177 | { | ||
178 | /* Enabling the interrupt in INTC. */ | ||
179 | OsalArch_enableInterrupt(interruptNum); | ||
180 | } | ||
181 | else | ||
182 | { | ||
183 | /* Disabling the interrupt in INTC. */ | ||
184 | OsalArch_disableInterrupt(interruptNum); | ||
185 | } | ||
177 | 186 | ||
178 | /* Enable the Globle interrupt AINTC */ | 187 | /* Enable the Globle interrupt AINTC */ |
179 | IntMasterIRQEnable(); | 188 | IntMasterIRQEnable(); |
diff --git a/arch/core/c6x/Arch_util.c b/arch/core/c6x/Arch_util.c index 7df6690..5300250 100644 --- a/arch/core/c6x/Arch_util.c +++ b/arch/core/c6x/Arch_util.c | |||
@@ -179,6 +179,18 @@ HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn, | |||
179 | CSL_intcPlugEventHandler(hwi_handle->handle, &evtHandler); | 179 | CSL_intcPlugEventHandler(hwi_handle->handle, &evtHandler); |
180 | CSL_intcHwControl(hwi_handle->handle,CSL_INTC_CMD_EVTCLEAR,NULL); | 180 | CSL_intcHwControl(hwi_handle->handle,CSL_INTC_CMD_EVTCLEAR,NULL); |
181 | CSL_intcHwControl(hwi_handle->handle,CSL_INTC_CMD_EVTENABLE,NULL); | 181 | CSL_intcHwControl(hwi_handle->handle,CSL_INTC_CMD_EVTENABLE,NULL); |
182 | |||
183 | /* Enabling the interrupt if configured */ | ||
184 | if (params->enableIntr == TRUE) | ||
185 | { | ||
186 | /* Enabling the interrupt in INTC. */ | ||
187 | OsalArch_enableInterrupt(interruptNum); | ||
188 | } | ||
189 | else | ||
190 | { | ||
191 | /* Disabling the interrupt in INTC. */ | ||
192 | OsalArch_disableInterrupt(interruptNum); | ||
193 | } | ||
182 | } | 194 | } |
183 | else | 195 | else |
184 | { | 196 | { |
diff --git a/arch/core/m4/Arch_util.c b/arch/core/m4/Arch_util.c index fcf1713..b40bd80 100644 --- a/arch/core/m4/Arch_util.c +++ b/arch/core/m4/Arch_util.c | |||
@@ -186,9 +186,18 @@ HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn, | |||
186 | 186 | ||
187 | /* Setting the priority for the UART interrupt in INTC. */ | 187 | /* Setting the priority for the UART interrupt in INTC. */ |
188 | Intc_IntPrioritySet((uint16_t)interruptNum, params->priority, 0); | 188 | Intc_IntPrioritySet((uint16_t)interruptNum, params->priority, 0); |
189 | 189 | ||
190 | /* Enabling the UART interrupt in INTC. */ | 190 | /* Enabling the interrupt if configured */ |
191 | HwiP_enableInterrupt(interruptNum); | 191 | if (params->enableIntr == TRUE) |
192 | { | ||
193 | /* Enabling the interrupt in INTC. */ | ||
194 | OsalArch_enableInterrupt(interruptNum); | ||
195 | } | ||
196 | else | ||
197 | { | ||
198 | /* Disabling the interrupt in INTC. */ | ||
199 | OsalArch_disableInterrupt(interruptNum); | ||
200 | } | ||
192 | } | 201 | } |
193 | return ( (HwiP_Handle) (retHandle) ); | 202 | return ( (HwiP_Handle) (retHandle) ); |
194 | 203 | ||
diff --git a/arch/core/r5/Arch_util.c b/arch/core/r5/Arch_util.c index d156907..dafc098 100755 --- a/arch/core/r5/Arch_util.c +++ b/arch/core/r5/Arch_util.c | |||
@@ -228,8 +228,17 @@ HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn, | |||
228 | /* Setting the priority for the UART interrupt in INTC. */ | 228 | /* Setting the priority for the UART interrupt in INTC. */ |
229 | Intc_IntPrioritySet((uint16_t)interruptNum, params->priority, 0); | 229 | Intc_IntPrioritySet((uint16_t)interruptNum, params->priority, 0); |
230 | 230 | ||
231 | /* Enabling the interrupt in INTC. */ | 231 | /* Enabling the interrupt if configured */ |
232 | Intc_IntEnable(interruptNum); | 232 | if (params->enableIntr == TRUE) |
233 | { | ||
234 | /* Enabling the interrupt in INTC. */ | ||
235 | Intc_IntEnable(interruptNum); | ||
236 | } | ||
237 | else | ||
238 | { | ||
239 | /* Disabling the interrupt in INTC. */ | ||
240 | Intc_IntDisable(interruptNum); | ||
241 | } | ||
233 | Intc_SystemEnable(); | 242 | Intc_SystemEnable(); |
234 | 243 | ||
235 | } | 244 | } |
diff --git a/src/nonos/HwiP_nonos.c b/src/nonos/HwiP_nonos.c index 80a18b1..0391cab 100644 --- a/src/nonos/HwiP_nonos.c +++ b/src/nonos/HwiP_nonos.c | |||
@@ -137,6 +137,7 @@ void HwiP_Params_init(HwiP_Params *params) | |||
137 | params->arg = 0; | 137 | params->arg = 0; |
138 | params->priority = HWIP_USE_DEFAULT_PRIORITY; | 138 | params->priority = HWIP_USE_DEFAULT_PRIORITY; |
139 | params->evtId = 0; | 139 | params->evtId = 0; |
140 | params->enableIntr = TRUE; | ||
140 | #if defined (__ARM_ARCH_7A__) || defined(__aarch64__) || defined (__TI_ARM_V7R4__) | 141 | #if defined (__ARM_ARCH_7A__) || defined(__aarch64__) || defined (__TI_ARM_V7R4__) |
141 | params->triggerSensitivity = OSAL_ARM_GIC_TRIG_TYPE_LEVEL; | 142 | params->triggerSensitivity = OSAL_ARM_GIC_TRIG_TYPE_LEVEL; |
142 | #if !defined (SOC_AM437x) && !defined(SOC_AM335x) && !defined (__TI_ARM_V7R4__) | 143 | #if !defined (SOC_AM437x) && !defined(SOC_AM335x) && !defined (__TI_ARM_V7R4__) |
diff --git a/src/tirtos/HwiP_tirtos.c b/src/tirtos/HwiP_tirtos.c index 1142a75..7e14c5d 100644 --- a/src/tirtos/HwiP_tirtos.c +++ b/src/tirtos/HwiP_tirtos.c | |||
@@ -198,7 +198,14 @@ HwiP_Handle HwiP_create(int32_t interruptNum, HwiP_Fxn hwiFxn, | |||
198 | } | 198 | } |
199 | 199 | ||
200 | hwiParams.eventId = (int)params->evtId; | 200 | hwiParams.eventId = (int)params->evtId; |
201 | hwiParams.enableInt = TRUE; | 201 | if (params->enableIntr == TRUE) |
202 | { | ||
203 | hwiParams.enableInt = TRUE; | ||
204 | } | ||
205 | else | ||
206 | { | ||
207 | hwiParams.enableInt = FALSE; | ||
208 | } | ||
202 | #ifdef __aarch64__ | 209 | #ifdef __aarch64__ |
203 | hwiParams.maskSetting = Hwi_MaskingOption_LOWER; | 210 | hwiParams.maskSetting = Hwi_MaskingOption_LOWER; |
204 | #else | 211 | #else |
@@ -296,7 +303,8 @@ void HwiP_Params_init(HwiP_Params *params) | |||
296 | params->name = NULL; | 303 | params->name = NULL; |
297 | params->arg = 0; | 304 | params->arg = 0; |
298 | params->priority = HWIP_USE_DEFAULT_PRIORITY; | 305 | params->priority = HWIP_USE_DEFAULT_PRIORITY; |
299 | params->evtId = 0; | 306 | params->evtId = 0; |
307 | params->enableIntr = TRUE; | ||
300 | #if defined (__ARM_ARCH_7A__) || defined(__aarch64__) || defined (__TI_ARM_V7R4__) || defined(gnu_targets_arm_A15F) || defined(gnu_targets_arm_A9F) | 308 | #if defined (__ARM_ARCH_7A__) || defined(__aarch64__) || defined (__TI_ARM_V7R4__) || defined(gnu_targets_arm_A15F) || defined(gnu_targets_arm_A9F) |
301 | params->triggerSensitivity = OSAL_ARM_GIC_TRIG_TYPE_LEVEL; | 309 | params->triggerSensitivity = OSAL_ARM_GIC_TRIG_TYPE_LEVEL; |
302 | #endif | 310 | #endif |