PRSDK-5612: added enable/disable interrupt option during HwiP Create

Signed-off-by: Aravind Batni <aravindbr@ti.com>

11 files changed, 98 insertions, 18 deletions

diff --git a/HwiP.h b/HwiP.h
index da9d7f5..43fd9c8 100644
--- a/HwiP.h
+++ b/HwiP.h
@@ -130,6 +130,8 @@ typedef struct HwiP_Params_s {
                                set to NULL if not needed. */
     uintptr_t  arg;       /*!< Argument passed into the Hwi function. */
     uint32_t   priority;  /*!< Device specific priority. */
+    uint32_t   enableIntr; /*!< When set to TRUE, interrupt is enabled after the create
+                                otherwise interrupt is disabled after HwiP_Create */
     uint32_t   evtId;     /*!< Event Id associated */
 #if defined (__ARM_ARCH_7A__) || defined(__aarch64__) || defined (__TI_ARM_V7R4__)
     uint32_t   triggerSensitivity; /*!< Set an interrupt's trigger sensitivity for 
diff --git a/arch/core/a15/Arch_util.c b/arch/core/a15/Arch_util.c
index 68be49a..f64f49f 100644
--- a/arch/core/a15/Arch_util.c
+++ b/arch/core/a15/Arch_util.c
@@ -225,6 +225,11 @@ HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn,
 
         /* Configure the interrupt Controller */
         CSL_armGicConfigIntr(gCpuIntrf, (uint32_t)interruptNum, &hwi_handle->gicParams);
+        /* above CSL call enables the IRQ by defaualt, disable it if configured */
+        if (params->enableIntr != TRUE)
+        {
+            CSL_a15DisableIrq();
+        }
     }
     /* Return Non Zero value for the handle for A15 target */
     return ((HwiP_Handle) (retHandle) );
diff --git a/arch/core/a53/Arch_util.c b/arch/core/a53/Arch_util.c
index afa8ea9..2f99e49 100644
--- a/arch/core/a53/Arch_util.c
+++ b/arch/core/a53/Arch_util.c
@@ -256,8 +256,15 @@ HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn,
         /* Return Non Zero value for the handle for A15 target */
         hwi_handle->intNum = interruptNum;
 
-        /* Enabling the interrupt in INTC. */
-        OsalArch_enableInterrupt(interruptNum);
+        /* Enabling the interrupt if configured */
+        if (params->enableIntr == TRUE)
+        {
+            OsalArch_enableInterrupt(interruptNum);
+        }
+        else
+        {
+            OsalArch_disableInterrupt(interruptNum);
+        }
     }
     return ((HwiP_Handle) (retHandle) );
 
diff --git a/arch/core/a8/Arch_util.c b/arch/core/a8/Arch_util.c
index 1c719af..79e9c34 100644
--- a/arch/core/a8/Arch_util.c
+++ b/arch/core/a8/Arch_util.c
@@ -217,9 +217,18 @@ HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn,
     
         /* Configure the interrupt Controller */
         INTCConfigIntr(interruptNum,&intrParams, FALSE);
-    
-        /* Enabling the interrupt in INTC. */
-        HwiP_enableInterrupt(interruptNum);
+
+        /* Enabling the interrupt if configured */
+        if (params->enableIntr == TRUE)
+        {
+            /* Enabling the interrupt in INTC. */
+            OsalArch_enableInterrupt(interruptNum);
+        }
+        else
+        {
+            /* Disabling the interrupt in INTC. */
+            OsalArch_disableInterrupt(interruptNum);
+        }
     }
     return ( (HwiP_Handle) (retHandle) );
 
diff --git a/arch/core/a9/Arch_util.c b/arch/core/a9/Arch_util.c
index 068a192..c1a352b 100644
--- a/arch/core/a9/Arch_util.c
+++ b/arch/core/a9/Arch_util.c
@@ -211,9 +211,18 @@ HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn,
     
         /* Configure the interrupt Controller */
         INTCConfigIntr(interruptNum,&intrParams, FALSE);
-    
-        /* Enabling the interrupt in INTC. */
-        HwiP_enableInterrupt(interruptNum);
+
+        /* Enabling the interrupt if configured */
+        if (params->enableIntr == TRUE)
+        {
+            /* Enabling the interrupt in INTC. */
+            OsalArch_enableInterrupt(interruptNum);
+        }
+        else
+        {
+            /* Disabling the interrupt in INTC. */
+            OsalArch_disableInterrupt(interruptNum);
+        }
     }
     return ( (HwiP_Handle) (retHandle) );
 
diff --git a/arch/core/arm9/Arch_util.c b/arch/core/arm9/Arch_util.c
index 9cf25fe..3f4b005 100644
--- a/arch/core/arm9/Arch_util.c
+++ b/arch/core/arm9/Arch_util.c
@@ -171,9 +171,18 @@ HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn,
           are mapped to FIQ and Channel numbers 2-31 are mapped to IRQ of ARM.*/
         channelNo = ((params->priority > 31) || (params->priority < 2)) ? 0x12U : params->priority;
         IntChannelSet((uint32_t)interruptNum, channelNo);
-    
-        /* Enabling the UART interrupt in INTC. */
-        OsalArch_enableInterrupt(interruptNum);
+
+        /* Enabling the interrupt if configured */
+        if (params->enableIntr == TRUE)
+        {
+            /* Enabling the interrupt in INTC. */
+            OsalArch_enableInterrupt(interruptNum);
+        }
+        else
+        {
+            /* Disabling the interrupt in INTC. */
+            OsalArch_disableInterrupt(interruptNum);
+        }
 
         /* Enable the Globle interrupt AINTC */
         IntMasterIRQEnable();
diff --git a/arch/core/c6x/Arch_util.c b/arch/core/c6x/Arch_util.c
index 7df6690..5300250 100644
--- a/arch/core/c6x/Arch_util.c
+++ b/arch/core/c6x/Arch_util.c
@@ -179,6 +179,18 @@ HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn,
              CSL_intcPlugEventHandler(hwi_handle->handle, &evtHandler);
              CSL_intcHwControl(hwi_handle->handle,CSL_INTC_CMD_EVTCLEAR,NULL);
              CSL_intcHwControl(hwi_handle->handle,CSL_INTC_CMD_EVTENABLE,NULL);
+
+             /* Enabling the interrupt if configured */
+             if (params->enableIntr == TRUE)
+             {
+                 /* Enabling the interrupt in INTC. */
+                 OsalArch_enableInterrupt(interruptNum);
+             }
+             else
+             {
+                 /* Disabling the interrupt in INTC. */
+                 OsalArch_disableInterrupt(interruptNum);
+             }
          }
          else
          {
diff --git a/arch/core/m4/Arch_util.c b/arch/core/m4/Arch_util.c
index fcf1713..b40bd80 100644
--- a/arch/core/m4/Arch_util.c
+++ b/arch/core/m4/Arch_util.c
@@ -186,9 +186,18 @@ HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn,
     
         /* Setting the priority for the UART interrupt in INTC. */
         Intc_IntPrioritySet((uint16_t)interruptNum, params->priority, 0);
-    
-        /* Enabling the UART interrupt in INTC. */
-        HwiP_enableInterrupt(interruptNum);
+
+        /* Enabling the interrupt if configured */
+        if (params->enableIntr == TRUE)
+        {
+            /* Enabling the interrupt in INTC. */
+            OsalArch_enableInterrupt(interruptNum);
+        }
+        else
+        {
+            /* Disabling the interrupt in INTC. */
+            OsalArch_disableInterrupt(interruptNum);
+        }
     }
     return ( (HwiP_Handle) (retHandle) );
 
diff --git a/arch/core/r5/Arch_util.c b/arch/core/r5/Arch_util.c
index d156907..dafc098 100755
--- a/arch/core/r5/Arch_util.c
+++ b/arch/core/r5/Arch_util.c
@@ -228,8 +228,17 @@ HwiP_Handle OsalArch_HwiPCreate(int32_t interruptNum, HwiP_Fxn hwiFxn,
         /* Setting the priority for the UART interrupt in INTC. */
         Intc_IntPrioritySet((uint16_t)interruptNum, params->priority, 0);
 
-        /* Enabling the interrupt in INTC. */
-        Intc_IntEnable(interruptNum);
+        /* Enabling the interrupt if configured */
+        if (params->enableIntr == TRUE)
+        {
+            /* Enabling the interrupt in INTC. */
+            Intc_IntEnable(interruptNum);
+        }
+        else
+        {
+            /* Disabling the interrupt in INTC. */
+            Intc_IntDisable(interruptNum);
+        }
         Intc_SystemEnable();
 
     }
diff --git a/src/nonos/HwiP_nonos.c b/src/nonos/HwiP_nonos.c
index 80a18b1..0391cab 100644
--- a/src/nonos/HwiP_nonos.c
+++ b/src/nonos/HwiP_nonos.c
@@ -137,6 +137,7 @@ void HwiP_Params_init(HwiP_Params *params)
     params->arg      = 0;
     params->priority = HWIP_USE_DEFAULT_PRIORITY;
     params->evtId    = 0;
+    params->enableIntr = TRUE;
 #if defined (__ARM_ARCH_7A__) || defined(__aarch64__) || defined (__TI_ARM_V7R4__)
     params->triggerSensitivity = OSAL_ARM_GIC_TRIG_TYPE_LEVEL;
 #if !defined (SOC_AM437x) &&  !defined(SOC_AM335x) && !defined (__TI_ARM_V7R4__)
diff --git a/src/tirtos/HwiP_tirtos.c b/src/tirtos/HwiP_tirtos.c
index 1142a75..7e14c5d 100644
--- a/src/tirtos/HwiP_tirtos.c
+++ b/src/tirtos/HwiP_tirtos.c
@@ -198,7 +198,14 @@ HwiP_Handle HwiP_create(int32_t interruptNum, HwiP_Fxn hwiFxn,
             }
 
             hwiParams.eventId        = (int)params->evtId;
-            hwiParams.enableInt      = TRUE;
+            if (params->enableIntr == TRUE)
+            {
+                hwiParams.enableInt      = TRUE;
+            }
+            else
+            {
+                hwiParams.enableInt      = FALSE;
+            }
 #ifdef __aarch64__
             hwiParams.maskSetting    = Hwi_MaskingOption_LOWER;
 #else
@@ -296,7 +303,8 @@ void HwiP_Params_init(HwiP_Params *params)
     params->name = NULL;
     params->arg = 0;
     params->priority = HWIP_USE_DEFAULT_PRIORITY;
-    params->evtId    = 0;    
+    params->evtId    = 0;
+    params->enableIntr = TRUE;
 #if defined (__ARM_ARCH_7A__) || defined(__aarch64__) || defined (__TI_ARM_V7R4__) || defined(gnu_targets_arm_A15F) || defined(gnu_targets_arm_A9F)
     params->triggerSensitivity = OSAL_ARM_GIC_TRIG_TYPE_LEVEL;
 #endif