osal: PRSDK-4967: support run-time VIM base address configuration for J7

Signed-off-by: Hao Zhang <hzhang@ti.com>

1 files changed, 18 insertions, 5 deletions

diff --git a/arch/core/r5/Arch_util.c b/arch/core/r5/Arch_util.c
index 37b6549..9b8bb83 100755
--- a/arch/core/r5/Arch_util.c
+++ b/arch/core/r5/Arch_util.c
@@ -37,6 +37,7 @@
 #include <stdint.h>
 #include <stdbool.h>
 #include <stdlib.h>
+#include <ti/csl/arch/r5/interrupt.h>
 #include <ti/osal/src/nonos/Nonos_config.h>
 
 #if defined (BUILD_MCU1_0)
@@ -91,9 +92,6 @@ static bool gTimestampFirstTime = TRUE;
 static TimeStamp_Struct gTimeStamp = {0U};
 static HwiP_Handle      gHwiPHandle;
 
-#define   OSAL_ARCH_VIM_BASE_ADDR (0x103E0 << 14)
-
-
 /* This function enables the interrupt for a given interrupt number */
 void OsalArch_enableInterrupt(uint32_t intNum)
 {
@@ -123,8 +121,23 @@ uintptr_t OsalArch_globalDisableInterrupt(void)
 /* Below function posts the interrupt */
 int32_t OsalArch_postInterrupt(uint32_t intrNum)
 {
-    CSL_vimRegs *vimRegs;
-    vimRegs = (CSL_vimRegs *)(uintptr_t)OSAL_ARCH_VIM_BASE_ADDR;
+    CSL_vimRegs      *vimRegs;
+    uint32_t          vimBaseAddr;
+    CSL_ArmR5CPUInfo  info;
+
+    CSL_armR5GetCpuID(&info);
+    if (info.grpId == (uint32_t)CSL_ARM_R5_CLUSTER_GROUP_ID_0)
+    {
+        /* MCU SS Pulsar R5 SS */
+        vimBaseAddr = (uint32_t)CSL_MCU_DOMAIN_VIM_BASE_ADDR;
+    }
+    else
+    {
+        /* MAIN SS Pulsar R5 SS */
+        vimBaseAddr = (uint32_t)CSL_MAIN_DOMAIN_VIM_BASE_ADDR;
+    }
+
+    vimRegs = (CSL_vimRegs *)(uintptr_t)vimBaseAddr;
     return (CSL_vimSetIntrPending(vimRegs, intrNum));
 }