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Diffstat (limited to 'soc/j721e/TimerP_default.c')
-rwxr-xr-xsoc/j721e/TimerP_default.c224
1 files changed, 112 insertions, 112 deletions
diff --git a/soc/j721e/TimerP_default.c b/soc/j721e/TimerP_default.c
index e50e512..658af30 100755
--- a/soc/j721e/TimerP_default.c
+++ b/soc/j721e/TimerP_default.c
@@ -56,20 +56,20 @@ TimerP_dmTimerDefault gDmTimerPInfoTbl[TimerP_numTimerDevices] = {
56 "DMTimer0", /* Timer Name */ 56 "DMTimer0", /* Timer Name */
57#if defined (BUILD_MCU) 57#if defined (BUILD_MCU)
58 /* Default configurations for R5 core */ 58 /* Default configurations for R5 core */
59 CSL_MCU_TIMER0_CFG_BASE, /* MCU domain's DM Timer base address */ 59 (uint32_t)CSL_MCU_TIMER0_CFG_BASE, /* MCU domain's DM Timer base address */
60 CSLR_MCU_R5FSS0_CORE0_INTR_MCU_TIMER0_INTR_PEND_0, /* MCU domain's DM Timer interrupt number */ 60 (int32_t)CSLR_MCU_R5FSS0_CORE0_INTR_MCU_TIMER0_INTR_PEND_0, /* MCU domain's DM Timer interrupt number */
61 TIMERP_EVENT_NOT_AVAILABLE /* Event Id */ 61 TIMERP_EVENT_NOT_AVAILABLE /* Event Id */
62#endif 62#endif
63#if defined (BUILD_MPU) 63#if defined (BUILD_MPU)
64 /* Default configurations for A72 core */ 64 /* Default configurations for A72 core */
65 CSL_TIMER0_CFG_BASE, /* Main domain's DM Timer base address */ 65 (uint32_t)CSL_TIMER0_CFG_BASE, /* Main domain's DM Timer base address */
66 CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER0_INTR_PEND_0, /* Main domain's DM Timer interrupt number */ 66 (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER0_INTR_PEND_0, /* Main domain's DM Timer interrupt number */
67 TIMERP_EVENT_NOT_AVAILABLE /* Event Id */ 67 TIMERP_EVENT_NOT_AVAILABLE /* Event Id */
68#endif 68#endif
69#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2) 69#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
70 /* Default configurations for DSP core */ 70 /* Default configurations for DSP core */
71 CSL_TIMER0_CFG_BASE, /* Main domain's DM Timer base address */ 71 (uint32_t)CSL_TIMER0_CFG_BASE, /* Main domain's DM Timer base address */
72 TIMERP_INTR_USER_CONFIGURE, /* User Confugure */ 72 (int32_t)TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
73 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */ 73 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
74#endif 74#endif
75 }, 75 },
@@ -77,17 +77,17 @@ TimerP_dmTimerDefault gDmTimerPInfoTbl[TimerP_numTimerDevices] = {
77 { 77 {
78 "DMTimer1", 78 "DMTimer1",
79#if defined (BUILD_MCU) 79#if defined (BUILD_MCU)
80 CSL_MCU_TIMER1_CFG_BASE, 80 (uint32_t)CSL_MCU_TIMER1_CFG_BASE,
81 CSLR_MCU_R5FSS0_CORE0_INTR_MCU_TIMER1_INTR_PEND_0, 81 (int32_t)CSLR_MCU_R5FSS0_CORE0_INTR_MCU_TIMER1_INTR_PEND_0,
82 TIMERP_EVENT_NOT_AVAILABLE 82 TIMERP_EVENT_NOT_AVAILABLE
83#endif 83#endif
84#if defined (BUILD_MPU) 84#if defined (BUILD_MPU)
85 CSL_TIMER1_CFG_BASE, 85 (uint32_t)CSL_TIMER1_CFG_BASE,
86 CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER1_INTR_PEND_0, 86 (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER1_INTR_PEND_0,
87 TIMERP_EVENT_NOT_AVAILABLE 87 TIMERP_EVENT_NOT_AVAILABLE
88#endif 88#endif
89#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2) 89#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
90 CSL_TIMER1_CFG_BASE, 90 (uint32_t)CSL_TIMER1_CFG_BASE,
91 TIMERP_INTR_USER_CONFIGURE, /* User Confugure */ 91 TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
92 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */ 92 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
93#endif 93#endif
@@ -96,18 +96,18 @@ TimerP_dmTimerDefault gDmTimerPInfoTbl[TimerP_numTimerDevices] = {
96 { 96 {
97 "DMTimer2", 97 "DMTimer2",
98#if defined (BUILD_MCU) 98#if defined (BUILD_MCU)
99 CSL_MCU_TIMER2_CFG_BASE, 99 (uint32_t)CSL_MCU_TIMER2_CFG_BASE,
100 CSLR_MCU_R5FSS0_CORE0_INTR_MCU_TIMER2_INTR_PEND_0, 100 (int32_t)CSLR_MCU_R5FSS0_CORE0_INTR_MCU_TIMER2_INTR_PEND_0,
101 TIMERP_EVENT_NOT_AVAILABLE 101 TIMERP_EVENT_NOT_AVAILABLE
102#endif 102#endif
103#if defined (BUILD_MPU) 103#if defined (BUILD_MPU)
104 CSL_TIMER2_CFG_BASE, 104 (uint32_t)CSL_TIMER2_CFG_BASE,
105 CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER2_INTR_PEND_0, 105 (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER2_INTR_PEND_0,
106 TIMERP_EVENT_NOT_AVAILABLE 106 TIMERP_EVENT_NOT_AVAILABLE
107#endif 107#endif
108#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2) 108#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
109 CSL_TIMER2_CFG_BASE, 109 (uint32_t)CSL_TIMER2_CFG_BASE,
110 TIMERP_INTR_USER_CONFIGURE, /* User Confugure */ 110 (int32_t)TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
111 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */ 111 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
112#endif 112#endif
113 }, 113 },
@@ -115,18 +115,18 @@ TimerP_dmTimerDefault gDmTimerPInfoTbl[TimerP_numTimerDevices] = {
115 { 115 {
116 "DMTimer3", 116 "DMTimer3",
117#if defined (BUILD_MCU) 117#if defined (BUILD_MCU)
118 CSL_MCU_TIMER3_CFG_BASE, 118 (uint32_t)CSL_MCU_TIMER3_CFG_BASE,
119 CSLR_MCU_R5FSS0_CORE0_INTR_MCU_TIMER3_INTR_PEND_0, 119 (int32_t)CSLR_MCU_R5FSS0_CORE0_INTR_MCU_TIMER3_INTR_PEND_0,
120 TIMERP_EVENT_NOT_AVAILABLE 120 TIMERP_EVENT_NOT_AVAILABLE
121#endif 121#endif
122#if defined (BUILD_MPU) 122#if defined (BUILD_MPU)
123 CSL_TIMER3_CFG_BASE, 123 (uint32_t)CSL_TIMER3_CFG_BASE,
124 CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER3_INTR_PEND_0, 124 (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER3_INTR_PEND_0,
125 TIMERP_EVENT_NOT_AVAILABLE 125 TIMERP_EVENT_NOT_AVAILABLE
126#endif 126#endif
127#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2) 127#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
128 CSL_TIMER3_CFG_BASE, 128 (uint32_t)CSL_TIMER3_CFG_BASE,
129 TIMERP_INTR_USER_CONFIGURE, /* User Confugure */ 129 (int32_t)TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
130 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */ 130 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
131#endif 131#endif
132 }, 132 },
@@ -134,18 +134,18 @@ TimerP_dmTimerDefault gDmTimerPInfoTbl[TimerP_numTimerDevices] = {
134 { 134 {
135 "DMTimer4", 135 "DMTimer4",
136#if defined (BUILD_MCU) 136#if defined (BUILD_MCU)
137 CSL_MCU_TIMER4_CFG_BASE, 137 (uint32_t)CSL_MCU_TIMER4_CFG_BASE,
138 CSLR_MCU_R5FSS0_CORE0_INTR_MCU_TIMER4_INTR_PEND_0, 138 (int32_t)CSLR_MCU_R5FSS0_CORE0_INTR_MCU_TIMER4_INTR_PEND_0,
139 TIMERP_EVENT_NOT_AVAILABLE 139 TIMERP_EVENT_NOT_AVAILABLE
140#endif 140#endif
141#if defined (BUILD_MPU) 141#if defined (BUILD_MPU)
142 CSL_TIMER4_CFG_BASE, 142 (uint32_t)CSL_TIMER4_CFG_BASE,
143 CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER4_INTR_PEND_0, 143 (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER4_INTR_PEND_0,
144 TIMERP_EVENT_NOT_AVAILABLE 144 TIMERP_EVENT_NOT_AVAILABLE
145#endif 145#endif
146#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2) 146#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
147 CSL_TIMER4_CFG_BASE, 147 (uint32_t)CSL_TIMER4_CFG_BASE,
148 TIMERP_INTR_USER_CONFIGURE, /* User Confugure */ 148 (int32_t)TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
149 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */ 149 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
150#endif 150#endif
151 }, 151 },
@@ -153,18 +153,18 @@ TimerP_dmTimerDefault gDmTimerPInfoTbl[TimerP_numTimerDevices] = {
153 { 153 {
154 "DMTimer5", 154 "DMTimer5",
155#if defined (BUILD_MCU) 155#if defined (BUILD_MCU)
156 CSL_MCU_TIMER5_CFG_BASE, 156 (uint32_t)CSL_MCU_TIMER5_CFG_BASE,
157 CSLR_MCU_R5FSS0_CORE0_INTR_MCU_TIMER5_INTR_PEND_0, 157 (int32_t)CSLR_MCU_R5FSS0_CORE0_INTR_MCU_TIMER5_INTR_PEND_0,
158 TIMERP_EVENT_NOT_AVAILABLE 158 TIMERP_EVENT_NOT_AVAILABLE
159#endif 159#endif
160#if defined (BUILD_MPU) 160#if defined (BUILD_MPU)
161 CSL_TIMER5_CFG_BASE, 161 (uint32_t)CSL_TIMER5_CFG_BASE,
162 CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER5_INTR_PEND_0, 162 (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER5_INTR_PEND_0,
163 TIMERP_EVENT_NOT_AVAILABLE 163 TIMERP_EVENT_NOT_AVAILABLE
164#endif 164#endif
165#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2) 165#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
166 CSL_TIMER5_CFG_BASE, 166 (uint32_t)CSL_TIMER5_CFG_BASE,
167 TIMERP_INTR_USER_CONFIGURE, /* User Confugure */ 167 (int32_t)TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
168 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */ 168 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
169#endif 169#endif
170 }, 170 },
@@ -172,18 +172,18 @@ TimerP_dmTimerDefault gDmTimerPInfoTbl[TimerP_numTimerDevices] = {
172 { 172 {
173 "DMTimer6", 173 "DMTimer6",
174#if defined (BUILD_MCU) 174#if defined (BUILD_MCU)
175 CSL_MCU_TIMER6_CFG_BASE, 175 (uint32_t)CSL_MCU_TIMER6_CFG_BASE,
176 CSLR_MCU_R5FSS0_CORE0_INTR_MCU_TIMER6_INTR_PEND_0, 176 (int32_t)CSLR_MCU_R5FSS0_CORE0_INTR_MCU_TIMER6_INTR_PEND_0,
177 TIMERP_EVENT_NOT_AVAILABLE 177 TIMERP_EVENT_NOT_AVAILABLE
178#endif 178#endif
179#if defined (BUILD_MPU) 179#if defined (BUILD_MPU)
180 CSL_TIMER6_CFG_BASE, 180 (uint32_t)CSL_TIMER6_CFG_BASE,
181 CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER6_INTR_PEND_0, 181 (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER6_INTR_PEND_0,
182 TIMERP_EVENT_NOT_AVAILABLE 182 TIMERP_EVENT_NOT_AVAILABLE
183#endif 183#endif
184#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2) 184#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
185 CSL_TIMER6_CFG_BASE, 185 (uint32_t)CSL_TIMER6_CFG_BASE,
186 TIMERP_INTR_USER_CONFIGURE, /* User Confugure */ 186 (int32_t)TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
187 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */ 187 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
188#endif 188#endif
189 }, 189 },
@@ -191,18 +191,18 @@ TimerP_dmTimerDefault gDmTimerPInfoTbl[TimerP_numTimerDevices] = {
191 { 191 {
192 "DMTimer7", 192 "DMTimer7",
193#if defined (BUILD_MCU) 193#if defined (BUILD_MCU)
194 CSL_MCU_TIMER7_CFG_BASE, 194 (uint32_t)CSL_MCU_TIMER7_CFG_BASE,
195 CSLR_MCU_R5FSS0_CORE0_INTR_MCU_TIMER7_INTR_PEND_0, 195 (int32_t)CSLR_MCU_R5FSS0_CORE0_INTR_MCU_TIMER7_INTR_PEND_0,
196 TIMERP_EVENT_NOT_AVAILABLE 196 TIMERP_EVENT_NOT_AVAILABLE
197#endif 197#endif
198#if defined (BUILD_MPU) 198#if defined (BUILD_MPU)
199 CSL_TIMER7_CFG_BASE, 199 (uint32_t)CSL_TIMER7_CFG_BASE,
200 CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER7_INTR_PEND_0, 200 (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER7_INTR_PEND_0,
201 TIMERP_EVENT_NOT_AVAILABLE 201 TIMERP_EVENT_NOT_AVAILABLE
202#endif 202#endif
203#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2) 203#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
204 CSL_TIMER7_CFG_BASE, 204 (uint32_t)CSL_TIMER7_CFG_BASE,
205 TIMERP_INTR_USER_CONFIGURE, /* User Confugure */ 205 (int32_t)TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
206 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */ 206 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
207#endif 207#endif
208 }, 208 },
@@ -210,18 +210,18 @@ TimerP_dmTimerDefault gDmTimerPInfoTbl[TimerP_numTimerDevices] = {
210 { 210 {
211 "DMTimer8", 211 "DMTimer8",
212#if defined (BUILD_MCU) 212#if defined (BUILD_MCU)
213 CSL_MCU_TIMER8_CFG_BASE, 213 (uint32_t)CSL_MCU_TIMER8_CFG_BASE,
214 CSLR_MCU_R5FSS0_CORE0_INTR_MCU_TIMER8_INTR_PEND_0, 214 (int32_t)CSLR_MCU_R5FSS0_CORE0_INTR_MCU_TIMER8_INTR_PEND_0,
215 TIMERP_EVENT_NOT_AVAILABLE 215 TIMERP_EVENT_NOT_AVAILABLE
216#endif 216#endif
217#if defined (BUILD_MPU) 217#if defined (BUILD_MPU)
218 CSL_TIMER8_CFG_BASE, 218 (uint32_t)CSL_TIMER8_CFG_BASE,
219 CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER8_INTR_PEND_0, 219 (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER8_INTR_PEND_0,
220 TIMERP_EVENT_NOT_AVAILABLE 220 TIMERP_EVENT_NOT_AVAILABLE
221#endif 221#endif
222#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2) 222#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
223 CSL_TIMER8_CFG_BASE, 223 (uint32_t)CSL_TIMER8_CFG_BASE,
224 TIMERP_INTR_USER_CONFIGURE, /* User Confugure */ 224 (int32_t)TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
225 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */ 225 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
226#endif 226#endif
227 }, 227 },
@@ -229,18 +229,18 @@ TimerP_dmTimerDefault gDmTimerPInfoTbl[TimerP_numTimerDevices] = {
229 { 229 {
230 "DMTimer9", 230 "DMTimer9",
231#if defined (BUILD_MCU) 231#if defined (BUILD_MCU)
232 CSL_MCU_TIMER9_CFG_BASE, 232 (uint32_t)CSL_MCU_TIMER9_CFG_BASE,
233 CSLR_MCU_R5FSS0_CORE0_INTR_MCU_TIMER9_INTR_PEND_0, 233 (int32_t)CSLR_MCU_R5FSS0_CORE0_INTR_MCU_TIMER9_INTR_PEND_0,
234 TIMERP_EVENT_NOT_AVAILABLE 234 TIMERP_EVENT_NOT_AVAILABLE
235#endif 235#endif
236#if defined (BUILD_MPU) 236#if defined (BUILD_MPU)
237 CSL_TIMER9_CFG_BASE, 237 (uint32_t)CSL_TIMER9_CFG_BASE,
238 CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER9_INTR_PEND_0, 238 (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER9_INTR_PEND_0,
239 TIMERP_EVENT_NOT_AVAILABLE 239 TIMERP_EVENT_NOT_AVAILABLE
240#endif 240#endif
241#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2) 241#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
242 CSL_TIMER9_CFG_BASE, 242 (uint32_t)CSL_TIMER9_CFG_BASE,
243 TIMERP_INTR_USER_CONFIGURE, /* User Confugure */ 243 (int32_t)TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
244 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */ 244 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
245#endif 245#endif
246 }, 246 },
@@ -249,17 +249,17 @@ TimerP_dmTimerDefault gDmTimerPInfoTbl[TimerP_numTimerDevices] = {
249 "DMTimer10", 249 "DMTimer10",
250#if defined (BUILD_MCU) 250#if defined (BUILD_MCU)
251 0U, 251 0U,
252 0U, 252 0,
253 TIMERP_EVENT_NOT_AVAILABLE 253 TIMERP_EVENT_NOT_AVAILABLE
254#endif 254#endif
255#if defined (BUILD_MPU) 255#if defined (BUILD_MPU)
256 CSL_TIMER10_CFG_BASE, 256 (uint32_t)CSL_TIMER10_CFG_BASE,
257 CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER10_INTR_PEND_0, 257 (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER10_INTR_PEND_0,
258 TIMERP_EVENT_NOT_AVAILABLE 258 TIMERP_EVENT_NOT_AVAILABLE
259#endif 259#endif
260#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2) 260#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
261 CSL_TIMER10_CFG_BASE, 261 (uint32_t)CSL_TIMER10_CFG_BASE,
262 TIMERP_INTR_USER_CONFIGURE, /* User Confugure */ 262 (int32_t)TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
263 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */ 263 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
264#endif 264#endif
265 }, 265 },
@@ -268,17 +268,17 @@ TimerP_dmTimerDefault gDmTimerPInfoTbl[TimerP_numTimerDevices] = {
268 "DMTimer11", 268 "DMTimer11",
269#if defined (BUILD_MCU) 269#if defined (BUILD_MCU)
270 0U, 270 0U,
271 0U, 271 0,
272 TIMERP_EVENT_NOT_AVAILABLE 272 TIMERP_EVENT_NOT_AVAILABLE
273#endif 273#endif
274#if defined (BUILD_MPU) 274#if defined (BUILD_MPU)
275 CSL_TIMER11_CFG_BASE, 275 (uint32_t)CSL_TIMER11_CFG_BASE,
276 CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER11_INTR_PEND_0, 276 (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER11_INTR_PEND_0,
277 TIMERP_EVENT_NOT_AVAILABLE 277 TIMERP_EVENT_NOT_AVAILABLE
278#endif 278#endif
279#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2) 279#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
280 CSL_TIMER11_CFG_BASE, 280 (uint32_t)CSL_TIMER11_CFG_BASE,
281 TIMERP_INTR_USER_CONFIGURE, /* User Confugure */ 281 (int32_t)TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
282 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */ 282 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
283#endif 283#endif
284 }, 284 },
@@ -287,17 +287,17 @@ TimerP_dmTimerDefault gDmTimerPInfoTbl[TimerP_numTimerDevices] = {
287 "DMTimer12", 287 "DMTimer12",
288#if defined (BUILD_MCU) 288#if defined (BUILD_MCU)
289 0U, 289 0U,
290 0U, 290 0,
291 TIMERP_EVENT_NOT_AVAILABLE 291 TIMERP_EVENT_NOT_AVAILABLE
292#endif 292#endif
293#if defined (BUILD_MPU) 293#if defined (BUILD_MPU)
294 CSL_TIMER12_CFG_BASE, 294 (uint32_t)CSL_TIMER12_CFG_BASE,
295 CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER12_INTR_PEND_0, 295 (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER12_INTR_PEND_0,
296 TIMERP_EVENT_NOT_AVAILABLE 296 TIMERP_EVENT_NOT_AVAILABLE
297#endif 297#endif
298#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2) 298#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
299 CSL_TIMER12_CFG_BASE, 299 (uint32_t)CSL_TIMER12_CFG_BASE,
300 TIMERP_INTR_USER_CONFIGURE, /* User Confugure */ 300 (int32_t)TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
301 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */ 301 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
302#endif 302#endif
303 }, 303 },
@@ -306,17 +306,17 @@ TimerP_dmTimerDefault gDmTimerPInfoTbl[TimerP_numTimerDevices] = {
306 "DMTimer13", 306 "DMTimer13",
307#if defined (BUILD_MCU) 307#if defined (BUILD_MCU)
308 0U, 308 0U,
309 0U, 309 0,
310 TIMERP_EVENT_NOT_AVAILABLE 310 TIMERP_EVENT_NOT_AVAILABLE
311#endif 311#endif
312#if defined (BUILD_MPU) 312#if defined (BUILD_MPU)
313 CSL_TIMER13_CFG_BASE, 313 (uint32_t)CSL_TIMER13_CFG_BASE,
314 CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER13_INTR_PEND_0, 314 (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER13_INTR_PEND_0,
315 TIMERP_EVENT_NOT_AVAILABLE 315 TIMERP_EVENT_NOT_AVAILABLE
316#endif 316#endif
317#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2) 317#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
318 CSL_TIMER13_CFG_BASE, 318 (uint32_t)CSL_TIMER13_CFG_BASE,
319 TIMERP_INTR_USER_CONFIGURE, /* User Confugure */ 319 (int32_t)TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
320 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */ 320 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
321#endif 321#endif
322 }, 322 },
@@ -325,17 +325,17 @@ TimerP_dmTimerDefault gDmTimerPInfoTbl[TimerP_numTimerDevices] = {
325 "DMTimer14", 325 "DMTimer14",
326#if defined (BUILD_MCU) 326#if defined (BUILD_MCU)
327 0U, 327 0U,
328 0U, 328 0,
329 TIMERP_EVENT_NOT_AVAILABLE 329 TIMERP_EVENT_NOT_AVAILABLE
330#endif 330#endif
331#if defined (BUILD_MPU) 331#if defined (BUILD_MPU)
332 CSL_TIMER14_CFG_BASE, 332 (uint32_t)CSL_TIMER14_CFG_BASE,
333 CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER14_INTR_PEND_0, 333 (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER14_INTR_PEND_0,
334 TIMERP_EVENT_NOT_AVAILABLE 334 TIMERP_EVENT_NOT_AVAILABLE
335#endif 335#endif
336#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2) 336#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
337 CSL_TIMER14_CFG_BASE, 337 (uint32_t)CSL_TIMER14_CFG_BASE,
338 TIMERP_INTR_USER_CONFIGURE, /* User Confugure */ 338 (int32_t)TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
339 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */ 339 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
340#endif 340#endif
341 }, 341 },
@@ -344,17 +344,17 @@ TimerP_dmTimerDefault gDmTimerPInfoTbl[TimerP_numTimerDevices] = {
344 "DMTimer15", 344 "DMTimer15",
345#if defined (BUILD_MCU) 345#if defined (BUILD_MCU)
346 0U, 346 0U,
347 0U, 347 0,
348 TIMERP_EVENT_NOT_AVAILABLE 348 TIMERP_EVENT_NOT_AVAILABLE
349#endif 349#endif
350#if defined (BUILD_MPU) 350#if defined (BUILD_MPU)
351 CSL_TIMER15_CFG_BASE, 351 (uint32_t)CSL_TIMER15_CFG_BASE,
352 CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER15_INTR_PEND_0, 352 (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER15_INTR_PEND_0,
353 TIMERP_EVENT_NOT_AVAILABLE 353 TIMERP_EVENT_NOT_AVAILABLE
354#endif 354#endif
355#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2) 355#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
356 CSL_TIMER15_CFG_BASE, 356 (uint32_t)CSL_TIMER15_CFG_BASE,
357 TIMERP_INTR_USER_CONFIGURE, /* User Confugure */ 357 (int32_t)TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
358 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */ 358 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
359#endif 359#endif
360 }, 360 },
@@ -363,17 +363,17 @@ TimerP_dmTimerDefault gDmTimerPInfoTbl[TimerP_numTimerDevices] = {
363 "DMTimer16", 363 "DMTimer16",
364#if defined (BUILD_MCU) 364#if defined (BUILD_MCU)
365 0U, 365 0U,
366 0U, 366 0,
367 TIMERP_EVENT_NOT_AVAILABLE 367 TIMERP_EVENT_NOT_AVAILABLE
368#endif 368#endif
369#if defined (BUILD_MPU) 369#if defined (BUILD_MPU)
370 CSL_TIMER16_CFG_BASE, 370 (uint32_t)CSL_TIMER16_CFG_BASE,
371 CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER16_INTR_PEND_0, 371 (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER16_INTR_PEND_0,
372 TIMERP_EVENT_NOT_AVAILABLE 372 TIMERP_EVENT_NOT_AVAILABLE
373#endif 373#endif
374#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2) 374#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
375 CSL_TIMER16_CFG_BASE, 375 (uint32_t)CSL_TIMER16_CFG_BASE,
376 TIMERP_INTR_USER_CONFIGURE, /* User Confugure */ 376 (int32_t)TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
377 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */ 377 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
378#endif 378#endif
379 }, 379 },
@@ -382,17 +382,17 @@ TimerP_dmTimerDefault gDmTimerPInfoTbl[TimerP_numTimerDevices] = {
382 "DMTimer17", 382 "DMTimer17",
383#if defined (BUILD_MCU) 383#if defined (BUILD_MCU)
384 0U, 384 0U,
385 0U, 385 0,
386 TIMERP_EVENT_NOT_AVAILABLE 386 TIMERP_EVENT_NOT_AVAILABLE
387#endif 387#endif
388#if defined (BUILD_MPU) 388#if defined (BUILD_MPU)
389 CSL_TIMER17_CFG_BASE, 389 (uint32_t)CSL_TIMER17_CFG_BASE,
390 CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER17_INTR_PEND_0, 390 (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER17_INTR_PEND_0,
391 TIMERP_EVENT_NOT_AVAILABLE 391 TIMERP_EVENT_NOT_AVAILABLE
392#endif 392#endif
393#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2) 393#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
394 CSL_TIMER17_CFG_BASE, 394 (uint32_t)CSL_TIMER17_CFG_BASE,
395 TIMERP_INTR_USER_CONFIGURE, /* User Confugure */ 395 (int32_t)TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
396 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */ 396 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
397#endif 397#endif
398 }, 398 },
@@ -401,17 +401,17 @@ TimerP_dmTimerDefault gDmTimerPInfoTbl[TimerP_numTimerDevices] = {
401 "DMTimer18", 401 "DMTimer18",
402#if defined (BUILD_MCU) 402#if defined (BUILD_MCU)
403 0U, 403 0U,
404 0U, 404 0,
405 TIMERP_EVENT_NOT_AVAILABLE 405 TIMERP_EVENT_NOT_AVAILABLE
406#endif 406#endif
407#if defined (BUILD_MPU) 407#if defined (BUILD_MPU)
408 CSL_TIMER18_CFG_BASE, 408 (uint32_t)CSL_TIMER18_CFG_BASE,
409 CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER18_INTR_PEND_0, 409 (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER18_INTR_PEND_0,
410 TIMERP_EVENT_NOT_AVAILABLE 410 TIMERP_EVENT_NOT_AVAILABLE
411#endif 411#endif
412#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2) 412#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
413 CSL_TIMER18_CFG_BASE, 413 (uint32_t)CSL_TIMER18_CFG_BASE,
414 TIMERP_INTR_USER_CONFIGURE, /* User Confugure */ 414 (int32_t)TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
415 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */ 415 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
416#endif 416#endif
417 }, 417 },
@@ -420,17 +420,17 @@ TimerP_dmTimerDefault gDmTimerPInfoTbl[TimerP_numTimerDevices] = {
420 "DMTimer19", 420 "DMTimer19",
421#if defined (BUILD_MCU) 421#if defined (BUILD_MCU)
422 0U, 422 0U,
423 0U, 423 0,
424 TIMERP_EVENT_NOT_AVAILABLE 424 TIMERP_EVENT_NOT_AVAILABLE
425#endif 425#endif
426#if defined (BUILD_MPU) 426#if defined (BUILD_MPU)
427 CSL_TIMER19_CFG_BASE, 427 (uint32_t)CSL_TIMER19_CFG_BASE,
428 CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER19_INTR_PEND_0, 428 (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER19_INTR_PEND_0,
429 TIMERP_EVENT_NOT_AVAILABLE 429 TIMERP_EVENT_NOT_AVAILABLE
430#endif 430#endif
431#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2) 431#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
432 CSL_TIMER19_CFG_BASE, 432 (uint32_t)CSL_TIMER19_CFG_BASE,
433 TIMERP_INTR_USER_CONFIGURE, /* User Confugure */ 433 (int32_t)TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
434 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */ 434 TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
435#endif 435#endif
436 } 436 }
@@ -464,14 +464,14 @@ void TimerP_updateDefaultInfoTbl(void)
464 for (i = 0U; i < TimerP_numTimerDevices; i++) 464 for (i = 0U; i < TimerP_numTimerDevices; i++)
465 { 465 {
466 gDmTimerPInfoTbl[i].baseAddr = ((uint32_t)CSL_TIMER0_CFG_BASE) + \ 466 gDmTimerPInfoTbl[i].baseAddr = ((uint32_t)CSL_TIMER0_CFG_BASE) + \
467 ((uint32_t)0x10000U) * i; 467 (((uint32_t)0x10000U) * i);
468 if (i < 12U) 468 if (i < 12U)
469 { 469 {
470 /* 470 /*
471 * The interrupt events of Main domain's DM Timer instance 0 - 11 are routed 471 * The interrupt events of Main domain's DM Timer instance 0 - 11 are routed
472 * by default through the MAIN_PULSARx Int Routers for connection to the R5 VIMs 472 * by default through the MAIN_PULSARx Int Routers for connection to the R5 VIMs
473 */ 473 */
474 gDmTimerPInfoTbl[i].intNum = CSLR_R5FSS0_INTROUTER0_IN_TIMER0_INTR_PEND_0 + i; 474 gDmTimerPInfoTbl[i].intNum = (int32_t)CSLR_R5FSS0_INTROUTER0_IN_TIMER0_INTR_PEND_0 + (int32_t)i;
475 } 475 }
476 else 476 else
477 { 477 {
@@ -479,7 +479,7 @@ void TimerP_updateDefaultInfoTbl(void)
479 * The interrupt events of Main domain's DM Timer instance 12 - 19 479 * The interrupt events of Main domain's DM Timer instance 12 - 19
480 * are directly connected to the MAIN Pulsar VIMs. 480 * are directly connected to the MAIN Pulsar VIMs.
481 */ 481 */
482 gDmTimerPInfoTbl[i].intNum = CSLR_R5FSS0_CORE0_INTR_TIMER12_INTR_PEND_0 + i - 12U; 482 gDmTimerPInfoTbl[i].intNum = (int32_t)CSLR_R5FSS0_CORE0_INTR_TIMER12_INTR_PEND_0 + (int32_t)i - 12;
483 } 483 }
484 } 484 }
485 } 485 }