summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat (limited to 'src/tirtos/Utils_tirtos.c')
-rwxr-xr-xsrc/tirtos/Utils_tirtos.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/src/tirtos/Utils_tirtos.c b/src/tirtos/Utils_tirtos.c
index 847d55f..277ab42 100755
--- a/src/tirtos/Utils_tirtos.c
+++ b/src/tirtos/Utils_tirtos.c
@@ -67,6 +67,7 @@ uint32_t gOsalHwiAllocCnt = 0U, gOsalHwiPeak = 0U;
67Osal_HwAttrs gOsal_HwAttrs = { 67Osal_HwAttrs gOsal_HwAttrs = {
68 OSAL_CPU_FREQ_KHZ_DEFAULT, 68 OSAL_CPU_FREQ_KHZ_DEFAULT,
69 EXTERNAL_CLOCK_KHZ_DEFAULT, 69 EXTERNAL_CLOCK_KHZ_DEFAULT,
70 OSAL_TARGET_PROC_MASK_DEFAULT,
70#ifdef _TMS320C6X 71#ifdef _TMS320C6X
71 /* ECM_intNum[]: Event combiner interrupts */ 72 /* ECM_intNum[]: Event combiner interrupts */
72 { OSAL_ECM_GROUP0_INT, /* Interrupt[4-15] to use for Event Combiner Group 0 */ 73 { OSAL_ECM_GROUP0_INT, /* Interrupt[4-15] to use for Event Combiner Group 0 */
@@ -191,6 +192,12 @@ int32_t Osal_setHwAttrs(uint32_t ctrlBitMap, const Osal_HwAttrs *hwAttrs)
191 ret = osal_OK; 192 ret = osal_OK;
192 } 193 }
193 194
195 /* Set the target processor list for routing the interrupt to specific core */
196 if (ctrlBitMap & OSAL_HWATTR_SET_TARG_PROC_LIST)
197 {
198 gOsal_HwAttrs.targetProcMask = hwAttrs->targetProcMask;
199 ret = osal_OK;
200 }
194 ret = osal_OK; 201 ret = osal_OK;
195 } 202 }
196 return(ret); 203 return(ret);