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authorAravind Batni2016-02-04 12:03:11 -0600
committerAravind Batni2016-02-04 12:03:11 -0600
commitbe727219f7d082e9f1c083ac116a87e2b907f84c (patch)
tree24d112edd7e8d85d2d4f1d5536d725f986b27b8c
parenta7ee60730f3ef46f1a7eb14df569cc6ebb507378 (diff)
downloadpa-lld-be727219f7d082e9f1c083ac116a87e2b907f84c.tar.gz
pa-lld-be727219f7d082e9f1c083ac116a87e2b907f84c.tar.xz
pa-lld-be727219f7d082e9f1c083ac116a87e2b907f84c.zip
fixed LUT2 FULL test issue for NSS_GEN2 and ver updates
-rw-r--r--example/emacExample/k2e/armv7/bios/PA_emacExample_K2EArmBiosExampleProject.txt24
-rw-r--r--example/emacExample/k2e/armv7/bios/cpsw_example_k2e.cfg145
-rw-r--r--example/emacExample/k2e/armv7/bios/singlecore_osal.c1095
-rw-r--r--example/emacExample/k2k/armv7/bios/PA_emacExample_K2KArmBiosExampleProject.txt24
-rw-r--r--example/emacExample/k2k/armv7/bios/cpsw_example_k2k.cfg145
-rw-r--r--example/emacExample/k2k/armv7/bios/singlecore_osal.c1095
-rw-r--r--example/emacExample/k2l/armv7/bios/PA_emacExample_K2LArmBiosExampleProject.txt24
-rw-r--r--example/emacExample/k2l/armv7/bios/cpsw_example_k2l.cfg145
-rw-r--r--example/emacExample/k2l/armv7/bios/singlecore_osal.c1095
-rw-r--r--fw/v0/pm_config.h2
-rw-r--r--[-rwxr-xr-x]fw/v1/pm_config.h2
-rw-r--r--paver.h4
-rw-r--r--[-rwxr-xr-x]test/PAUnitTest/src/tests/test16pkts.h2
13 files changed, 3797 insertions, 5 deletions
diff --git a/example/emacExample/k2e/armv7/bios/PA_emacExample_K2EArmBiosExampleProject.txt b/example/emacExample/k2e/armv7/bios/PA_emacExample_K2EArmBiosExampleProject.txt
new file mode 100644
index 0000000..8fed299
--- /dev/null
+++ b/example/emacExample/k2e/armv7/bios/PA_emacExample_K2EArmBiosExampleProject.txt
@@ -0,0 +1,24 @@
1-ccs.linkFile "PASS_INSTALL_PATH/ti/drv/pa/example/emacExample/src/cpsw_singlecore.c"
2-ccs.linkFile "PASS_INSTALL_PATH/ti/drv/pa/example/emacExample/src/pa_mgmt.c"
3-ccs.linkFile "PASS_INSTALL_PATH/ti/drv/pa/example/emacExample/src/cppi_qmss_mgmt.c"
4-ccs.linkFile "PASS_INSTALL_PATH/ti/drv/pa/example/emacExample/src/setuprm.c"
5-ccs.linkFile "PASS_INSTALL_PATH/ti/drv/pa/example/emacExample/src/view_ale_table.c"
6-ccs.linkFile "PASS_INSTALL_PATH/ti/drv/pa/example/emacExample/src/armv7/bios/framework.c"
7-ccs.linkFile "PASS_INSTALL_PATH/ti/drv/pa/example/emacExample/src/armv7/bios/fw_main.c"
8-ccs.linkFile "PASS_INSTALL_PATH/ti/drv/pa/example/emacExample/src/armv7/bios/cpsw_mgmt.c"
9-ccs.linkFile "PASS_INSTALL_PATH/ti/drv/pa/example/emacExample/k2e/armv7/bios/singlecore_osal.c"
10-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/device/k2e/policy_dsp-only.c"
11-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/device/k2e/policy_dsp_arm.c"
12-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/device/k2e/global-resource-list.c"
13-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/cppi/device/k2e/src/cppi_device.c"
14-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/qmss/device/k2e/src/qmss_device.c"
15-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/pa/device/k2e/src/nss_device.c"
16-ccs.linkFile "PDK_INSTALL_PATH/ti/csl/src/ip/sgmii/V0/csl_cpsgmii.c"
17-ccs.linkFile "PDK_INSTALL_PATH/ti/csl/src/ip/cpsw/V0/csl_cpsw_5gf.c"
18-ccs.linkFile "PDK_INSTALL_PATH/ti/csl/src/ip/serdes_sb/V0/csl_wiz8_sb_refclk125MHz_10bit_5Gbps.c"
19-ccs.linkFile "PDK_INSTALL_PATH/ti/csl/src/ip/serdes_sb/V0/csl_wiz8_sb_refclk125MHz_20bit_6p25Gbps.c"
20-ccs.linkFile "PDK_INSTALL_PATH/ti/csl/src/ip/serdes_sb/V0/csl_wiz8_sb_refclk156p25MHz_10bit_5Gbps.c"
21-ccs.linkFile "PDK_INSTALL_PATH/ti/csl/src/ip/serdes_sb/V0/csl_wiz8_sb_refclk156p25MHz_20bit_6p25Gbps.c"
22-ccs.linkFile "PASS_INSTALL_PATH/ti/drv/pa/example/emacExample/k2e/armv7/bios/cpsw_example_k2l.cfg"
23-ccs.setCompilerOptions "-c -mcpu=cortex-a15 -mtune=cortex-a15 -marm -mfloat-abi=hard -DSOC_K2E -DNSS_GEN2 -DNUM_PORTS=5 -D_LITTLE_ENDIAN=1 -g -gstrict-dwarf -Wall -MMD -MP -I${PDK_INSTALL_PATH} -I${PDK_INSTALL_PATH}/ti/drv/pa/example/emacExample/src -I${PASS_INSTALL_PATH}/ti/drv/pa/example/emacExample/src/armv7/bios -I${PDK_INSTALL_PATH}/ti/drv/cppi -I${PDK_INSTALL_PATH}/ti/drv/qmss" -rtsc.enableRtsc
24-ccs.setLinkerOptions " -lrdimon -lgcc -lm -lnosys -nostartfiles -static -Wl,--gc-sections -L$(XDCTOOLS)/packages/gnu/targets/arm/libs/install-native/arm-none-eabi/lib/fpu "
diff --git a/example/emacExample/k2e/armv7/bios/cpsw_example_k2e.cfg b/example/emacExample/k2e/armv7/bios/cpsw_example_k2e.cfg
new file mode 100644
index 0000000..1377af6
--- /dev/null
+++ b/example/emacExample/k2e/armv7/bios/cpsw_example_k2e.cfg
@@ -0,0 +1,145 @@
1/*
2 * Copyright 2015 by Texas Instruments Incorporated.
3 *
4 * All rights reserved. Property of Texas Instruments Incorporated.
5 * Restricted rights to use, duplicate or disclose this code are
6 * granted through contract.
7 *
8 */
9
10/*
11 * ======== cpsw_example.cfg ========
12 *
13 */
14
15/* Load all required BIOS/XDC runtime packages */
16var Memory = xdc.useModule('xdc.runtime.Memory');
17var BIOS = xdc.useModule('ti.sysbios.BIOS');
18var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
19var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
20var Log = xdc.useModule('xdc.runtime.Log');
21var LoggerBuf = xdc.useModule('xdc.runtime.LoggerBuf');
22var Task = xdc.useModule('ti.sysbios.knl.Task');
23var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');
24var Main = xdc.useModule('xdc.runtime.Main');
25var Defaults = xdc.useModule('xdc.runtime.Defaults');
26var Diags = xdc.useModule('xdc.runtime.Diags');
27var SysMin = xdc.useModule('xdc.runtime.SysMin');
28var System = xdc.useModule('xdc.runtime.System');
29var Text = xdc.useModule('xdc.runtime.Text');
30
31Task.defaultStackSize = 0x4000;
32
33/* Load the CPPI package */
34var Cppi = xdc.loadPackage('ti.drv.cppi');
35/* Load the QMSS package */
36var Qmss = xdc.loadPackage('ti.drv.qmss');
37
38/* Load the PA package */
39var devType = "k2e"
40var Pa = xdc.useModule('ti.drv.pa.Settings');
41Pa.deviceType = devType;
42
43/* Load the RM package */
44var Rm = xdc.loadPackage('ti.drv.rm');
45
46/*
47 * Program.argSize sets the size of the .args section.
48 * The examples don't use command line args so argSize is set to 0.
49 */
50Program.argSize = 0x0;
51
52/*
53 * The BIOS module will create the default heap for the system.
54 * Specify the size of this default heap.
55 */
56BIOS.heapSize = 8192 * 30;
57
58/*
59 * Build a custom SYS/BIOS library from sources.
60 */
61BIOS.libType = BIOS.LibType_Custom;
62
63/* System stack size (used by ISRs and Swis) */
64Program.stack = 0x20000;
65
66/* Circular buffer size for System_printf() */
67SysMin.bufSize = 0x400;
68
69/*
70 * Create and install logger for the whole system
71 */
72var loggerBufParams = new LoggerBuf.Params();
73loggerBufParams.numEntries = 32;
74var logger0 = LoggerBuf.create(loggerBufParams);
75Defaults.common$.logger = logger0;
76Main.common$.diags_INFO = Diags.ALWAYS_ON;
77
78System.SupportProxy = SysMin;
79var SemiHost = xdc.useModule('ti.sysbios.rts.gnu.SemiHostSupport');
80
81var Cache = xdc.useModule('ti.sysbios.family.arm.a15.Cache');
82var Mmu = xdc.useModule('ti.sysbios.family.arm.a15.Mmu');
83
84/* Enable the cache */
85Cache.enableCache = true;
86
87// Enable the MMU (Required for L1/L2 data caching)
88Mmu.enableMMU = true;
89
90// descriptor attribute structure
91var peripheralAttrs = new Mmu.DescriptorAttrs();
92
93Mmu.initDescAttrsMeta(peripheralAttrs);
94
95peripheralAttrs.type = Mmu.DescriptorType_BLOCK; // BLOCK descriptor
96peripheralAttrs.noExecute = true; // not executable
97peripheralAttrs.accPerm = 0; // read/write at PL1
98peripheralAttrs.attrIndx = 1; // MAIR0 Byte1 describes
99 // memory attributes for
100// Define the base address of the 2 MB page
101// the peripheral resides in.
102var peripheralBaseAddrs = [
103 { base: 0x02620000, size: 0x00001000 }, // bootcfg
104 { base: 0x0bc00000, size: 0x00100000 }, // MSMC config
105 { base: 0x26000000, size: 0x01000000 }, // NETCP memory
106 { base: 0x02a00000, size: 0x00100000 }, // QMSS config memory
107 { base: 0x23A00000, size: 0x00100000 }, // QMSS Data memory
108 { base: 0x02901000, size: 0x00002000 }, // SRIO pkt dma config memory
109 { base: 0x01f14000, size: 0x00007000 }, // AIF pkt dma config memory
110 { base: 0x021F0200, size: 0x00000600 }, // FFTC 0 pkt dma config memory
111 { base: 0x021F0a00, size: 0x00000600 }, // FFTC 4 pkt dma config memory
112 { base: 0x021F1200, size: 0x00000600 }, // FFTC 5 pkt dma config memory
113 { base: 0x021F4200, size: 0x00000600 }, // FFTC 1 pkt dma config memory
114 { base: 0x021F8200, size: 0x00000600 }, // FFTC 2 pkt dma config memory
115 { base: 0x021FC200, size: 0x00000600 }, // FFTC 3 pkt dma config memory
116 { base: 0x02554000, size: 0x00009000 } // BCP pkt dma config memory
117];
118
119// Configure the corresponding MMU page descriptor accordingly
120for (var i =0; i < peripheralBaseAddrs.length; i++)
121{
122 for (var j = 0; j < peripheralBaseAddrs[i].size; j += 0x200000)
123 {
124 var addr = peripheralBaseAddrs[i].base + j;
125 Mmu.setSecondLevelDescMeta(addr, addr, peripheralAttrs);
126 }
127}
128
129// Reconfigure DDR to use coherent address
130Mmu.initDescAttrsMeta(peripheralAttrs);
131
132peripheralAttrs.type = Mmu.DescriptorType_BLOCK;
133peripheralAttrs.shareable = 2; // outer-shareable (3=inner, 0=none)
134peripheralAttrs.accPerm = 1; // read/write at any privelege level
135peripheralAttrs.attrIndx = 2; // normal cacheable (0=no cache, 1=strict order)
136for (var vaddr = 0x80000000, paddr = 0x800000000; vaddr < 0x100000000; vaddr += 0x200000, paddr+= 0x200000)
137{
138 Mmu.setSecondLevelDescMeta(vaddr, paddr, peripheralAttrs);
139}
140// Add MSMC as coherent
141for (var addr = 0x0c000000; addr < 0x0c600000; addr += 0x200000)
142{
143 Mmu.setSecondLevelDescMeta(addr, addr, peripheralAttrs);
144}
145
diff --git a/example/emacExample/k2e/armv7/bios/singlecore_osal.c b/example/emacExample/k2e/armv7/bios/singlecore_osal.c
new file mode 100644
index 0000000..5f4353d
--- /dev/null
+++ b/example/emacExample/k2e/armv7/bios/singlecore_osal.c
@@ -0,0 +1,1095 @@
1/**
2 * @file singlecore_osal.c
3 *
4 * @brief
5 * This is a sample OS Abstraction Layer (AL) file implemented
6 * using XDC/BIOS APIs.
7 *
8 * System integrator is advised to review these implementations and
9 * modify them to suit it to application requirements.
10 *
11 * This OSAL implementation uses the <b> Approach 1 </b> documented.
12 *
13 * \par
14 * ============================================================================
15 * @n (C) Copyright 2009, Texas Instruments, Inc.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
19 * are met:
20 *
21 * Redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer.
23 *
24 * Redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the
27 * distribution.
28 *
29 * Neither the name of Texas Instruments Incorporated nor the names of
30 * its contributors may be used to endorse or promote products derived
31 * from this software without specific prior written permission.
32 *
33 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
34 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
35 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
36 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
37 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
38 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
39 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
40 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
41 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
42 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
43 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 *
45*/
46/* Standard C-native includes */
47#include <stdlib.h>
48#include <string.h>
49
50/* XDC/BIOS includes */
51#include <xdc/std.h>
52#include <xdc/runtime/IHeap.h>
53#include <xdc/runtime/System.h>
54#include <xdc/runtime/Memory.h>
55#include <xdc/runtime/Error.h>
56
57#include <ti/sysbios/BIOS.h>
58#include <ti/sysbios/hal/Hwi.h>
59#include <ti/sysbios/knl/Task.h>
60#include <ti/sysbios/knl/Semaphore.h>
61#include <ti/sysbios/heaps/HeapBuf.h>
62#include <ti/sysbios/heaps/HeapMem.h>
63
64#include <xdc/cfg/global.h>
65
66/* CSL CHIP, SEM Functional layer includes */
67#include <ti/csl/csl_chip.h>
68#include <ti/csl/csl_semAux.h>
69
70#ifdef _TMS320C6X
71/* CSL Cache module includes */
72#include <ti/csl/csl_cacheAux.h>
73/* CSL XMC module includes */
74#include <ti/csl/csl_xmcAux.h>
75#endif
76
77/**********************************************************************
78 ****************************** Defines *******************************
79 **********************************************************************/
80
81#define MAX_NUM_CORES 8
82
83/* Hardware Semaphore to synchronize access from
84 * multiple applications (PA applications and non-PASS applications)
85 * across different cores to the QMSS library.
86 */
87#define QMSS_HW_SEM 3
88
89/* Hardware Semaphore to synchronize access from
90 * multiple applications (PASS applications and non-PASS applications)
91 * across different cores to the CPPI library.
92 */
93#define CPPI_HW_SEM 4
94
95/* Hardware Semaphore to synchronize access from
96 * multiple applications (PASS applications and non-PASS applications)
97 * across different cores to the PA library.
98 */
99#define PA_HW_SEM 5
100
101#undef L2_CACHE
102#ifdef L2_CACHE
103 /* Invalidate L2 cache. This should invalidate L1D as well.
104 * Wait until operation is complete. */
105#define SYS_CACHE_INV(addr, size, code) CACHE_invL2 (addr, size, code)
106
107 /* Writeback L2 cache. This should Writeback L1D as well.
108 * Wait until operation is complete. */
109#define SYS_CACHE_WB(addr, size, code) CACHE_wbL2 (addr, size, code)
110
111#else
112 /* Invalidate L1D cache and wait until operation is complete.
113 * Use this approach if L2 cache is not enabled */
114#define SYS_CACHE_INV(addr, size, code) CACHE_invL1d (addr, size, code)
115 /* Writeback L1D cache and wait until operation is complete.
116 * Use this approach if L2 cache is not enabled */
117#define SYS_CACHE_WB(addr, size, code) CACHE_wbL1d (addr, size, code)
118
119#endif
120
121/**
122 * @b Description
123 * @n
124 * General Memory Barrier guarantees that all LOAD and STORE operations that were issued before the
125 * barrier occur before the LOAD and STORE operations issued after the barrier
126 *
127 */
128static inline void memBarrier(void) {__sync_synchronize();}
129
130/**********************************************************************
131 ************************** Global Variables **************************
132 **********************************************************************/
133UInt32 cpswCppiMallocCounter = 0;
134UInt32 cpswCppiFreeCounter = 0;
135UInt32 cpswQmssMallocCounter = 0;
136UInt32 cpswQmssFreeCounter = 0;
137uint32_t rmMallocCounter = 0;
138uint32_t rmFreeCounter = 0;
139UInt32 coreKey [MAX_NUM_CORES];
140
141/**********************************************************************
142 *********************** CPPI OSAL Functions **************************
143 **********************************************************************/
144
145/**
146 * ============================================================================
147 * @n@b Osal_cppiCsEnter
148 *
149 * @b brief
150 * @n This API ensures multi-core and multi-threaded
151 * synchronization to the caller.
152 *
153 * This is a BLOCKING API.
154 *
155 * This API ensures multi-core synchronization between
156 * multiple processes trying to access CPPI shared
157 * library at the same time.
158 *
159 * @param[in]
160 * @n None
161 *
162 * @return
163 * @n Handle used to lock critical section
164 * =============================================================================
165 */
166Ptr Osal_cppiCsEnter (Void)
167{
168#ifdef _TMS320C6X
169 uint32_t coreNum = CSL_chipReadReg (CSL_CHIP_DNUM);
170#else
171 uint32_t coreNum = 0;
172#endif
173 /* Get the hardware semaphore.
174 *
175 * Acquire Multi core CPPI synchronization lock
176 */
177 while ((CSL_semAcquireDirect (CPPI_HW_SEM)) == 0);
178
179 /* Disable all interrupts and OS scheduler.
180 *
181 * Acquire Multi threaded / process synchronization lock.
182 */
183 coreKey [coreNum] = Hwi_disable();
184
185 return NULL;
186}
187
188/**
189 * ============================================================================
190 * @n@b Osal_cppiCsExit
191 *
192 * @b brief
193 * @n This API needs to be called to exit a previously
194 * acquired critical section lock using @a Osal_cppiCsEnter ()
195 * API. It resets the multi-core and multi-threaded lock,
196 * enabling another process/core to grab CPPI access.
197 *
198 * @param[in] CsHandle
199 * Handle for unlocking critical section.
200 *
201 * @return None
202 * =============================================================================
203 */
204Void Osal_cppiCsExit (Ptr CsHandle)
205{
206#ifdef _TMS320C6X
207 uint32_t coreNum = CSL_chipReadReg (CSL_CHIP_DNUM);
208#else
209 uint32_t coreNum = 0;
210#endif
211 /* Enable all interrupts and enables the OS scheduler back on.
212 *
213 * Release multi-threaded / multi-process lock on this core.
214 */
215 Hwi_restore(coreKey [coreNum]);
216
217 /* Release the hardware semaphore
218 *
219 * Release multi-core lock.
220 */
221 CSL_semReleaseSemaphore (CPPI_HW_SEM);
222
223 return;
224}
225
226/**
227 * ============================================================================
228 * @n@b Osal_cppiMalloc
229 *
230 * @b brief
231 * @n This API allocates a memory block of a given
232 * size specified by input parameter 'num_bytes'.
233 *
234 * This API should allocate memory from shared memory if the test applications
235 * are to be run on multiple cores.
236 *
237 * @param[in] num_bytes
238 * Number of bytes to be allocated.
239 *
240 * @return
241 * Allocated block address
242 * =============================================================================
243 */
244Ptr Osal_cppiMalloc (UInt32 num_bytes)
245{
246 Error_Block errorBlock;
247
248 /* Increment the allocation counter. */
249 cpswCppiMallocCounter++;
250
251 /* Allocate memory. */
252 return Memory_alloc(NULL, num_bytes, 0, &errorBlock);
253}
254
255/**
256 * ============================================================================
257 * @n@b Osal_cppiFree
258 *
259 * @b brief
260 * @n This API frees and restores a given memory location
261 * pointer 'dataPtr' of size 'num_bytes' to its
262 * original heap location. Frees up memory allocated using
263 * @a Osal_cppiMalloc ()
264 *
265 * @param[in] dataPtr
266 * Pointer to the memory block to be cleaned up.
267 *
268 * @param[in] num_bytes
269 * Size of the memory block to be cleaned up.
270 *
271 * @return
272 * Not Applicable
273 * =============================================================================
274 */
275Void Osal_cppiFree (Ptr dataPtr, UInt32 num_bytes)
276{
277 /* Increment the free counter. */
278 cpswCppiFreeCounter++;
279
280 /* Free up the memory */
281 if (dataPtr)
282 {
283 /* Convert the global address to local address since
284 * thats what the heap understands.
285 */
286 Memory_free(NULL, dataPtr, num_bytes);
287 }
288}
289
290/**
291 * @b Description
292 * @n
293 * The function is used to indicate that a block of memory is
294 * about to be accessed. If the memory block is cached then this
295 * indicates that the application would need to ensure that the
296 * cache is updated with the data from the actual memory.
297 *
298 * @param[in] blockPtr
299 * Address of the block which is to be invalidated
300 *
301 * @param[in] size
302 * Size of the block to be invalidated
303
304 * @retval
305 * Not Applicable
306 */
307void Osal_cppiBeginMemAccess (void *blockPtr, uint32_t size)
308{
309#ifdef _TMS320C6X
310 uint32_t key;
311
312 /* Disable Interrupts */
313 key = Hwi_disable();
314
315 /* Cleanup the prefetch buffer also. */
316 CSL_XMC_invalidatePrefetchBuffer();
317
318 SYS_CACHE_INV (blockPtr, size, CACHE_FENCE_WAIT);
319
320 asm (" nop 4");
321 asm (" nop 4");
322 asm (" nop 4");
323 asm (" nop 4");
324
325 /* Reenable Interrupts. */
326 Hwi_restore(key);
327#endif
328 return;
329}
330
331/**
332 * @b Description
333 * @n
334 * The function is used to indicate that the block of memory has
335 * finished being accessed. If the memory block is cached then the
336 * application would need to ensure that the contents of the cache
337 * are updated immediately to the actual memory.
338 *
339 * @param[in] blockPtr
340 * Address of the block which is to be written back
341 *
342 * @param[in] size
343 * Size of the block to be written back
344
345 * @retval
346 * Not Applicable
347 */
348void Osal_cppiEndMemAccess (void *blockPtr, uint32_t size)
349{
350#ifdef _TMS320C6X
351 uint32_t key;
352
353 /* Disable Interrupts */
354 key = Hwi_disable();
355
356 SYS_CACHE_WB (blockPtr, size, CACHE_FENCE_WAIT);
357
358 asm (" nop 4");
359 asm (" nop 4");
360 asm (" nop 4");
361 asm (" nop 4");
362
363 /* Reenable Interrupts. */
364 Hwi_restore(key);
365#endif
366 return;
367}
368
369/**********************************************************************
370 *********************** QMSS OSAL Functions **************************
371 **********************************************************************/
372
373/**
374 * ============================================================================
375 * @n@b Osal_qmssCsEnter
376 *
377 * @b brief
378 * @n This API ensures multi-core and multi-threaded
379 * synchronization to the caller.
380 *
381 * This is a BLOCKING API.
382 *
383 * This API ensures multi-core synchronization between
384 * multiple processes trying to access QMSS shared
385 * library at the same time.
386 *
387 * @param[in] None
388 *
389 * @return
390 * Handle used to lock critical section
391 * =============================================================================
392 */
393Ptr Osal_qmssCsEnter (Void)
394{
395#ifdef _TMS320C6X
396 uint32_t coreNum = CSL_chipReadReg (CSL_CHIP_DNUM);
397#else
398 uint32_t coreNum = 0;
399#endif
400 /* Get the hardware semaphore.
401 *
402 * Acquire Multi core QMSS synchronization lock
403 */
404 while ((CSL_semAcquireDirect (QMSS_HW_SEM)) == 0);
405
406 /* Disable all interrupts and OS scheduler.
407 *
408 * Acquire Multi threaded / process synchronization lock.
409 */
410 coreKey [coreNum] = Hwi_disable();
411
412 return NULL;
413}
414
415/**
416 * ============================================================================
417 * @n@b Osal_qmssCsExit
418 *
419 * @b brief
420 * @n This API needs to be called to exit a previously
421 * acquired critical section lock using @a Osal_cpswQmssCsEnter ()
422 * API. It resets the multi-core and multi-threaded lock,
423 * enabling another process/core to grab QMSS access.
424 *
425 * @param[in] CsHandle
426 * Handle for unlocking critical section.
427 *
428 * @return None
429 * =============================================================================
430 */
431Void Osal_qmssCsExit (Ptr CsHandle)
432{
433#ifdef _TMS320C6X
434 uint32_t coreNum = CSL_chipReadReg (CSL_CHIP_DNUM);
435#else
436 uint32_t coreNum = 0;
437#endif
438 /* Enable all interrupts and enables the OS scheduler back on.
439 *
440 * Release multi-threaded / multi-process lock on this core.
441 */
442 Hwi_restore(coreKey [coreNum]);
443
444 /* Release the hardware semaphore
445 *
446 * Release multi-core lock.
447 */
448 CSL_semReleaseSemaphore (QMSS_HW_SEM);
449
450 return;
451}
452
453 /**
454 * ============================================================================
455 * @n@b Osal_qmssAccCsEnter
456 *
457 * @b brief
458 * @n This API ensures multi-core and multi-threaded
459 * synchronization to the caller.
460 *
461 * This is a BLOCKING API.
462 *
463 * This API ensures multi-core synchronization between
464 * multiple processes trying to access QMSS shared
465 * library at the same time.
466 *
467 * @param[in] None
468 *
469 * @return
470 * Handle used to lock critical section
471 * =============================================================================
472 */
473Ptr Osal_qmssAccCsEnter (Void)
474{
475 /* This is a suboptimal implementation for this OSAL, please refer to
476 * QMSS examples for optimal implementation of this function
477 */
478
479 return (Osal_qmssCsEnter());
480}
481
482/**
483 * ============================================================================
484 * @n@b Osal_qmssAccCsExit
485 *
486 * @b brief
487 * @n This API needs to be called to exit a previously
488 * acquired critical section lock using @a Osal_qmssAccCsEnter ()
489 * API. It resets the multi-core and multi-threaded lock,
490 * enabling another process/core to grab QMSS access.
491 *
492 * @param[in] CsHandle
493 * Handle for unlocking critical section.
494 *
495 * @return None
496 * =============================================================================
497 */
498Void Osal_qmssAccCsExit (Ptr CsHandle)
499{
500 /* This is a suboptimal implementation for this OSAL, please refer to
501 * QMSS examples for optimal implementation of this function
502 */
503 Osal_qmssCsExit(CsHandle);
504 return;
505}
506/**
507 * ============================================================================
508 * @n@b Osal_qmssMtCsEnter
509 *
510 * @b brief
511 * @n This API ensures ONLY multi-threaded
512 * synchronization to the QMSS user.
513 *
514 * This is a BLOCKING API.
515 *
516 * @param[in] None
517 *
518 * @return
519 * Handle used to lock critical section
520 * =============================================================================
521 */
522Ptr Osal_qmssMtCsEnter (Void)
523{
524 /* Disable all interrupts and OS scheduler.
525 *
526 * Acquire Multi threaded / process synchronization lock.
527 */
528 //coreKey [CSL_chipReadReg (CSL_CHIP_DNUM)] = Hwi_disable();
529
530 return NULL;
531}
532
533/**
534 * ============================================================================
535 * @n@b Osal_qmssMtCsExit
536 *
537 * @b brief
538 * @n This API needs to be called to exit a previously
539 * acquired critical section lock using @a Osal_cpswQmssMtCsEnter ()
540 * API. It resets the multi-threaded lock, enabling another process
541 * on the current core to grab it.
542 *
543 * @param[in] CsHandle
544 * Handle for unlocking critical section.
545 *
546 * @return None
547 * =============================================================================
548 */
549Void Osal_qmssMtCsExit (Ptr CsHandle)
550{
551 /* Enable all interrupts and enables the OS scheduler back on.
552 *
553 * Release multi-threaded / multi-process lock on this core.
554 */
555 //Hwi_restore(key);
556
557 return;
558}
559
560/**
561 * ============================================================================
562 * @n@b Osal_qmssMalloc
563 *
564 * @b brief
565 * @n This API allocates a memory block of a given
566 * size specified by input parameter 'num_bytes'.
567 *
568 * @param[in] num_bytes
569 * Number of bytes to be allocated.
570 *
571 * @return
572 * Allocated block address
573 * =============================================================================
574 */
575Ptr Osal_qmssMalloc (UInt32 num_bytes)
576{
577 Error_Block errorBlock;
578
579 /* Increment the allocation counter. */
580 cpswQmssMallocCounter++;
581
582 /* Allocate memory. */
583 return Memory_alloc(NULL, num_bytes, 0, &errorBlock);
584}
585
586/**
587 * ============================================================================
588 * @n@b Osal_qmssFree
589 *
590 * @b brief
591 * @n This API frees and restores a given memory location
592 * pointer 'dataPtr' of size 'num_bytes' to its
593 * original heap location. Frees up memory allocated using
594 * @a Osal_qmssMalloc ()
595 *
596 * @param[in] dataPtr
597 * Pointer to the memory block to be cleaned up.
598 *
599 * @param[in] num_bytes
600 * Size of the memory block to be cleaned up.
601 *
602 * @return
603 * Not Applicable
604 * =============================================================================
605 */
606Void Osal_qmssFree (Ptr dataPtr, UInt32 num_bytes)
607{
608 /* Increment the free counter. */
609 cpswQmssFreeCounter++;
610
611 /* Free up the memory */
612 if (dataPtr)
613 {
614 /* Convert the global address to local address since
615 * thats what the heap understands.
616 */
617 Memory_free(NULL, dataPtr, num_bytes);
618 }
619}
620
621/**
622 * @b Description
623 * @n
624 * The function is used to indicate that a block of memory is
625 * about to be accessed. If the memory block is cached then this
626 * indicates that the application would need to ensure that the
627 * cache is updated with the data from the actual memory.
628 *
629 * @param[in] blockPtr
630 * Address of the block which is to be invalidated
631 *
632 * @param[in] size
633 * Size of the block to be invalidated
634
635 * @retval
636 * Not Applicable
637 */
638void Osal_qmssBeginMemAccess (void *blockPtr, uint32_t size)
639{
640#ifdef _TMS320C6X
641 uint32_t key;
642
643 /* Disable Interrupts */
644 key = Hwi_disable();
645
646 /* Cleanup the prefetch buffer also. */
647 CSL_XMC_invalidatePrefetchBuffer();
648
649 SYS_CACHE_INV (blockPtr, size, CACHE_FENCE_WAIT);
650
651 asm (" nop 4");
652 asm (" nop 4");
653 asm (" nop 4");
654 asm (" nop 4");
655
656 /* Reenable Interrupts. */
657 Hwi_restore(key);
658#endif
659 return;
660}
661
662/**
663 * @b Description
664 * @n
665 * The function is used to indicate that the block of memory has
666 * finished being accessed. If the memory block is cached then the
667 * application would need to ensure that the contents of the cache
668 * are updated immediately to the actual memory.
669 *
670 * @param[in] blockPtr
671 * Address of the block which is to be written back
672 *
673 * @param[in] size
674 * Size of the block to be written back
675
676 * @retval
677 * Not Applicable
678 */
679void Osal_qmssEndMemAccess (void *blockPtr, uint32_t size)
680{
681#ifdef _TMS320C6X
682 uint32_t key;
683
684 /* Disable Interrupts */
685 key = Hwi_disable();
686
687 SYS_CACHE_WB (blockPtr, size, CACHE_FENCE_WAIT);
688
689 asm (" nop 4");
690 asm (" nop 4");
691 asm (" nop 4");
692 asm (" nop 4");
693
694 /* Reenable Interrupts. */
695 Hwi_restore(key);
696#endif
697 return;
698}
699
700/******************************************************************************
701* Function to issue memory barrier
702*
703* NOTE: QMSS unit tests are not using CPPI descriptors
704******************************************************************************/
705void* Osal_qmssMemBarrier(uint32_t QID, void *descAddr)
706{
707 /* Issue memory barrier */
708 memBarrier();
709 return descAddr;
710}
711
712/**********************************************************************
713 *********************** PASS OSAL Functions **************************
714 **********************************************************************/
715
716/**
717 * @brief This macro is used to alert the application that the PA is
718 * going to access table memory. The application must ensure
719 * cache coherency
720 *
721 *
722 * <b> Prototype: </b>
723 * The following is the C prototype for the expected OSAL API.
724 *
725 * @verbatim
726 void Osal_paBeginMemAccess (void* addr, uint32_t sizeWords)
727 @endverbatim
728 *
729 * <b> Parameters </b>
730 * @n The address of the table to be accessed
731 * @n The number of bytes in the table
732 *
733 * @note PA will make nested calls to this function for memory access
734 * protection of different memory tables.
735 */
736
737void Osal_paBeginMemAccess (Ptr addr, UInt32 size)
738{
739#ifdef _TMS320C6X
740 uint32_t key;
741
742 /* Disable Interrupts */
743 key = Hwi_disable();
744
745 /* Cleanup the prefetch buffer also. */
746 CSL_XMC_invalidatePrefetchBuffer();
747
748 SYS_CACHE_INV (addr, size, CACHE_FENCE_WAIT);
749
750 asm (" nop 4");
751 asm (" nop 4");
752 asm (" nop 4");
753 asm (" nop 4");
754
755 /* Reenable Interrupts. */
756 Hwi_restore(key);
757#endif
758}
759
760/**
761 * @brief This macro is used to alert the application that the PA
762 * has completed access to table memory. This call will always
763 * be made following a call to Osal_paBeginMemAccess and have
764 * the same parameters
765 *
766 * <b> Prototype: </b>
767 * The following is the C prototype for the expected OSAL API.
768 *
769 * @verbatim
770 void Osal_paEndMemAccess (void* addr, uint32_t sizeWords)
771 @endverbatim
772 *
773 * <b> Parameters </b>
774 * @n The address of the table to be accessed
775 * @n The number of bytes in the table
776 *
777 * @note PA will make nested calls to this function for memory access
778 * protection of different memory tables.
779 */
780
781void Osal_paEndMemAccess (Ptr addr, UInt32 size)
782{
783#ifdef _TMS320C6X
784 uint32_t key;
785
786 /* Disable Interrupts */
787 key = Hwi_disable();
788
789 SYS_CACHE_WB (addr, size, CACHE_FENCE_WAIT);
790
791 asm (" nop 4");
792 asm (" nop 4");
793 asm (" nop 4");
794 asm (" nop 4");
795
796 /* Reenable Interrupts. */
797 Hwi_restore(key);
798#endif
799}
800
801
802/**
803 * @b Description
804 * @n
805 * The function is used to enter a critical section.
806 * Function protects against
807 *
808 * access from multiple threads on single core
809 * and
810 * access from multiple cores
811 *
812 * @param[in] key
813 * Key used to lock the critical section.
814 *
815 * @retval
816 * Not Applicable
817 */
818Void Osal_paMtCsEnter (uint32_t *key)
819{
820
821 /* Get the hardware semaphore.
822 *
823 * Acquire Multi core PA synchronization lock
824 */
825 while ((CSL_semAcquireDirect (PA_HW_SEM)) == 0);
826 *key = 0;
827}
828
829/**
830 * @b Description
831 * @n
832 * The function is used to exit a critical section
833 * protected using Osal_salldCsEnter() API.
834 *
835 * @param[in] key
836 * Key used to unlock the critical section.
837 *
838 * @retval
839 * Not Applicable
840 */
841Void Osal_paMtCsExit (uint32_t key)
842{
843 /* Release the hardware semaphore */
844 CSL_semReleaseSemaphore (PA_HW_SEM);
845}
846
847/**
848 * @b Description
849 * @n
850 * The function is used to allocate a memory block of the specified size.
851 *
852 * @param[in] num_bytes
853 * Number of bytes to be allocated.
854 *
855 * @retval
856 * Allocated block address
857 */
858void *Osal_rmMalloc (uint32_t num_bytes)
859{
860 Error_Block errorBlock;
861
862 /* Increment the allocation counter. */
863 rmMallocCounter++;
864
865 /* Allocate memory. */
866 return Memory_alloc(NULL, num_bytes, 0, &errorBlock);
867}
868
869/**
870 * @b Description
871 * @n
872 * The function is used to free a memory block of the specified size.
873 *
874 * @param[in] ptr
875 * Pointer to the memory block to be cleaned up.
876 *
877 * @param[in] size
878 * Size of the memory block to be cleaned up.
879 *
880 * @retval
881 * Not Applicable
882 */
883void Osal_rmFree (void *ptr, uint32_t size)
884{
885 /* Increment the free counter. */
886 rmFreeCounter++;
887 Memory_free(NULL, ptr, size);
888}
889
890/* FUNCTION PURPOSE: Critical section enter
891 ***********************************************************************
892 * DESCRIPTION: The function is used to enter a critical section.
893 * Function protects against
894 *
895 * access from multiple cores
896 * and
897 * access from multiple threads on single core
898 */
899void *Osal_rmCsEnter(void)
900{
901
902 return NULL;
903}
904
905/* FUNCTION PURPOSE: Critical section exit
906 ***********************************************************************
907 * DESCRIPTION: The function is used to exit a critical section
908 * protected using Osal_cppiCsEnter() API.
909 */
910void Osal_rmCsExit(void *CsHandle)
911{
912
913}
914
915/* FUNCTION PURPOSE: Multi-threaded critical section enter
916***********************************************************************
917* DESCRIPTION: The function is used to enter a multi-threaded critical
918* section. Function protects against
919 *
920 * access from multiple threads on single core
921*/
922void *Osal_rmMtCsEnter(void *mtSemObj)
923{
924
925 return NULL;
926}
927
928/* FUNCTION PURPOSE: Multi-threaded critical section exit
929***********************************************************************
930* DESCRIPTION: The function is used to exit a multi-threaded critical
931* section protected using Osal_rmMtCsEnter() API.
932*/
933void Osal_rmMtCsExit(void *mtSemObj, void *CsHandle)
934{
935
936}
937
938/* FUNCTION PURPOSE: Critical section exit
939 ***********************************************************************
940 * DESCRIPTION: The function is used to indicate that a block of memory is
941 * about to be accessed. If the memory block is cached then this
942 * indicates that the application would need to ensure that the
943 * cache is updated with the data from the actual memory.
944 */
945void Osal_rmBeginMemAccess(void *ptr, uint32_t size)
946{
947#ifdef _TMS320C6X
948 uint32_t key;
949
950 /* Disable Interrupts */
951 key = Hwi_disable();
952
953 /* Cleanup the prefetch buffer also. */
954 CSL_XMC_invalidatePrefetchBuffer();
955
956#ifdef L2_CACHE
957 /* Invalidate L2 cache. This should invalidate L1D as well.
958 * Wait until operation is complete. */
959 CACHE_invL2 (ptr, size, CACHE_FENCE_WAIT);
960#else
961 /* Invalidate L1D cache and wait until operation is complete.
962 * Use this approach if L2 cache is not enabled */
963 CACHE_invL1d (ptr, size, CACHE_FENCE_WAIT);
964#endif
965
966 /* Reenable Interrupts. */
967 Hwi_restore(key);
968#endif
969 return;
970}
971
972/* FUNCTION PURPOSE: Critical section exit
973 ***********************************************************************
974 * DESCRIPTION: The function is used to indicate that the block of memory has
975 * finished being accessed. If the memory block is cached then the
976 * application would need to ensure that the contents of the cache
977 * are updated immediately to the actual memory.
978 */
979void Osal_rmEndMemAccess(void *ptr, uint32_t size)
980{
981#ifdef _TMS320C6X
982 uint32_t key;
983
984 /* Disable Interrupts */
985 key = Hwi_disable();
986
987#ifdef L2_CACHE
988 /* Writeback L2 cache. This should Writeback L1D as well.
989 * Wait until operation is complete. */
990 CACHE_wbL2 (ptr, size, CACHE_FENCE_WAIT);
991
992#else
993 /* Writeback L1D cache and wait until operation is complete.
994 * Use this approach if L2 cache is not enabled */
995 CACHE_wbL1d (ptr, size, CACHE_FENCE_WAIT);
996#endif
997
998 /* Reenable Interrupts. */
999 Hwi_restore(key);
1000#endif
1001 return;
1002}
1003
1004/**
1005 * @b Description
1006 * @n
1007 * The function is used to create a task blocking object
1008 * capable of blocking the task a RM instance is running
1009 * within
1010 *
1011 * @retval
1012 * Allocated task blocking object
1013 */
1014void *Osal_rmTaskBlockCreate(void)
1015{
1016 Semaphore_Params semParams;
1017
1018 Semaphore_Params_init(&semParams);
1019 return((void *)Semaphore_create(0, &semParams, NULL));
1020}
1021
1022/**
1023 * @b Description
1024 * @n
1025 * The function is used to block a task whose context a
1026 * RM instance is running within.
1027 *
1028 * @param[in] handle
1029 * Task blocking object handle.
1030 *
1031 * @retval
1032 * Not Applicable
1033 */
1034void Osal_rmTaskBlock(void *handle)
1035{
1036 Semaphore_pend((Semaphore_Handle)handle, BIOS_WAIT_FOREVER);
1037}
1038
1039/**
1040 * @b Description
1041 * @n
1042 * The function is used to unblock a task whose context a
1043 * RM instance is running within.
1044 *
1045 * @param[in] handle
1046 * Task blocking object handle.
1047 *
1048 * @retval
1049 * Not Applicable
1050 */
1051void Osal_rmTaskUnblock(void *handle)
1052{
1053 Semaphore_post((Semaphore_Handle)handle);
1054}
1055
1056/**
1057 * @b Description
1058 * @n
1059 * The function is used to delete a task blocking object
1060 * provided to a RM instance
1061 *
1062 * @param[in] handle
1063 * Task blocking object handle.
1064 *
1065 * @retval
1066 * Not Applicable
1067 */
1068void Osal_rmTaskBlockDelete(void *handle)
1069{
1070 Semaphore_delete((Semaphore_Handle *)&handle);
1071}
1072
1073/**
1074 * @b Description
1075 * @n
1076 * The function is the RM OSAL Logging API which logs
1077 * the messages on the console.
1078 *
1079 * @param[in] fmt
1080 * Formatted String.
1081 *
1082 * @retval
1083 * Not Applicable
1084 */
1085void Osal_rmLog (char *fmt, ... )
1086{
1087 VaList ap;
1088
1089 va_start(ap, fmt);
1090 System_vprintf(fmt, ap);
1091 va_end(ap);
1092}
1093
1094
1095
diff --git a/example/emacExample/k2k/armv7/bios/PA_emacExample_K2KArmBiosExampleProject.txt b/example/emacExample/k2k/armv7/bios/PA_emacExample_K2KArmBiosExampleProject.txt
new file mode 100644
index 0000000..4458bb1
--- /dev/null
+++ b/example/emacExample/k2k/armv7/bios/PA_emacExample_K2KArmBiosExampleProject.txt
@@ -0,0 +1,24 @@
1-ccs.linkFile "PASS_INSTALL_PATH/ti/drv/pa/example/emacExample/src/cpsw_singlecore.c"
2-ccs.linkFile "PASS_INSTALL_PATH/ti/drv/pa/example/emacExample/src/pa_mgmt.c"
3-ccs.linkFile "PASS_INSTALL_PATH/ti/drv/pa/example/emacExample/src/cppi_qmss_mgmt.c"
4-ccs.linkFile "PASS_INSTALL_PATH/ti/drv/pa/example/emacExample/src/setuprm.c"
5-ccs.linkFile "PASS_INSTALL_PATH/ti/drv/pa/example/emacExample/src/view_ale_table.c"
6-ccs.linkFile "PASS_INSTALL_PATH/ti/drv/pa/example/emacExample/src/armv7/bios/framework.c"
7-ccs.linkFile "PASS_INSTALL_PATH/ti/drv/pa/example/emacExample/src/armv7/bios/fw_main.c"
8-ccs.linkFile "PASS_INSTALL_PATH/ti/drv/pa/example/emacExample/src/armv7/bios/cpsw_mgmt.c"
9-ccs.linkFile "PASS_INSTALL_PATH/ti/drv/pa/example/emacExample/k2k/armv7/bios/singlecore_osal.c"
10-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/device/k2k/policy_dsp-only.c"
11-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/device/k2k/policy_dsp_arm.c"
12-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/device/k2k/global-resource-list.c"
13-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/cppi/device/k2k/src/cppi_device.c"
14-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/qmss/device/k2k/src/qmss_device.c"
15-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/pa/device/k2k/src/nss_device.c"
16-ccs.linkFile "PDK_INSTALL_PATH/ti/csl/src/ip/sgmii/V0/csl_cpsgmii.c"
17-ccs.linkFile "PDK_INSTALL_PATH/ti/csl/src/ip/cpsw/V0/csl_cpsw_5gf.c"
18-ccs.linkFile "PDK_INSTALL_PATH/ti/csl/src/ip/serdes_sb/V0/csl_wiz8_sb_refclk125MHz_10bit_5Gbps.c"
19-ccs.linkFile "PDK_INSTALL_PATH/ti/csl/src/ip/serdes_sb/V0/csl_wiz8_sb_refclk125MHz_20bit_6p25Gbps.c"
20-ccs.linkFile "PDK_INSTALL_PATH/ti/csl/src/ip/serdes_sb/V0/csl_wiz8_sb_refclk156p25MHz_10bit_5Gbps.c"
21-ccs.linkFile "PDK_INSTALL_PATH/ti/csl/src/ip/serdes_sb/V0/csl_wiz8_sb_refclk156p25MHz_20bit_6p25Gbps.c"
22-ccs.linkFile "PASS_INSTALL_PATH/ti/drv/pa/example/emacExample/k2k/armv7/bios/cpsw_example_k2k.cfg"
23-ccs.setCompilerOptions "-c -mcpu=cortex-a15 -mtune=cortex-a15 -marm -mfloat-abi=hard -DSOC_K2K -DNUM_PORTS=5 -D_LITTLE_ENDIAN=1 -g -gstrict-dwarf -Wall -MMD -MP -I${PDK_INSTALL_PATH} -I${PDK_INSTALL_PATH}/ti/drv/pa/example/emacExample/src -I${PASS_INSTALL_PATH}/ti/drv/pa/example/emacExample/src/armv7/bios -I${PDK_INSTALL_PATH}/ti/drv/cppi -I${PDK_INSTALL_PATH}/ti/drv/qmss" -rtsc.enableRtsc
24-ccs.setLinkerOptions " -lrdimon -lgcc -lm -lnosys -nostartfiles -static -Wl,--gc-sections -L$(XDCTOOLS)/packages/gnu/targets/arm/libs/install-native/arm-none-eabi/lib/fpu "
diff --git a/example/emacExample/k2k/armv7/bios/cpsw_example_k2k.cfg b/example/emacExample/k2k/armv7/bios/cpsw_example_k2k.cfg
new file mode 100644
index 0000000..5b6d8e3
--- /dev/null
+++ b/example/emacExample/k2k/armv7/bios/cpsw_example_k2k.cfg
@@ -0,0 +1,145 @@
1/*
2 * Copyright 2015 by Texas Instruments Incorporated.
3 *
4 * All rights reserved. Property of Texas Instruments Incorporated.
5 * Restricted rights to use, duplicate or disclose this code are
6 * granted through contract.
7 *
8 */
9
10/*
11 * ======== cpsw_example.cfg ========
12 *
13 */
14
15/* Load all required BIOS/XDC runtime packages */
16var Memory = xdc.useModule('xdc.runtime.Memory');
17var BIOS = xdc.useModule('ti.sysbios.BIOS');
18var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
19var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
20var Log = xdc.useModule('xdc.runtime.Log');
21var LoggerBuf = xdc.useModule('xdc.runtime.LoggerBuf');
22var Task = xdc.useModule('ti.sysbios.knl.Task');
23var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');
24var Main = xdc.useModule('xdc.runtime.Main');
25var Defaults = xdc.useModule('xdc.runtime.Defaults');
26var Diags = xdc.useModule('xdc.runtime.Diags');
27var SysMin = xdc.useModule('xdc.runtime.SysMin');
28var System = xdc.useModule('xdc.runtime.System');
29var Text = xdc.useModule('xdc.runtime.Text');
30
31Task.defaultStackSize = 0x4000;
32
33/* Load the CPPI package */
34var Cppi = xdc.loadPackage('ti.drv.cppi');
35/* Load the QMSS package */
36var Qmss = xdc.loadPackage('ti.drv.qmss');
37
38/* Load the PA package */
39var devType = "k2k"
40var Pa = xdc.useModule('ti.drv.pa.Settings');
41Pa.deviceType = devType;
42
43/* Load the RM package */
44var Rm = xdc.loadPackage('ti.drv.rm');
45
46/*
47 * Program.argSize sets the size of the .args section.
48 * The examples don't use command line args so argSize is set to 0.
49 */
50Program.argSize = 0x0;
51
52/*
53 * The BIOS module will create the default heap for the system.
54 * Specify the size of this default heap.
55 */
56BIOS.heapSize = 8192 * 30;
57
58/*
59 * Build a custom SYS/BIOS library from sources.
60 */
61BIOS.libType = BIOS.LibType_Custom;
62
63/* System stack size (used by ISRs and Swis) */
64Program.stack = 0x20000;
65
66/* Circular buffer size for System_printf() */
67SysMin.bufSize = 0x400;
68
69/*
70 * Create and install logger for the whole system
71 */
72var loggerBufParams = new LoggerBuf.Params();
73loggerBufParams.numEntries = 32;
74var logger0 = LoggerBuf.create(loggerBufParams);
75Defaults.common$.logger = logger0;
76Main.common$.diags_INFO = Diags.ALWAYS_ON;
77
78System.SupportProxy = SysMin;
79var SemiHost = xdc.useModule('ti.sysbios.rts.gnu.SemiHostSupport');
80
81var Cache = xdc.useModule('ti.sysbios.family.arm.a15.Cache');
82var Mmu = xdc.useModule('ti.sysbios.family.arm.a15.Mmu');
83
84/* Enable the cache */
85Cache.enableCache = true;
86
87// Enable the MMU (Required for L1/L2 data caching)
88Mmu.enableMMU = true;
89
90// descriptor attribute structure
91var peripheralAttrs = new Mmu.DescriptorAttrs();
92
93Mmu.initDescAttrsMeta(peripheralAttrs);
94
95peripheralAttrs.type = Mmu.DescriptorType_BLOCK; // BLOCK descriptor
96peripheralAttrs.noExecute = true; // not executable
97peripheralAttrs.accPerm = 0; // read/write at PL1
98peripheralAttrs.attrIndx = 1; // MAIR0 Byte1 describes
99 // memory attributes for
100// Define the base address of the 2 MB page
101// the peripheral resides in.
102var peripheralBaseAddrs = [
103 { base: 0x02620000, size: 0x00001000 }, // bootcfg
104 { base: 0x0bc00000, size: 0x00100000 }, // MSMC config
105 { base: 0x02000000, size: 0x00100000 }, // NETCP memory
106 { base: 0x02a00000, size: 0x00100000 }, // QMSS config memory
107 { base: 0x23A00000, size: 0x00100000 }, // QMSS Data memory
108 { base: 0x02901000, size: 0x00002000 }, // SRIO pkt dma config memory
109 { base: 0x01f14000, size: 0x00007000 }, // AIF pkt dma config memory
110 { base: 0x021F0200, size: 0x00000600 }, // FFTC 0 pkt dma config memory
111 { base: 0x021F0a00, size: 0x00000600 }, // FFTC 4 pkt dma config memory
112 { base: 0x021F1200, size: 0x00000600 }, // FFTC 5 pkt dma config memory
113 { base: 0x021F4200, size: 0x00000600 }, // FFTC 1 pkt dma config memory
114 { base: 0x021F8200, size: 0x00000600 }, // FFTC 2 pkt dma config memory
115 { base: 0x021FC200, size: 0x00000600 }, // FFTC 3 pkt dma config memory
116 { base: 0x02554000, size: 0x00009000 } // BCP pkt dma config memory
117];
118
119// Configure the corresponding MMU page descriptor accordingly
120for (var i =0; i < peripheralBaseAddrs.length; i++)
121{
122 for (var j = 0; j < peripheralBaseAddrs[i].size; j += 0x200000)
123 {
124 var addr = peripheralBaseAddrs[i].base + j;
125 Mmu.setSecondLevelDescMeta(addr, addr, peripheralAttrs);
126 }
127}
128
129// Reconfigure DDR to use coherent address
130Mmu.initDescAttrsMeta(peripheralAttrs);
131
132peripheralAttrs.type = Mmu.DescriptorType_BLOCK;
133peripheralAttrs.shareable = 2; // outer-shareable (3=inner, 0=none)
134peripheralAttrs.accPerm = 1; // read/write at any privelege level
135peripheralAttrs.attrIndx = 2; // normal cacheable (0=no cache, 1=strict order)
136for (var vaddr = 0x80000000, paddr = 0x800000000; vaddr < 0x100000000; vaddr += 0x200000, paddr+= 0x200000)
137{
138 Mmu.setSecondLevelDescMeta(vaddr, paddr, peripheralAttrs);
139}
140// Add MSMC as coherent
141for (var addr = 0x0c000000; addr < 0x0c600000; addr += 0x200000)
142{
143 Mmu.setSecondLevelDescMeta(addr, addr, peripheralAttrs);
144}
145
diff --git a/example/emacExample/k2k/armv7/bios/singlecore_osal.c b/example/emacExample/k2k/armv7/bios/singlecore_osal.c
new file mode 100644
index 0000000..5f4353d
--- /dev/null
+++ b/example/emacExample/k2k/armv7/bios/singlecore_osal.c
@@ -0,0 +1,1095 @@
1/**
2 * @file singlecore_osal.c
3 *
4 * @brief
5 * This is a sample OS Abstraction Layer (AL) file implemented
6 * using XDC/BIOS APIs.
7 *
8 * System integrator is advised to review these implementations and
9 * modify them to suit it to application requirements.
10 *
11 * This OSAL implementation uses the <b> Approach 1 </b> documented.
12 *
13 * \par
14 * ============================================================================
15 * @n (C) Copyright 2009, Texas Instruments, Inc.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
19 * are met:
20 *
21 * Redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer.
23 *
24 * Redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the
27 * distribution.
28 *
29 * Neither the name of Texas Instruments Incorporated nor the names of
30 * its contributors may be used to endorse or promote products derived
31 * from this software without specific prior written permission.
32 *
33 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
34 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
35 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
36 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
37 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
38 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
39 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
40 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
41 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
42 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
43 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 *
45*/
46/* Standard C-native includes */
47#include <stdlib.h>
48#include <string.h>
49
50/* XDC/BIOS includes */
51#include <xdc/std.h>
52#include <xdc/runtime/IHeap.h>
53#include <xdc/runtime/System.h>
54#include <xdc/runtime/Memory.h>
55#include <xdc/runtime/Error.h>
56
57#include <ti/sysbios/BIOS.h>
58#include <ti/sysbios/hal/Hwi.h>
59#include <ti/sysbios/knl/Task.h>
60#include <ti/sysbios/knl/Semaphore.h>
61#include <ti/sysbios/heaps/HeapBuf.h>
62#include <ti/sysbios/heaps/HeapMem.h>
63
64#include <xdc/cfg/global.h>
65
66/* CSL CHIP, SEM Functional layer includes */
67#include <ti/csl/csl_chip.h>
68#include <ti/csl/csl_semAux.h>
69
70#ifdef _TMS320C6X
71/* CSL Cache module includes */
72#include <ti/csl/csl_cacheAux.h>
73/* CSL XMC module includes */
74#include <ti/csl/csl_xmcAux.h>
75#endif
76
77/**********************************************************************
78 ****************************** Defines *******************************
79 **********************************************************************/
80
81#define MAX_NUM_CORES 8
82
83/* Hardware Semaphore to synchronize access from
84 * multiple applications (PA applications and non-PASS applications)
85 * across different cores to the QMSS library.
86 */
87#define QMSS_HW_SEM 3
88
89/* Hardware Semaphore to synchronize access from
90 * multiple applications (PASS applications and non-PASS applications)
91 * across different cores to the CPPI library.
92 */
93#define CPPI_HW_SEM 4
94
95/* Hardware Semaphore to synchronize access from
96 * multiple applications (PASS applications and non-PASS applications)
97 * across different cores to the PA library.
98 */
99#define PA_HW_SEM 5
100
101#undef L2_CACHE
102#ifdef L2_CACHE
103 /* Invalidate L2 cache. This should invalidate L1D as well.
104 * Wait until operation is complete. */
105#define SYS_CACHE_INV(addr, size, code) CACHE_invL2 (addr, size, code)
106
107 /* Writeback L2 cache. This should Writeback L1D as well.
108 * Wait until operation is complete. */
109#define SYS_CACHE_WB(addr, size, code) CACHE_wbL2 (addr, size, code)
110
111#else
112 /* Invalidate L1D cache and wait until operation is complete.
113 * Use this approach if L2 cache is not enabled */
114#define SYS_CACHE_INV(addr, size, code) CACHE_invL1d (addr, size, code)
115 /* Writeback L1D cache and wait until operation is complete.
116 * Use this approach if L2 cache is not enabled */
117#define SYS_CACHE_WB(addr, size, code) CACHE_wbL1d (addr, size, code)
118
119#endif
120
121/**
122 * @b Description
123 * @n
124 * General Memory Barrier guarantees that all LOAD and STORE operations that were issued before the
125 * barrier occur before the LOAD and STORE operations issued after the barrier
126 *
127 */
128static inline void memBarrier(void) {__sync_synchronize();}
129
130/**********************************************************************
131 ************************** Global Variables **************************
132 **********************************************************************/
133UInt32 cpswCppiMallocCounter = 0;
134UInt32 cpswCppiFreeCounter = 0;
135UInt32 cpswQmssMallocCounter = 0;
136UInt32 cpswQmssFreeCounter = 0;
137uint32_t rmMallocCounter = 0;
138uint32_t rmFreeCounter = 0;
139UInt32 coreKey [MAX_NUM_CORES];
140
141/**********************************************************************
142 *********************** CPPI OSAL Functions **************************
143 **********************************************************************/
144
145/**
146 * ============================================================================
147 * @n@b Osal_cppiCsEnter
148 *
149 * @b brief
150 * @n This API ensures multi-core and multi-threaded
151 * synchronization to the caller.
152 *
153 * This is a BLOCKING API.
154 *
155 * This API ensures multi-core synchronization between
156 * multiple processes trying to access CPPI shared
157 * library at the same time.
158 *
159 * @param[in]
160 * @n None
161 *
162 * @return
163 * @n Handle used to lock critical section
164 * =============================================================================
165 */
166Ptr Osal_cppiCsEnter (Void)
167{
168#ifdef _TMS320C6X
169 uint32_t coreNum = CSL_chipReadReg (CSL_CHIP_DNUM);
170#else
171 uint32_t coreNum = 0;
172#endif
173 /* Get the hardware semaphore.
174 *
175 * Acquire Multi core CPPI synchronization lock
176 */
177 while ((CSL_semAcquireDirect (CPPI_HW_SEM)) == 0);
178
179 /* Disable all interrupts and OS scheduler.
180 *
181 * Acquire Multi threaded / process synchronization lock.
182 */
183 coreKey [coreNum] = Hwi_disable();
184
185 return NULL;
186}
187
188/**
189 * ============================================================================
190 * @n@b Osal_cppiCsExit
191 *
192 * @b brief
193 * @n This API needs to be called to exit a previously
194 * acquired critical section lock using @a Osal_cppiCsEnter ()
195 * API. It resets the multi-core and multi-threaded lock,
196 * enabling another process/core to grab CPPI access.
197 *
198 * @param[in] CsHandle
199 * Handle for unlocking critical section.
200 *
201 * @return None
202 * =============================================================================
203 */
204Void Osal_cppiCsExit (Ptr CsHandle)
205{
206#ifdef _TMS320C6X
207 uint32_t coreNum = CSL_chipReadReg (CSL_CHIP_DNUM);
208#else
209 uint32_t coreNum = 0;
210#endif
211 /* Enable all interrupts and enables the OS scheduler back on.
212 *
213 * Release multi-threaded / multi-process lock on this core.
214 */
215 Hwi_restore(coreKey [coreNum]);
216
217 /* Release the hardware semaphore
218 *
219 * Release multi-core lock.
220 */
221 CSL_semReleaseSemaphore (CPPI_HW_SEM);
222
223 return;
224}
225
226/**
227 * ============================================================================
228 * @n@b Osal_cppiMalloc
229 *
230 * @b brief
231 * @n This API allocates a memory block of a given
232 * size specified by input parameter 'num_bytes'.
233 *
234 * This API should allocate memory from shared memory if the test applications
235 * are to be run on multiple cores.
236 *
237 * @param[in] num_bytes
238 * Number of bytes to be allocated.
239 *
240 * @return
241 * Allocated block address
242 * =============================================================================
243 */
244Ptr Osal_cppiMalloc (UInt32 num_bytes)
245{
246 Error_Block errorBlock;
247
248 /* Increment the allocation counter. */
249 cpswCppiMallocCounter++;
250
251 /* Allocate memory. */
252 return Memory_alloc(NULL, num_bytes, 0, &errorBlock);
253}
254
255/**
256 * ============================================================================
257 * @n@b Osal_cppiFree
258 *
259 * @b brief
260 * @n This API frees and restores a given memory location
261 * pointer 'dataPtr' of size 'num_bytes' to its
262 * original heap location. Frees up memory allocated using
263 * @a Osal_cppiMalloc ()
264 *
265 * @param[in] dataPtr
266 * Pointer to the memory block to be cleaned up.
267 *
268 * @param[in] num_bytes
269 * Size of the memory block to be cleaned up.
270 *
271 * @return
272 * Not Applicable
273 * =============================================================================
274 */
275Void Osal_cppiFree (Ptr dataPtr, UInt32 num_bytes)
276{
277 /* Increment the free counter. */
278 cpswCppiFreeCounter++;
279
280 /* Free up the memory */
281 if (dataPtr)
282 {
283 /* Convert the global address to local address since
284 * thats what the heap understands.
285 */
286 Memory_free(NULL, dataPtr, num_bytes);
287 }
288}
289
290/**
291 * @b Description
292 * @n
293 * The function is used to indicate that a block of memory is
294 * about to be accessed. If the memory block is cached then this
295 * indicates that the application would need to ensure that the
296 * cache is updated with the data from the actual memory.
297 *
298 * @param[in] blockPtr
299 * Address of the block which is to be invalidated
300 *
301 * @param[in] size
302 * Size of the block to be invalidated
303
304 * @retval
305 * Not Applicable
306 */
307void Osal_cppiBeginMemAccess (void *blockPtr, uint32_t size)
308{
309#ifdef _TMS320C6X
310 uint32_t key;
311
312 /* Disable Interrupts */
313 key = Hwi_disable();
314
315 /* Cleanup the prefetch buffer also. */
316 CSL_XMC_invalidatePrefetchBuffer();
317
318 SYS_CACHE_INV (blockPtr, size, CACHE_FENCE_WAIT);
319
320 asm (" nop 4");
321 asm (" nop 4");
322 asm (" nop 4");
323 asm (" nop 4");
324
325 /* Reenable Interrupts. */
326 Hwi_restore(key);
327#endif
328 return;
329}
330
331/**
332 * @b Description
333 * @n
334 * The function is used to indicate that the block of memory has
335 * finished being accessed. If the memory block is cached then the
336 * application would need to ensure that the contents of the cache
337 * are updated immediately to the actual memory.
338 *
339 * @param[in] blockPtr
340 * Address of the block which is to be written back
341 *
342 * @param[in] size
343 * Size of the block to be written back
344
345 * @retval
346 * Not Applicable
347 */
348void Osal_cppiEndMemAccess (void *blockPtr, uint32_t size)
349{
350#ifdef _TMS320C6X
351 uint32_t key;
352
353 /* Disable Interrupts */
354 key = Hwi_disable();
355
356 SYS_CACHE_WB (blockPtr, size, CACHE_FENCE_WAIT);
357
358 asm (" nop 4");
359 asm (" nop 4");
360 asm (" nop 4");
361 asm (" nop 4");
362
363 /* Reenable Interrupts. */
364 Hwi_restore(key);
365#endif
366 return;
367}
368
369/**********************************************************************
370 *********************** QMSS OSAL Functions **************************
371 **********************************************************************/
372
373/**
374 * ============================================================================
375 * @n@b Osal_qmssCsEnter
376 *
377 * @b brief
378 * @n This API ensures multi-core and multi-threaded
379 * synchronization to the caller.
380 *
381 * This is a BLOCKING API.
382 *
383 * This API ensures multi-core synchronization between
384 * multiple processes trying to access QMSS shared
385 * library at the same time.
386 *
387 * @param[in] None
388 *
389 * @return
390 * Handle used to lock critical section
391 * =============================================================================
392 */
393Ptr Osal_qmssCsEnter (Void)
394{
395#ifdef _TMS320C6X
396 uint32_t coreNum = CSL_chipReadReg (CSL_CHIP_DNUM);
397#else
398 uint32_t coreNum = 0;
399#endif
400 /* Get the hardware semaphore.
401 *
402 * Acquire Multi core QMSS synchronization lock
403 */
404 while ((CSL_semAcquireDirect (QMSS_HW_SEM)) == 0);
405
406 /* Disable all interrupts and OS scheduler.
407 *
408 * Acquire Multi threaded / process synchronization lock.
409 */
410 coreKey [coreNum] = Hwi_disable();
411
412 return NULL;
413}
414
415/**
416 * ============================================================================
417 * @n@b Osal_qmssCsExit
418 *
419 * @b brief
420 * @n This API needs to be called to exit a previously
421 * acquired critical section lock using @a Osal_cpswQmssCsEnter ()
422 * API. It resets the multi-core and multi-threaded lock,
423 * enabling another process/core to grab QMSS access.
424 *
425 * @param[in] CsHandle
426 * Handle for unlocking critical section.
427 *
428 * @return None
429 * =============================================================================
430 */
431Void Osal_qmssCsExit (Ptr CsHandle)
432{
433#ifdef _TMS320C6X
434 uint32_t coreNum = CSL_chipReadReg (CSL_CHIP_DNUM);
435#else
436 uint32_t coreNum = 0;
437#endif
438 /* Enable all interrupts and enables the OS scheduler back on.
439 *
440 * Release multi-threaded / multi-process lock on this core.
441 */
442 Hwi_restore(coreKey [coreNum]);
443
444 /* Release the hardware semaphore
445 *
446 * Release multi-core lock.
447 */
448 CSL_semReleaseSemaphore (QMSS_HW_SEM);
449
450 return;
451}
452
453 /**
454 * ============================================================================
455 * @n@b Osal_qmssAccCsEnter
456 *
457 * @b brief
458 * @n This API ensures multi-core and multi-threaded
459 * synchronization to the caller.
460 *
461 * This is a BLOCKING API.
462 *
463 * This API ensures multi-core synchronization between
464 * multiple processes trying to access QMSS shared
465 * library at the same time.
466 *
467 * @param[in] None
468 *
469 * @return
470 * Handle used to lock critical section
471 * =============================================================================
472 */
473Ptr Osal_qmssAccCsEnter (Void)
474{
475 /* This is a suboptimal implementation for this OSAL, please refer to
476 * QMSS examples for optimal implementation of this function
477 */
478
479 return (Osal_qmssCsEnter());
480}
481
482/**
483 * ============================================================================
484 * @n@b Osal_qmssAccCsExit
485 *
486 * @b brief
487 * @n This API needs to be called to exit a previously
488 * acquired critical section lock using @a Osal_qmssAccCsEnter ()
489 * API. It resets the multi-core and multi-threaded lock,
490 * enabling another process/core to grab QMSS access.
491 *
492 * @param[in] CsHandle
493 * Handle for unlocking critical section.
494 *
495 * @return None
496 * =============================================================================
497 */
498Void Osal_qmssAccCsExit (Ptr CsHandle)
499{
500 /* This is a suboptimal implementation for this OSAL, please refer to
501 * QMSS examples for optimal implementation of this function
502 */
503 Osal_qmssCsExit(CsHandle);
504 return;
505}
506/**
507 * ============================================================================
508 * @n@b Osal_qmssMtCsEnter
509 *
510 * @b brief
511 * @n This API ensures ONLY multi-threaded
512 * synchronization to the QMSS user.
513 *
514 * This is a BLOCKING API.
515 *
516 * @param[in] None
517 *
518 * @return
519 * Handle used to lock critical section
520 * =============================================================================
521 */
522Ptr Osal_qmssMtCsEnter (Void)
523{
524 /* Disable all interrupts and OS scheduler.
525 *
526 * Acquire Multi threaded / process synchronization lock.
527 */
528 //coreKey [CSL_chipReadReg (CSL_CHIP_DNUM)] = Hwi_disable();
529
530 return NULL;
531}
532
533/**
534 * ============================================================================
535 * @n@b Osal_qmssMtCsExit
536 *
537 * @b brief
538 * @n This API needs to be called to exit a previously
539 * acquired critical section lock using @a Osal_cpswQmssMtCsEnter ()
540 * API. It resets the multi-threaded lock, enabling another process
541 * on the current core to grab it.
542 *
543 * @param[in] CsHandle
544 * Handle for unlocking critical section.
545 *
546 * @return None
547 * =============================================================================
548 */
549Void Osal_qmssMtCsExit (Ptr CsHandle)
550{
551 /* Enable all interrupts and enables the OS scheduler back on.
552 *
553 * Release multi-threaded / multi-process lock on this core.
554 */
555 //Hwi_restore(key);
556
557 return;
558}
559
560/**
561 * ============================================================================
562 * @n@b Osal_qmssMalloc
563 *
564 * @b brief
565 * @n This API allocates a memory block of a given
566 * size specified by input parameter 'num_bytes'.
567 *
568 * @param[in] num_bytes
569 * Number of bytes to be allocated.
570 *
571 * @return
572 * Allocated block address
573 * =============================================================================
574 */
575Ptr Osal_qmssMalloc (UInt32 num_bytes)
576{
577 Error_Block errorBlock;
578
579 /* Increment the allocation counter. */
580 cpswQmssMallocCounter++;
581
582 /* Allocate memory. */
583 return Memory_alloc(NULL, num_bytes, 0, &errorBlock);
584}
585
586/**
587 * ============================================================================
588 * @n@b Osal_qmssFree
589 *
590 * @b brief
591 * @n This API frees and restores a given memory location
592 * pointer 'dataPtr' of size 'num_bytes' to its
593 * original heap location. Frees up memory allocated using
594 * @a Osal_qmssMalloc ()
595 *
596 * @param[in] dataPtr
597 * Pointer to the memory block to be cleaned up.
598 *
599 * @param[in] num_bytes
600 * Size of the memory block to be cleaned up.
601 *
602 * @return
603 * Not Applicable
604 * =============================================================================
605 */
606Void Osal_qmssFree (Ptr dataPtr, UInt32 num_bytes)
607{
608 /* Increment the free counter. */
609 cpswQmssFreeCounter++;
610
611 /* Free up the memory */
612 if (dataPtr)
613 {
614 /* Convert the global address to local address since
615 * thats what the heap understands.
616 */
617 Memory_free(NULL, dataPtr, num_bytes);
618 }
619}
620
621/**
622 * @b Description
623 * @n
624 * The function is used to indicate that a block of memory is
625 * about to be accessed. If the memory block is cached then this
626 * indicates that the application would need to ensure that the
627 * cache is updated with the data from the actual memory.
628 *
629 * @param[in] blockPtr
630 * Address of the block which is to be invalidated
631 *
632 * @param[in] size
633 * Size of the block to be invalidated
634
635 * @retval
636 * Not Applicable
637 */
638void Osal_qmssBeginMemAccess (void *blockPtr, uint32_t size)
639{
640#ifdef _TMS320C6X
641 uint32_t key;
642
643 /* Disable Interrupts */
644 key = Hwi_disable();
645
646 /* Cleanup the prefetch buffer also. */
647 CSL_XMC_invalidatePrefetchBuffer();
648
649 SYS_CACHE_INV (blockPtr, size, CACHE_FENCE_WAIT);
650
651 asm (" nop 4");
652 asm (" nop 4");
653 asm (" nop 4");
654 asm (" nop 4");
655
656 /* Reenable Interrupts. */
657 Hwi_restore(key);
658#endif
659 return;
660}
661
662/**
663 * @b Description
664 * @n
665 * The function is used to indicate that the block of memory has
666 * finished being accessed. If the memory block is cached then the
667 * application would need to ensure that the contents of the cache
668 * are updated immediately to the actual memory.
669 *
670 * @param[in] blockPtr
671 * Address of the block which is to be written back
672 *
673 * @param[in] size
674 * Size of the block to be written back
675
676 * @retval
677 * Not Applicable
678 */
679void Osal_qmssEndMemAccess (void *blockPtr, uint32_t size)
680{
681#ifdef _TMS320C6X
682 uint32_t key;
683
684 /* Disable Interrupts */
685 key = Hwi_disable();
686
687 SYS_CACHE_WB (blockPtr, size, CACHE_FENCE_WAIT);
688
689 asm (" nop 4");
690 asm (" nop 4");
691 asm (" nop 4");
692 asm (" nop 4");
693
694 /* Reenable Interrupts. */
695 Hwi_restore(key);
696#endif
697 return;
698}
699
700/******************************************************************************
701* Function to issue memory barrier
702*
703* NOTE: QMSS unit tests are not using CPPI descriptors
704******************************************************************************/
705void* Osal_qmssMemBarrier(uint32_t QID, void *descAddr)
706{
707 /* Issue memory barrier */
708 memBarrier();
709 return descAddr;
710}
711
712/**********************************************************************
713 *********************** PASS OSAL Functions **************************
714 **********************************************************************/
715
716/**
717 * @brief This macro is used to alert the application that the PA is
718 * going to access table memory. The application must ensure
719 * cache coherency
720 *
721 *
722 * <b> Prototype: </b>
723 * The following is the C prototype for the expected OSAL API.
724 *
725 * @verbatim
726 void Osal_paBeginMemAccess (void* addr, uint32_t sizeWords)
727 @endverbatim
728 *
729 * <b> Parameters </b>
730 * @n The address of the table to be accessed
731 * @n The number of bytes in the table
732 *
733 * @note PA will make nested calls to this function for memory access
734 * protection of different memory tables.
735 */
736
737void Osal_paBeginMemAccess (Ptr addr, UInt32 size)
738{
739#ifdef _TMS320C6X
740 uint32_t key;
741
742 /* Disable Interrupts */
743 key = Hwi_disable();
744
745 /* Cleanup the prefetch buffer also. */
746 CSL_XMC_invalidatePrefetchBuffer();
747
748 SYS_CACHE_INV (addr, size, CACHE_FENCE_WAIT);
749
750 asm (" nop 4");
751 asm (" nop 4");
752 asm (" nop 4");
753 asm (" nop 4");
754
755 /* Reenable Interrupts. */
756 Hwi_restore(key);
757#endif
758}
759
760/**
761 * @brief This macro is used to alert the application that the PA
762 * has completed access to table memory. This call will always
763 * be made following a call to Osal_paBeginMemAccess and have
764 * the same parameters
765 *
766 * <b> Prototype: </b>
767 * The following is the C prototype for the expected OSAL API.
768 *
769 * @verbatim
770 void Osal_paEndMemAccess (void* addr, uint32_t sizeWords)
771 @endverbatim
772 *
773 * <b> Parameters </b>
774 * @n The address of the table to be accessed
775 * @n The number of bytes in the table
776 *
777 * @note PA will make nested calls to this function for memory access
778 * protection of different memory tables.
779 */
780
781void Osal_paEndMemAccess (Ptr addr, UInt32 size)
782{
783#ifdef _TMS320C6X
784 uint32_t key;
785
786 /* Disable Interrupts */
787 key = Hwi_disable();
788
789 SYS_CACHE_WB (addr, size, CACHE_FENCE_WAIT);
790
791 asm (" nop 4");
792 asm (" nop 4");
793 asm (" nop 4");
794 asm (" nop 4");
795
796 /* Reenable Interrupts. */
797 Hwi_restore(key);
798#endif
799}
800
801
802/**
803 * @b Description
804 * @n
805 * The function is used to enter a critical section.
806 * Function protects against
807 *
808 * access from multiple threads on single core
809 * and
810 * access from multiple cores
811 *
812 * @param[in] key
813 * Key used to lock the critical section.
814 *
815 * @retval
816 * Not Applicable
817 */
818Void Osal_paMtCsEnter (uint32_t *key)
819{
820
821 /* Get the hardware semaphore.
822 *
823 * Acquire Multi core PA synchronization lock
824 */
825 while ((CSL_semAcquireDirect (PA_HW_SEM)) == 0);
826 *key = 0;
827}
828
829/**
830 * @b Description
831 * @n
832 * The function is used to exit a critical section
833 * protected using Osal_salldCsEnter() API.
834 *
835 * @param[in] key
836 * Key used to unlock the critical section.
837 *
838 * @retval
839 * Not Applicable
840 */
841Void Osal_paMtCsExit (uint32_t key)
842{
843 /* Release the hardware semaphore */
844 CSL_semReleaseSemaphore (PA_HW_SEM);
845}
846
847/**
848 * @b Description
849 * @n
850 * The function is used to allocate a memory block of the specified size.
851 *
852 * @param[in] num_bytes
853 * Number of bytes to be allocated.
854 *
855 * @retval
856 * Allocated block address
857 */
858void *Osal_rmMalloc (uint32_t num_bytes)
859{
860 Error_Block errorBlock;
861
862 /* Increment the allocation counter. */
863 rmMallocCounter++;
864
865 /* Allocate memory. */
866 return Memory_alloc(NULL, num_bytes, 0, &errorBlock);
867}
868
869/**
870 * @b Description
871 * @n
872 * The function is used to free a memory block of the specified size.
873 *
874 * @param[in] ptr
875 * Pointer to the memory block to be cleaned up.
876 *
877 * @param[in] size
878 * Size of the memory block to be cleaned up.
879 *
880 * @retval
881 * Not Applicable
882 */
883void Osal_rmFree (void *ptr, uint32_t size)
884{
885 /* Increment the free counter. */
886 rmFreeCounter++;
887 Memory_free(NULL, ptr, size);
888}
889
890/* FUNCTION PURPOSE: Critical section enter
891 ***********************************************************************
892 * DESCRIPTION: The function is used to enter a critical section.
893 * Function protects against
894 *
895 * access from multiple cores
896 * and
897 * access from multiple threads on single core
898 */
899void *Osal_rmCsEnter(void)
900{
901
902 return NULL;
903}
904
905/* FUNCTION PURPOSE: Critical section exit
906 ***********************************************************************
907 * DESCRIPTION: The function is used to exit a critical section
908 * protected using Osal_cppiCsEnter() API.
909 */
910void Osal_rmCsExit(void *CsHandle)
911{
912
913}
914
915/* FUNCTION PURPOSE: Multi-threaded critical section enter
916***********************************************************************
917* DESCRIPTION: The function is used to enter a multi-threaded critical
918* section. Function protects against
919 *
920 * access from multiple threads on single core
921*/
922void *Osal_rmMtCsEnter(void *mtSemObj)
923{
924
925 return NULL;
926}
927
928/* FUNCTION PURPOSE: Multi-threaded critical section exit
929***********************************************************************
930* DESCRIPTION: The function is used to exit a multi-threaded critical
931* section protected using Osal_rmMtCsEnter() API.
932*/
933void Osal_rmMtCsExit(void *mtSemObj, void *CsHandle)
934{
935
936}
937
938/* FUNCTION PURPOSE: Critical section exit
939 ***********************************************************************
940 * DESCRIPTION: The function is used to indicate that a block of memory is
941 * about to be accessed. If the memory block is cached then this
942 * indicates that the application would need to ensure that the
943 * cache is updated with the data from the actual memory.
944 */
945void Osal_rmBeginMemAccess(void *ptr, uint32_t size)
946{
947#ifdef _TMS320C6X
948 uint32_t key;
949
950 /* Disable Interrupts */
951 key = Hwi_disable();
952
953 /* Cleanup the prefetch buffer also. */
954 CSL_XMC_invalidatePrefetchBuffer();
955
956#ifdef L2_CACHE
957 /* Invalidate L2 cache. This should invalidate L1D as well.
958 * Wait until operation is complete. */
959 CACHE_invL2 (ptr, size, CACHE_FENCE_WAIT);
960#else
961 /* Invalidate L1D cache and wait until operation is complete.
962 * Use this approach if L2 cache is not enabled */
963 CACHE_invL1d (ptr, size, CACHE_FENCE_WAIT);
964#endif
965
966 /* Reenable Interrupts. */
967 Hwi_restore(key);
968#endif
969 return;
970}
971
972/* FUNCTION PURPOSE: Critical section exit
973 ***********************************************************************
974 * DESCRIPTION: The function is used to indicate that the block of memory has
975 * finished being accessed. If the memory block is cached then the
976 * application would need to ensure that the contents of the cache
977 * are updated immediately to the actual memory.
978 */
979void Osal_rmEndMemAccess(void *ptr, uint32_t size)
980{
981#ifdef _TMS320C6X
982 uint32_t key;
983
984 /* Disable Interrupts */
985 key = Hwi_disable();
986
987#ifdef L2_CACHE
988 /* Writeback L2 cache. This should Writeback L1D as well.
989 * Wait until operation is complete. */
990 CACHE_wbL2 (ptr, size, CACHE_FENCE_WAIT);
991
992#else
993 /* Writeback L1D cache and wait until operation is complete.
994 * Use this approach if L2 cache is not enabled */
995 CACHE_wbL1d (ptr, size, CACHE_FENCE_WAIT);
996#endif
997
998 /* Reenable Interrupts. */
999 Hwi_restore(key);
1000#endif
1001 return;
1002}
1003
1004/**
1005 * @b Description
1006 * @n
1007 * The function is used to create a task blocking object
1008 * capable of blocking the task a RM instance is running
1009 * within
1010 *
1011 * @retval
1012 * Allocated task blocking object
1013 */
1014void *Osal_rmTaskBlockCreate(void)
1015{
1016 Semaphore_Params semParams;
1017
1018 Semaphore_Params_init(&semParams);
1019 return((void *)Semaphore_create(0, &semParams, NULL));
1020}
1021
1022/**
1023 * @b Description
1024 * @n
1025 * The function is used to block a task whose context a
1026 * RM instance is running within.
1027 *
1028 * @param[in] handle
1029 * Task blocking object handle.
1030 *
1031 * @retval
1032 * Not Applicable
1033 */
1034void Osal_rmTaskBlock(void *handle)
1035{
1036 Semaphore_pend((Semaphore_Handle)handle, BIOS_WAIT_FOREVER);
1037}
1038
1039/**
1040 * @b Description
1041 * @n
1042 * The function is used to unblock a task whose context a
1043 * RM instance is running within.
1044 *
1045 * @param[in] handle
1046 * Task blocking object handle.
1047 *
1048 * @retval
1049 * Not Applicable
1050 */
1051void Osal_rmTaskUnblock(void *handle)
1052{
1053 Semaphore_post((Semaphore_Handle)handle);
1054}
1055
1056/**
1057 * @b Description
1058 * @n
1059 * The function is used to delete a task blocking object
1060 * provided to a RM instance
1061 *
1062 * @param[in] handle
1063 * Task blocking object handle.
1064 *
1065 * @retval
1066 * Not Applicable
1067 */
1068void Osal_rmTaskBlockDelete(void *handle)
1069{
1070 Semaphore_delete((Semaphore_Handle *)&handle);
1071}
1072
1073/**
1074 * @b Description
1075 * @n
1076 * The function is the RM OSAL Logging API which logs
1077 * the messages on the console.
1078 *
1079 * @param[in] fmt
1080 * Formatted String.
1081 *
1082 * @retval
1083 * Not Applicable
1084 */
1085void Osal_rmLog (char *fmt, ... )
1086{
1087 VaList ap;
1088
1089 va_start(ap, fmt);
1090 System_vprintf(fmt, ap);
1091 va_end(ap);
1092}
1093
1094
1095
diff --git a/example/emacExample/k2l/armv7/bios/PA_emacExample_K2LArmBiosExampleProject.txt b/example/emacExample/k2l/armv7/bios/PA_emacExample_K2LArmBiosExampleProject.txt
new file mode 100644
index 0000000..e80b581
--- /dev/null
+++ b/example/emacExample/k2l/armv7/bios/PA_emacExample_K2LArmBiosExampleProject.txt
@@ -0,0 +1,24 @@
1-ccs.linkFile "PASS_INSTALL_PATH/ti/drv/pa/example/emacExample/src/cpsw_singlecore.c"
2-ccs.linkFile "PASS_INSTALL_PATH/ti/drv/pa/example/emacExample/src/pa_mgmt.c"
3-ccs.linkFile "PASS_INSTALL_PATH/ti/drv/pa/example/emacExample/src/cppi_qmss_mgmt.c"
4-ccs.linkFile "PASS_INSTALL_PATH/ti/drv/pa/example/emacExample/src/setuprm.c"
5-ccs.linkFile "PASS_INSTALL_PATH/ti/drv/pa/example/emacExample/src/view_ale_table.c"
6-ccs.linkFile "PASS_INSTALL_PATH/ti/drv/pa/example/emacExample/src/armv7/bios/framework.c"
7-ccs.linkFile "PASS_INSTALL_PATH/ti/drv/pa/example/emacExample/src/armv7/bios/fw_main.c"
8-ccs.linkFile "PASS_INSTALL_PATH/ti/drv/pa/example/emacExample/src/armv7/bios/cpsw_mgmt.c"
9-ccs.linkFile "PASS_INSTALL_PATH/ti/drv/pa/example/emacExample/k2l/armv7/bios/singlecore_osal.c"
10-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/device/k2l/policy_dsp-only.c"
11-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/device/k2l/policy_dsp_arm.c"
12-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/device/k2l/global-resource-list.c"
13-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/cppi/device/k2l/src/cppi_device.c"
14-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/qmss/device/k2l/src/qmss_device.c"
15-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/pa/device/k2l/src/nss_device.c"
16-ccs.linkFile "PDK_INSTALL_PATH/ti/csl/src/ip/sgmii/V0/csl_cpsgmii.c"
17-ccs.linkFile "PDK_INSTALL_PATH/ti/csl/src/ip/cpsw/V0/csl_cpsw_5gf.c"
18-ccs.linkFile "PDK_INSTALL_PATH/ti/csl/src/ip/serdes_sb/V0/csl_wiz8_sb_refclk125MHz_10bit_5Gbps.c"
19-ccs.linkFile "PDK_INSTALL_PATH/ti/csl/src/ip/serdes_sb/V0/csl_wiz8_sb_refclk125MHz_20bit_6p25Gbps.c"
20-ccs.linkFile "PDK_INSTALL_PATH/ti/csl/src/ip/serdes_sb/V0/csl_wiz8_sb_refclk156p25MHz_10bit_5Gbps.c"
21-ccs.linkFile "PDK_INSTALL_PATH/ti/csl/src/ip/serdes_sb/V0/csl_wiz8_sb_refclk156p25MHz_20bit_6p25Gbps.c"
22-ccs.linkFile "PASS_INSTALL_PATH/ti/drv/pa/example/emacExample/k2l/armv7/bios/cpsw_example_k2l.cfg"
23-ccs.setCompilerOptions "-c -mcpu=cortex-a15 -mtune=cortex-a15 -marm -mfloat-abi=hard -DSOC_K2L -DNSS_GEN2 -DNUM_PORTS=5 -D_LITTLE_ENDIAN=1 -g -gstrict-dwarf -Wall -MMD -MP -I${PDK_INSTALL_PATH} -I${PDK_INSTALL_PATH}/ti/drv/pa/example/emacExample/src -I${PASS_INSTALL_PATH}/ti/drv/pa/example/emacExample/src/armv7/bios -I${PDK_INSTALL_PATH}/ti/drv/cppi -I${PDK_INSTALL_PATH}/ti/drv/qmss" -rtsc.enableRtsc
24-ccs.setLinkerOptions " -lrdimon -lgcc -lm -lnosys -nostartfiles -static -Wl,--gc-sections -L$(XDCTOOLS)/packages/gnu/targets/arm/libs/install-native/arm-none-eabi/lib/fpu "
diff --git a/example/emacExample/k2l/armv7/bios/cpsw_example_k2l.cfg b/example/emacExample/k2l/armv7/bios/cpsw_example_k2l.cfg
new file mode 100644
index 0000000..00944fd
--- /dev/null
+++ b/example/emacExample/k2l/armv7/bios/cpsw_example_k2l.cfg
@@ -0,0 +1,145 @@
1/*
2 * Copyright 2015 by Texas Instruments Incorporated.
3 *
4 * All rights reserved. Property of Texas Instruments Incorporated.
5 * Restricted rights to use, duplicate or disclose this code are
6 * granted through contract.
7 *
8 */
9
10/*
11 * ======== cpsw_example.cfg ========
12 *
13 */
14
15/* Load all required BIOS/XDC runtime packages */
16var Memory = xdc.useModule('xdc.runtime.Memory');
17var BIOS = xdc.useModule('ti.sysbios.BIOS');
18var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
19var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
20var Log = xdc.useModule('xdc.runtime.Log');
21var LoggerBuf = xdc.useModule('xdc.runtime.LoggerBuf');
22var Task = xdc.useModule('ti.sysbios.knl.Task');
23var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');
24var Main = xdc.useModule('xdc.runtime.Main');
25var Defaults = xdc.useModule('xdc.runtime.Defaults');
26var Diags = xdc.useModule('xdc.runtime.Diags');
27var SysMin = xdc.useModule('xdc.runtime.SysMin');
28var System = xdc.useModule('xdc.runtime.System');
29var Text = xdc.useModule('xdc.runtime.Text');
30
31Task.defaultStackSize = 0x4000;
32
33/* Load the CPPI package */
34var Cppi = xdc.loadPackage('ti.drv.cppi');
35/* Load the QMSS package */
36var Qmss = xdc.loadPackage('ti.drv.qmss');
37
38/* Load the PA package */
39var devType = "k2l"
40var Pa = xdc.useModule('ti.drv.pa.Settings');
41Pa.deviceType = devType;
42
43/* Load the RM package */
44var Rm = xdc.loadPackage('ti.drv.rm');
45
46/*
47 * Program.argSize sets the size of the .args section.
48 * The examples don't use command line args so argSize is set to 0.
49 */
50Program.argSize = 0x0;
51
52/*
53 * The BIOS module will create the default heap for the system.
54 * Specify the size of this default heap.
55 */
56BIOS.heapSize = 8192 * 30;
57
58/*
59 * Build a custom SYS/BIOS library from sources.
60 */
61BIOS.libType = BIOS.LibType_Custom;
62
63/* System stack size (used by ISRs and Swis) */
64Program.stack = 0x20000;
65
66/* Circular buffer size for System_printf() */
67SysMin.bufSize = 0x400;
68
69/*
70 * Create and install logger for the whole system
71 */
72var loggerBufParams = new LoggerBuf.Params();
73loggerBufParams.numEntries = 32;
74var logger0 = LoggerBuf.create(loggerBufParams);
75Defaults.common$.logger = logger0;
76Main.common$.diags_INFO = Diags.ALWAYS_ON;
77
78System.SupportProxy = SysMin;
79var SemiHost = xdc.useModule('ti.sysbios.rts.gnu.SemiHostSupport');
80
81var Cache = xdc.useModule('ti.sysbios.family.arm.a15.Cache');
82var Mmu = xdc.useModule('ti.sysbios.family.arm.a15.Mmu');
83
84/* Enable the cache */
85Cache.enableCache = true;
86
87// Enable the MMU (Required for L1/L2 data caching)
88Mmu.enableMMU = true;
89
90// descriptor attribute structure
91var peripheralAttrs = new Mmu.DescriptorAttrs();
92
93Mmu.initDescAttrsMeta(peripheralAttrs);
94
95peripheralAttrs.type = Mmu.DescriptorType_BLOCK; // BLOCK descriptor
96peripheralAttrs.noExecute = true; // not executable
97peripheralAttrs.accPerm = 0; // read/write at PL1
98peripheralAttrs.attrIndx = 1; // MAIR0 Byte1 describes
99 // memory attributes for
100// Define the base address of the 2 MB page
101// the peripheral resides in.
102var peripheralBaseAddrs = [
103 { base: 0x02620000, size: 0x00001000 }, // bootcfg
104 { base: 0x0bc00000, size: 0x00100000 }, // MSMC config
105 { base: 0x26000000, size: 0x01000000 }, // NETCP memory
106 { base: 0x02a00000, size: 0x00100000 }, // QMSS config memory
107 { base: 0x23A00000, size: 0x00100000 }, // QMSS Data memory
108 { base: 0x02901000, size: 0x00002000 }, // SRIO pkt dma config memory
109 { base: 0x01f14000, size: 0x00007000 }, // AIF pkt dma config memory
110 { base: 0x021F0200, size: 0x00000600 }, // FFTC 0 pkt dma config memory
111 { base: 0x021F0a00, size: 0x00000600 }, // FFTC 4 pkt dma config memory
112 { base: 0x021F1200, size: 0x00000600 }, // FFTC 5 pkt dma config memory
113 { base: 0x021F4200, size: 0x00000600 }, // FFTC 1 pkt dma config memory
114 { base: 0x021F8200, size: 0x00000600 }, // FFTC 2 pkt dma config memory
115 { base: 0x021FC200, size: 0x00000600 }, // FFTC 3 pkt dma config memory
116 { base: 0x02554000, size: 0x00009000 } // BCP pkt dma config memory
117];
118
119// Configure the corresponding MMU page descriptor accordingly
120for (var i =0; i < peripheralBaseAddrs.length; i++)
121{
122 for (var j = 0; j < peripheralBaseAddrs[i].size; j += 0x200000)
123 {
124 var addr = peripheralBaseAddrs[i].base + j;
125 Mmu.setSecondLevelDescMeta(addr, addr, peripheralAttrs);
126 }
127}
128
129// Reconfigure DDR to use coherent address
130Mmu.initDescAttrsMeta(peripheralAttrs);
131
132peripheralAttrs.type = Mmu.DescriptorType_BLOCK;
133peripheralAttrs.shareable = 2; // outer-shareable (3=inner, 0=none)
134peripheralAttrs.accPerm = 1; // read/write at any privelege level
135peripheralAttrs.attrIndx = 2; // normal cacheable (0=no cache, 1=strict order)
136for (var vaddr = 0x80000000, paddr = 0x800000000; vaddr < 0x100000000; vaddr += 0x200000, paddr+= 0x200000)
137{
138 Mmu.setSecondLevelDescMeta(vaddr, paddr, peripheralAttrs);
139}
140// Add MSMC as coherent
141for (var addr = 0x0c000000; addr < 0x0c600000; addr += 0x200000)
142{
143 Mmu.setSecondLevelDescMeta(addr, addr, peripheralAttrs);
144}
145
diff --git a/example/emacExample/k2l/armv7/bios/singlecore_osal.c b/example/emacExample/k2l/armv7/bios/singlecore_osal.c
new file mode 100644
index 0000000..5f4353d
--- /dev/null
+++ b/example/emacExample/k2l/armv7/bios/singlecore_osal.c
@@ -0,0 +1,1095 @@
1/**
2 * @file singlecore_osal.c
3 *
4 * @brief
5 * This is a sample OS Abstraction Layer (AL) file implemented
6 * using XDC/BIOS APIs.
7 *
8 * System integrator is advised to review these implementations and
9 * modify them to suit it to application requirements.
10 *
11 * This OSAL implementation uses the <b> Approach 1 </b> documented.
12 *
13 * \par
14 * ============================================================================
15 * @n (C) Copyright 2009, Texas Instruments, Inc.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
19 * are met:
20 *
21 * Redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer.
23 *
24 * Redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the
27 * distribution.
28 *
29 * Neither the name of Texas Instruments Incorporated nor the names of
30 * its contributors may be used to endorse or promote products derived
31 * from this software without specific prior written permission.
32 *
33 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
34 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
35 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
36 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
37 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
38 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
39 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
40 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
41 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
42 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
43 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 *
45*/
46/* Standard C-native includes */
47#include <stdlib.h>
48#include <string.h>
49
50/* XDC/BIOS includes */
51#include <xdc/std.h>
52#include <xdc/runtime/IHeap.h>
53#include <xdc/runtime/System.h>
54#include <xdc/runtime/Memory.h>
55#include <xdc/runtime/Error.h>
56
57#include <ti/sysbios/BIOS.h>
58#include <ti/sysbios/hal/Hwi.h>
59#include <ti/sysbios/knl/Task.h>
60#include <ti/sysbios/knl/Semaphore.h>
61#include <ti/sysbios/heaps/HeapBuf.h>
62#include <ti/sysbios/heaps/HeapMem.h>
63
64#include <xdc/cfg/global.h>
65
66/* CSL CHIP, SEM Functional layer includes */
67#include <ti/csl/csl_chip.h>
68#include <ti/csl/csl_semAux.h>
69
70#ifdef _TMS320C6X
71/* CSL Cache module includes */
72#include <ti/csl/csl_cacheAux.h>
73/* CSL XMC module includes */
74#include <ti/csl/csl_xmcAux.h>
75#endif
76
77/**********************************************************************
78 ****************************** Defines *******************************
79 **********************************************************************/
80
81#define MAX_NUM_CORES 8
82
83/* Hardware Semaphore to synchronize access from
84 * multiple applications (PA applications and non-PASS applications)
85 * across different cores to the QMSS library.
86 */
87#define QMSS_HW_SEM 3
88
89/* Hardware Semaphore to synchronize access from
90 * multiple applications (PASS applications and non-PASS applications)
91 * across different cores to the CPPI library.
92 */
93#define CPPI_HW_SEM 4
94
95/* Hardware Semaphore to synchronize access from
96 * multiple applications (PASS applications and non-PASS applications)
97 * across different cores to the PA library.
98 */
99#define PA_HW_SEM 5
100
101#undef L2_CACHE
102#ifdef L2_CACHE
103 /* Invalidate L2 cache. This should invalidate L1D as well.
104 * Wait until operation is complete. */
105#define SYS_CACHE_INV(addr, size, code) CACHE_invL2 (addr, size, code)
106
107 /* Writeback L2 cache. This should Writeback L1D as well.
108 * Wait until operation is complete. */
109#define SYS_CACHE_WB(addr, size, code) CACHE_wbL2 (addr, size, code)
110
111#else
112 /* Invalidate L1D cache and wait until operation is complete.
113 * Use this approach if L2 cache is not enabled */
114#define SYS_CACHE_INV(addr, size, code) CACHE_invL1d (addr, size, code)
115 /* Writeback L1D cache and wait until operation is complete.
116 * Use this approach if L2 cache is not enabled */
117#define SYS_CACHE_WB(addr, size, code) CACHE_wbL1d (addr, size, code)
118
119#endif
120
121/**
122 * @b Description
123 * @n
124 * General Memory Barrier guarantees that all LOAD and STORE operations that were issued before the
125 * barrier occur before the LOAD and STORE operations issued after the barrier
126 *
127 */
128static inline void memBarrier(void) {__sync_synchronize();}
129
130/**********************************************************************
131 ************************** Global Variables **************************
132 **********************************************************************/
133UInt32 cpswCppiMallocCounter = 0;
134UInt32 cpswCppiFreeCounter = 0;
135UInt32 cpswQmssMallocCounter = 0;
136UInt32 cpswQmssFreeCounter = 0;
137uint32_t rmMallocCounter = 0;
138uint32_t rmFreeCounter = 0;
139UInt32 coreKey [MAX_NUM_CORES];
140
141/**********************************************************************
142 *********************** CPPI OSAL Functions **************************
143 **********************************************************************/
144
145/**
146 * ============================================================================
147 * @n@b Osal_cppiCsEnter
148 *
149 * @b brief
150 * @n This API ensures multi-core and multi-threaded
151 * synchronization to the caller.
152 *
153 * This is a BLOCKING API.
154 *
155 * This API ensures multi-core synchronization between
156 * multiple processes trying to access CPPI shared
157 * library at the same time.
158 *
159 * @param[in]
160 * @n None
161 *
162 * @return
163 * @n Handle used to lock critical section
164 * =============================================================================
165 */
166Ptr Osal_cppiCsEnter (Void)
167{
168#ifdef _TMS320C6X
169 uint32_t coreNum = CSL_chipReadReg (CSL_CHIP_DNUM);
170#else
171 uint32_t coreNum = 0;
172#endif
173 /* Get the hardware semaphore.
174 *
175 * Acquire Multi core CPPI synchronization lock
176 */
177 while ((CSL_semAcquireDirect (CPPI_HW_SEM)) == 0);
178
179 /* Disable all interrupts and OS scheduler.
180 *
181 * Acquire Multi threaded / process synchronization lock.
182 */
183 coreKey [coreNum] = Hwi_disable();
184
185 return NULL;
186}
187
188/**
189 * ============================================================================
190 * @n@b Osal_cppiCsExit
191 *
192 * @b brief
193 * @n This API needs to be called to exit a previously
194 * acquired critical section lock using @a Osal_cppiCsEnter ()
195 * API. It resets the multi-core and multi-threaded lock,
196 * enabling another process/core to grab CPPI access.
197 *
198 * @param[in] CsHandle
199 * Handle for unlocking critical section.
200 *
201 * @return None
202 * =============================================================================
203 */
204Void Osal_cppiCsExit (Ptr CsHandle)
205{
206#ifdef _TMS320C6X
207 uint32_t coreNum = CSL_chipReadReg (CSL_CHIP_DNUM);
208#else
209 uint32_t coreNum = 0;
210#endif
211 /* Enable all interrupts and enables the OS scheduler back on.
212 *
213 * Release multi-threaded / multi-process lock on this core.
214 */
215 Hwi_restore(coreKey [coreNum]);
216
217 /* Release the hardware semaphore
218 *
219 * Release multi-core lock.
220 */
221 CSL_semReleaseSemaphore (CPPI_HW_SEM);
222
223 return;
224}
225
226/**
227 * ============================================================================
228 * @n@b Osal_cppiMalloc
229 *
230 * @b brief
231 * @n This API allocates a memory block of a given
232 * size specified by input parameter 'num_bytes'.
233 *
234 * This API should allocate memory from shared memory if the test applications
235 * are to be run on multiple cores.
236 *
237 * @param[in] num_bytes
238 * Number of bytes to be allocated.
239 *
240 * @return
241 * Allocated block address
242 * =============================================================================
243 */
244Ptr Osal_cppiMalloc (UInt32 num_bytes)
245{
246 Error_Block errorBlock;
247
248 /* Increment the allocation counter. */
249 cpswCppiMallocCounter++;
250
251 /* Allocate memory. */
252 return Memory_alloc(NULL, num_bytes, 0, &errorBlock);
253}
254
255/**
256 * ============================================================================
257 * @n@b Osal_cppiFree
258 *
259 * @b brief
260 * @n This API frees and restores a given memory location
261 * pointer 'dataPtr' of size 'num_bytes' to its
262 * original heap location. Frees up memory allocated using
263 * @a Osal_cppiMalloc ()
264 *
265 * @param[in] dataPtr
266 * Pointer to the memory block to be cleaned up.
267 *
268 * @param[in] num_bytes
269 * Size of the memory block to be cleaned up.
270 *
271 * @return
272 * Not Applicable
273 * =============================================================================
274 */
275Void Osal_cppiFree (Ptr dataPtr, UInt32 num_bytes)
276{
277 /* Increment the free counter. */
278 cpswCppiFreeCounter++;
279
280 /* Free up the memory */
281 if (dataPtr)
282 {
283 /* Convert the global address to local address since
284 * thats what the heap understands.
285 */
286 Memory_free(NULL, dataPtr, num_bytes);
287 }
288}
289
290/**
291 * @b Description
292 * @n
293 * The function is used to indicate that a block of memory is
294 * about to be accessed. If the memory block is cached then this
295 * indicates that the application would need to ensure that the
296 * cache is updated with the data from the actual memory.
297 *
298 * @param[in] blockPtr
299 * Address of the block which is to be invalidated
300 *
301 * @param[in] size
302 * Size of the block to be invalidated
303
304 * @retval
305 * Not Applicable
306 */
307void Osal_cppiBeginMemAccess (void *blockPtr, uint32_t size)
308{
309#ifdef _TMS320C6X
310 uint32_t key;
311
312 /* Disable Interrupts */
313 key = Hwi_disable();
314
315 /* Cleanup the prefetch buffer also. */
316 CSL_XMC_invalidatePrefetchBuffer();
317
318 SYS_CACHE_INV (blockPtr, size, CACHE_FENCE_WAIT);
319
320 asm (" nop 4");
321 asm (" nop 4");
322 asm (" nop 4");
323 asm (" nop 4");
324
325 /* Reenable Interrupts. */
326 Hwi_restore(key);
327#endif
328 return;
329}
330
331/**
332 * @b Description
333 * @n
334 * The function is used to indicate that the block of memory has
335 * finished being accessed. If the memory block is cached then the
336 * application would need to ensure that the contents of the cache
337 * are updated immediately to the actual memory.
338 *
339 * @param[in] blockPtr
340 * Address of the block which is to be written back
341 *
342 * @param[in] size
343 * Size of the block to be written back
344
345 * @retval
346 * Not Applicable
347 */
348void Osal_cppiEndMemAccess (void *blockPtr, uint32_t size)
349{
350#ifdef _TMS320C6X
351 uint32_t key;
352
353 /* Disable Interrupts */
354 key = Hwi_disable();
355
356 SYS_CACHE_WB (blockPtr, size, CACHE_FENCE_WAIT);
357
358 asm (" nop 4");
359 asm (" nop 4");
360 asm (" nop 4");
361 asm (" nop 4");
362
363 /* Reenable Interrupts. */
364 Hwi_restore(key);
365#endif
366 return;
367}
368
369/**********************************************************************
370 *********************** QMSS OSAL Functions **************************
371 **********************************************************************/
372
373/**
374 * ============================================================================
375 * @n@b Osal_qmssCsEnter
376 *
377 * @b brief
378 * @n This API ensures multi-core and multi-threaded
379 * synchronization to the caller.
380 *
381 * This is a BLOCKING API.
382 *
383 * This API ensures multi-core synchronization between
384 * multiple processes trying to access QMSS shared
385 * library at the same time.
386 *
387 * @param[in] None
388 *
389 * @return
390 * Handle used to lock critical section
391 * =============================================================================
392 */
393Ptr Osal_qmssCsEnter (Void)
394{
395#ifdef _TMS320C6X
396 uint32_t coreNum = CSL_chipReadReg (CSL_CHIP_DNUM);
397#else
398 uint32_t coreNum = 0;
399#endif
400 /* Get the hardware semaphore.
401 *
402 * Acquire Multi core QMSS synchronization lock
403 */
404 while ((CSL_semAcquireDirect (QMSS_HW_SEM)) == 0);
405
406 /* Disable all interrupts and OS scheduler.
407 *
408 * Acquire Multi threaded / process synchronization lock.
409 */
410 coreKey [coreNum] = Hwi_disable();
411
412 return NULL;
413}
414
415/**
416 * ============================================================================
417 * @n@b Osal_qmssCsExit
418 *
419 * @b brief
420 * @n This API needs to be called to exit a previously
421 * acquired critical section lock using @a Osal_cpswQmssCsEnter ()
422 * API. It resets the multi-core and multi-threaded lock,
423 * enabling another process/core to grab QMSS access.
424 *
425 * @param[in] CsHandle
426 * Handle for unlocking critical section.
427 *
428 * @return None
429 * =============================================================================
430 */
431Void Osal_qmssCsExit (Ptr CsHandle)
432{
433#ifdef _TMS320C6X
434 uint32_t coreNum = CSL_chipReadReg (CSL_CHIP_DNUM);
435#else
436 uint32_t coreNum = 0;
437#endif
438 /* Enable all interrupts and enables the OS scheduler back on.
439 *
440 * Release multi-threaded / multi-process lock on this core.
441 */
442 Hwi_restore(coreKey [coreNum]);
443
444 /* Release the hardware semaphore
445 *
446 * Release multi-core lock.
447 */
448 CSL_semReleaseSemaphore (QMSS_HW_SEM);
449
450 return;
451}
452
453 /**
454 * ============================================================================
455 * @n@b Osal_qmssAccCsEnter
456 *
457 * @b brief
458 * @n This API ensures multi-core and multi-threaded
459 * synchronization to the caller.
460 *
461 * This is a BLOCKING API.
462 *
463 * This API ensures multi-core synchronization between
464 * multiple processes trying to access QMSS shared
465 * library at the same time.
466 *
467 * @param[in] None
468 *
469 * @return
470 * Handle used to lock critical section
471 * =============================================================================
472 */
473Ptr Osal_qmssAccCsEnter (Void)
474{
475 /* This is a suboptimal implementation for this OSAL, please refer to
476 * QMSS examples for optimal implementation of this function
477 */
478
479 return (Osal_qmssCsEnter());
480}
481
482/**
483 * ============================================================================
484 * @n@b Osal_qmssAccCsExit
485 *
486 * @b brief
487 * @n This API needs to be called to exit a previously
488 * acquired critical section lock using @a Osal_qmssAccCsEnter ()
489 * API. It resets the multi-core and multi-threaded lock,
490 * enabling another process/core to grab QMSS access.
491 *
492 * @param[in] CsHandle
493 * Handle for unlocking critical section.
494 *
495 * @return None
496 * =============================================================================
497 */
498Void Osal_qmssAccCsExit (Ptr CsHandle)
499{
500 /* This is a suboptimal implementation for this OSAL, please refer to
501 * QMSS examples for optimal implementation of this function
502 */
503 Osal_qmssCsExit(CsHandle);
504 return;
505}
506/**
507 * ============================================================================
508 * @n@b Osal_qmssMtCsEnter
509 *
510 * @b brief
511 * @n This API ensures ONLY multi-threaded
512 * synchronization to the QMSS user.
513 *
514 * This is a BLOCKING API.
515 *
516 * @param[in] None
517 *
518 * @return
519 * Handle used to lock critical section
520 * =============================================================================
521 */
522Ptr Osal_qmssMtCsEnter (Void)
523{
524 /* Disable all interrupts and OS scheduler.
525 *
526 * Acquire Multi threaded / process synchronization lock.
527 */
528 //coreKey [CSL_chipReadReg (CSL_CHIP_DNUM)] = Hwi_disable();
529
530 return NULL;
531}
532
533/**
534 * ============================================================================
535 * @n@b Osal_qmssMtCsExit
536 *
537 * @b brief
538 * @n This API needs to be called to exit a previously
539 * acquired critical section lock using @a Osal_cpswQmssMtCsEnter ()
540 * API. It resets the multi-threaded lock, enabling another process
541 * on the current core to grab it.
542 *
543 * @param[in] CsHandle
544 * Handle for unlocking critical section.
545 *
546 * @return None
547 * =============================================================================
548 */
549Void Osal_qmssMtCsExit (Ptr CsHandle)
550{
551 /* Enable all interrupts and enables the OS scheduler back on.
552 *
553 * Release multi-threaded / multi-process lock on this core.
554 */
555 //Hwi_restore(key);
556
557 return;
558}
559
560/**
561 * ============================================================================
562 * @n@b Osal_qmssMalloc
563 *
564 * @b brief
565 * @n This API allocates a memory block of a given
566 * size specified by input parameter 'num_bytes'.
567 *
568 * @param[in] num_bytes
569 * Number of bytes to be allocated.
570 *
571 * @return
572 * Allocated block address
573 * =============================================================================
574 */
575Ptr Osal_qmssMalloc (UInt32 num_bytes)
576{
577 Error_Block errorBlock;
578
579 /* Increment the allocation counter. */
580 cpswQmssMallocCounter++;
581
582 /* Allocate memory. */
583 return Memory_alloc(NULL, num_bytes, 0, &errorBlock);
584}
585
586/**
587 * ============================================================================
588 * @n@b Osal_qmssFree
589 *
590 * @b brief
591 * @n This API frees and restores a given memory location
592 * pointer 'dataPtr' of size 'num_bytes' to its
593 * original heap location. Frees up memory allocated using
594 * @a Osal_qmssMalloc ()
595 *
596 * @param[in] dataPtr
597 * Pointer to the memory block to be cleaned up.
598 *
599 * @param[in] num_bytes
600 * Size of the memory block to be cleaned up.
601 *
602 * @return
603 * Not Applicable
604 * =============================================================================
605 */
606Void Osal_qmssFree (Ptr dataPtr, UInt32 num_bytes)
607{
608 /* Increment the free counter. */
609 cpswQmssFreeCounter++;
610
611 /* Free up the memory */
612 if (dataPtr)
613 {
614 /* Convert the global address to local address since
615 * thats what the heap understands.
616 */
617 Memory_free(NULL, dataPtr, num_bytes);
618 }
619}
620
621/**
622 * @b Description
623 * @n
624 * The function is used to indicate that a block of memory is
625 * about to be accessed. If the memory block is cached then this
626 * indicates that the application would need to ensure that the
627 * cache is updated with the data from the actual memory.
628 *
629 * @param[in] blockPtr
630 * Address of the block which is to be invalidated
631 *
632 * @param[in] size
633 * Size of the block to be invalidated
634
635 * @retval
636 * Not Applicable
637 */
638void Osal_qmssBeginMemAccess (void *blockPtr, uint32_t size)
639{
640#ifdef _TMS320C6X
641 uint32_t key;
642
643 /* Disable Interrupts */
644 key = Hwi_disable();
645
646 /* Cleanup the prefetch buffer also. */
647 CSL_XMC_invalidatePrefetchBuffer();
648
649 SYS_CACHE_INV (blockPtr, size, CACHE_FENCE_WAIT);
650
651 asm (" nop 4");
652 asm (" nop 4");
653 asm (" nop 4");
654 asm (" nop 4");
655
656 /* Reenable Interrupts. */
657 Hwi_restore(key);
658#endif
659 return;
660}
661
662/**
663 * @b Description
664 * @n
665 * The function is used to indicate that the block of memory has
666 * finished being accessed. If the memory block is cached then the
667 * application would need to ensure that the contents of the cache
668 * are updated immediately to the actual memory.
669 *
670 * @param[in] blockPtr
671 * Address of the block which is to be written back
672 *
673 * @param[in] size
674 * Size of the block to be written back
675
676 * @retval
677 * Not Applicable
678 */
679void Osal_qmssEndMemAccess (void *blockPtr, uint32_t size)
680{
681#ifdef _TMS320C6X
682 uint32_t key;
683
684 /* Disable Interrupts */
685 key = Hwi_disable();
686
687 SYS_CACHE_WB (blockPtr, size, CACHE_FENCE_WAIT);
688
689 asm (" nop 4");
690 asm (" nop 4");
691 asm (" nop 4");
692 asm (" nop 4");
693
694 /* Reenable Interrupts. */
695 Hwi_restore(key);
696#endif
697 return;
698}
699
700/******************************************************************************
701* Function to issue memory barrier
702*
703* NOTE: QMSS unit tests are not using CPPI descriptors
704******************************************************************************/
705void* Osal_qmssMemBarrier(uint32_t QID, void *descAddr)
706{
707 /* Issue memory barrier */
708 memBarrier();
709 return descAddr;
710}
711
712/**********************************************************************
713 *********************** PASS OSAL Functions **************************
714 **********************************************************************/
715
716/**
717 * @brief This macro is used to alert the application that the PA is
718 * going to access table memory. The application must ensure
719 * cache coherency
720 *
721 *
722 * <b> Prototype: </b>
723 * The following is the C prototype for the expected OSAL API.
724 *
725 * @verbatim
726 void Osal_paBeginMemAccess (void* addr, uint32_t sizeWords)
727 @endverbatim
728 *
729 * <b> Parameters </b>
730 * @n The address of the table to be accessed
731 * @n The number of bytes in the table
732 *
733 * @note PA will make nested calls to this function for memory access
734 * protection of different memory tables.
735 */
736
737void Osal_paBeginMemAccess (Ptr addr, UInt32 size)
738{
739#ifdef _TMS320C6X
740 uint32_t key;
741
742 /* Disable Interrupts */
743 key = Hwi_disable();
744
745 /* Cleanup the prefetch buffer also. */
746 CSL_XMC_invalidatePrefetchBuffer();
747
748 SYS_CACHE_INV (addr, size, CACHE_FENCE_WAIT);
749
750 asm (" nop 4");
751 asm (" nop 4");
752 asm (" nop 4");
753 asm (" nop 4");
754
755 /* Reenable Interrupts. */
756 Hwi_restore(key);
757#endif
758}
759
760/**
761 * @brief This macro is used to alert the application that the PA
762 * has completed access to table memory. This call will always
763 * be made following a call to Osal_paBeginMemAccess and have
764 * the same parameters
765 *
766 * <b> Prototype: </b>
767 * The following is the C prototype for the expected OSAL API.
768 *
769 * @verbatim
770 void Osal_paEndMemAccess (void* addr, uint32_t sizeWords)
771 @endverbatim
772 *
773 * <b> Parameters </b>
774 * @n The address of the table to be accessed
775 * @n The number of bytes in the table
776 *
777 * @note PA will make nested calls to this function for memory access
778 * protection of different memory tables.
779 */
780
781void Osal_paEndMemAccess (Ptr addr, UInt32 size)
782{
783#ifdef _TMS320C6X
784 uint32_t key;
785
786 /* Disable Interrupts */
787 key = Hwi_disable();
788
789 SYS_CACHE_WB (addr, size, CACHE_FENCE_WAIT);
790
791 asm (" nop 4");
792 asm (" nop 4");
793 asm (" nop 4");
794 asm (" nop 4");
795
796 /* Reenable Interrupts. */
797 Hwi_restore(key);
798#endif
799}
800
801
802/**
803 * @b Description
804 * @n
805 * The function is used to enter a critical section.
806 * Function protects against
807 *
808 * access from multiple threads on single core
809 * and
810 * access from multiple cores
811 *
812 * @param[in] key
813 * Key used to lock the critical section.
814 *
815 * @retval
816 * Not Applicable
817 */
818Void Osal_paMtCsEnter (uint32_t *key)
819{
820
821 /* Get the hardware semaphore.
822 *
823 * Acquire Multi core PA synchronization lock
824 */
825 while ((CSL_semAcquireDirect (PA_HW_SEM)) == 0);
826 *key = 0;
827}
828
829/**
830 * @b Description
831 * @n
832 * The function is used to exit a critical section
833 * protected using Osal_salldCsEnter() API.
834 *
835 * @param[in] key
836 * Key used to unlock the critical section.
837 *
838 * @retval
839 * Not Applicable
840 */
841Void Osal_paMtCsExit (uint32_t key)
842{
843 /* Release the hardware semaphore */
844 CSL_semReleaseSemaphore (PA_HW_SEM);
845}
846
847/**
848 * @b Description
849 * @n
850 * The function is used to allocate a memory block of the specified size.
851 *
852 * @param[in] num_bytes
853 * Number of bytes to be allocated.
854 *
855 * @retval
856 * Allocated block address
857 */
858void *Osal_rmMalloc (uint32_t num_bytes)
859{
860 Error_Block errorBlock;
861
862 /* Increment the allocation counter. */
863 rmMallocCounter++;
864
865 /* Allocate memory. */
866 return Memory_alloc(NULL, num_bytes, 0, &errorBlock);
867}
868
869/**
870 * @b Description
871 * @n
872 * The function is used to free a memory block of the specified size.
873 *
874 * @param[in] ptr
875 * Pointer to the memory block to be cleaned up.
876 *
877 * @param[in] size
878 * Size of the memory block to be cleaned up.
879 *
880 * @retval
881 * Not Applicable
882 */
883void Osal_rmFree (void *ptr, uint32_t size)
884{
885 /* Increment the free counter. */
886 rmFreeCounter++;