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authorAravind Batni2016-07-15 04:36:42 -0500
committerAravind Batni2016-07-15 04:36:42 -0500
commitcd56a523b6faf784c198a11b3fa6bafd1fba0f9b (patch)
treeac3ab05b10303e3b1f306aeb89c8d2b79fc3cc8d
parentd3f3f5d93d3febc24099974bbc77e67c80a83b1e (diff)
downloadpa-lld-cd56a523b6faf784c198a11b3fa6bafd1fba0f9b.tar.gz
pa-lld-cd56a523b6faf784c198a11b3fa6bafd1fba0f9b.tar.xz
pa-lld-cd56a523b6faf784c198a11b3fa6bafd1fba0f9b.zip
support linux bin format request, implements PRSDK-971
Signed-off-by: Aravind Batni <aravindbr@ti.com>
-rw-r--r--fw/classify1_0_bin.c4
-rw-r--r--fw/classify1_1_bin.c4
-rw-r--r--fw/classify1_2_bin.c4
-rw-r--r--fw/classify2_bin.c4
-rw-r--r--fw/pam_bin.c4
-rwxr-xr-xfw/v0/build.sh6
-rw-r--r--fw/v0/classify1_0.bibbin6764 -> 6764 bytes
-rw-r--r--fw/v0/classify1_0.p1
-rw-r--r--fw/v0/classify1_0_bin.c4
-rw-r--r--fw/v0/classify1_1.bibbin6728 -> 6728 bytes
-rw-r--r--fw/v0/classify1_1.p1
-rw-r--r--fw/v0/classify1_1_bin.c4
-rw-r--r--fw/v0/classify1_2.bibbin6728 -> 6728 bytes
-rw-r--r--fw/v0/classify1_2.p1
-rw-r--r--fw/v0/classify1_2_bin.c4
-rw-r--r--fw/v0/classify2.bibbin4100 -> 4100 bytes
-rw-r--r--fw/v0/classify2.p1
-rw-r--r--fw/v0/classify2_bin.c4
-rw-r--r--fw/v0/ks2_pa_pdsp0_classify1.binbin0 -> 6796 bytes
-rw-r--r--fw/v0/ks2_pa_pdsp1_classify1.binbin0 -> 6760 bytes
-rw-r--r--fw/v0/ks2_pa_pdsp2_classify1.binbin0 -> 6760 bytes
-rw-r--r--fw/v0/ks2_pa_pdsp3_classify2.binbin0 -> 4132 bytes
-rw-r--r--fw/v0/ks2_pa_pdsp4_pam.binbin0 -> 7412 bytes
-rw-r--r--fw/v0/ks2_pa_pdsp5_pam.binbin0 -> 7412 bytes
-rw-r--r--fw/v0/pa2bin.c100
-rw-r--r--fw/v0/pam.bibbin7380 -> 7380 bytes
-rw-r--r--fw/v0/pam.p1
-rw-r--r--fw/v0/pam_bin.c4
-rw-r--r--fw/v0/pdsp_ver.h70
-rw-r--r--fw/v0/pm_config.h3
-rwxr-xr-xfw/v1/build.sh7
-rw-r--r--fw/v1/classify1.p1
-rw-r--r--fw/v1/classify2.p1
-rw-r--r--fw/v1/classify3.p1
-rw-r--r--fw/v1/efp.p1
-rw-r--r--fw/v1/eg0_pdsp0.bibbin4112 -> 4112 bytes
-rw-r--r--fw/v1/eg0_pdsp0.p1
-rw-r--r--fw/v1/eg0_pdsp1.bibbin8240 -> 8240 bytes
-rw-r--r--fw/v1/eg0_pdsp1.p1
-rw-r--r--fw/v1/eg0_pdsp2.bibbin7608 -> 7608 bytes
-rw-r--r--fw/v1/eg0_pdsp2.p1
-rw-r--r--fw/v1/eg1_pdsp0.bibbin5728 -> 5728 bytes
-rw-r--r--fw/v1/eg1_pdsp0.p1
-rw-r--r--fw/v1/eg2_pdsp0.bibbin6716 -> 6716 bytes
-rw-r--r--fw/v1/eg2_pdsp0.p1
-rw-r--r--fw/v1/in0_pdsp0.bibbin7160 -> 7160 bytes
-rw-r--r--fw/v1/in0_pdsp0.p1
-rw-r--r--fw/v1/in0_pdsp1.bibbin8324 -> 8324 bytes
-rw-r--r--fw/v1/in0_pdsp1.p1
-rw-r--r--fw/v1/in1_pdsp0.bibbin7304 -> 7304 bytes
-rw-r--r--fw/v1/in1_pdsp0.p1
-rw-r--r--fw/v1/in1_pdsp1.bibbin5580 -> 5580 bytes
-rw-r--r--fw/v1/in1_pdsp1.p1
-rw-r--r--fw/v1/in2_pdsp0.bibbin5420 -> 5420 bytes
-rw-r--r--fw/v1/in2_pdsp0.p1
-rw-r--r--fw/v1/in3_pdsp0.bibbin6772 -> 6772 bytes
-rw-r--r--fw/v1/in3_pdsp0.p1
-rw-r--r--fw/v1/in4_pdsp0.bibbin7264 -> 7264 bytes
-rw-r--r--fw/v1/in4_pdsp0.p1
-rw-r--r--fw/v1/in4_pdsp1.bibbin4932 -> 4932 bytes
-rw-r--r--fw/v1/in4_pdsp1.p1
-rw-r--r--fw/v1/ks2_pa_eg0_pdsp0.binbin0 -> 4256 bytes
-rw-r--r--fw/v1/ks2_pa_eg0_pdsp1.binbin0 -> 8384 bytes
-rw-r--r--fw/v1/ks2_pa_eg0_pdsp2.binbin0 -> 7752 bytes
-rw-r--r--fw/v1/ks2_pa_eg1_pdsp0.binbin0 -> 5872 bytes
-rw-r--r--fw/v1/ks2_pa_eg2_pdsp0.binbin0 -> 6860 bytes
-rw-r--r--fw/v1/ks2_pa_in0_pdsp0.binbin0 -> 7304 bytes
-rw-r--r--fw/v1/ks2_pa_in0_pdsp1.binbin0 -> 8468 bytes
-rw-r--r--fw/v1/ks2_pa_in1_pdsp0.binbin0 -> 7448 bytes
-rw-r--r--fw/v1/ks2_pa_in1_pdsp1.binbin0 -> 5724 bytes
-rw-r--r--fw/v1/ks2_pa_in2_pdsp0.binbin0 -> 5564 bytes
-rw-r--r--fw/v1/ks2_pa_in3_pdsp0.binbin0 -> 6916 bytes
-rw-r--r--fw/v1/ks2_pa_in4_pdsp0.binbin0 -> 7408 bytes
-rw-r--r--fw/v1/ks2_pa_in4_pdsp1.binbin0 -> 5076 bytes
-rw-r--r--fw/v1/ks2_pa_post_pdsp0.binbin0 -> 5556 bytes
-rw-r--r--fw/v1/ks2_pa_post_pdsp1.binbin0 -> 3872 bytes
-rw-r--r--fw/v1/pa2_eg0_pdsp0_bin.c4
-rw-r--r--fw/v1/pa2_eg0_pdsp1_bin.c4
-rw-r--r--fw/v1/pa2_eg0_pdsp2_bin.c4
-rw-r--r--fw/v1/pa2_eg1_pdsp0_bin.c4
-rw-r--r--fw/v1/pa2_eg2_pdsp0_bin.c4
-rw-r--r--fw/v1/pa2_in0_pdsp0_bin.c4
-rw-r--r--fw/v1/pa2_in0_pdsp1_bin.c4
-rw-r--r--fw/v1/pa2_in1_pdsp0_bin.c4
-rw-r--r--fw/v1/pa2_in1_pdsp1_bin.c4
-rw-r--r--fw/v1/pa2_in2_pdsp0_bin.c4
-rw-r--r--fw/v1/pa2_in3_pdsp0_bin.c4
-rw-r--r--fw/v1/pa2_in4_pdsp0_bin.c4
-rw-r--r--fw/v1/pa2_in4_pdsp1_bin.c4
-rw-r--r--fw/v1/pa2_post_pdsp0_bin.c4
-rw-r--r--fw/v1/pa2_post_pdsp1_bin.c4
-rw-r--r--fw/v1/pa2bin.c127
-rw-r--r--fw/v1/pdsp_ver.h70
-rw-r--r--fw/v1/pm_config.h3
-rw-r--r--fw/v1/post_pdsp0.bibbin5412 -> 5412 bytes
-rw-r--r--fw/v1/post_pdsp0.p1
-rw-r--r--fw/v1/post_pdsp1.bibbin3728 -> 3728 bytes
-rw-r--r--fw/v1/post_pdsp1.p1
-rw-r--r--package.xdc2
-rw-r--r--paver.h4
-rw-r--r--[-rwxr-xr-x]src/Module.xs6
-rw-r--r--[-rwxr-xr-x]src/v0/pa.c62
-rw-r--r--src/v0/paconst.c101
-rw-r--r--[-rwxr-xr-x]src/v0/pafrm.h0
-rw-r--r--[-rwxr-xr-x]src/v1/pa.c555
-rw-r--r--src/v1/paconst.c595
-rw-r--r--[-rwxr-xr-x]src/v1/pafrm.h0
107 files changed, 1171 insertions, 664 deletions
diff --git a/fw/classify1_0_bin.c b/fw/classify1_0_bin.c
index 8f28650..f5c214a 100644
--- a/fw/classify1_0_bin.c
+++ b/fw/classify1_0_bin.c
@@ -72,7 +72,7 @@
72const uint32_t c1_0[] = { 72const uint32_t c1_0[] = {
73 0x21008a00, 73 0x21008a00,
74 0xbabe0001, 74 0xbabe0001,
75 0x03000112, 75 0x03000200,
76 0x24505084, 76 0x24505084,
77 0x108484c4, 77 0x108484c4,
78 0x10e4e4e5, 78 0x10e4e4e5,
@@ -222,7 +222,7 @@ const uint32_t c1_0[] = {
222 0x2eff819d, 222 0x2eff819d,
223 0x2eff819c, 223 0x2eff819c,
224 0x9100171d, 224 0x9100171d,
225 0x24011282, 225 0x24020082,
226 0x240300c2, 226 0x240300c2,
227 0x81043782, 227 0x81043782,
228 0xc909ff06, 228 0xc909ff06,
diff --git a/fw/classify1_1_bin.c b/fw/classify1_1_bin.c
index 415f115..25ad624 100644
--- a/fw/classify1_1_bin.c
+++ b/fw/classify1_1_bin.c
@@ -73,7 +73,7 @@
73const uint32_t c1_1[] = { 73const uint32_t c1_1[] = {
74 0x21000300, 74 0x21000300,
75 0xbabe0001, 75 0xbabe0001,
76 0x03000112, 76 0x03000200,
77 0x2301b29e, 77 0x2301b29e,
78 0x2eff8582, 78 0x2eff8582,
79 0x8104a482, 79 0x8104a482,
@@ -84,7 +84,7 @@ const uint32_t c1_1[] = {
84 0x2eff819d, 84 0x2eff819d,
85 0x2eff819c, 85 0x2eff819c,
86 0x9100171d, 86 0x9100171d,
87 0x24011282, 87 0x24020082,
88 0x240300c2, 88 0x240300c2,
89 0x81043782, 89 0x81043782,
90 0xc901ff0f, 90 0xc901ff0f,
diff --git a/fw/classify1_2_bin.c b/fw/classify1_2_bin.c
index ec03b94..ab6d7b6 100644
--- a/fw/classify1_2_bin.c
+++ b/fw/classify1_2_bin.c
@@ -74,7 +74,7 @@
74const uint32_t c1_2[] = { 74const uint32_t c1_2[] = {
75 0x21000300, 75 0x21000300,
76 0xbabe0001, 76 0xbabe0001,
77 0x03000112, 77 0x03000200,
78 0x2301b29e, 78 0x2301b29e,
79 0x2eff8582, 79 0x2eff8582,
80 0x8104a482, 80 0x8104a482,
@@ -85,7 +85,7 @@ const uint32_t c1_2[] = {
85 0x2eff819d, 85 0x2eff819d,
86 0x2eff819c, 86 0x2eff819c,
87 0x9100171d, 87 0x9100171d,
88 0x24011282, 88 0x24020082,
89 0x240300c2, 89 0x240300c2,
90 0x81043782, 90 0x81043782,
91 0xc901ff0f, 91 0xc901ff0f,
diff --git a/fw/classify2_bin.c b/fw/classify2_bin.c
index d1a3d53..d71301b 100644
--- a/fw/classify2_bin.c
+++ b/fw/classify2_bin.c
@@ -74,7 +74,7 @@
74const uint32_t c2[] = { 74const uint32_t c2[] = {
75 0x21000300, 75 0x21000300,
76 0xbabe0002, 76 0xbabe0002,
77 0x03000112, 77 0x03000200,
78 0x2300e99e, 78 0x2300e99e,
79 0x2eff8582, 79 0x2eff8582,
80 0x8104a482, 80 0x8104a482,
@@ -85,7 +85,7 @@ const uint32_t c2[] = {
85 0x2eff819d, 85 0x2eff819d,
86 0x2eff819c, 86 0x2eff819c,
87 0x9100175d, 87 0x9100175d,
88 0x24011282, 88 0x24020082,
89 0x240300c2, 89 0x240300c2,
90 0x81043782, 90 0x81043782,
91 0x5100fc03, 91 0x5100fc03,
diff --git a/fw/pam_bin.c b/fw/pam_bin.c
index 819f0ea..ec88ddf 100644
--- a/fw/pam_bin.c
+++ b/fw/pam_bin.c
@@ -74,7 +74,7 @@
74const uint32_t m[] = { 74const uint32_t m[] = {
75 0x21000300, 75 0x21000300,
76 0xbabe0003, 76 0xbabe0003,
77 0x03000112, 77 0x03000200,
78 0x2eff8582, 78 0x2eff8582,
79 0x8104a482, 79 0x8104a482,
80 0x240001e2, 80 0x240001e2,
@@ -84,7 +84,7 @@ const uint32_t m[] = {
84 0x9100171d, 84 0x9100171d,
85 0x11017d7d, 85 0x11017d7d,
86 0x2400005d, 86 0x2400005d,
87 0x24011282, 87 0x24020082,
88 0x240300c2, 88 0x240300c2,
89 0x81043782, 89 0x81043782,
90 0x2eff8780, 90 0x2eff8780,
diff --git a/fw/v0/build.sh b/fw/v0/build.sh
index 42907cf..e1d8ab7 100755
--- a/fw/v0/build.sh
+++ b/fw/v0/build.sh
@@ -38,3 +38,9 @@ cp classify1_1_bin.c ..
38cp classify1_2_bin.c .. 38cp classify1_2_bin.c ..
39cp classify2_bin.c .. 39cp classify2_bin.c ..
40cp pam_bin.c .. 40cp pam_bin.c ..
41
42# rem create the bin files for linux
43gcc -I../../../../.. -I../.. -I../../src/v0 pa2bin.c
44./a.out
45rm a.out
46
diff --git a/fw/v0/classify1_0.bib b/fw/v0/classify1_0.bib
index 54c4dee..77ce38d 100644
--- a/fw/v0/classify1_0.bib
+++ b/fw/v0/classify1_0.bib
Binary files differ
diff --git a/fw/v0/classify1_0.p b/fw/v0/classify1_0.p
index 4a79584..1203aa6 100644
--- a/fw/v0/classify1_0.p
+++ b/fw/v0/classify1_0.p
@@ -57,6 +57,7 @@
57// 57//
58 58
59#include "pm_config.h" 59#include "pm_config.h"
60#include "pdsp_ver.h"
60#include "pdsp_mem.h" 61#include "pdsp_mem.h"
61#define PASS_GLOBAL_INIT 62#define PASS_GLOBAL_INIT
62#define PASS_PROC_LUT1 63#define PASS_PROC_LUT1
diff --git a/fw/v0/classify1_0_bin.c b/fw/v0/classify1_0_bin.c
index 8f28650..f5c214a 100644
--- a/fw/v0/classify1_0_bin.c
+++ b/fw/v0/classify1_0_bin.c
@@ -72,7 +72,7 @@
72const uint32_t c1_0[] = { 72const uint32_t c1_0[] = {
73 0x21008a00, 73 0x21008a00,
74 0xbabe0001, 74 0xbabe0001,
75 0x03000112, 75 0x03000200,
76 0x24505084, 76 0x24505084,
77 0x108484c4, 77 0x108484c4,
78 0x10e4e4e5, 78 0x10e4e4e5,
@@ -222,7 +222,7 @@ const uint32_t c1_0[] = {
222 0x2eff819d, 222 0x2eff819d,
223 0x2eff819c, 223 0x2eff819c,
224 0x9100171d, 224 0x9100171d,
225 0x24011282, 225 0x24020082,
226 0x240300c2, 226 0x240300c2,
227 0x81043782, 227 0x81043782,
228 0xc909ff06, 228 0xc909ff06,
diff --git a/fw/v0/classify1_1.bib b/fw/v0/classify1_1.bib
index 5f9fc1b..7a9264d 100644
--- a/fw/v0/classify1_1.bib
+++ b/fw/v0/classify1_1.bib
Binary files differ
diff --git a/fw/v0/classify1_1.p b/fw/v0/classify1_1.p
index 663328a..1a3dcd0 100644
--- a/fw/v0/classify1_1.p
+++ b/fw/v0/classify1_1.p
@@ -57,6 +57,7 @@
57// 57//
58 58
59#include "pm_config.h" 59#include "pm_config.h"
60#include "pdsp_ver.h"
60#include "pdsp_mem.h" 61#include "pdsp_mem.h"
61#define PASS_PROC_LUT1 62#define PASS_PROC_LUT1
62#define PASS_PROC_L3 63#define PASS_PROC_L3
diff --git a/fw/v0/classify1_1_bin.c b/fw/v0/classify1_1_bin.c
index 415f115..25ad624 100644
--- a/fw/v0/classify1_1_bin.c
+++ b/fw/v0/classify1_1_bin.c
@@ -73,7 +73,7 @@
73const uint32_t c1_1[] = { 73const uint32_t c1_1[] = {
74 0x21000300, 74 0x21000300,
75 0xbabe0001, 75 0xbabe0001,
76 0x03000112, 76 0x03000200,
77 0x2301b29e, 77 0x2301b29e,
78 0x2eff8582, 78 0x2eff8582,
79 0x8104a482, 79 0x8104a482,
@@ -84,7 +84,7 @@ const uint32_t c1_1[] = {
84 0x2eff819d, 84 0x2eff819d,
85 0x2eff819c, 85 0x2eff819c,
86 0x9100171d, 86 0x9100171d,
87 0x24011282, 87 0x24020082,
88 0x240300c2, 88 0x240300c2,
89 0x81043782, 89 0x81043782,
90 0xc901ff0f, 90 0xc901ff0f,
diff --git a/fw/v0/classify1_2.bib b/fw/v0/classify1_2.bib
index 53899a6..fe543c4 100644
--- a/fw/v0/classify1_2.bib
+++ b/fw/v0/classify1_2.bib
Binary files differ
diff --git a/fw/v0/classify1_2.p b/fw/v0/classify1_2.p
index 99e907f..9362a72 100644
--- a/fw/v0/classify1_2.p
+++ b/fw/v0/classify1_2.p
@@ -57,6 +57,7 @@
57// 57//
58 58
59#include "pm_config.h" 59#include "pm_config.h"
60#include "pdsp_ver.h"
60#include "pdsp_mem.h" 61#include "pdsp_mem.h"
61#define PASS_PROC_LUT1 62#define PASS_PROC_LUT1
62#define PASS_PROC_L3 63#define PASS_PROC_L3
diff --git a/fw/v0/classify1_2_bin.c b/fw/v0/classify1_2_bin.c
index ec03b94..ab6d7b6 100644
--- a/fw/v0/classify1_2_bin.c
+++ b/fw/v0/classify1_2_bin.c
@@ -74,7 +74,7 @@
74const uint32_t c1_2[] = { 74const uint32_t c1_2[] = {
75 0x21000300, 75 0x21000300,
76 0xbabe0001, 76 0xbabe0001,
77 0x03000112, 77 0x03000200,
78 0x2301b29e, 78 0x2301b29e,
79 0x2eff8582, 79 0x2eff8582,
80 0x8104a482, 80 0x8104a482,
@@ -85,7 +85,7 @@ const uint32_t c1_2[] = {
85 0x2eff819d, 85 0x2eff819d,
86 0x2eff819c, 86 0x2eff819c,
87 0x9100171d, 87 0x9100171d,
88 0x24011282, 88 0x24020082,
89 0x240300c2, 89 0x240300c2,
90 0x81043782, 90 0x81043782,
91 0xc901ff0f, 91 0xc901ff0f,
diff --git a/fw/v0/classify2.bib b/fw/v0/classify2.bib
index 6ae325f..16cb2a6 100644
--- a/fw/v0/classify2.bib
+++ b/fw/v0/classify2.bib
Binary files differ
diff --git a/fw/v0/classify2.p b/fw/v0/classify2.p
index 857668d..fc21d90 100644
--- a/fw/v0/classify2.p
+++ b/fw/v0/classify2.p
@@ -69,6 +69,7 @@
69#include "pdsp_mem.h" 69#include "pdsp_mem.h"
70#include "pdsp_subs.h" 70#include "pdsp_subs.h"
71#include "pm_config.h" 71#include "pm_config.h"
72#include "pdsp_ver.h"
72#include "pm_constants.h" 73#include "pm_constants.h"
73#include "parsescope.h" 74#include "parsescope.h"
74 75
diff --git a/fw/v0/classify2_bin.c b/fw/v0/classify2_bin.c
index d1a3d53..d71301b 100644
--- a/fw/v0/classify2_bin.c
+++ b/fw/v0/classify2_bin.c
@@ -74,7 +74,7 @@
74const uint32_t c2[] = { 74const uint32_t c2[] = {
75 0x21000300, 75 0x21000300,
76 0xbabe0002, 76 0xbabe0002,
77 0x03000112, 77 0x03000200,
78 0x2300e99e, 78 0x2300e99e,
79 0x2eff8582, 79 0x2eff8582,
80 0x8104a482, 80 0x8104a482,
@@ -85,7 +85,7 @@ const uint32_t c2[] = {
85 0x2eff819d, 85 0x2eff819d,
86 0x2eff819c, 86 0x2eff819c,
87 0x9100175d, 87 0x9100175d,
88 0x24011282, 88 0x24020082,
89 0x240300c2, 89 0x240300c2,
90 0x81043782, 90 0x81043782,
91 0x5100fc03, 91 0x5100fc03,
diff --git a/fw/v0/ks2_pa_pdsp0_classify1.bin b/fw/v0/ks2_pa_pdsp0_classify1.bin
new file mode 100644
index 0000000..3caa355
--- /dev/null
+++ b/fw/v0/ks2_pa_pdsp0_classify1.bin
Binary files differ
diff --git a/fw/v0/ks2_pa_pdsp1_classify1.bin b/fw/v0/ks2_pa_pdsp1_classify1.bin
new file mode 100644
index 0000000..6c3f0c6
--- /dev/null
+++ b/fw/v0/ks2_pa_pdsp1_classify1.bin
Binary files differ
diff --git a/fw/v0/ks2_pa_pdsp2_classify1.bin b/fw/v0/ks2_pa_pdsp2_classify1.bin
new file mode 100644
index 0000000..2a66aff
--- /dev/null
+++ b/fw/v0/ks2_pa_pdsp2_classify1.bin
Binary files differ
diff --git a/fw/v0/ks2_pa_pdsp3_classify2.bin b/fw/v0/ks2_pa_pdsp3_classify2.bin
new file mode 100644
index 0000000..f384073
--- /dev/null
+++ b/fw/v0/ks2_pa_pdsp3_classify2.bin
Binary files differ
diff --git a/fw/v0/ks2_pa_pdsp4_pam.bin b/fw/v0/ks2_pa_pdsp4_pam.bin
new file mode 100644
index 0000000..8d92ee4
--- /dev/null
+++ b/fw/v0/ks2_pa_pdsp4_pam.bin
Binary files differ
diff --git a/fw/v0/ks2_pa_pdsp5_pam.bin b/fw/v0/ks2_pa_pdsp5_pam.bin
new file mode 100644
index 0000000..2042462
--- /dev/null
+++ b/fw/v0/ks2_pa_pdsp5_pam.bin
Binary files differ
diff --git a/fw/v0/pa2bin.c b/fw/v0/pa2bin.c
new file mode 100644
index 0000000..3cad6a6
--- /dev/null
+++ b/fw/v0/pa2bin.c
@@ -0,0 +1,100 @@
1#include <stdio.h>
2#include <stdlib.h>
3#include <string.h>
4#include "pa.h"
5#include "pdsp_ver.h"
6#include "paconst.c"
7
8#define DEVICE_PA_NUM_PDSPS (6U)
9#define PA_PDSP_CONST_NUM_REG (4U)
10#define PASS_VER_STR_LEN (16U)
11
12typedef unsigned int u32;
13
14/* header to the firmware blob */
15struct pa_pdsp_firmware {
16 char version[PASS_VER_STR_LEN];
17 u32 constants[PA_PDSP_CONST_NUM_REG];
18};
19
20static char *versions[DEVICE_PA_NUM_PDSPS] = {
21 PASS_VERSION_STR,
22 PASS_VERSION_STR,
23 PASS_VERSION_STR,
24 PASS_VERSION_STR,
25 PASS_VERSION_STR,
26 PASS_VERSION_STR
27};
28static char *pdsp_in_file_names[DEVICE_PA_NUM_PDSPS] = {
29 "classify1_0.bib",
30 "classify1_1.bib",
31 "classify1_2.bib",
32 "classify2.bib",
33 "pam.bib",
34 "pam.bib",
35};
36
37static char *pdsp_out_file_names[DEVICE_PA_NUM_PDSPS] = {
38 "ks2_pa_pdsp0_classify1",
39 "ks2_pa_pdsp1_classify1",
40 "ks2_pa_pdsp2_classify1",
41 "ks2_pa_pdsp3_classify2",
42 "ks2_pa_pdsp4_pam",
43 "ks2_pa_pdsp5_pam",
44};
45
46int main(int argc, char **argv)
47{
48 unsigned long b_sz, total = 0;
49 struct pa_pdsp_firmware pdsp;
50 char in_file_name[128];
51 char out_file_name[128];
52 char buf[1024];
53 char *pc;
54 FILE *outfp, *infp;
55 int j, i;
56 int size;
57
58 for (i = 0; i < DEVICE_PA_NUM_PDSPS; i++) {
59 if (!pdsp_in_file_names[i])
60 continue;
61 bzero(in_file_name, sizeof(in_file_name));
62 bzero(out_file_name, sizeof(out_file_name));
63 strcpy(in_file_name, (char *)pdsp_in_file_names[i]);
64 strcpy(out_file_name, (char *)pdsp_out_file_names[i]);
65 pc = &out_file_name[strlen(out_file_name)];
66#if 0
67 strcat(pc, "-");
68 strcat(pc, (char *)versions[i]);
69#endif
70 strcat(pc, ".bin");
71 outfp=fopen(out_file_name,"wb");
72 infp=fopen(in_file_name,"rb");
73 printf("input file: %s\n",in_file_name);
74 printf("output file: %s\n",out_file_name);
75 if (!outfp)
76 {
77 printf("Unable to open output file! %s", out_file_name);
78 exit(1);
79 }
80
81 if (!infp)
82 {
83 printf("Unable to open input file! %s", in_file_name);
84 fclose(outfp);
85 exit(2);
86 }
87
88 strncpy((char *)&pdsp.version[0], (char *)versions[i], PASS_VER_STR_LEN);
89 memcpy(&pdsp.constants[0], &pap_pdsp_const_reg_map[i][0], sizeof(u32) * PA_PDSP_CONST_NUM_REG);
90 fwrite(&pdsp, sizeof(pdsp), 1, outfp);
91 while(1) {
92 size = fread(buf, 1, 1024, infp);
93 if (size <= 0)
94 break;
95 fwrite(buf, size, 1, outfp);
96 }
97 fclose(outfp);
98 fclose(infp);
99 }
100}
diff --git a/fw/v0/pam.bib b/fw/v0/pam.bib
index 60c68a5..994a93f 100644
--- a/fw/v0/pam.bib
+++ b/fw/v0/pam.bib
Binary files differ
diff --git a/fw/v0/pam.p b/fw/v0/pam.p
index b10cb44..6c57586 100644
--- a/fw/v0/pam.p
+++ b/fw/v0/pam.p
@@ -75,6 +75,7 @@
75#include "pdsp_mem.h" 75#include "pdsp_mem.h"
76#include "pdsp_subs.h" 76#include "pdsp_subs.h"
77#include "pm_config.h" 77#include "pm_config.h"
78#include "pdsp_ver.h"
78#include "pm_constants.h" 79#include "pm_constants.h"
79#include "parsescope.h" 80#include "parsescope.h"
80 81
diff --git a/fw/v0/pam_bin.c b/fw/v0/pam_bin.c
index 819f0ea..ec88ddf 100644
--- a/fw/v0/pam_bin.c
+++ b/fw/v0/pam_bin.c
@@ -74,7 +74,7 @@
74const uint32_t m[] = { 74const uint32_t m[] = {
75 0x21000300, 75 0x21000300,
76 0xbabe0003, 76 0xbabe0003,
77 0x03000112, 77 0x03000200,
78 0x2eff8582, 78 0x2eff8582,
79 0x8104a482, 79 0x8104a482,
80 0x240001e2, 80 0x240001e2,
@@ -84,7 +84,7 @@ const uint32_t m[] = {
84 0x9100171d, 84 0x9100171d,
85 0x11017d7d, 85 0x11017d7d,
86 0x2400005d, 86 0x2400005d,
87 0x24011282, 87 0x24020082,
88 0x240300c2, 88 0x240300c2,
89 0x81043782, 89 0x81043782,
90 0x2eff8780, 90 0x2eff8780,
diff --git a/fw/v0/pdsp_ver.h b/fw/v0/pdsp_ver.h
new file mode 100644
index 0000000..e13050c
--- /dev/null
+++ b/fw/v0/pdsp_ver.h
@@ -0,0 +1,70 @@
1//============================================================================
2// pdsp_ver_gen1.h
3//
4//
5//
6// TEXAS INSTRUMENTS TEXT FILE LICENSE
7//
8// Copyright (c) 2016 Texas Instruments Incorporated
9//
10// All rights reserved not granted herein.
11//
12// Limited License.
13//
14// Texas Instruments Incorporated grants a world-wide, royalty-free, non-exclusive
15// license under copyrights and patents it now or hereafter owns or controls to
16// make, have made, use, import, offer to sell and sell ("Utilize") this software
17// subject to the terms herein. With respect to the foregoing patent license,
18// such license is granted solely to the extent that any such patent is necessary
19// to Utilize the software alone. The patent license shall not apply to any
20// combinations which include this software, other than combinations with devices
21// manufactured by or for TI (ďTI DevicesĒ). No hardware patent is licensed hereunder.
22//
23// Redistributions must preserve existing copyright notices and reproduce this license
24// (including the above copyright notice and the disclaimer and (if applicable) source
25// code license limitations below) in the documentation and/or other materials provided
26// with the distribution.
27//
28// Redistribution and use in binary form, without modification, are permitted provided
29// that the following conditions are met:
30// No reverse engineering, decompilation, or disassembly of this software is
31// permitted with respect to any software provided in binary form.
32// Any redistribution and use are licensed by TI for use only with TI Devices.
33// Nothing shall obligate TI to provide you with source code for the software
34// licensed and provided to you in object code.
35//
36// If software source code is provided to you, modification and redistribution of the
37// source code are permitted provided that the following conditions are met:
38// Any redistribution and use of the source code, including any resulting derivative
39// works, are licensed by TI for use only with TI Devices.
40// Any redistribution and use of any object code compiled from the source code
41// and any resulting derivative works, are licensed by TI for use only with TI Devices.
42//
43// Neither the name of Texas Instruments Incorporated nor the names of its suppliers
44// may be used to endorse or promote products derived from this software without
45// specific prior written permission.
46//
47// DISCLAIMER.
48//
49// THIS SOFTWARE IS PROVIDED BY TI AND TIíS LICENSORS "AS IS" AND ANY EXPRESS OR IMPLIED
50// WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
51// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL TI AND TIíS
52// LICENSORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
53// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
54// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
55// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
56// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
57// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
58//
59//
60//
61
62#ifndef _PDSP_VER_GEN1_H
63#define _PDSP_VER_GEN1_H 1
64
65#define PASS_VERSION_STR "03.00.02.00"
66
67// Common PDSP version number
68#define PASS_VERSION 0x03000200
69
70#endif \ No newline at end of file
diff --git a/fw/v0/pm_config.h b/fw/v0/pm_config.h
index 7b8c690..0609046 100644
--- a/fw/v0/pm_config.h
+++ b/fw/v0/pm_config.h
@@ -66,9 +66,6 @@
66// Big Endian Environment 66// Big Endian Environment
67#define PA_BIGENDIAN 1 67#define PA_BIGENDIAN 1
68 68
69// Common PDSP version number (It should be the same as PALLD version number)
70#define PASS_VERSION 0x03000112
71
72// PDSP IRAM 2K instructions = 8K bytes 69// PDSP IRAM 2K instructions = 8K bytes
73// PDSP IRAM 4K instructions = 16K bytes 70// PDSP IRAM 4K instructions = 16K bytes
74#define PDSP_IRAM_SIZE_PA 2048 71#define PDSP_IRAM_SIZE_PA 2048
diff --git a/fw/v1/build.sh b/fw/v1/build.sh
index 2114502..95d3471 100755
--- a/fw/v1/build.sh
+++ b/fw/v1/build.sh
@@ -91,3 +91,10 @@ rm eg0_pdsp1_bin.h
91rm eg0_pdsp2_bin.h 91rm eg0_pdsp2_bin.h
92rm eg1_pdsp0_bin.h 92rm eg1_pdsp0_bin.h
93rm eg2_pdsp0_bin.h 93rm eg2_pdsp0_bin.h
94
95
96# rem create the bin files for linux
97gcc -I../../../../.. -I../.. -I../../src/v1 pa2bin.c
98./a.out
99rm a.out
100
diff --git a/fw/v1/classify1.p b/fw/v1/classify1.p
index 0ff4ffb..1b17cec 100644
--- a/fw/v1/classify1.p
+++ b/fw/v1/classify1.p
@@ -67,6 +67,7 @@
67#include "pdsp_mem.h" 67#include "pdsp_mem.h"
68#include "pdsp_subs.h" 68#include "pdsp_subs.h"
69#include "pm_config.h" 69#include "pm_config.h"
70#include "pdsp_ver.h"
70#include "pm_constants.h" 71#include "pm_constants.h"
71#include "parsescope.h" 72#include "parsescope.h"
72 73
diff --git a/fw/v1/classify2.p b/fw/v1/classify2.p
index d7b4c61..32bfc02 100644
--- a/fw/v1/classify2.p
+++ b/fw/v1/classify2.p
@@ -67,6 +67,7 @@
67#include "pdsp_mem.h" 67#include "pdsp_mem.h"
68#include "pdsp_subs.h" 68#include "pdsp_subs.h"
69#include "pm_config.h" 69#include "pm_config.h"
70#include "pdsp_ver.h"
70#include "pm_constants.h" 71#include "pm_constants.h"
71#include "parsescope.h" 72#include "parsescope.h"
72 73
diff --git a/fw/v1/classify3.p b/fw/v1/classify3.p
index 82605f3..d94e5e9 100644
--- a/fw/v1/classify3.p
+++ b/fw/v1/classify3.p
@@ -68,6 +68,7 @@
68#include "pdsp_mem2.h" 68#include "pdsp_mem2.h"
69#include "pdsp_subs.h" 69#include "pdsp_subs.h"
70#include "pm_config.h" 70#include "pm_config.h"
71#include "pdsp_ver.h"
71#include "pm_constants.h" 72#include "pm_constants.h"
72#include "parsescope.h" 73#include "parsescope.h"
73 74
diff --git a/fw/v1/efp.p b/fw/v1/efp.p
index ab3689f..92fbb80 100644
--- a/fw/v1/efp.p
+++ b/fw/v1/efp.p
@@ -75,6 +75,7 @@
75#include "pdsp_mem2.h" 75#include "pdsp_mem2.h"
76#include "pdsp_subs.h" 76#include "pdsp_subs.h"
77#include "pm_config.h" 77#include "pm_config.h"
78#include "pdsp_ver.h"
78#include "pm_constants.h" 79#include "pm_constants.h"
79#include "parsescope.h" 80#include "parsescope.h"
80 81
diff --git a/fw/v1/eg0_pdsp0.bib b/fw/v1/eg0_pdsp0.bib
index 1bc69cc..c859f5d 100644
--- a/fw/v1/eg0_pdsp0.bib
+++ b/fw/v1/eg0_pdsp0.bib
Binary files differ
diff --git a/fw/v1/eg0_pdsp0.p b/fw/v1/eg0_pdsp0.p
index 34a08f9..9489b61 100644
--- a/fw/v1/eg0_pdsp0.p
+++ b/fw/v1/eg0_pdsp0.p
@@ -55,6 +55,7 @@
55// 55//
56// 56//
57#include "pm_config.h" 57#include "pm_config.h"
58#include "pdsp_ver.h"
58#define PASS_FIRST_PDSP 59#define PASS_FIRST_PDSP
59#define HEADER_MAGIC 0xBABE0600 60#define HEADER_MAGIC 0xBABE0600
60#define PASS_PDSP_ID 10 61#define PASS_PDSP_ID 10
diff --git a/fw/v1/eg0_pdsp1.bib b/fw/v1/eg0_pdsp1.bib
index d1cbec0..54b494d 100644
--- a/fw/v1/eg0_pdsp1.bib
+++ b/fw/v1/eg0_pdsp1.bib
Binary files differ
diff --git a/fw/v1/eg0_pdsp1.p b/fw/v1/eg0_pdsp1.p
index b76e717..3f240d0 100644
--- a/fw/v1/eg0_pdsp1.p
+++ b/fw/v1/eg0_pdsp1.p
@@ -55,6 +55,7 @@
55// 55//
56// 56//
57#include "pm_config.h" 57#include "pm_config.h"
58#include "pdsp_ver.h"
58#define PASS_PROC_PKT_FORWARD 59#define PASS_PROC_PKT_FORWARD
59#define PASS_PROC_EGRESS_CMD 60#define PASS_PROC_EGRESS_CMD
60#define PASS_PROC_EGRESS_CMD_PROTECT 61#define PASS_PROC_EGRESS_CMD_PROTECT
diff --git a/fw/v1/eg0_pdsp2.bib b/fw/v1/eg0_pdsp2.bib
index cb0d308..892325a 100644
--- a/fw/v1/eg0_pdsp2.bib
+++ b/fw/v1/eg0_pdsp2.bib
Binary files differ
diff --git a/fw/v1/eg0_pdsp2.p b/fw/v1/eg0_pdsp2.p
index c27449c..63f2de3 100644
--- a/fw/v1/eg0_pdsp2.p
+++ b/fw/v1/eg0_pdsp2.p
@@ -55,6 +55,7 @@
55// 55//
56// 56//
57#include "pm_config.h" 57#include "pm_config.h"
58#include "pdsp_ver.h"
58#define PASS_LAST_PDSP 59#define PASS_LAST_PDSP
59#define PASS_PROC_PKT_FORWARD 60#define PASS_PROC_PKT_FORWARD
60#define PASS_PROC_EGRESS_CMD 61#define PASS_PROC_EGRESS_CMD
diff --git a/fw/v1/eg1_pdsp0.bib b/fw/v1/eg1_pdsp0.bib
index e1aeab6..9e06382 100644
--- a/fw/v1/eg1_pdsp0.bib
+++ b/fw/v1/eg1_pdsp0.bib
Binary files differ
diff --git a/fw/v1/eg1_pdsp0.p b/fw/v1/eg1_pdsp0.p
index d9506be..11bc324 100644
--- a/fw/v1/eg1_pdsp0.p
+++ b/fw/v1/eg1_pdsp0.p
@@ -55,6 +55,7 @@
55// 55//
56// 56//
57#include "pm_config.h" 57#include "pm_config.h"
58#include "pdsp_ver.h"
58#define PASS_FIRST_PDSP 59#define PASS_FIRST_PDSP
59#define PASS_LAST_PDSP 60#define PASS_LAST_PDSP
60#define PASS_PROC_PKT_FORWARD 61#define PASS_PROC_PKT_FORWARD
diff --git a/fw/v1/eg2_pdsp0.bib b/fw/v1/eg2_pdsp0.bib
index 3378cba..d76a7ac 100644
--- a/fw/v1/eg2_pdsp0.bib
+++ b/fw/v1/eg2_pdsp0.bib
Binary files differ
diff --git a/fw/v1/eg2_pdsp0.p b/fw/v1/eg2_pdsp0.p
index 069706e..7b961fc 100644
--- a/fw/v1/eg2_pdsp0.p
+++ b/fw/v1/eg2_pdsp0.p
@@ -55,6 +55,7 @@
55// 55//
56// 56//
57#include "pm_config.h" 57#include "pm_config.h"
58#include "pdsp_ver.h"
58#define PASS_FIRST_PDSP 59#define PASS_FIRST_PDSP
59#define PASS_LAST_PDSP 60#define PASS_LAST_PDSP
60#define PASS_PROC_PKT_FORWARD 61#define PASS_PROC_PKT_FORWARD
diff --git a/fw/v1/in0_pdsp0.bib b/fw/v1/in0_pdsp0.bib
index 10d40ed..ea17285 100644
--- a/fw/v1/in0_pdsp0.bib
+++ b/fw/v1/in0_pdsp0.bib
Binary files differ
diff --git a/fw/v1/in0_pdsp0.p b/fw/v1/in0_pdsp0.p
index 1cd1020..c769a7f 100644
--- a/fw/v1/in0_pdsp0.p
+++ b/fw/v1/in0_pdsp0.p
@@ -55,6 +55,7 @@
55// 55//
56// 56//
57#include "pm_config.h" 57#include "pm_config.h"
58#include "pdsp_ver.h"
58#include "pdsp_mem.h" 59#include "pdsp_mem.h"
59#define PASS_FIRST_PDSP 60#define PASS_FIRST_PDSP
60#define PASS_PROC_L2 61#define PASS_PROC_L2
diff --git a/fw/v1/in0_pdsp1.bib b/fw/v1/in0_pdsp1.bib
index 170de56..9237a27 100644
--- a/fw/v1/in0_pdsp1.bib
+++ b/fw/v1/in0_pdsp1.bib
Binary files differ
diff --git a/fw/v1/in0_pdsp1.p b/fw/v1/in0_pdsp1.p
index b118f40..3079e16 100644
--- a/fw/v1/in0_pdsp1.p
+++ b/fw/v1/in0_pdsp1.p
@@ -55,6 +55,7 @@
55// 55//
56// 56//
57#include "pm_config.h" 57#include "pm_config.h"
58#include "pdsp_ver.h"
58#include "pdsp_mem.h" 59#include "pdsp_mem.h"
59#define PASS_LAST_PDSP 60#define PASS_LAST_PDSP
60#define PASS_PROC_L3 61#define PASS_PROC_L3
diff --git a/fw/v1/in1_pdsp0.bib b/fw/v1/in1_pdsp0.bib
index 1132c55..d072f3d 100644
--- a/fw/v1/in1_pdsp0.bib
+++ b/fw/v1/in1_pdsp0.bib
Binary files differ
diff --git a/fw/v1/in1_pdsp0.p b/fw/v1/in1_pdsp0.p
index 532bcb1..3ab9f54 100644
--- a/fw/v1/in1_pdsp0.p
+++ b/fw/v1/in1_pdsp0.p
@@ -55,6 +55,7 @@
55// 55//
56// 56//
57#include "pm_config.h" 57#include "pm_config.h"
58#include "pdsp_ver.h"
58#include "pdsp_mem.h" 59#include "pdsp_mem.h"
59#define PASS_FIRST_PDSP 60#define PASS_FIRST_PDSP
60#define PASS_PROC_IPSEC 61#define PASS_PROC_IPSEC
diff --git a/fw/v1/in1_pdsp1.bib b/fw/v1/in1_pdsp1.bib
index 76a37ba..acc49db 100644
--- a/fw/v1/in1_pdsp1.bib
+++ b/fw/v1/in1_pdsp1.bib
Binary files differ
diff --git a/fw/v1/in1_pdsp1.p b/fw/v1/in1_pdsp1.p
index 274f213..0e32399 100644
--- a/fw/v1/in1_pdsp1.p
+++ b/fw/v1/in1_pdsp1.p
@@ -55,6 +55,7 @@
55// 55//
56// 56//
57#include "pm_config.h" 57#include "pm_config.h"
58#include "pdsp_ver.h"
58#include "pdsp_mem.h" 59#include "pdsp_mem.h"
59#define PASS_LAST_PDSP 60#define PASS_LAST_PDSP
60#define PASS_PROC_IPSEC 61#define PASS_PROC_IPSEC
diff --git a/fw/v1/in2_pdsp0.bib b/fw/v1/in2_pdsp0.bib
index 0a2ca8a..29baed1 100644
--- a/fw/v1/in2_pdsp0.bib
+++ b/fw/v1/in2_pdsp0.bib
Binary files differ
diff --git a/fw/v1/in2_pdsp0.p b/fw/v1/in2_pdsp0.p
index 49c6b77..c0eb0f7 100644
--- a/fw/v1/in2_pdsp0.p
+++ b/fw/v1/in2_pdsp0.p
@@ -55,6 +55,7 @@
55// 55//
56// 56//
57#include "pm_config.h" 57#include "pm_config.h"
58#include "pdsp_ver.h"
58#include "pdsp_mem.h" 59#include "pdsp_mem.h"
59#define PASS_FIRST_PDSP 60#define PASS_FIRST_PDSP
60#define PASS_LAST_PDSP 61#define PASS_LAST_PDSP
diff --git a/fw/v1/in3_pdsp0.bib b/fw/v1/in3_pdsp0.bib
index 987aa37..d666b4f 100644
--- a/fw/v1/in3_pdsp0.bib
+++ b/fw/v1/in3_pdsp0.bib
Binary files differ
diff --git a/fw/v1/in3_pdsp0.p b/fw/v1/in3_pdsp0.p
index 9dbd0cc..269512f 100644
--- a/fw/v1/in3_pdsp0.p
+++ b/fw/v1/in3_pdsp0.p
@@ -55,6 +55,7 @@
55// 55//
56// 56//
57#include "pm_config.h" 57#include "pm_config.h"
58#include "pdsp_ver.h"
58#include "pdsp_mem.h" 59#include "pdsp_mem.h"
59#define PASS_FIRST_PDSP 60#define PASS_FIRST_PDSP
60#define PASS_LAST_PDSP 61#define PASS_LAST_PDSP
diff --git a/fw/v1/in4_pdsp0.bib b/fw/v1/in4_pdsp0.bib
index 3c669cf..2a2d3c3 100644
--- a/fw/v1/in4_pdsp0.bib
+++ b/fw/v1/in4_pdsp0.bib
Binary files differ
diff --git a/fw/v1/in4_pdsp0.p b/fw/v1/in4_pdsp0.p
index c20cd3c..a32bf68 100644
--- a/fw/v1/in4_pdsp0.p
+++ b/fw/v1/in4_pdsp0.p
@@ -55,6 +55,7 @@
55// 55//
56// 56//
57#include "pm_config.h" 57#include "pm_config.h"
58#include "pdsp_ver.h"
58#include "pdsp_mem.h" 59#include "pdsp_mem.h"
59#define PASS_FIRST_PDSP 60#define PASS_FIRST_PDSP
60#define PASS_PROC_L3 61#define PASS_PROC_L3
diff --git a/fw/v1/in4_pdsp1.bib b/fw/v1/in4_pdsp1.bib
index e779e0d..c60071b 100644
--- a/fw/v1/in4_pdsp1.bib
+++ b/fw/v1/in4_pdsp1.bib
Binary files differ
diff --git a/fw/v1/in4_pdsp1.p b/fw/v1/in4_pdsp1.p
index d41fb5b..c007012 100644
--- a/fw/v1/in4_pdsp1.p
+++ b/fw/v1/in4_pdsp1.p
@@ -55,6 +55,7 @@
55// 55//
56// 56//
57#include "pm_config.h" 57#include "pm_config.h"
58#include "pdsp_ver.h"
58#define PASS_LAST_PDSP 59#define PASS_LAST_PDSP
59#define PASS_PROC_PKT_FORWARD 60#define PASS_PROC_PKT_FORWARD
60#define PASS_PROC_L4_CHECKSUM 61#define PASS_PROC_L4_CHECKSUM
diff --git a/fw/v1/ks2_pa_eg0_pdsp0.bin b/fw/v1/ks2_pa_eg0_pdsp0.bin
new file mode 100644
index 0000000..17228e7
--- /dev/null
+++ b/fw/v1/ks2_pa_eg0_pdsp0.bin
Binary files differ
diff --git a/fw/v1/ks2_pa_eg0_pdsp1.bin b/fw/v1/ks2_pa_eg0_pdsp1.bin
new file mode 100644
index 0000000..acb1297
--- /dev/null
+++ b/fw/v1/ks2_pa_eg0_pdsp1.bin
Binary files differ
diff --git a/fw/v1/ks2_pa_eg0_pdsp2.bin b/fw/v1/ks2_pa_eg0_pdsp2.bin
new file mode 100644
index 0000000..12acc52
--- /dev/null
+++ b/fw/v1/ks2_pa_eg0_pdsp2.bin
Binary files differ
diff --git a/fw/v1/ks2_pa_eg1_pdsp0.bin b/fw/v1/ks2_pa_eg1_pdsp0.bin
new file mode 100644
index 0000000..5e8e083
--- /dev/null
+++ b/fw/v1/ks2_pa_eg1_pdsp0.bin
Binary files differ
diff --git a/fw/v1/ks2_pa_eg2_pdsp0.bin b/fw/v1/ks2_pa_eg2_pdsp0.bin
new file mode 100644
index 0000000..717b1d7
--- /dev/null
+++ b/fw/v1/ks2_pa_eg2_pdsp0.bin
Binary files differ
diff --git a/fw/v1/ks2_pa_in0_pdsp0.bin b/fw/v1/ks2_pa_in0_pdsp0.bin
new file mode 100644
index 0000000..a48f212
--- /dev/null
+++ b/fw/v1/ks2_pa_in0_pdsp0.bin
Binary files differ
diff --git a/fw/v1/ks2_pa_in0_pdsp1.bin b/fw/v1/ks2_pa_in0_pdsp1.bin
new file mode 100644
index 0000000..83aad1b
--- /dev/null
+++ b/fw/v1/ks2_pa_in0_pdsp1.bin
Binary files differ
diff --git a/fw/v1/ks2_pa_in1_pdsp0.bin b/fw/v1/ks2_pa_in1_pdsp0.bin
new file mode 100644
index 0000000..530a29f
--- /dev/null
+++ b/fw/v1/ks2_pa_in1_pdsp0.bin
Binary files differ
diff --git a/fw/v1/ks2_pa_in1_pdsp1.bin b/fw/v1/ks2_pa_in1_pdsp1.bin
new file mode 100644
index 0000000..8c9a816
--- /dev/null
+++ b/fw/v1/ks2_pa_in1_pdsp1.bin
Binary files differ
diff --git a/fw/v1/ks2_pa_in2_pdsp0.bin b/fw/v1/ks2_pa_in2_pdsp0.bin
new file mode 100644
index 0000000..8499739
--- /dev/null
+++ b/fw/v1/ks2_pa_in2_pdsp0.bin
Binary files differ
diff --git a/fw/v1/ks2_pa_in3_pdsp0.bin b/fw/v1/ks2_pa_in3_pdsp0.bin
new file mode 100644
index 0000000..e7b6f95
--- /dev/null
+++ b/fw/v1/ks2_pa_in3_pdsp0.bin
Binary files differ
diff --git a/fw/v1/ks2_pa_in4_pdsp0.bin b/fw/v1/ks2_pa_in4_pdsp0.bin
new file mode 100644
index 0000000..431313d
--- /dev/null
+++ b/fw/v1/ks2_pa_in4_pdsp0.bin
Binary files differ
diff --git a/fw/v1/ks2_pa_in4_pdsp1.bin b/fw/v1/ks2_pa_in4_pdsp1.bin
new file mode 100644
index 0000000..31aaaea
--- /dev/null
+++ b/fw/v1/ks2_pa_in4_pdsp1.bin
Binary files differ
diff --git a/fw/v1/ks2_pa_post_pdsp0.bin b/fw/v1/ks2_pa_post_pdsp0.bin
new file mode 100644
index 0000000..2626429
--- /dev/null
+++ b/fw/v1/ks2_pa_post_pdsp0.bin
Binary files differ
diff --git a/fw/v1/ks2_pa_post_pdsp1.bin b/fw/v1/ks2_pa_post_pdsp1.bin
new file mode 100644
index 0000000..a6cf804
--- /dev/null
+++ b/fw/v1/ks2_pa_post_pdsp1.bin
Binary files differ
diff --git a/fw/v1/pa2_eg0_pdsp0_bin.c b/fw/v1/pa2_eg0_pdsp0_bin.c
index df86430..8151628 100644
--- a/fw/v1/pa2_eg0_pdsp0_bin.c
+++ b/fw/v1/pa2_eg0_pdsp0_bin.c
@@ -74,9 +74,9 @@
74const uint32_t eg0_pdsp0[] = { 74const uint32_t eg0_pdsp0[] = {
75 0x21000300, 75 0x21000300,
76 0xbabe0600, 76 0xbabe0600,
77 0x03000112, 77 0x03000200,
78 0x2300d69e, 78 0x2300d69e,
79 0x24011282, 79 0x24020082,
80 0x240300c2, 80 0x240300c2,
81 0x81043782, 81 0x81043782,
82 0x2eff8582, 82 0x2eff8582,
diff --git a/fw/v1/pa2_eg0_pdsp1_bin.c b/fw/v1/pa2_eg0_pdsp1_bin.c
index 78932fc..3f583cd 100644
--- a/fw/v1/pa2_eg0_pdsp1_bin.c
+++ b/fw/v1/pa2_eg0_pdsp1_bin.c
@@ -74,7 +74,7 @@
74const uint32_t eg0_pdsp1[] = { 74const uint32_t eg0_pdsp1[] = {
75 0x21017600, 75 0x21017600,
76 0xbabe0601, 76 0xbabe0601,
77 0x03000112, 77 0x03000200,
78 0xc907ff00, 78 0xc907ff00,
79 0x911007c0, 79 0x911007c0,
80 0x1f0f8080, 80 0x1f0f8080,
@@ -454,7 +454,7 @@ const uint32_t eg0_pdsp1[] = {
454 0xc900ff00, 454 0xc900ff00,
455 0xd100ff00, 455 0xd100ff00,
456 0x2eff819d, 456 0x2eff819d,
457 0x24011282, 457 0x24020082,
458 0x240300c2, 458 0x240300c2,
459 0x81043782, 459 0x81043782,
460 0x2eff8780, 460 0x2eff8780,
diff --git a/fw/v1/pa2_eg0_pdsp2_bin.c b/fw/v1/pa2_eg0_pdsp2_bin.c
index 023d81e..8dff610 100644
--- a/fw/v1/pa2_eg0_pdsp2_bin.c
+++ b/fw/v1/pa2_eg0_pdsp2_bin.c
@@ -74,7 +74,7 @@
74const uint32_t eg0_pdsp2[] = { 74const uint32_t eg0_pdsp2[] = {
75 0x21028f00, 75 0x21028f00,
76 0xbabe0602, 76 0xbabe0602,
77 0x03000112, 77 0x03000200,
78 0xc907ff00, 78 0xc907ff00,
79 0x911007c0, 79 0x911007c0,
80 0x1d0f8080, 80 0x1d0f8080,
@@ -735,7 +735,7 @@ const uint32_t eg0_pdsp2[] = {
735 0xc900ff00, 735 0xc900ff00,
736 0xd100ff00, 736 0xd100ff00,
737 0x2eff819d, 737 0x2eff819d,
738 0x24011282, 738 0x24020082,
739 0x240300c2, 739 0x240300c2,
740 0x81043782, 740 0x81043782,
741 0x2eff8780, 741 0x2eff8780,
diff --git a/fw/v1/pa2_eg1_pdsp0_bin.c b/fw/v1/pa2_eg1_pdsp0_bin.c
index 5e7780e..3fe315f 100644
--- a/fw/v1/pa2_eg1_pdsp0_bin.c
+++ b/fw/v1/pa2_eg1_pdsp0_bin.c
@@ -74,7 +74,7 @@
74const uint32_t eg1_pdsp0[] = { 74const uint32_t eg1_pdsp0[] = {
75 0x2100f800, 75 0x2100f800,
76 0xbabe0700, 76 0xbabe0700,
77 0x03000112, 77 0x03000200,
78 0xc907ff00, 78 0xc907ff00,
79 0x911007c0, 79 0x911007c0,
80 0x1d0f8080, 80 0x1d0f8080,
@@ -328,7 +328,7 @@ const uint32_t eg1_pdsp0[] = {
328 0xc900ff00, 328 0xc900ff00,
329 0xd100ff00, 329 0xd100ff00,
330 0x2eff819d, 330 0x2eff819d,
331 0x24011282, 331 0x24020082,
332 0x240300c2, 332 0x240300c2,
333 0x81043782, 333 0x81043782,
334 0x2eff8780, 334 0x2eff8780,
diff --git a/fw/v1/pa2_eg2_pdsp0_bin.c b/fw/v1/pa2_eg2_pdsp0_bin.c
index 6e7988b..bc23c76 100644
--- a/fw/v1/pa2_eg2_pdsp0_bin.c
+++ b/fw/v1/pa2_eg2_pdsp0_bin.c
@@ -74,7 +74,7 @@
74const uint32_t eg2_pdsp0[] = { 74const uint32_t eg2_pdsp0[] = {
75 0x2101ef00, 75 0x2101ef00,
76 0xbabe0800, 76 0xbabe0800,
77 0x03000112, 77 0x03000200,
78 0xc907ff00, 78 0xc907ff00,
79 0x911007c0, 79 0x911007c0,
80 0x1d0f8080, 80 0x1d0f8080,
@@ -575,7 +575,7 @@ const uint32_t eg2_pdsp0[] = {
575 0xc900ff00, 575 0xc900ff00,
576 0xd100ff00, 576 0xd100ff00,
577 0x2eff819d, 577 0x2eff819d,
578 0x24011282, 578 0x24020082,
579 0x240300c2, 579 0x240300c2,
580 0x81043782, 580 0x81043782,
581 0x2eff8780, 581 0x2eff8780,
diff --git a/fw/v1/pa2_in0_pdsp0_bin.c b/fw/v1/pa2_in0_pdsp0_bin.c
index 4062bc3..0678519 100644
--- a/fw/v1/pa2_in0_pdsp0_bin.c
+++ b/fw/v1/pa2_in0_pdsp0_bin.c
@@ -74,7 +74,7 @@
74const uint32_t in0_pdsp0[] = { 74const uint32_t in0_pdsp0[] = {
75 0x21002c00, 75 0x21002c00,
76 0xbabe0000, 76 0xbabe0000,
77 0x03000112, 77 0x03000200,
78 0x2effa780, 78 0x2effa780,
79 0x8900f380, 79 0x8900f380,
80 0x8950f380, 80 0x8950f380,
@@ -117,7 +117,7 @@ const uint32_t in0_pdsp0[] = {
117 0x81c4338a, 117 0x81c4338a,
118 0x209e0000, 118 0x209e0000,
119 0x23037a9e, 119 0x23037a9e,
120 0x24011282, 120 0x24020082,
121 0x240300c2, 121 0x240300c2,
122 0x81043782, 122 0x81043782,
123 0x2eff8582, 123 0x2eff8582,
diff --git a/fw/v1/pa2_in0_pdsp1_bin.c b/fw/v1/pa2_in0_pdsp1_bin.c
index 49577c0..708a122 100644
--- a/fw/v1/pa2_in0_pdsp1_bin.c
+++ b/fw/v1/pa2_in0_pdsp1_bin.c
@@ -74,9 +74,9 @@
74const uint32_t in0_pdsp1[] = { 74const uint32_t in0_pdsp1[] = {
75 0x21000300, 75 0x21000300,
76 0xbabe0001, 76 0xbabe0001,
77 0x03000112, 77 0x03000200,
78 0x2303409e, 78 0x2303409e,
79 0x24011282, 79 0x24020082,
80 0x240300c2, 80 0x240300c2,
81 0x81043782, 81 0x81043782,
82 0x2eff8582, 82 0x2eff8582,
diff --git a/fw/v1/pa2_in1_pdsp0_bin.c b/fw/v1/pa2_in1_pdsp0_bin.c
index eef3605..795357a 100644
--- a/fw/v1/pa2_in1_pdsp0_bin.c
+++ b/fw/v1/pa2_in1_pdsp0_bin.c
@@ -74,9 +74,9 @@
74const uint32_t in1_pdsp0[] = { 74const uint32_t in1_pdsp0[] = {
75 0x21000300, 75 0x21000300,
76 0xbabe0002, 76 0xbabe0002,
77 0x03000112, 77 0x03000200,
78 0x2302aa9e, 78 0x2302aa9e,
79 0x24011282, 79 0x24020082,
80 0x240300c2, 80 0x240300c2,
81 0x81043782, 81 0x81043782,
82 0x2eff8582, 82 0x2eff8582,
diff --git a/fw/v1/pa2_in1_pdsp1_bin.c b/fw/v1/pa2_in1_pdsp1_bin.c
index 396167b..ad85dfc 100644
--- a/fw/v1/pa2_in1_pdsp1_bin.c
+++ b/fw/v1/pa2_in1_pdsp1_bin.c
@@ -74,9 +74,9 @@
74const uint32_t in1_pdsp1[] = { 74const uint32_t in1_pdsp1[] = {
75 0x21000300, 75 0x21000300,
76 0xbabe0101, 76 0xbabe0101,
77 0x03000112, 77 0x03000200,
78 0x23027e9e, 78 0x23027e9e,
79 0x24011282, 79 0x24020082,
80 0x240300c2, 80 0x240300c2,
81 0x81043782, 81 0x81043782,
82 0x2eff8582, 82 0x2eff8582,
diff --git a/fw/v1/pa2_in2_pdsp0_bin.c b/fw/v1/pa2_in2_pdsp0_bin.c
index f0c9c87..c3f646a 100644
--- a/fw/v1/pa2_in2_pdsp0_bin.c
+++ b/fw/v1/pa2_in2_pdsp0_bin.c
@@ -74,9 +74,9 @@
74const uint32_t in2_pdsp0[] = { 74const uint32_t in2_pdsp0[] = {
75 0x21000300, 75 0x21000300,
76 0xbabe0200, 76 0xbabe0200,
77 0x03000112, 77 0x03000200,
78 0x23027a9e, 78 0x23027a9e,
79 0x24011282, 79 0x24020082,
80 0x240300c2, 80 0x240300c2,
81 0x81043782, 81 0x81043782,
82 0x2eff8582, 82 0x2eff8582,
diff --git a/fw/v1/pa2_in3_pdsp0_bin.c b/fw/v1/pa2_in3_pdsp0_bin.c
index c810574..fa95791 100644
--- a/fw/v1/pa2_in3_pdsp0_bin.c
+++ b/fw/v1/pa2_in3_pdsp0_bin.c
@@ -74,9 +74,9 @@
74const uint32_t in3_pdsp0[] = { 74const uint32_t in3_pdsp0[] = {
75 0x21000300, 75 0x21000300,
76 0xbabe0300, 76 0xbabe0300,
77 0x03000112, 77 0x03000200,
78 0x23029d9e, 78 0x23029d9e,
79 0x24011282, 79 0x24020082,
80 0x240300c2, 80 0x240300c2,
81 0x81043782, 81 0x81043782,
82 0x2eff8582, 82 0x2eff8582,
diff --git a/fw/v1/pa2_in4_pdsp0_bin.c b/fw/v1/pa2_in4_pdsp0_bin.c
index e749e2e..a3229ec 100644
--- a/fw/v1/pa2_in4_pdsp0_bin.c
+++ b/fw/v1/pa2_in4_pdsp0_bin.c
@@ -74,9 +74,9 @@
74const uint32_t in4_pdsp0[] = { 74const uint32_t in4_pdsp0[] = {
75 0x21000300, 75 0x21000300,
76 0xbabe0401, 76 0xbabe0401,
77 0x03000112, 77 0x03000200,
78 0x2302b59e, 78 0x2302b59e,
79 0x24011282, 79 0x24020082,
80 0x240300c2, 80 0x240300c2,
81 0x81043782, 81 0x81043782,
82 0x2eff8582, 82 0x2eff8582,
diff --git a/fw/v1/pa2_in4_pdsp1_bin.c b/fw/v1/pa2_in4_pdsp1_bin.c
index 09ee3d0..a849199 100644
--- a/fw/v1/pa2_in4_pdsp1_bin.c
+++ b/fw/v1/pa2_in4_pdsp1_bin.c
@@ -74,7 +74,7 @@
74const uint32_t in4_pdsp1[] = { 74const uint32_t in4_pdsp1[] = {
75 0x21000300, 75 0x21000300,
76 0xbabe0401, 76 0xbabe0401,
77 0x03000112, 77 0x03000200,
78 0x2300f79e, 78 0x2300f79e,
79 0x2eff8582, 79 0x2eff8582,
80 0x8104a482, 80 0x8104a482,
@@ -85,7 +85,7 @@ const uint32_t in4_pdsp1[] = {
85 0x2eff819d, 85 0x2eff819d,
86 0x24000702, 86 0x24000702,
87 0x81001762, 87 0x81001762,
88 0x24011282, 88 0x24020082,
89 0x240300c2, 89 0x240300c2,
90 0x81043782, 90 0x81043782,
91 0xc901ff08, 91 0xc901ff08,
diff --git a/fw/v1/pa2_post_pdsp0_bin.c b/fw/v1/pa2_post_pdsp0_bin.c
index 638b1fd..e75ccb7 100644
--- a/fw/v1/pa2_post_pdsp0_bin.c
+++ b/fw/v1/pa2_post_pdsp0_bin.c
@@ -74,7 +74,7 @@
74const uint32_t post_pdsp0[] = { 74const uint32_t post_pdsp0[] = {
75 0x21000300, 75 0x21000300,
76 0xbabe0500, 76 0xbabe0500,
77 0x03000112, 77 0x03000200,
78 0x2305369e, 78 0x2305369e,
79 0x2eff8582, 79 0x2eff8582,
80 0x8104a482, 80 0x8104a482,
@@ -83,7 +83,7 @@ const uint32_t post_pdsp0[] = {
83 0xc900ff00, 83 0xc900ff00,
84 0xd100ff00, 84 0xd100ff00,
85 0x2eff819d, 85 0x2eff819d,
86 0x24011282, 86 0x24020082,
87 0x240300c2, 87 0x240300c2,
88 0x81043782, 88 0x81043782,
89 0x2eff8780, 89 0x2eff8780,
diff --git a/fw/v1/pa2_post_pdsp1_bin.c b/fw/v1/pa2_post_pdsp1_bin.c
index 38b0a7a..c87ddb4 100644
--- a/fw/v1/pa2_post_pdsp1_bin.c
+++ b/fw/v1/pa2_post_pdsp1_bin.c
@@ -74,7 +74,7 @@
74const uint32_t post_pdsp1[] = { 74const uint32_t post_pdsp1[] = {
75 0x21000300, 75 0x21000300,
76 0xbabe0501, 76 0xbabe0501,
77 0x03000112, 77 0x03000200,
78 0x23039d9e, 78 0x23039d9e,
79 0x2eff8582, 79 0x2eff8582,
80 0x8104a482, 80 0x8104a482,
@@ -83,7 +83,7 @@ const uint32_t post_pdsp1[] = {
83 0xc900ff00, 83 0xc900ff00,
84 0xd100ff00, 84 0xd100ff00,
85 0x2eff819d, 85 0x2eff819d,
86 0x24011282, 86 0x24020082,
87 0x240300c2, 87 0x240300c2,
88 0x81043782, 88 0x81043782,
89 0x2eff8780, 89 0x2eff8780,
diff --git a/fw/v1/pa2bin.c b/fw/v1/pa2bin.c
new file mode 100644
index 0000000..8e588f9
--- /dev/null
+++ b/fw/v1/pa2bin.c
@@ -0,0 +1,127 @@
1#include <stdio.h>
2#include <stdlib.h>
3#include <string.h>
4#include "pa.h"
5#include "pdsp_ver.h"
6#include "paconst.c"
7
8#define DEVICE_PA_NUM_PDSPS (15U)
9#define PA_PDSP_CONST_NUM_REG (32U)
10#define PASS_VER_STR_LEN (16U)
11
12typedef unsigned int u32;
13
14/* header to the firmware blob */
15struct pa_pdsp_firmware {
16 char version[PASS_VER_STR_LEN];
17 u32 constants[PA_PDSP_CONST_NUM_REG];
18};
19
20static char *versions[DEVICE_PA_NUM_PDSPS] = {
21 PASS_VERSION_STR,
22 PASS_VERSION_STR,
23 PASS_VERSION_STR,
24 PASS_VERSION_STR,
25 PASS_VERSION_STR,
26 PASS_VERSION_STR,
27 PASS_VERSION_STR,
28 PASS_VERSION_STR,
29 PASS_VERSION_STR,
30 PASS_VERSION_STR,
31 PASS_VERSION_STR,
32 PASS_VERSION_STR,
33 PASS_VERSION_STR,
34 PASS_VERSION_STR,
35 PASS_VERSION_STR
36};
37static char *pdsp_in_file_names[DEVICE_PA_NUM_PDSPS] = {
38 "in0_pdsp0.bib", /* 0 */
39 "in0_pdsp1.bib", /* 1 */
40 "in1_pdsp0.bib", /* 2 */
41 "in1_pdsp1.bib", /* 3 */
42 "in2_pdsp0.bib", /* 4 */
43 "in3_pdsp0.bib", /* 5 */
44 "in4_pdsp0.bib", /* 6 */
45 "in4_pdsp1.bib", /* 7 */
46 "post_pdsp0.bib", /* 8 */
47 "post_pdsp1.bib", /* 9 */
48 "eg0_pdsp0.bib", /* 10 */
49 "eg0_pdsp1.bib", /* 11 */
50 "eg0_pdsp2.bib", /* 12 */
51 "eg1_pdsp0.bib", /* 13 */
52 "eg2_pdsp0.bib", /* 14 */
53};
54
55static char *pdsp_out_file_names[DEVICE_PA_NUM_PDSPS] = {
56 "ks2_pa_in0_pdsp0", /* 0 */
57 "ks2_pa_in0_pdsp1", /* 1 */
58 "ks2_pa_in1_pdsp0", /* 2 */
59 "ks2_pa_in1_pdsp1", /* 3 */
60 "ks2_pa_in2_pdsp0", /* 4 */
61 "ks2_pa_in3_pdsp0", /* 5 */
62 "ks2_pa_in4_pdsp0", /* 6 */
63 "ks2_pa_in4_pdsp1", /* 7 */
64 "ks2_pa_post_pdsp0", /* 8 */
65 "ks2_pa_post_pdsp1", /* 9 */
66 "ks2_pa_eg0_pdsp0", /* 10 */
67 "ks2_pa_eg0_pdsp1", /* 11 */
68 "ks2_pa_eg0_pdsp2", /* 12 */
69 "ks2_pa_eg1_pdsp0", /* 13 */
70 "ks2_pa_eg2_pdsp0", /* 14 */
71};
72
73int main(int argc, char **argv)
74{
75 unsigned long b_sz, total = 0;
76 struct pa_pdsp_firmware pdsp;
77 char in_file_name[128];
78 char out_file_name[128];
79 char buf[1024];
80 char *pc;
81 FILE *outfp, *infp;
82 int j, i;
83 int size;
84
85 for (i = 0; i < DEVICE_PA_NUM_PDSPS; i++) {
86 if (!pdsp_in_file_names[i])
87 continue;
88 bzero(in_file_name, sizeof(in_file_name));
89 bzero(out_file_name, sizeof(out_file_name));
90 strcpy(in_file_name, (char *)pdsp_in_file_names[i]);
91 strcpy(out_file_name, (char *)pdsp_out_file_names[i]);
92 pc = &out_file_name[strlen(out_file_name)];
93#if 0
94 strcat(pc, "-");
95 strcat(pc, (char *)versions[i]);
96#endif
97 strcat(pc, ".bin");
98 outfp=fopen(out_file_name,"wb");
99 infp=fopen(in_file_name,"rb");
100 printf("input file: %s\n",in_file_name);
101 printf("output file: %s\n",out_file_name);
102 if (!outfp)
103 {
104 printf("Unable to open output file! %s", out_file_name);
105 exit(1);
106 }
107
108 if (!infp)
109 {
110 printf("Unable to open input file! %s", in_file_name);
111 fclose(outfp);
112 exit(2);
113 }
114
115 strncpy((char *)&pdsp.version[0], (char *)versions[i], PASS_VER_STR_LEN);
116 memcpy(&pdsp.constants[0], &pap_pdsp_const_reg_map[i][0], sizeof(u32) * PA_PDSP_CONST_NUM_REG);
117 fwrite(&pdsp, sizeof(pdsp), 1, outfp);
118 while(1) {
119 size = fread(buf, 1, 1024, infp);
120 if (size <= 0)
121 break;
122 fwrite(buf, size, 1, outfp);
123 }
124 fclose(outfp);
125 fclose(infp);
126 }
127}
diff --git a/fw/v1/pdsp_ver.h b/fw/v1/pdsp_ver.h
new file mode 100644
index 0000000..713d6d3
--- /dev/null
+++ b/fw/v1/pdsp_ver.h
@@ -0,0 +1,70 @@
1//============================================================================
2// pdsp_ver_gen1.h
3//
4//
5//
6// TEXAS INSTRUMENTS TEXT FILE LICENSE
7//
8// Copyright (c) 2016 Texas Instruments Incorporated
9//
10// All rights reserved not granted herein.
11//
12// Limited License.
13//
14// Texas Instruments Incorporated grants a world-wide, royalty-free, non-exclusive
15// license under copyrights and patents it now or hereafter owns or controls to
16// make, have made, use, import, offer to sell and sell ("Utilize") this software
17// subject to the terms herein. With respect to the foregoing patent license,
18// such license is granted solely to the extent that any such patent is necessary
19// to Utilize the software alone. The patent license shall not apply to any
20// combinations which include this software, other than combinations with devices
21// manufactured by or for TI (ďTI DevicesĒ). No hardware patent is licensed hereunder.
22//
23// Redistributions must preserve existing copyright notices and reproduce this license
24// (including the above copyright notice and the disclaimer and (if applicable) source
25// code license limitations below) in the documentation and/or other materials provided
26// with the distribution.
27//
28// Redistribution and use in binary form, without modification, are permitted provided
29// that the following conditions are met:
30// No reverse engineering, decompilation, or disassembly of this software is
31// permitted with respect to any software provided in binary form.
32// Any redistribution and use are licensed by TI for use only with TI Devices.
33// Nothing shall obligate TI to provide you with source code for the software
34// licensed and provided to you in object code.
35//
36// If software source code is provided to you, modification and redistribution of the
37// source code are permitted provided that the following conditions are met:
38// Any redistribution and use of the source code, including any resulting derivative
39// works, are licensed by TI for use only with TI Devices.
40// Any redistribution and use of any object code compiled from the source code
41// and any resulting derivative works, are licensed by TI for use only with TI Devices.
42//
43// Neither the name of Texas Instruments Incorporated nor the names of its suppliers
44// may be used to endorse or promote products derived from this software without
45// specific prior written permission.
46//
47// DISCLAIMER.
48//
49// THIS SOFTWARE IS PROVIDED BY TI AND TIíS LICENSORS "AS IS" AND ANY EXPRESS OR IMPLIED
50// WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
51// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL TI AND TIíS
52// LICENSORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
53// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
54// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
55// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
56// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
57// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
58//
59//
60//
61
62#ifndef _PDSP_VER_GEN2_H
63#define _PDSP_VER_GEN2_H 1
64
65#define PASS_VERSION_STR "03.00.02.00"
66
67// Common PDSP version number
68#define PASS_VERSION 0x03000200
69
70#endif
diff --git a/fw/v1/pm_config.h b/fw/v1/pm_config.h
index e3d5c37..ffab43b 100644
--- a/fw/v1/pm_config.h
+++ b/fw/v1/pm_config.h
@@ -65,9 +65,6 @@
65// Big Endian Environment 65// Big Endian Environment
66#define PA_BIGENDIAN 1 66#define PA_BIGENDIAN 1
67 67
68// Common PDSP version number (It should be the same as PALLD version number)
69#define PASS_VERSION 0x03000112
70
71// PDSP IRAM 3K instructions = 12K bytes 68// PDSP IRAM 3K instructions = 12K bytes
72// PDSP IRAM 4K instructions = 16K bytes 69// PDSP IRAM 4K instructions = 16K bytes
73#define PDSP_IRAM_SIZE_PA 3072 70#define PDSP_IRAM_SIZE_PA 3072
diff --git a/fw/v1/post_pdsp0.bib b/fw/v1/post_pdsp0.bib
index b1f0432..7c161d4 100644
--- a/fw/v1/post_pdsp0.bib
+++ b/fw/v1/post_pdsp0.bib
Binary files differ
diff --git a/fw/v1/post_pdsp0.p b/fw/v1/post_pdsp0.p
index ab24b3f..863718d 100644
--- a/fw/v1/post_pdsp0.p
+++ b/fw/v1/post_pdsp0.p
@@ -55,6 +55,7 @@
55// 55//
56// 56//
57#include "pm_config.h" 57#include "pm_config.h"
58#include "pdsp_ver.h"
58#define PASS_FIRST_PDSP 59#define PASS_FIRST_PDSP
59#define PASS_PROC_PKT_FORWARD 60#define PASS_PROC_PKT_FORWARD
60#define PASS_PROC_USR_STATS_FIFO 61#define PASS_PROC_USR_STATS_FIFO
diff --git a/fw/v1/post_pdsp1.bib b/fw/v1/post_pdsp1.bib
index 4003a0d..8559cfe 100644
--- a/fw/v1/post_pdsp1.bib
+++ b/fw/v1/post_pdsp1.bib
Binary files differ
diff --git a/fw/v1/post_pdsp1.p b/fw/v1/post_pdsp1.p
index af83a6c..7f02a9d 100644
--- a/fw/v1/post_pdsp1.p
+++ b/fw/v1/post_pdsp1.p
@@ -55,6 +55,7 @@
55// 55//
56// 56//
57#include "pm_config.h" 57#include "pm_config.h"
58#include "pdsp_ver.h"
58#define PASS_LAST_PDSP 59#define PASS_LAST_PDSP
59#define PASS_PROC_PKT_FORWARD 60#define PASS_PROC_PKT_FORWARD
60#define PASS_POST_PROCESSING 61#define PASS_POST_PROCESSING
diff --git a/package.xdc b/package.xdc
index 4224d68..d880d6a 100644
--- a/package.xdc
+++ b/package.xdc
@@ -9,7 +9,7 @@
9 * Copyright (C) 2009-2016, Texas Instruments, Inc. 9 * Copyright (C) 2009-2016, Texas Instruments, Inc.
10 *****************************************************************************/ 10 *****************************************************************************/
11 11
12package ti.drv.pa[3,0,1,18] { 12package ti.drv.pa[3,0,2,00] {
13 module Settings; 13 module Settings;
14} 14}
15 15
diff --git a/paver.h b/paver.h
index 8e818c7..4882e46 100644
--- a/paver.h
+++ b/paver.h
@@ -51,13 +51,13 @@ extern "C" {
51 * format: 51 * format:
52 * 0xAABBCCDD -> Arch (AA); API Changes (BB); Major (CC); Minor (DD) 52 * 0xAABBCCDD -> Arch (AA); API Changes (BB); Major (CC); Minor (DD)
53 */ 53 */
54#define PA_LLD_VERSION_ID (0x03000112) 54#define PA_LLD_VERSION_ID (0x03000200)
55 55
56/** 56/**
57 * @brief This is the version string which describes the PA LLD along with the 57 * @brief This is the version string which describes the PA LLD along with the
58 * date and build information. 58 * date and build information.
59 */ 59 */
60#define PA_LLD_VERSION_STR "PA LLD Revision: 03.00.01.18" 60#define PA_LLD_VERSION_STR "PA LLD Revision: 03.00.02.00"
61 61
62 62
63#ifdef __cplusplus 63#ifdef __cplusplus
diff --git a/src/Module.xs b/src/Module.xs
index ea1b562..3a3c99f 100755..100644
--- a/src/Module.xs
+++ b/src/Module.xs
@@ -21,7 +21,8 @@ var pa =
21 21
22 /* Souce File List */ 22 /* Souce File List */
23 srcFile: ["src/v0/painit.c", 23 srcFile: ["src/v0/painit.c",
24 "src/v0/pa.c"], 24 "src/v0/pa.c",
25 "src/v0/paconst.c"],
25 26
26 /* Library options */ 27 /* Library options */
27 copts: " -DDEVICE_K2K -DSOC_K2K" 28 copts: " -DDEVICE_K2K -DSOC_K2K"
@@ -34,7 +35,8 @@ var pa2 =
34 35
35 /* Souce File List */ 36 /* Souce File List */
36 srcFile: ["src/v1/painit.c", 37 srcFile: ["src/v1/painit.c",
37 "src/v1/pa.c"], 38 "src/v1/pa.c",
39 "src/v1/paconst.c"],
38 40
39 /* Library options */ 41 /* Library options */
40 copts: " -DDEVICE_K2L -DSOC_K2L -DNSS_GEN2" 42 copts: " -DDEVICE_K2L -DSOC_K2L -DNSS_GEN2"
diff --git a/src/v0/pa.c b/src/v0/pa.c
index efa90d5..c94bbd6 100755..100644
--- a/src/v0/pa.c
+++ b/src/v0/pa.c
@@ -4513,6 +4513,9 @@ paReturn_t Pa_forwardResult (Pa_Handle iHandle, void *vresult, paEntryHandle_t *
4513 if (fcmd->commandResult == PAFRM_COMMAND_RESULT_LUT2_ADD_BUSY) { 4513 if (fcmd->commandResult == PAFRM_COMMAND_RESULT_LUT2_ADD_BUSY) {
4514 *cmdDest = pa_CMD_TX_DEST_3; 4514 *cmdDest = pa_CMD_TX_DEST_3;
4515 ret = pa_RESUBMIT_COMMAND; 4515 ret = pa_RESUBMIT_COMMAND;
4516 /* Swizzle back the header */
4517 fcmd->commandResult = 0U;
4518 swizFcmd(fcmd);
4516 } 4519 }
4517 else if (fcmd->commandResult == PAFRM_COMMAND_RESULT_LUT2_FULL) { 4520 else if (fcmd->commandResult == PAFRM_COMMAND_RESULT_LUT2_FULL) {
4518 ret = pa_LUT2_TABLE_FULL; 4521 ret = pa_LUT2_TABLE_FULL;
@@ -6920,61 +6923,10 @@ paReturn_t Pa_getTimestamp (Pa_Handle iHandle,
6920 6923
6921} /* Pa_getTimestamp */ 6924} /* Pa_getTimestamp */
6922 6925
6923/**************************************************************************** 6926/* Moved the constant defintions outside this file *
6924 * DATA PURPOSE: PDSP Constant Registers 6927 * This helps to generate the bin files required for
6925 **************************************************************************** 6928 * linux */
6926 * DESCRIPTION: Specify the user-defined PDSP constant registers (c24-c31) 6929extern const uint32_t pap_pdsp_const_reg_map[6][4];
6927 ****************************************************************************/
6928 const uint32_t pap_pdsp_const_reg_map[6][4] =
6929 {
6930 /* PDSP0: C24-C31 */
6931 {
6932 0x0000007F, /* C25-C24 */
6933 0x0000006E, /* C27-C26 */
6934 0x00000000, /* C29-C28 */
6935 0x00000473 /* C31-C30 */
6936 },
6937
6938 /* PDSP1: C24-C31 */
6939 {
6940 0x0001007F, /* C25-C24 */
6941 0x00480040, /* C27-C26 */
6942 0x00000000, /* C29-C28 */
6943 0x00000473 /* C31-C30 */
6944 },
6945
6946 /* PDSP2: C24-C31 */
6947 {
6948 0x0002007F, /* C25-C24 */
6949 0x00490044, /* C27-C26 */
6950 0x00000000, /* C29-C28 */
6951 0x00000473 /* C31-C30 */
6952 },
6953
6954 /* PDSP3: C24-C31 */
6955 {
6956 0x0003007F, /* C25-C24 */
6957 0x0000006E, /* C27-C26 */
6958 0x00000000, /* C29-C28 */
6959 0x00000473 /* C31-C30 */
6960 },
6961
6962 /* PDSP4: C24-C31 */
6963 {
6964 0x0070007F, /* C25-C24 */
6965 0x00000003, /* C27-C26 */
6966 0x04080404, /* C29-C28 */
6967 0x00000473 /* C31-C30 */
6968 },
6969
6970 /* PDSP5: C24-C31 */
6971 {
6972 0x0071007F, /* C25-C24 */
6973 0x00000003, /* C27-C26 */
6974 0x04080404, /* C29-C28 */
6975 0x00000473 /* C31-C30 */
6976 }
6977};
6978 6930
6979#define PA_PDSP_CONST_REG_INDEX_C25_C24 0 6931#define PA_PDSP_CONST_REG_INDEX_C25_C24 0
6980#define PA_PDSP_CONST_REG_INDEX_C27_C26 1 6932#define PA_PDSP_CONST_REG_INDEX_C27_C26 1
diff --git a/src/v0/paconst.c b/src/v0/paconst.c
new file mode 100644
index 0000000..c32d8f4
--- /dev/null
+++ b/src/v0/paconst.c
@@ -0,0 +1,101 @@
1/******************************************************************************
2 * FILE PURPOSE: Constant Register values for PASS
3 ******************************************************************************
4 * FILE NAME: paconst.c
5 *
6 * DESCRIPTION: Constant Registers for PA
7 *
8 * FUNCTION DESCRIPTION
9 * ======== ===========
10 *
11 * REVISION HISTORY:
12 *
13 * Copyright (c) Texas Instruments Incorporated 2016
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
17 * are met:
18 *
19 * Redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer.
21 *
22 * Redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the
25 * distribution.
26 *
27 * Neither the name of Texas Instruments Incorporated nor the names of
28 * its contributors may be used to endorse or promote products derived
29 * from this software without specific prior written permission.
30 *
31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
32 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
33 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
34 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
35 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
36 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
37 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
38 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
39 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
41 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 *
43*/
44
45#include "pa.h"
46/****************************************************************************
47 * DATA PURPOSE: PDSP Constant Registers
48 ****************************************************************************
49 * DESCRIPTION: Specify the user-defined PDSP constant registers (c24-c31)
50 ****************************************************************************/
51 const uint32_t pap_pdsp_const_reg_map[6][4] =
52 {
53 /* PDSP0: C24-C31 */
54 {
55 0x0000007F, /* C25-C24 */
56 0x0000006E, /* C27-C26 */
57 0x00000000, /* C29-C28 */
58 0x00000473 /* C31-C30 */
59 },
60
61 /* PDSP1: C24-C31 */
62 {
63 0x0001007F, /* C25-C24 */
64 0x00480040, /* C27-C26 */
65 0x00000000, /* C29-C28 */
66 0x00000473 /* C31-C30 */
67 },
68
69 /* PDSP2: C24-C31 */
70 {
71 0x0002007F, /* C25-C24 */
72 0x00490044, /* C27-C26 */
73 0x00000000, /* C29-C28 */
74 0x00000473 /* C31-C30 */
75 },
76
77 /* PDSP3: C24-C31 */
78 {
79 0x0003007F, /* C25-C24 */
80 0x0000006E, /* C27-C26 */
81 0x00000000, /* C29-C28 */
82 0x00000473 /* C31-C30 */
83 },
84
85 /* PDSP4: C24-C31 */
86 {
87 0x0070007F, /* C25-C24 */
88 0x00000003, /* C27-C26 */
89 0x04080404, /* C29-C28 */
90 0x00000473 /* C31-C30 */
91 },
92
93 /* PDSP5: C24-C31 */
94 {
95 0x0071007F, /* C25-C24 */
96 0x00000003, /* C27-C26 */
97 0x04080404, /* C29-C28 */
98 0x00000473 /* C31-C30 */
99 }
100};
101
diff --git a/src/v0/pafrm.h b/src/v0/pafrm.h
index b60686e..b60686e 100755..100644
--- a/src/v0/pafrm.h
+++ b/src/v0/pafrm.h
diff --git a/src/v1/pa.c b/src/v1/pa.c
index 834bf4d..2acc44c 100755..100644
--- a/src/v1/pa.c
+++ b/src/v1/pa.c
@@ -6949,6 +6949,9 @@ paReturn_t Pa_forwardResult (Pa_Handle iHandle, void *vresult, paEntryHandle_t *
6949 if (fcmd->commandResult == PAFRM_COMMAND_RESULT_LUT2_ADD_BUSY) { 6949 if (fcmd->commandResult == PAFRM_COMMAND_RESULT_LUT2_ADD_BUSY) {
6950 *cmdDest = pa_CMD_TX_DEST_4; 6950 *cmdDest = pa_CMD_TX_DEST_4;
6951 ret = pa_RESUBMIT_COMMAND; 6951 ret = pa_RESUBMIT_COMMAND;
6952 /* Swizzle back the header */
6953 fcmd->commandResult = 0U;
6954 swizFcmd(fcmd);
6952 } 6955 }
6953 else if (fcmd->commandResult == PAFRM_COMMAND_RESULT_LUT2_FULL) { 6956 else if (fcmd->commandResult == PAFRM_COMMAND_RESULT_LUT2_FULL) {
6954 ret = pa_LUT2_TABLE_FULL; 6957 ret = pa_LUT2_TABLE_FULL;
@@ -10441,554 +10444,10 @@ paReturn_t Pa_getTimestamp (Pa_Handle iHandle,
10441 10444
10442} /* Pa_getTimestamp */ 10445} /* Pa_getTimestamp */
10443 10446
10444/**************************************************************************** 10447/* Moved the constant defintions outside this file *
10445 * DATA PURPOSE: PDSP Constant Registers 10448 * This helps to generate the bin files required for
10446 **************************************************************************** 10449 * linux */
10447 * DESCRIPTION: Specify the pre-defined PDSP constant registers (c0-c31) 10450extern const uint32_t pap_pdsp_const_reg_map[PASS_NUM_PDSPS][32];
10448 ****************************************************************************/
10449 const uint32_t pap_pdsp_const_reg_map[PASS_NUM_PDSPS][32] =
10450 {
10451 /* Ingress0 PDSP0: Classify1 */
10452 {
10453 0xFFF84000, /* C0: LUT1 Info */
10454 0xFFF80000, /* C1: Loacl SRAM */
10455 0xFF020000, /* C2: Global SRAM */
10456 0xFF408800, /* C3: System Timer (PDSP0 Timer) */
10457 0xFF000000, /* C4: MailBox */
10458 0x00000000, /* C5: Reserved*/
10459 0xFFF04000, /* C6: CDE new packet input region */
10460 0xFFF00100, /* C7: CDE new packet output region */
10461 0xFFF00200, /* C8: CDE held packet region */
10462 0xFFF08800, /* C9: PDSP Timer (PDSP specific) */
10463 0xFFF09000, /* C10: LUT1 Registers */
10464 0xFFF09400, /* C11: LUT2 Registers */
10465 0x00000000, /* C12: Reserved */
10466 0x00000000, /* C13: Reserved */
10467 0xFFF80000, /* C14: PDSP Context */
10468 0x00000000, /* C15: Reserved*/
10469 0xFFF80400, /* C16: Time Accumulation Constants and EOAM Exception table */
10470 0xFFF80800, /* C17: IP Reassembly Control Block */
10471 0xFFF80C00, /* C18: IP Protocol Table */
10472 0xFF020000, /* C19: Custom LUT1 and global configuration */
10473 0xFF020200, /* C20: Exception Routes */
10474 0xFFF81000, /* C21: Classify1 Parsing Call Table */
10475 0x00000000, /* C22: Reserved */
10476 0xFFF83F00, /* C23: PDSP Info */
10477 0xFFF81400, /* C24: Next Route Global address table */
10478 0xFF980000, /* C25: User Stats CB and FIFO (Global address of Post cluster) */
10479 0x00000000, /* C26: Reserved*/
10480 0x00000000, /* C27: Reserved*/
10481 0xFF020500, /* C28: Port (Interface-based) configurations */
10482 0x00000000, /* C29: Reserved*/
10483 0x00000000, /* C30: Reserved*/
10484 0x00000000 /* C31: Reserved*/
10485 },
10486
10487 /* Ingress0 PDSP1: Classify1 */
10488 {
10489 0xFFF88000, /* C0: LUT1 Info */
10490 0xFFF80000, /* C1: Loacl SRAM */
10491 0xFF020000, /* C2: Global SRAM */
10492 0xFF408800, /* C3: System Timer (PDSP0 Timer) */
10493 0xFF000010, /* C4: MailBox */
10494 0x00000000, /* C5: Reserved*/
10495 0xFFF14000, /* C6: CDE new packet input region */
10496 0xFFF10100, /* C7: CDE new packet output region */
10497 0xFFF10200, /* C8: CDE held packet region */
10498 0xFFF18800, /* C9: PDSP Timer (PDSP specific) */
10499 0xFFF19000, /* C10: LUT1 Registers */
10500 0xFFF19400, /* C11: LUT2 Registers */
10501 0x00000000, /* C12: Reserved */
10502 0x00000000, /* C13: Reserved*/
10503 0xFFF80100, /* C14: PDSP Context */
10504 0x00000000, /* C15: Reserved*/
10505 0xFFF80400, /* C16: Time Accumulation Constants and EOAM Exception table */
10506 0xFFF80800, /* C17: IP Reassembly Control Block */
10507 0xFFF80D00, /* C18: IP Protocol Table */
10508 0xFF020000, /* C19: Custom LUT1 and global configuration */
10509 0xFF020200, /* C20: Exception Routes */
10510 0xFFF81100, /* C21: Classify1 Parsing Call Table */
10511 0x00000000, /* C22: Reserved */
10512 0xFFF83F20, /* C23: PDSP Info */
10513 0xFFF81400, /* C24: Next Route Global address table */
10514 0xFF980040, /* C25: User Stats CB and FIFO (Global address of Post cluster) */
10515 0x00000000, /* C26: Reserved*/
10516 0x00000000, /* C27: Reserved*/
10517 0xFF020500, /* C28: Port (Interface-based) configurations */
10518 0x00000000, /* C29: Reserved*/
10519 0x00000000, /* C30: Reserved*/
10520 0x00000000 /* C31: Reserved*/
10521 },
10522
10523 /* Ingress1 PDSP0: Classify1 */
10524 {
10525 0xFFF84000, /* C0: LUT1 Info */
10526 0xFFF80000, /* C1: Loacl SRAM */
10527 0xFF020000, /* C2: Global SRAM */
10528 0xFF408800, /* C3: System Timer (PDSP0 Timer) */
10529 0xFF000020, /* C4: MailBox */
10530 0x00000000, /* C5: Reserved*/
10531 0xFFF04000, /* C6: CDE new packet input region */
10532 0xFFF00100, /* C7: CDE new packet output region */
10533 0xFFF00200, /* C8: CDE held packet region */
10534 0xFFF08800, /* C9: PDSP Timer (PDSP specific) */
10535 0xFFF09000, /* C10: LUT1 Registers */
10536 0xFFF09400, /* C11: LUT2 Registers */
10537 0x00000000, /* C12: Reserved */
10538 0x00000000, /* C13: Reserved*/
10539 0xFFF80000, /* C14: PDSP Context */
10540 0x00000000, /* C15: Reserved*/
10541 0xFFF80400, /* C16: IP Traffic Flow */
10542 0xFFF80800, /* C17: IP Reassembly Control Block */
10543 0xFFF80C00, /* C18: IP Protocol Table */
10544 0xFF020000, /* C19: Custom LUT1 and global configuration */
10545 0xFF020200, /* C20: Exception Routes */
10546 0xFFF81000, /* C21: Classify1 Parsing Call Table */
10547 0x00000000, /* C22: Reserved */
10548 0xFFF83F00, /* C23: PDSP Info */
10549 0xFFF81400, /* C24: Next Route Global address table */
10550 0xFF980080, /* C25: User Stats CB and FIFO (Global address of Post cluster) */
10551 0x00000000, /* C26: Reserved*/
10552 0x00000000, /* C27: Reserved*/
10553 0xFF020500, /* C28: Port (Interface-based) configurations */
10554 0x00000000, /* C29: Reserved*/
10555 0x00000000, /* C30: Reserved*/
10556 0x00000000 /* C31: Reserved*/
10557 },
10558
10559 /* Ingress1 PDSP1: Classify1 */
10560 {
10561 0xFFF88000, /* C0: LUT1 Info */
10562 0xFFF80000, /* C1: Loacl SRAM */
10563 0xFF020000, /* C2: Global SRAM */
10564 0xFF408800, /* C3: System Timer (PDSP0 Timer) */
10565 0xFF000030, /* C4: MailBox */
10566 0x00000000, /* C5: Reserved*/
10567 0xFFF14000, /* C6: CDE new packet input region */
10568 0xFFF10100, /* C7: CDE new packet output region */
10569 0xFFF10200, /* C8: CDE held packet region */
10570 0xFFF18800, /* C9: PDSP Timer (PDSP specific) */
10571 0xFFF19000, /* C10: LUT1 Registers */
10572 0xFFF19400, /* C11: LUT2 Registers */
10573 0x00000000, /* C12: Reserved */
10574 0x00000000, /* C13: Reserved*/
10575 0xFFF80100, /* C14: PDSP Context */
10576 0x00000000, /* C15: Reserved*/
10577 0xFFF80400, /* C16: IP Traffic Flow */
10578 0xFFF80800, /* C17: IP Reassembly Control Block */
10579 0xFFF80D00, /* C18: IP Protocol Table */
10580 0xFF020000, /* C19: Custom LUT1 and global configuration */
10581 0xFF020200, /* C20: Exception Routes */
10582 0xFFF81100, /* C21: Classify1 Parsing Call Table */
10583 0x00000000, /* C22: Reserved */
10584 0xFFF83F20, /* C23: PDSP Info */
10585 0xFFF81400, /* C24: Next Route Global address table */
10586 0xFF9800C0, /* C25: User Stats CB and FIFO (Global address of Post cluster) */
10587 0x00000000, /* C26: Reserved*/
10588 0x00000000, /* C27: Reserved*/
10589 0xFF020500, /* C28: Port (Interface-based) configurations */
10590 0x00000000, /* C29: Reserved*/
10591 0x00000000, /* C30: Reserved*/
10592 0x00000000 /* C31: Reserved*/
10593 },
10594
10595 /* Ingress2 PDSP0: Classify1 */
10596 {
10597 0xFFF82000, /* C0: LUT1 Info */
10598 0xFFF80000, /* C1: Loacl SRAM */
10599 0xFF020000, /* C2: Global SRAM */
10600 0xFF408800, /* C3: System Timer (PDSP0 Timer) */
10601 0xFF000040, /* C4: MailBox */
10602 0x00000000, /* C5: Reserved*/
10603 0xFFF04000, /* C6: CDE new packet input region */
10604 0xFFF00100, /* C7: CDE new packet output region */
10605 0xFFF00200, /* C8: CDE held packet region */
10606 0xFFF08800, /* C9: PDSP Timer (PDSP specific) */
10607 0xFFF09000, /* C10: LUT1 Registers */
10608 0xFFF09400, /* C11: LUT2 Registers */
10609 0x00000000, /* C12: Reserved */
10610 0x00000000, /* C13: Reserved*/
10611 0xFFF80000, /* C14: PDSP Context */
10612 0x00000000, /* C15: Reserved*/
10613 0xFFF80400, /* C16: IP Traffic Flow */
10614 0xFFF80800, /* C17: IP Reassembly Control Block */
10615 0xFFF80C00, /* C18: IP Protocol Table */
10616 0xFF020000, /* C19: Custom LUT1 and global configuration */
10617 0xFF020200, /* C20: Exception Routes */
10618 0xFFF81000, /* C21: Classify1 Parsing Call Table */
10619 0x00000000, /* C22: Reserved */
10620 0xFFF81F00, /* C23: PDSP Info */
10621 0xFFF81400, /* C24: Next Route Global address table */
10622 0xFF980100, /* C25: User Stats CB and FIFO (Global address of Post cluster) */
10623 0x00000000, /* C26: Reserved*/
10624 0x00000000, /* C27: Reserved*/
10625 0xFF020500, /* C28: Port (Interface-based) configurations */
10626 0x00000000, /* C29: Reserved*/
10627 0x00000000, /* C30: Reserved*/
10628 0x00000000 /* C31: Reserved*/
10629 },
10630
10631 /* Ingress3 PDSP0: Classify1 */
10632 {
10633 0xFFF82000, /* C0: LUT1 Info */
10634 0xFFF80000, /* C1: Loacl SRAM */
10635 0xFF020000, /* C2: Global SRAM */
10636 0xFF408800, /* C3: System Timer (PDSP0 Timer) */
10637 0xFF000050, /* C4: MailBox */
10638 0x00000000, /* C5: Reserved*/
10639 0xFFF04000, /* C6: CDE new packet input region */
10640 0xFFF00100, /* C7: CDE new packet output region */
10641 0xFFF00200, /* C8: CDE held packet region */
10642 0xFFF08800, /* C9: PDSP Timer (PDSP specific) */
10643 0xFFF09000, /* C10: LUT1 Registers */
10644 0xFFF09400, /* C11: LUT2 Registers */
10645 0x00000000, /* C12: Reserved */
10646 0x00000000, /* C13: Reserved*/
10647 0xFFF80000, /* C14: PDSP Context */
10648 0x00000000, /* C15: Reserved*/
10649 0xFFF80400, /* C16: IP Traffic Flow */
10650 0xFFF80800, /* C17: IP Reassembly Control Block */
10651 0xFFF80C00, /* C18: IP Protocol Table */
10652 0xFF020000, /* C19: Custom LUT1 and global configuration */
10653 0xFF020200, /* C20: Exception Routes */
10654 0xFFF81000, /* C21: Classify1 Parsing Call Table */
10655 0x00000000, /* C22: Reserved */
10656 0xFFF81F00, /* C23: PDSP Info */
10657 0xFFF81400, /* C24: Next Route Global address table */
10658 0xFF980140, /* C25: User Stats CB and FIFO (Global address of Post cluster) */
10659 0x00000000, /* C26: Reserved*/
10660 0x00000000, /* C27: Reserved*/
10661 0xFF020500, /* C28: Port (Interface-based) configurations */
10662 0x00000000, /* C29: Reserved*/
10663 0x00000000, /* C30: Reserved*/
10664 0x00000000 /* C31: Reserved*/
10665 },
10666
10667 /* Ingress4 PDSP0: Classify1 */
10668 {
10669 0xFFF84000, /* C0: LUT1 Info */
10670 0xFFF80000, /* C1: Loacl SRAM */
10671 0xFF020000, /* C2: Global SRAM */
10672 0xFF408800, /* C3: System Timer (PDSP0 Timer) */
10673 0xFF000060, /* C4: MailBox */
10674 0x00000000, /* C5: Reserved*/
10675 0xFFF04000, /* C6: CDE new packet input region */
10676 0xFFF00100, /* C7: CDE new packet output region */
10677 0xFFF00200, /* C8: CDE held packet region */
10678 0xFFF08800, /* C9: PDSP Timer (PDSP specific) */
10679 0xFFF09000, /* C10: LUT1 Registers */
10680 0xFFF09400, /* C11: LUT2 Registers */
10681 0x00000000, /* C12: Reserved */
10682 0x00000000, /* C13: Reserved*/
10683 0xFFF80000, /* C14: PDSP Context */
10684 0x00000000, /* C15: Reserved*/
10685 0xFFF80400, /* C16: IP Traffic Flow */
10686 0xFFF80800, /* C17: IP Reassembly Control Block */
10687 0xFFF80C00, /* C18: IP Protocol Table */
10688 0xFF020000, /* C19: Custom LUT1 and global configuration */
10689 0xFF020200, /* C20: Exception Routes */
10690 0xFFF81000, /* C21: Classify1 Parsing Call Table */
10691 0x00000000, /* C22: Reserved */
10692 0xFFF83F00, /* C23: PDSP Info */
10693 0xFFF81400, /* C24: Next Route Global address table */
10694 0xFF980180, /* C25: User Stats CB and FIFO (Global address of Post Cluster) */
10695 0x00000000, /* C26: Reserved*/
10696 0x00000000, /* C27: Reserved*/
10697 0xFF020500, /* C28: Port (Interface-based) configurations */
10698 0x00000000, /* C29: Reserved*/
10699 0x00000000, /* C30: Reserved*/
10700 0x00000000 /* C31: Reserved*/
10701 },
10702
10703 /* Ingress4 PDSP1: Classify2 */
10704 {
10705 0xFFF88000, /* C0: LUT1 Info */
10706 0xFFF80000, /* C1: Loacl SRAM */
10707 0xFF020000, /* C2: Global SRAM */
10708 0xFF408800, /* C3: System Timer (PDSP0 Timer) */
10709 0xFF000070, /* C4: MailBox */
10710 0x00000000, /* C5: Reserved*/
10711 0xFFF14000, /* C6: CDE new packet input region */
10712 0xFFF10100, /* C7: CDE new packet output region */
10713 0xFFF10200, /* C8: CDE held packet region */
10714 0xFFF18800, /* C9: PDSP Timer (PDSP specific) */
10715 0xFFF19000, /* C10: LUT1 Registers */
10716 0xFFF19400, /* C11: LUT2 Registers */
10717 0x00000000, /* C12: Reserved */
10718 0x00000000, /* C13: Reserved*/
10719 0x00000000, /* C14: Reserved*/
10720 0x00000000, /* C15: Reserved*/
10721 0xFFF81800, /* C16: Custom2 Info */
10722 0x00000000, /* C17: Reserved*/
10723 0x00000000, /* C18: Reserved*/
10724 0xFF020000, /* C19: Custom LUT1 and global configuration */
10725 0xFF020200, /* C20: Exception Routes */
10726 0xFFF81100, /* C21: Classify2 Parsing Call Table */
10727 0x00000000, /* C22: Reserved */
10728 0xFFF83F20, /* C23: PDSP Info */
10729 0xFFF81400, /* C24: Next Route Global address table */
10730 0xFF9801C0, /* C25: User Stats CB and FIFO (Global address of Post cluster) */
10731 0x00000000, /* C26: Reserved*/
10732 0x00000000, /* C27: Reserved*/
10733 0xFF020500, /* C28: Port (Interface-based) configurations */
10734 0x00000000, /* C29: Reserved*/
10735 0x00000000, /* C30: Reserved*/
10736 0x00000000 /* C31: Reserved*/
10737 },
10738
10739 /* Post PDSP0: Modifier */
10740 {
10741 0xFFF80000, /* C0: User Stats FIFO Base */
10742 0xFFF80000, /* C1: Loacl SRAM */
10743 0xFF020000, /* C2: Global SRAM */
10744 0xFF408800, /* C3: System Timer (PDSP0 Timer) */
10745 0xFF000080, /* C4: MailBox */
10746 0x00000000, /* C5: Reserved*/
10747 0xFFF04000, /* C6: CDE new packet input region */
10748 0xFFF00100, /* C7: CDE new packet output region */
10749 0xFFF00200, /* C8: CDE held packet region */
10750 0xFFF08800, /* C9: PDSP Timer (PDSP specific) */
10751 0xFFF09000, /* C10: LUT1 Registers */
10752 0xFFF09400, /* C11: LUT2 Registers */
10753 0x00000000, /* C12: Reserved */
10754 0x00000000, /* C13: Reserved*/
10755 0x00000000, /* C14: Reserved*/
10756 0xFFF80400, /* C15: User Stats Control Block */
10757 0xFFF80800, /* C16: User Stats */
10758 0xFFF81000, /* C17: Command Set Table */
10759 0xFFF81800, /* C18: Multi-route table */
10760 0xFF020000, /* C19: Custom LUT1 and global configuration */
10761 0xFF020200, /* C20: Exception Routes */
10762 0xFFF82800, /* C21: CRC Verify FIFO */
10763 0xFFF82900, /* C22: Split Context FIFO */
10764 0xFFF83F00, /* C23: PDSP Info*/
10765 0x00000000, /* C24: Reserved */
10766 0xFFF80200, /* C25: User Stats CB and FIFO (Global address of Post cluster) */
10767 0x00000000, /* C26: Reserved*/
10768 0x00000000, /* C27: Reserved*/
10769 0xFF020500, /* C28: Port (Interface-based) configurations */
10770 0x00000000, /* C29: Reserved*/
10771 0x00000000, /* C30: Reserved*/
10772 0x00000000 /* C31: Reserved*/
10773 },
10774
10775 /* Post PDSP1: Modifier */
10776 {
10777 0xFFF80000, /* C0: User Stats FIFO Base */
10778 0xFFF80000, /* C1: Loacl SRAM */
10779 0xFF020000, /* C2: Global SRAM */
10780 0xFF408800, /* C3: System Timer (PDSP0 Timer) */
10781 0xFF000090, /* C4: MailBox */
10782 0x00000000, /* C5: Reserved*/
10783 0xFFF14000, /* C6: CDE new packet input region */
10784 0xFFF10100, /* C7: CDE new packet output region */
10785 0xFFF10200, /* C8: CDE held packet region */
10786 0xFFF18800, /* C9: PDSP Timer (PDSP specific) */
10787 0xFFF19000, /* C10: LUT1 Registers */
10788 0xFFF19400, /* C11: LUT2 Registers */
10789 0x00000000, /* C12: Reserved */
10790 0x00000000, /* C13: Reserved*/
10791 0x00000000, /* C14: Reserved*/
10792 0xFFF80400, /* C15: User Stats Control Block */
10793 0xFFF80800, /* C16: User Stats */
10794 0xFFF81000, /* C17: Command Set Table */
10795 0xFFF82000, /* C18: Multi-route table */
10796 0xFF020000, /* C19: Custom LUT1 and global configuration */
10797 0xFF020200, /* C20: Exception Routes */
10798 0xFFF82800, /* C21: CRC Verify FIFO */
10799 0xFFF82900, /* C22: Split Context FIFO */
10800 0xFFF83F20, /* C23: PDSP Info*/
10801 0x00000000, /* C24: Reserved */
10802 0xFFF80240, /* C25: User Stats CB and FIFO (Global address of Post cluster) */
10803 0x00000000, /* C26: Reserved*/
10804 0x00000000, /* C27: Reserved*/
10805 0xFF020500, /* C28: Port (Interface-based) configurations */
10806 0x00000000, /* C29: Reserved*/
10807 0x00000000, /* C30: Reserved*/
10808 0x00000000 /* C31: Reserved*/
10809 },
10810
10811 /* Egress0 PDSP0: Flow Cache */
10812 {
10813 0xFFF82000, /* C0: LUT1 Info */
10814 0xFFF80000, /* C1: Loacl SRAM */
10815 0xFF020000, /* C2: Global SRAM */
10816 0xFF408800, /* C3: System Timer (PDSP0 Timer) */
10817 0xFF0000A0, /* C4: MailBox */
10818 0x00000000, /* C5: Reserved*/
10819 0xFFF04000, /* C6: CDE new packet input region */
10820 0xFFF00100, /* C7: CDE new packet output region */
10821 0xFFF00200, /* C8: CDE held packet region */
10822 0xFFF08800, /* C9: PDSP Timer (PDSP specific) */
10823 0xFFF09000, /* C10: LUT1 Registers */
10824 0xFFF09400, /* C11: LUT2 Registers */
10825 0xFFF84000, /* C12: Egress Flow Record0 */
10826 0xFFF88000, /* C13: Egress Flow Record1 */
10827 0xFFF80000, /* C14: PDSP Context */
10828 0xFF980400, /* C15: User Stats Control Block */
10829 0xFF980800, /* C16: User Stats */
10830 0xFFF81000, /* C17: Modify Context */
10831 0xFFF80200, /* C18: IP Protocol Table */
10832 0xFF020000, /* C19: Custom LUT1 and global configuration */
10833 0xFF020200, /* C20: Exception Routes */
10834 0xFFF80500, /* C21: Parse table */
10835 0x00000000, /* C22: Reserved */
10836 0xFFF81F00, /* C23: PDSP Info */
10837 0xFFF80A00, /* C24: Temporary Buffer */
10838 0xFF980280, /* C25: User Stats CB and FIFO (Global address of Post cluster) */
10839 0xFF020400, /* C26: Eflow Exception route */
10840 0x00000000, /* C27: Reserved*/
10841 0xFF020500, /* C28: Port (Interface-based) configurations */
10842 0x00000000, /* C29: Reserved*/
10843 0x00000000, /* C30: Reserved*/
10844 0x00000000 /* C31: Reserved*/
10845 },
10846
10847 /* Egress0 PDSP1: Flow Cache */
10848 {
10849 0x00000000, /* C0: Reserved */
10850 0xFFF80000, /* C1: Loacl SRAM */
10851 0xFF020000, /* C2: Global SRAM */
10852 0xFF408800, /* C3: System Timer (PDSP0 Timer) */
10853 0xFF0000B0, /* C4: MailBox */
10854 0x00000000, /* C5: Reserved*/
10855 0xFFF14000, /* C6: CDE new packet input region */
10856 0xFFF10100, /* C7: CDE new packet output region */
10857 0xFFF10200, /* C8: CDE held packet region */
10858 0xFFF18800, /* C9: PDSP Timer (PDSP specific) */
10859 0xFFF19000, /* C10: LUT1 Registers */
10860 0xFFF19400, /* C11: LUT2 Registers */
10861 0xFFF84000, /* C12: Egress Flow Record0 */
10862 0xFFF88000, /* C13: Egress Flow Record1 */
10863 0x00000000, /* C14: Reserved */
10864 0xFF980400, /* C15: User Stats Control Block */
10865 0xFF980800, /* C16: User Stats */
10866 0xFFF81000, /* C17: Modify Context */
10867 0xFFF80300, /* C18: IP Protocol Table */
10868 0xFF020000, /* C19: Custom LUT1 and global configuration */
10869 0xFF020200, /* C20: Exception Routes */
10870 0xFFF80600, /* C21: Parse table */
10871 0x00000000, /* C22: Reserved */
10872 0xFFF81F20, /* C23: PDSP Info */
10873 0xFFF80A00, /* C24: Temporary Buffer */
10874 0xFF9802C0, /* C25: User Stats CB and FIFO (Global address of Post cluster) */
10875 0xFF020400, /* C26: Eflow Exception route */
10876 0xFFF80800, /* C27: Command Buffer */
10877 0xFF020500, /* C28: Port (Interface-based) configurations */
10878 0x00000000, /* C29: Reserved*/
10879 0x00000000, /* C30: Reserved*/
10880 0x00000000 /* C31: Reserved*/
10881 },
10882
10883 /* Egress0 PDSP2: Flow Cache */
10884 {
10885 0x00000000, /* C0: Reserved */
10886 0xFFF80000, /* C1: Loacl SRAM */
10887 0xFF020000, /* C2: Global SRAM */
10888 0xFF408800, /* C3: System Timer (PDSP0 Timer) */
10889 0xFF0000C0, /* C4: MailBox */
10890 0x00000000, /* C5: Reserved*/
10891 0xFFF24000, /* C6: CDE new packet input region */
10892 0xFFF20100, /* C7: CDE new packet output region */
10893 0xFFF20200, /* C8: CDE held packet region */
10894 0xFFF28800, /* C9: PDSP Timer (PDSP specific) */
10895 0xFFF29000, /* C10: LUT1 Registers */
10896 0xFFF29400, /* C11: LUT2 Registers */
10897 0xFFF84000, /* C12: Egress Flow Record0 */
10898 0xFFF88000, /* C13: Egress Flow Record1 */
10899 0x00000000, /* C14: Reserved */
10900 0xFF980400, /* C15: User Stats Control Block */
10901 0xFF980800, /* C16: User Stats */
10902 0xFFF81000, /* C17: Modify Context */
10903 0xFFF80400, /* C18: IP Protocol Table */
10904 0xFF020000, /* C19: Custom LUT1 and global configuration */
10905 0xFF020200, /* C20: Exception Routes */
10906 0xFFF80700, /* C21: Parse table */
10907 0x00000000, /* C22: Reserved */
10908 0xFFF81F40, /* C23: PDSP Info */
10909 0xFFF80A00, /* C24: Temporary Buffer */
10910 0xFF980300, /* C25: User Stats CB and FIFO (Global address of Post cluster) */
10911 0xFF020400, /* C26: Eflow Exception route */
10912 0xFFF80900, /* C27: Command Buffer */
10913 0xFF020500, /* C28: Port (Interface-based) configurations */
10914 0x00000000, /* C29: Reserved*/
10915 0x00000000, /* C30: Reserved*/
10916 0x00000000 /* C31: Reserved*/
10917 },
10918
10919 /* Egress1 PDSP0: Flow Cache */
10920 {
10921 0x00000000, /* C0: Reserved */
10922 0xFFF80000, /* C1: Loacl SRAM */
10923 0xFF020000, /* C2: Global SRAM */
10924 0xFF408800, /* C3: System Timer (PDSP0 Timer) */
10925 0xFF0000D0, /* C4: MailBox */
10926 0x00000000, /* C5: Reserved*/
10927 0xFFF04000, /* C6: CDE new packet input region */
10928 0xFFF00100, /* C7: CDE new packet output region */
10929 0xFFF00200, /* C8: CDE held packet region */
10930 0xFFF08800, /* C9: PDSP Timer (PDSP specific) */
10931 0xFFF09000, /* C10: LUT1 Registers */
10932 0xFFF09400, /* C11: LUT2 Registers */
10933 0xFFF81000, /* C12: Egress Flow Record2 */
10934 0x00000000, /* C13: Reserved*/
10935 0xFFF80000, /* C14: PDSP Context */
10936 0xFF980400, /* C15: User Stats Control Block */
10937 0xFF980800, /* C16: User Stats */
10938 0xFFF81000, /* C17: Modify Context */
10939 0xFFF80200, /* C18: IP Protocol Table */
10940 0xFF020000, /* C19: Custom LUT1 and global configuration */
10941 0xFF020200, /* C20: Egress Exception Routes */
10942 0xFFF80500, /* C21: Parse table */
10943 0x00000000, /* C22: Reserved */
10944 0xFFF80F00, /* C23: PDSP Info */
10945 0xFFF80A00, /* C24: Temporary Buffer */
10946 0xFF980340, /* C25: User Stats CB and FIFO (Global address of Post cluster) */
10947 0xFF020400, /* C26: Eflow Exception route */
10948 0xFFF80800, /* C27: Command Buffer */
10949 0xFF020500, /* C28: Port (Interface-based) configurations */
10950 0x00000000, /* C29: Reserved*/
10951 0x00000000, /* C30: Reserved*/
10952 0x00000000 /* C31: Reserved*/
10953 },
10954
10955 /* Egress2 PDSP0: Flow Cache */
10956 {
10957 0x00000000, /* C0: Reserved */
10958 0xFFF80000, /* C1: Loacl SRAM */
10959 0xFF020000, /* C2: Global SRAM */
10960 0xFF408800, /* C3: System Timer (PDSP0 Timer) */
10961 0xFF0000E0, /* C4: MailBox */
10962 0x00000000, /* C5: Reserved*/
10963 0xFFF04000, /* C6: CDE new packet input region */
10964 0xFFF00100, /* C7: CDE new packet output region */
10965 0xFFF00200, /* C8: CDE held packet region */
10966 0xFFF08800, /* C9: PDSP Timer (PDSP specific) */
10967 0xFFF09000, /* C10: LUT1 Registers */
10968 0xFFF09400, /* C11: LUT2 Registers */
10969 0xFFF81000, /* C12: Egress Flow Record3 */
10970 0x00000000, /* C13: Reserved*/
10971 0xFFF80000, /* C14: PDSP Context */
10972 0xFF980400, /* C15: User Stats Control Block */
10973 0xFF980800, /* C16: User Stats */
10974 0xFFF81000, /* C17: Modify Context */
10975 0xFFF80200, /* C18: IP Protocol Table */
10976 0xFF020000, /* C19: Custom LUT1 and global configuration */
10977 0xFF020200, /* C20: Egress Exception Routes */
10978 0xFFF80500, /* C21: Parse table */
10979 0x00000000, /* C22: Reserved */
10980 0xFFF80F00, /* C23: PDSP Info */
10981 0xFFF80A00, /* C24: Temporary Buffer */
10982 0xFF980380, /* C25: User Stats CB and FIFO (Global address of Post cluster) */
10983 0xFF020400, /* C26: Eflow Exception route */
10984 0xFFF80800, /* C27: Command Buffer */
10985 0xFF020500, /* C28: Port (Interface-based) configurations */
10986 0x00000000, /* C29: Reserved*/
10987 0x00000000, /* C30: Reserved*/
10988 0x00000000 /* C31: Reserved*/
10989 }
10990
10991};
10992 10451
10993/*********************************************************************************************** 10452/***********************************************************************************************
10994 * FUNCTION PURPOSE: Download a PDSP image 10453 * FUNCTION PURPOSE: Download a PDSP image
diff --git a/src/v1/paconst.c b/src/v1/paconst.c
new file mode 100644
index 0000000..6c4ac6a
--- /dev/null
+++ b/src/v1/paconst.c
@@ -0,0 +1,595 @@
1/******************************************************************************
2 * FILE PURPOSE: Constant Register values for PASS
3 ******************************************************************************
4 * FILE NAME: paconst.c
5 *
6 * DESCRIPTION: Constant Registers for PA
7 *
8 * FUNCTION DESCRIPTION
9 * ======== ===========
10 *
11 * REVISION HISTORY:
12 *
13 * Copyright (c) Texas Instruments Incorporated 2016
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
17 * are met:
18 *
19 * Redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer.
21 *
22 * Redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the
25 * distribution.
26 *
27 * Neither the name of Texas Instruments Incorporated nor the names of
28 * its contributors may be used to endorse or promote products derived
29 * from this software without specific prior written permission.
30 *
31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
32 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
33 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
34 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
35 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
36 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
37 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
38 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
39 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
41 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 *
43*/
44
45#include "pa.h"
46
47#define PASS_NUM_PDSPS (15U)
48/****************************************************************************
49 * DATA PURPOSE: PDSP Constant Registers
50 ****************************************************************************
51 * DESCRIPTION: Specify the pre-defined PDSP constant registers (c0-c31)
52 ****************************************************************************/
53 const uint32_t pap_pdsp_const_reg_map[PASS_NUM_PDSPS][32] =
54 {
55 /* Ingress0 PDSP0: Classify1 */
56 {
57 0xFFF84000, /* C0: LUT1 Info */
58 0xFFF80000, /* C1: Loacl SRAM */
59 0xFF020000, /* C2: Global SRAM */
60 0xFF408800, /* C3: System Timer (PDSP0 Timer) */
61 0xFF000000, /* C4: MailBox */
62 0x00000000, /* C5: Reserved*/
63 0xFFF04000, /* C6: CDE new packet input region */
64 0xFFF00100, /* C7: CDE new packet output region */
65 0xFFF00200, /* C8: CDE held packet region */
66 0xFFF08800, /* C9: PDSP Timer (PDSP specific) */
67 0xFFF09000, /* C10: LUT1 Registers */
68 0xFFF09400, /* C11: LUT2 Registers */
69 0x00000000, /* C12: Reserved */
70 0x00000000, /* C13: Reserved */
71 0xFFF80000, /* C14: PDSP Context */
72 0x00000000, /* C15: Reserved*/
73 0xFFF80400, /* C16: Time Accumulation Constants and EOAM Exception table */
74 0xFFF80800, /* C17: IP Reassembly Control Block */
75 0xFFF80C00, /* C18: IP Protocol Table */
76 0xFF020000, /* C19: Custom LUT1 and global configuration */
77 0xFF020200, /* C20: Exception Routes */
78 0xFFF81000, /* C21: Classify1 Parsing Call Table */
79 0x00000000, /* C22: Reserved */
80 0xFFF83F00, /* C23: PDSP Info */
81 0xFFF81400, /* C24: Next Route Global address table */
82 0xFF980000, /* C25: User Stats CB and FIFO (Global address of Post cluster) */
83 0x00000000, /* C26: Reserved*/
84 0x00000000, /* C27: Reserved*/
85 0xFF020500, /* C28: Port (Interface-based) configurations */
86 0x00000000, /* C29: Reserved*/
87 0x00000000, /* C30: Reserved*/
88 0x00000000 /* C31: Reserved*/
89 },
90
91 /* Ingress0 PDSP1: Classify1 */
92 {
93 0xFFF88000, /* C0: LUT1 Info */
94 0xFFF80000, /* C1: Loacl SRAM */
95 0xFF020000, /* C2: Global SRAM */
96 0xFF408800, /* C3: System Timer (PDSP0 Timer) */
97 0xFF000010, /* C4: MailBox */
98 0x00000000, /* C5: Reserved*/
99 0xFFF14000, /* C6: CDE new packet input region */
100 0xFFF10100, /* C7: CDE new packet output region */
101 0xFFF10200, /* C8: CDE held packet region */
102 0xFFF18800, /* C9: PDSP Timer (PDSP specific) */
103 0xFFF19000, /* C10: LUT1 Registers */
104 0xFFF19400, /* C11: LUT2 Registers */
105 0x00000000, /* C12: Reserved */
106 0x00000000, /* C13: Reserved*/
107 0xFFF80100, /* C14: PDSP Context */
108 0x00000000, /* C15: Reserved*/
109 0xFFF80400, /* C16: Time Accumulation Constants and EOAM Exception table */
110 0xFFF80800, /* C17: IP Reassembly Control Block */
111 0xFFF80D00, /* C18: IP Protocol Table */
112 0xFF020000, /* C19: Custom LUT1 and global configuration */
113 0xFF020200, /* C20: Exception Routes */
114 0xFFF81100, /* C21: Classify1 Parsing Call Table */
115 0x00000000, /* C22: Reserved */
116 0xFFF83F20, /* C23: PDSP Info */
117 0xFFF81400, /* C24: Next Route Global address table */
118 0xFF980040, /* C25: User Stats CB and FIFO (Global address of Post cluster) */
119 0x00000000, /* C26: Reserved*/
120 0x00000000, /* C27: Reserved*/
121 0xFF020500, /* C28: Port (Interface-based) configurations */
122 0x00000000, /* C29: Reserved*/
123 0x00000000, /* C30: Reserved*/
124 0x00000000 /* C31: Reserved*/
125 },
126
127 /* Ingress1 PDSP0: Classify1 */
128 {
129 0xFFF84000, /* C0: LUT1 Info */
130 0xFFF80000, /* C1: Loacl SRAM */
131 0xFF020000, /* C2: Global SRAM */
132 0xFF408800, /* C3: System Timer (PDSP0 Timer) */
133 0xFF000020, /* C4: MailBox */
134 0x00000000, /* C5: Reserved*/
135 0xFFF04000, /* C6: CDE new packet input region */
136 0xFFF00100, /* C7: CDE new packet output region */
137 0xFFF00200, /* C8: CDE held packet region */
138 0xFFF08800, /* C9: PDSP Timer (PDSP specific) */
139 0xFFF09000, /* C10: LUT1 Registers */
140 0xFFF09400, /* C11: LUT2 Registers */
141 0x00000000, /* C12: Reserved */
142 0x00000000, /* C13: Reserved*/
143 0xFFF80000, /* C14: PDSP Context */
144 0x00000000, /* C15: Reserved*/
145 0xFFF80400, /* C16: IP Traffic Flow */
146 0xFFF80800, /* C17: IP Reassembly Control Block */
147 0xFFF80C00, /* C18: IP Protocol Table */
148 0xFF020000, /* C19: Custom LUT1 and global configuration */
149 0xFF020200, /* C20: Exception Routes */
150 0xFFF81000, /* C21: Classify1 Parsing Call Table */
151 0x00000000, /* C22: Reserved */
152 0xFFF83F00, /* C23: PDSP Info */
153 0xFFF81400, /* C24: Next Route Global address table */
154 0xFF980080, /* C25: User Stats CB and FIFO (Global address of Post cluster) */
155 0x00000000, /* C26: Reserved*/
156 0x00000000, /* C27: Reserved*/
157 0xFF020500, /* C28: Port (Interface-based) configurations */
158 0x00000000, /* C29: Reserved*/
159 0x00000000, /* C30: Reserved*/
160 0x00000000 /* C31: Reserved*/
161 },
162
163 /* Ingress1 PDSP1: Classify1 */
164 {
165 0xFFF88000, /* C0: LUT1 Info */
166 0xFFF80000, /* C1: Loacl SRAM */
167 0xFF020000, /* C2: Global SRAM */
168 0xFF408800, /* C3: System Timer (PDSP0 Timer) */
169 0xFF000030, /* C4: MailBox */
170 0x00000000, /* C5: Reserved*/
171 0xFFF14000, /* C6: CDE new packet input region */
172 0xFFF10100, /* C7: CDE new packet output region */
173 0xFFF10200, /* C8: CDE held packet region */
174 0xFFF18800, /* C9: PDSP Timer (PDSP specific) */
175 0xFFF19000, /* C10: LUT1 Registers */
176 0xFFF19400, /* C11: LUT2 Registers */
177 0x00000000, /* C12: Reserved */
178 0x00000000, /* C13: Reserved*/
179 0xFFF80100, /* C14: PDSP Context */
180 0x00000000, /* C15: Reserved*/
181 0xFFF80400, /* C16: IP Traffic Flow */
182 0xFFF80800, /* C17: IP Reassembly Control Block */
183 0xFFF80D00, /* C18: IP Protocol Table */
184 0xFF020000, /* C19: Custom LUT1 and global configuration */
185 0xFF020200, /* C20: Exception Routes */
186 0xFFF81100, /* C21: Classify1 Parsing Call Table */
187 0x00000000, /* C22: Reserved */
188 0xFFF83F20, /* C23: PDSP Info */
189 0xFFF81400, /* C24: Next Route Global address table */
190 0xFF9800C0, /* C25: User Stats CB and FIFO (Global address of Post cluster) */
191 0x00000000, /* C26: Reserved*/
192 0x00000000, /* C27: Reserved*/
193 0xFF020500, /* C28: Port (Interface-based) configurations */
194 0x00000000, /* C29: Reserved*/
195 0x00000000, /* C30: Reserved*/
196 0x00000000 /* C31: Reserved*/
197 },
198
199 /* Ingress2 PDSP0: Classify1 */
200 {
201 0xFFF82000, /* C0: LUT1 Info */
202 0xFFF80000, /* C1: Loacl SRAM */
203 0xFF020000, /* C2: Global SRAM */
204 0xFF408800, /* C3: System Timer (PDSP0 Timer) */
205 0xFF000040, /* C4: MailBox */
206 0x00000000, /* C5: Reserved*/
207 0xFFF04000, /* C6: CDE new packet input region */
208 0xFFF00100, /* C7: CDE new packet output region */
209 0xFFF00200, /* C8: CDE held packet region */
210 0xFFF08800, /* C9: PDSP Timer (PDSP specific) */
211 0xFFF09000, /* C10: LUT1 Registers */
212 0xFFF09400, /* C11: LUT2 Registers */
213 0x00000000, /* C12: Reserved */
214 0x00000000, /* C13: Reserved*/
215 0xFFF80000, /* C14: PDSP Context */
216 0x00000000, /* C15: Reserved*/
217 0xFFF80400, /* C16: IP Traffic Flow */
218 0xFFF80800, /* C17: IP Reassembly Control Block */
219 0xFFF80C00, /* C18: IP Protocol Table */
220 0xFF020000, /* C19: Custom LUT1 and global configuration */
221 0xFF020200, /* C20: Exception Routes */
222 0xFFF81000, /* C21: Classify1 Parsing Call Table */
223 0x00000000, /* C22: Reserved */
224 0xFFF81F00, /* C23: PDSP Info */
225 0xFFF81400, /* C24: Next Route Global address table */
226 0xFF980100, /* C25: User Stats CB and FIFO (Global address of Post cluster) */
227 0x00000000, /* C26: Reserved*/
228 0x00000000, /* C27: Reserved*/
229 0xFF020500, /* C28: Port (Interface-based) configurations */
230 0x00000000, /* C29: Reserved*/
231 0x00000000, /* C30: Reserved*/
232 0x00000000 /* C31: Reserved*/
233 },
234
235 /* Ingress3 PDSP0: Classify1 */
236 {
237 0xFFF82000, /* C0: LUT1 Info */
238 0xFFF80000, /* C1: Loacl SRAM */
239 0xFF020000, /* C2: Global SRAM */
240 0xFF408800, /* C3: System Timer (PDSP0 Timer) */
241 0xFF000050, /* C4: MailBox */
242 0x00000000, /* C5: Reserved*/
243 0xFFF04000, /* C6: CDE new packet input region */
244 0xFFF00100, /* C7: CDE new packet output region */
245 0xFFF00200, /* C8: CDE held packet region */
246 0xFFF08800, /* C9: PDSP Timer (PDSP specific) */
247 0xFFF09000, /* C10: LUT1 Registers */
248 0xFFF09400, /* C11: LUT2 Registers */
249 0x00000000, /* C12: Reserved */
250 0x00000000, /* C13: Reserved*/
251 0xFFF80000, /* C14: PDSP Context */
252 0x00000000, /* C15: Reserved*/
253 0xFFF80400, /* C16: IP Traffic Flow */
254 0xFFF80800, /* C17: IP Reassembly Control Block */
255 0xFFF80C00, /* C18: IP Protocol Table */
256 0xFF020000, /* C19: Custom LUT1 and global configuration */
257 0xFF020200, /* C20: Exception Routes */
258 0xFFF81000, /* C21: Classify1 Parsing Call Table */
259 0x00000000, /* C22: Reserved */
260 0xFFF81F00, /* C23: PDSP Info */
261 0xFFF81400, /* C24: Next Route Global address table */
262 0xFF980140, /* C25: User Stats CB and FIFO (Global address of Post cluster) */
263 0x00000000, /* C26: Reserved*/
264 0x00000000, /* C27: Reserved*/
265 0xFF020500, /* C28: Port (Interface-based) configurations */
266 0x00000000, /* C29: Reserved*/
267 0x00000000, /* C30: Reserved*/
268 0x00000000 /* C31: Reserved*/
269 },
270
271 /* Ingress4 PDSP0: Classify1 */
272 {
273 0xFFF84000, /* C0: LUT1 Info */
274 0xFFF80000, /* C1: Loacl SRAM */
275 0xFF020000, /* C2: Global SRAM */
276 0xFF408800, /* C3: System Timer (PDSP0 Timer) */
277 0xFF000060, /* C4: MailBox */
278 0x00000000, /* C5: Reserved*/
279 0xFFF04000, /* C6: CDE new packet input region */
280 0xFFF00100, /* C7: CDE new packet output region */
281 0xFFF00200, /* C8: CDE held packet region */
282 0xFFF08800, /* C9: PDSP Timer (PDSP specific) */
283 0xFFF09000, /* C10: LUT1 Registers */
284 0xFFF09400, /* C11: LUT2 Registers */
285 0x00000000, /* C12: Reserved */
286 0x00000000, /* C13: Reserved*/
287 0xFFF80000, /* C14: PDSP Context */
288 0x00000000, /* C15: Reserved*/
289 0xFFF80400, /* C16: IP Traffic Flow */
290 0xFFF80800, /* C17: IP Reassembly Control Block */
291 0xFFF80C00, /* C18: IP Protocol Table */
292 0xFF020000, /* C19: Custom LUT1 and global configuration */
293 0xFF020200, /* C20: Exception Routes */
294 0xFFF81000, /* C21: Classify1 Parsing Call Table */
295 0x00000000, /* C22: Reserved */
296 0xFFF83F00, /* C23: PDSP Info */
297 0xFFF81400, /* C24: Next Route Global address table */
298 0xFF980180, /* C25: User Stats CB and FIFO (Global address of Post Cluster) */
299 0x00000000, /* C26: Reserved*/
300 0x00000000, /* C27: Reserved*/
301 0xFF020500, /* C28: Port (Interface-based) configurations */
302 0x00000000, /* C29: Reserved*/
303 0x00000000, /* C30: Reserved*/
304 0x00000000 /* C31: Reserved*/
305 },
306
307 /* Ingress4 PDSP1: Classify2 */
308 {
309 0xFFF88000, /* C0: LUT1 Info */
310 0xFFF80000, /* C1: Loacl SRAM */
311 0xFF020000, /* C2: Global SRAM */
312 0xFF408800, /* C3: System Timer (PDSP0 Timer) */
313 0xFF000070, /* C4: MailBox */
314 0x00000000, /* C5: Reserved*/
315 0xFFF14000, /* C6: CDE new packet input region */
316 0xFFF10100, /* C7: CDE new packet output region */
317 0xFFF10200, /* C8: CDE held packet region */
318 0xFFF18800, /* C9: PDSP Timer (PDSP specific) */
319 0xFFF19000, /* C10: LUT1 Registers */
320 0xFFF19400, /* C11: LUT2 Registers */
321 0x00000000, /* C12: Reserved */
322 0x00000000, /* C13: Reserved*/
323 0x00000000, /* C14: Reserved*/
324 0x00000000, /* C15: Reserved*/
325 0xFFF81800, /* C16: Custom2 Info */
326 0x00000000, /* C17: Reserved*/
327 0x00000000, /* C18: Reserved*/
328 0xFF020000, /* C19: Custom LUT1 and global configuration */
329 0xFF020200, /* C20: Exception Routes */
330 0xFFF81100, /* C21: Classify2 Parsing Call Table */
331 0x00000000, /* C22: Reserved */
332 0xFFF83F20, /* C23: PDSP Info */
333 0xFFF81400, /* C24: Next Route Global address table */
334 0xFF9801C0, /* C25: User Stats CB and FIFO (Global address of Post cluster) */
335 0x00000000, /* C26: Reserved*/
336 0x00000000, /* C27: Reserved*/
337 0xFF020500, /* C28: Port (Interface-based) configurations */
338 0x00000000, /* C29: Reserved*/
339 0x00000000, /* C30: Reserved*/
340 0x00000000 /* C31: Reserved*/
341 },
342
343 /* Post PDSP0: Modifier */
344 {
345 0xFFF80000, /* C0: User Stats FIFO Base */
346 0xFFF80000, /* C1: Loacl SRAM */
347 0xFF020000, /* C2: Global SRAM */
348 0xFF408800, /* C3: System Timer (PDSP0 Timer) */
349 0xFF000080, /* C4: MailBox */
350 0x00000000, /* C5: Reserved*/
351 0xFFF04000, /* C6: CDE new packet input region */
352 0xFFF00100, /* C7: CDE new packet output region */
353 0xFFF00200, /* C8: CDE held packet region */
354 0xFFF08800, /* C9: PDSP Timer (PDSP specific) */
355 0xFFF09000, /* C10: LUT1 Registers */
356 0xFFF09400, /* C11: LUT2 Registers */
357 0x00000000, /* C12: Reserved */
358 0x00000000, /* C13: Reserved*/
359 0x00000000, /* C14: Reserved*/
360 0xFFF80400, /* C15: User Stats Control Block */
361 0xFFF80800, /* C16: User Stats */
362 0xFFF81000, /* C17: Command Set Table */
363 0xFFF81800, /* C18: Multi-route table */
364 0xFF020000, /* C19: Custom LUT1 and global configuration */
365 0xFF020200, /* C20: Exception Routes */
366 0xFFF82800, /* C21: CRC Verify FIFO */
367 0xFFF82900, /* C22: Split Context FIFO */
368 0xFFF83F00, /* C23: PDSP Info*/
369 0x00000000, /* C24: Reserved */
370 0xFFF80200, /* C25: User Stats CB and FIFO (Global address of Post cluster) */
371 0x00000000, /* C26: Reserved*/
372 0x00000000, /* C27: Reserved*/
373 0xFF020500, /* C28: Port (Interface-based) configurations */
374 0x00000000, /* C29: Reserved*/
375 0x00000000, /* C30: Reserved*/
376 0x00000000 /* C31: Reserved*/
377 },
378
379 /* Post PDSP1: Modifier */
380 {
381 0xFFF80000, /* C0: User Stats FIFO Base */
382 0xFFF80000, /* C1: Loacl SRAM */
383 0xFF020000, /* C2: Global SRAM */
384 0xFF408800, /* C3: System Timer (PDSP0 Timer) */
385 0xFF000090, /* C4: MailBox */
386 0x00000000, /* C5: Reserved*/
387 0xFFF14000, /* C6: CDE new packet input region */
388 0xFFF10100, /* C7: CDE new packet output region */
389 0xFFF10200, /* C8: CDE held packet region */
390 0xFFF18800, /* C9: PDSP Timer (PDSP specific) */
391 0xFFF19000, /* C10: LUT1 Registers */
392 0xFFF19400, /* C11: LUT2 Registers */
393 0x00000000, /* C12: Reserved */
394 0x00000000, /* C13: Reserved*/
395 0x00000000, /* C14: Reserved*/
396 0xFFF80400, /* C15: User Stats Control Block */
397 0xFFF80800, /* C16: User Stats */
398 0xFFF81000, /* C17: Command Set Table */
399 0xFFF82000, /* C18: Multi-route table */
400 0xFF020000, /* C19: Custom LUT1 and global configuration */
401 0xFF020200, /* C20: Exception Routes */
402 0xFFF82800, /* C21: CRC Verify FIFO */
403 0xFFF82900, /* C22: Split Context FIFO */
404 0xFFF83F20, /* C23: PDSP Info*/
405 0x00000000, /* C24: Reserved */
406 0xFFF80240, /* C25: User Stats CB and FIFO (Global address of Post cluster) */
407 0x00000000, /* C26: Reserved*/
408 0x00000000, /* C27: Reserved*/
409 0xFF020500, /* C28: Port (Interface-based) configurations */
410 0x00000000, /* C29: Reserved*/
411 0x00000000, /* C30: Reserved*/
412 0x00000000 /* C31: Reserved*/
413 },
414
415 /* Egress0 PDSP0: Flow Cache */
416 {
417 0xFFF82000, /* C0: LUT1 Info */
418 0xFFF80000, /* C1: Loacl SRAM */
419 0xFF020000, /* C2: Global SRAM */
420 0xFF408800, /* C3: System Timer (PDSP0 Timer) */
421 0xFF0000A0, /* C4: MailBox */
422 0x00000000, /* C5: Reserved*/
423 0xFFF04000, /* C6: CDE new packet input region */
424 0xFFF00100, /* C7: CDE new packet output region */
425 0xFFF00200, /* C8: CDE held packet region */
426 0xFFF08800, /* C9: PDSP Timer (PDSP specific) */
427 0xFFF09000, /* C10: LUT1 Registers */
428 0xFFF09400, /* C11: LUT2 Registers */
429 0xFFF84000, /* C12: Egress Flow Record0 */
430 0xFFF88000, /* C13: Egress Flow Record1 */
431 0xFFF80000, /* C14: PDSP Context */
432 0xFF980400, /* C15: User Stats Control Block */
433 0xFF980800, /* C16: User Stats */
434 0xFFF81000, /* C17: Modify Context */
435 0xFFF80200, /* C18: IP Protocol Table */
436 0xFF020000, /* C19: Custom LUT1 and global configuration */
437 0xFF020200, /* C20: Exception Routes */
438 0xFFF80500, /* C21: Parse table */
439 0x00000000, /* C22: Reserved */
440 0xFFF81F00, /* C23: PDSP Info */
441 0xFFF80A00, /* C24: Temporary Buffer */
442 0xFF980280, /* C25: User Stats CB and FIFO (Global address of Post cluster) */
443 0xFF020400, /* C26: Eflow Exception route */
444 0x00000000, /* C27: Reserved*/
445 0xFF020500, /* C28: Port (Interface-based) configurations */
446 0x00000000, /* C29: Reserved*/
447 0x00000000, /* C30: Reserved*/
448 0x00000000 /* C31: Reserved*/
449 },
450
451 /* Egress0 PDSP1: Flow Cache */
452 {
453 0x00000000, /* C0: Reserved */
454 0xFFF80000, /* C1: Loacl SRAM */
455 0xFF020000, /* C2: Global SRAM */
456 0xFF408800, /* C3: System Timer (PDSP0 Timer) */
457 0xFF0000B0, /* C4: MailBox */
458 0x00000000, /* C5: Reserved*/
459 0xFFF14000, /* C6: CDE new packet input region */
460 0xFFF10100, /* C7: CDE new packet output region */
461 0xFFF10200, /* C8: CDE held packet region */
462 0xFFF18800, /* C9: PDSP Timer (PDSP specific) */
463 0xFFF19000, /* C10: LUT1 Registers */
464 0xFFF19400, /* C11: LUT2 Registers */
465 0xFFF84000, /* C12: Egress Flow Record0 */
466 0xFFF88000, /* C13: Egress Flow Record1 */
467 0x00000000, /* C14: Reserved */
468 0xFF980400, /* C15: User Stats Control Block */
469 0xFF980800, /* C16: User Stats */
470 0xFFF81000, /* C17: Modify Context */
471 0xFFF80300, /* C18: IP Protocol Table */
472 0xFF020000, /* C19: Custom LUT1 and global configuration */
473 0xFF020200, /* C20: Exception Routes */
474 0xFFF80600, /* C21: Parse table */
475 0x00000000, /* C22: Reserved */
476 0xFFF81F20, /* C23: PDSP Info */
477 0xFFF80A00, /* C24: Temporary Buffer */
478 0xFF9802C0, /* C25: User Stats CB and FIFO (Global address of Post cluster) */
479 0xFF020400, /* C26: Eflow Exception route */
480 0xFFF80800, /* C27: Command Buffer */
481 0xFF020500, /* C28: Port (Interface-based) configurations */
482 0x00000000, /* C29: Reserved*/
483 0x00000000, /* C30: Reserved*/
484 0x00000000 /* C31: Reserved*/
485 },
486
487 /* Egress0 PDSP2: Flow Cache */
488 {
489 0x00000000, /* C0: Reserved */
490 0xFFF80000, /* C1: Loacl SRAM */
491 0xFF020000, /* C2: Global SRAM */
492 0xFF408800, /* C3: System Timer (PDSP0 Timer) */
493 0xFF0000C0, /* C4: MailBox */
494 0x00000000, /* C5: Reserved*/
495 0xFFF24000, /* C6: CDE new packet input region */
496 0xFFF20100, /* C7: CDE new packet output region */
497 0xFFF20200, /* C8: CDE held packet region */
498 0xFFF28800, /* C9: PDSP Timer (PDSP specific) */
499 0xFFF29000, /* C10: LUT1 Registers */
500 0xFFF29400, /* C11: LUT2 Registers */
501 0xFFF84000, /* C12: Egress Flow Record0 */
502 0xFFF88000, /* C13: Egress Flow Record1 */
503 0x00000000, /* C14: Reserved */
504 0xFF980400, /* C15: User Stats Control Block */
505 0xFF980800, /* C16: User Stats */
506 0xFFF81000, /* C17: Modify Context */
507 0xFFF80400, /* C18: IP Protocol Table */
508 0xFF020000, /* C19: Custom LUT1 and global configuration */
509 0xFF020200, /* C20: Exception Routes */
510 0xFFF80700, /* C21: Parse table */
511 0x00000000, /* C22: Reserved */
512 0xFFF81F40, /* C23: PDSP Info */
513 0xFFF80A00, /* C24: Temporary Buffer */
514 0xFF980300, /* C25: User Stats CB and FIFO (Global address of Post cluster) */
515 0xFF020400, /* C26: Eflow Exception route */
516 0xFFF80900, /* C27: Command Buffer */
517 0xFF020500, /* C28: Port (Interface-based) configurations */
518 0x00000000, /* C29: Reserved*/
519 0x00000000, /* C30: Reserved*/
520 0x00000000 /* C31: Reserved*/
521 },
522
523 /* Egress1 PDSP0: Flow Cache */
524 {
525 0x00000000, /* C0: Reserved */
526 0xFFF80000, /* C1: Loacl SRAM */
527 0xFF020000, /* C2: Global SRAM */
528 0xFF408800, /* C3: System Timer (PDSP0 Timer) */
529 0xFF0000D0, /* C4: MailBox */
530 0x00000000, /* C5: Reserved*/
531 0xFFF04000, /* C6: CDE new packet input region */
532 0xFFF00100, /* C7: CDE new packet output region */
533 0xFFF00200, /* C8: CDE held packet region */
534 0xFFF08800, /* C9: PDSP Timer (PDSP specific) */
535 0xFFF09000, /* C10: LUT1 Registers */
536 0xFFF09400, /* C11: LUT2 Registers */
537 0xFFF81000, /* C12: Egress Flow Record2 */
538 0x00000000, /* C13: Reserved*/
539 0xFFF80000, /* C14: PDSP Context */
540 0xFF980400, /* C15: User Stats Control Block */
541 0xFF980800, /* C16: User Stats */
542 0xFFF81000, /* C17: Modify Context */
543 0xFFF80200, /* C18: IP Protocol Table */
544 0xFF020000, /* C19: Custom LUT1 and global configuration */
545 0xFF020200, /* C20: Egress Exception Routes */
546 0xFFF80500, /* C21: Parse table */
547 0x00000000, /* C22: Reserved */
548 0xFFF80F00, /* C23: PDSP Info */
549 0xFFF80A00, /* C24: Temporary Buffer */
550 0xFF980340, /* C25: User Stats CB and FIFO (Global address of Post cluster) */
551 0xFF020400, /* C26: Eflow Exception route */
552 0xFFF80800, /* C27: Command Buffer */
553 0xFF020500, /* C28: Port (Interface-based) configurations */
554 0x00000000, /* C29: Reserved*/
555 0x00000000, /* C30: Reserved*/
556 0x00000000 /* C31: Reserved*/
557 },
558
559 /* Egress2 PDSP0: Flow Cache */
560 {
561 0x00000000, /* C0: Reserved */
562 0xFFF80000, /* C1: Loacl SRAM */
563 0xFF020000, /* C2: Global SRAM */
564 0xFF408800, /* C3: System Timer (PDSP0 Timer) */
565 0xFF0000E0, /* C4: MailBox */
566 0x00000000, /* C5: Reserved*/
567 0xFFF04000, /* C6: CDE new packet input region */
568 0xFFF00100, /* C7: CDE new packet output region */
569 0xFFF00200, /* C8: CDE held packet region */
570 0xFFF08800, /* C9: PDSP Timer (PDSP specific) */
571 0xFFF09000, /* C10: LUT1 Registers */
572 0xFFF09400, /* C11: LUT2 Registers */
573 0xFFF81000, /* C12: Egress Flow Record3 */
574 0x00000000, /* C13: Reserved*/
575 0xFFF80000, /* C14: PDSP Context */
576 0xFF980400, /* C15: User Stats Control Block */
577 0xFF980800, /* C16: User Stats */
578 0xFFF81000, /* C17: Modify Context */
579 0xFFF80200, /* C18: IP Protocol Table */
580 0xFF020000, /* C19: Custom LUT1 and global configuration */
581 0xFF020200, /* C20: Egress Exception Routes */
582 0xFFF80500, /* C21: Parse table */
583 0x00000000, /* C22: Reserved */
584 0xFFF80F00, /* C23: PDSP Info */
585 0xFFF80A00, /* C24: Temporary Buffer */
586 0xFF980380, /* C25: User Stats CB and FIFO (Global address of Post cluster) */
587 0xFF020400, /* C26: Eflow Exception route */
588 0xFFF80800, /* C27: Command Buffer */
589 0xFF020500, /* C28: Port (Interface-based) configurations */
590 0x00000000, /* C29: Reserved*/
591 0x00000000, /* C30: Reserved*/
592 0x00000000 /* C31: Reserved*/
593 }
594
595};
diff --git a/src/v1/pafrm.h b/src/v1/pafrm.h
index ec904ac..ec904ac 100755..100644
--- a/src/v1/pafrm.h
+++ b/src/v1/pafrm.h