diff options
Diffstat (limited to 'test/PAUnitTest/k2l/armv7/bios/pa_utest_k2l.cfg')
-rwxr-xr-x | test/PAUnitTest/k2l/armv7/bios/pa_utest_k2l.cfg | 148 |
1 files changed, 148 insertions, 0 deletions
diff --git a/test/PAUnitTest/k2l/armv7/bios/pa_utest_k2l.cfg b/test/PAUnitTest/k2l/armv7/bios/pa_utest_k2l.cfg new file mode 100755 index 0000000..73f25f0 --- /dev/null +++ b/test/PAUnitTest/k2l/armv7/bios/pa_utest_k2l.cfg | |||
@@ -0,0 +1,148 @@ | |||
1 | /* | ||
2 | * Copyright 2015 by Texas Instruments Incorporated. | ||
3 | * | ||
4 | * All rights reserved. Property of Texas Instruments Incorporated. | ||
5 | * Restricted rights to use, duplicate or disclose this code are | ||
6 | * granted through contract. | ||
7 | * | ||
8 | */ | ||
9 | |||
10 | /* | ||
11 | * ======== pa_utest_k2h.cfg ======== | ||
12 | * | ||
13 | */ | ||
14 | |||
15 | var Memory = xdc.useModule('xdc.runtime.Memory'); | ||
16 | var BIOS = xdc.useModule('ti.sysbios.BIOS'); | ||
17 | var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem'); | ||
18 | var Task = xdc.useModule('ti.sysbios.knl.Task'); | ||
19 | var Idle = xdc.useModule('ti.sysbios.knl.Idle'); | ||
20 | var Swi = xdc.useModule('ti.sysbios.knl.Swi'); | ||
21 | var Clock = xdc.useModule('ti.sysbios.knl.Clock'); | ||
22 | var Event = xdc.useModule('ti.sysbios.knl.Event'); | ||
23 | var Mailbox = xdc.useModule('ti.sysbios.knl.Mailbox'); | ||
24 | var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore'); | ||
25 | var Log = xdc.useModule('xdc.runtime.Log'); | ||
26 | var LoggerBuf = xdc.useModule('xdc.runtime.LoggerBuf'); | ||
27 | var Main = xdc.useModule('xdc.runtime.Main'); | ||
28 | var Defaults = xdc.useModule('xdc.runtime.Defaults'); | ||
29 | var Diags = xdc.useModule('xdc.runtime.Diags'); | ||
30 | var SysMin = xdc.useModule('xdc.runtime.SysMin'); | ||
31 | var System = xdc.useModule('xdc.runtime.System'); | ||
32 | var Text = xdc.useModule('xdc.runtime.Text'); | ||
33 | |||
34 | /* Load the CPPI package */ | ||
35 | var Cppi = xdc.loadPackage('ti.drv.cppi'); | ||
36 | /* Load the QMSS package */ | ||
37 | var Qmss = xdc.loadPackage('ti.drv.qmss'); | ||
38 | |||
39 | var devType = "k2l" | ||
40 | var Pa = xdc.useModule('ti.drv.pa.Settings'); | ||
41 | Pa.deviceType = devType; | ||
42 | |||
43 | /* Load the RM package */ | ||
44 | var Rm = xdc.loadPackage('ti.drv.rm'); | ||
45 | |||
46 | Clock.timerId = -1; | ||
47 | Task.defaultStackSize = 4096 * 4; | ||
48 | |||
49 | /* | ||
50 | * Program.argSize sets the size of the .args section. | ||
51 | * The examples don't use command line args so argSize is set to 0. | ||
52 | */ | ||
53 | Program.argSize = 0x0; | ||
54 | |||
55 | /* | ||
56 | * The BIOS module will create the default heap for the system. | ||
57 | * Specify the size of this default heap. | ||
58 | */ | ||
59 | BIOS.heapSize = 0x10000; | ||
60 | |||
61 | /* | ||
62 | * Build a custom SYS/BIOS library from sources. | ||
63 | */ | ||
64 | BIOS.libType = BIOS.LibType_Custom; | ||
65 | |||
66 | /* System stack size (used by ISRs and Swis) */ | ||
67 | Program.stack = 0x20000; | ||
68 | |||
69 | /* Circular buffer size for System_printf() */ | ||
70 | SysMin.bufSize = 0x400; | ||
71 | |||
72 | /* | ||
73 | * Create and install logger for the whole system | ||
74 | */ | ||
75 | var loggerBufParams = new LoggerBuf.Params(); | ||
76 | loggerBufParams.numEntries = 32; | ||
77 | var logger0 = LoggerBuf.create(loggerBufParams); | ||
78 | Defaults.common$.logger = logger0; | ||
79 | Main.common$.diags_INFO = Diags.ALWAYS_ON; | ||
80 | |||
81 | System.SupportProxy = SysMin; | ||
82 | var SemiHost = xdc.useModule('ti.sysbios.rts.gnu.SemiHostSupport'); | ||
83 | |||
84 | var Cache = xdc.useModule('ti.sysbios.family.arm.a15.Cache'); | ||
85 | var Mmu = xdc.useModule('ti.sysbios.family.arm.a15.Mmu'); | ||
86 | |||
87 | /* Enable the cache */ | ||
88 | Cache.enableCache = true; | ||
89 | |||
90 | // Enable the MMU (Required for L1/L2 data caching) | ||
91 | Mmu.enableMMU = true; | ||
92 | |||
93 | // descriptor attribute structure | ||
94 | var peripheralAttrs = new Mmu.DescriptorAttrs(); | ||
95 | |||
96 | Mmu.initDescAttrsMeta(peripheralAttrs); | ||
97 | |||
98 | peripheralAttrs.type = Mmu.DescriptorType_BLOCK; // BLOCK descriptor | ||
99 | peripheralAttrs.noExecute = true; // not executable | ||
100 | peripheralAttrs.accPerm = 0; // read/write at PL1 | ||
101 | peripheralAttrs.attrIndx = 1; // MAIR0 Byte1 describes | ||
102 | // memory attributes for | ||
103 | // Define the base address of the 2 MB page | ||
104 | // the peripheral resides in. | ||
105 | var peripheralBaseAddrs = [ | ||
106 | { base: 0x02620000, size: 0x00001000 }, // bootcfg | ||
107 | { base: 0x0bc00000, size: 0x00100000 }, // MSMC config | ||
108 | { base: 0x26000000, size: 0x01000000 }, // NETCP memory | ||
109 | { base: 0x02a00000, size: 0x00100000 }, // QMSS config memory | ||
110 | { base: 0x23A00000, size: 0x00100000 }, // QMSS Data memory | ||
111 | { base: 0x02901000, size: 0x00002000 }, // SRIO pkt dma config memory | ||
112 | { base: 0x01f14000, size: 0x00007000 }, // AIF pkt dma config memory | ||
113 | { base: 0x021F0200, size: 0x00000600 }, // FFTC 0 pkt dma config memory | ||
114 | { base: 0x021F0a00, size: 0x00000600 }, // FFTC 4 pkt dma config memory | ||
115 | { base: 0x021F1200, size: 0x00000600 }, // FFTC 5 pkt dma config memory | ||
116 | { base: 0x021F4200, size: 0x00000600 }, // FFTC 1 pkt dma config memory | ||
117 | { base: 0x021F8200, size: 0x00000600 }, // FFTC 2 pkt dma config memory | ||
118 | { base: 0x021FC200, size: 0x00000600 }, // FFTC 3 pkt dma config memory | ||
119 | { base: 0x02554000, size: 0x00009000 } // BCP pkt dma config memory | ||
120 | ]; | ||
121 | |||
122 | // Configure the corresponding MMU page descriptor accordingly | ||
123 | for (var i =0; i < peripheralBaseAddrs.length; i++) | ||
124 | { | ||
125 | for (var j = 0; j < peripheralBaseAddrs[i].size; j += 0x200000) | ||
126 | { | ||
127 | var addr = peripheralBaseAddrs[i].base + j; | ||
128 | Mmu.setSecondLevelDescMeta(addr, addr, peripheralAttrs); | ||
129 | } | ||
130 | } | ||
131 | |||
132 | // Reconfigure DDR to use coherent address | ||
133 | Mmu.initDescAttrsMeta(peripheralAttrs); | ||
134 | |||
135 | peripheralAttrs.type = Mmu.DescriptorType_BLOCK; | ||
136 | peripheralAttrs.shareable = 2; // outer-shareable (3=inner, 0=none) | ||
137 | peripheralAttrs.accPerm = 1; // read/write at any privelege level | ||
138 | peripheralAttrs.attrIndx = 2; // normal cacheable (0=no cache, 1=strict order) | ||
139 | for (var vaddr = 0x80000000, paddr = 0x800000000; vaddr < 0x100000000; vaddr += 0x200000, paddr+= 0x200000) | ||
140 | { | ||
141 | Mmu.setSecondLevelDescMeta(vaddr, paddr, peripheralAttrs); | ||
142 | } | ||
143 | // Add MSMC as coherent | ||
144 | for (var addr = 0x0c000000; addr < 0x0c600000; addr += 0x200000) | ||
145 | { | ||
146 | Mmu.setSecondLevelDescMeta(addr, addr, peripheralAttrs); | ||
147 | } | ||
148 | |||