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authorJohn Dowdal2019-05-29 15:48:59 -0500
committerJohn Dowdal2019-05-29 15:48:59 -0500
commit089e21810100ad3c56254e607fd417cee2ea3af9 (patch)
tree946dfbeb7df05c23f4a97d304d3dffb243bcc6a0
parent202a89929d8da0ac923978145b4cc44cfafc12d5 (diff)
downloadpcie-lld-089e21810100ad3c56254e607fd417cee2ea3af9.tar.gz
pcie-lld-089e21810100ad3c56254e607fd417cee2ea3af9.tar.xz
pcie-lld-089e21810100ad3c56254e607fd417cee2ea3af9.zip
PRSDK-5874 : enable 2 lane on IDK
-rw-r--r--example/sample/am65xx/src/pcie_sample_board.c54
-rw-r--r--example/sample/am65xx/src/pcie_sample_board.h2
-rw-r--r--example/sample/src/pcie_sample.c10
3 files changed, 41 insertions, 25 deletions
diff --git a/example/sample/am65xx/src/pcie_sample_board.c b/example/sample/am65xx/src/pcie_sample_board.c
index 06082af..4c804f2 100644
--- a/example/sample/am65xx/src/pcie_sample_board.c
+++ b/example/sample/am65xx/src/pcie_sample_board.c
@@ -141,10 +141,11 @@ static void unlock_mmrs(void)
141 141
142void CSL_serdesWaitForCMUOK(uint32_t baseAddr); 142void CSL_serdesWaitForCMUOK(uint32_t baseAddr);
143 143
144void PlatformPCIESSSerdesConfig(int32_t serdes) 144void PlatformPCIESSSerdesConfig(int32_t serdes, int32_t iface)
145{ 145{
146 uint32_t serdesBase; 146 uint32_t serdesBase;
147 uint32_t i; 147 uint32_t i;
148 static int32_t sciInit = 0;
148 int32_t sciStatus = CSL_EFAIL; 149 int32_t sciStatus = CSL_EFAIL;
149 CSL_SerdesResult status; 150 CSL_SerdesResult status;
150 CSL_SerdesLaneEnableParams serdesLaneEnableParams; 151 CSL_SerdesLaneEnableParams serdesLaneEnableParams;
@@ -169,26 +170,30 @@ void PlatformPCIESSSerdesConfig(int32_t serdes)
169 (uint8_t *) &sciResponse, 170 (uint8_t *) &sciResponse,
170 (uint32_t)sizeof (sciResponse) 171 (uint32_t)sizeof (sciResponse)
171 }; 172 };
172 173
173 sciStatus = Sciclient_init(&sciConfig); 174 if (! sciInit)
174 if (sciStatus != CSL_PASS)
175 {
176 UART_printf("SYSFW init ...FAILED\n");
177 exit(1);
178 }
179 /* Check that sciclient is working (tap the mic) */
180 sciStatus = Sciclient_service(&sciReqPrm, &sciRespPrm);
181 if (CSL_PASS == sciStatus)
182 { 175 {
183 if (sciRespPrm.flags == (uint32_t)TISCI_MSG_FLAG_ACK) 176 sciStatus = Sciclient_init(&sciConfig);
177 if (sciStatus != CSL_PASS)
184 { 178 {
185 UART_printf("SYSFW ver %s running\n", (char *) sciResponse.str); 179 UART_printf("SYSFW init ...FAILED\n");
180 exit(1);
186 } 181 }
187 else 182 /* Check that sciclient is working (tap the mic) */
183 sciStatus = Sciclient_service(&sciReqPrm, &sciRespPrm);
184 if (CSL_PASS == sciStatus)
188 { 185 {
189 UART_printf("SYSFW Get Version failed \n"); 186 if (sciRespPrm.flags == (uint32_t)TISCI_MSG_FLAG_ACK)
190 exit(1); 187 {
188 UART_printf("SYSFW ver %s running\n", (char *) sciResponse.str);
189 }
190 else
191 {
192 UART_printf("SYSFW Get Version failed \n");
193 exit(1);
194 }
191 } 195 }
196 sciInit = 1;
192 } 197 }
193 memset (&serdesLaneEnableParams, 0, sizeof(serdesLaneEnableParams)); 198 memset (&serdesLaneEnableParams, 0, sizeof(serdesLaneEnableParams));
194 199
@@ -228,11 +233,9 @@ void PlatformPCIESSSerdesConfig(int32_t serdes)
228 Bit3 - Right side chaining enable is inverted from Left side (Bit1) 233 Bit3 - Right side chaining enable is inverted from Left side (Bit1)
229 */ 234 */
230 235
231 CSL_FINSR(*(volatile uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_SERDES0_CTRL), 1, 0, 0x1);
232 CSL_FINSR(*(volatile uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_SERDES1_CTRL), 1, 0, 0x0);
233
234 if (serdes == 0) 236 if (serdes == 0)
235 { 237 {
238 CSL_FINSR(*(volatile uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_SERDES0_CTRL), 1, 0, 0x1);
236 CSL_FINSR(*(volatile uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_SERDES0_CTRL), 7, 4, 0x4); //Left CML 239 CSL_FINSR(*(volatile uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_SERDES0_CTRL), 7, 4, 0x4); //Left CML
237 sciStatus = Sciclient_pmSetModuleClkParent ( 240 sciStatus = Sciclient_pmSetModuleClkParent (
238 TISCI_DEV_SERDES0, 241 TISCI_DEV_SERDES0,
@@ -242,7 +245,16 @@ void PlatformPCIESSSerdesConfig(int32_t serdes)
242 } 245 }
243 else 246 else
244 { 247 {
245 CSL_FINSR(*(volatile uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_SERDES1_CTRL), 7, 4, 0x0); //Right CML 248 if (iface == 0)
249 {
250 CSL_FINSR(*(volatile uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_SERDES1_CTRL), 1, 0, 0x1);
251 }
252 else
253 {
254 CSL_FINSR(*(volatile uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_SERDES1_CTRL), 1, 0, 0x0);
255 }
256 CSL_FINSR(*(volatile uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_SERDES1_CTRL), 7, 4, 0x1); //Right CML
257
246 sciStatus = Sciclient_pmSetModuleClkParent ( 258 sciStatus = Sciclient_pmSetModuleClkParent (
247 TISCI_DEV_SERDES1, 259 TISCI_DEV_SERDES1,
248 TISCI_DEV_SERDES1_BUS_RI_REFCLK, 260 TISCI_DEV_SERDES1_BUS_RI_REFCLK,
@@ -295,7 +307,7 @@ void PlatformPCIESSSerdesConfig(int32_t serdes)
295 exit (1); 307 exit (1);
296 } 308 }
297 309
298 PCIE_logPrintf ("Serdes Init Complete\n"); 310 PCIE_logPrintf ("Serdes Init Complete (%d)\n", serdes);
299 311
300 /* Check CMU_OK */ 312 /* Check CMU_OK */
301 CSL_serdesWaitForCMUOK(serdesLaneEnableParams.baseAddr); 313 CSL_serdesWaitForCMUOK(serdesLaneEnableParams.baseAddr);
diff --git a/example/sample/am65xx/src/pcie_sample_board.h b/example/sample/am65xx/src/pcie_sample_board.h
index 84e7be4..b2a2e3a 100644
--- a/example/sample/am65xx/src/pcie_sample_board.h
+++ b/example/sample/am65xx/src/pcie_sample_board.h
@@ -42,7 +42,7 @@
42 42
43#include <ti/osal/osal.h> 43#include <ti/osal/osal.h>
44 44
45void PlatformPCIESSSerdesConfig(int32_t serdes); 45void PlatformPCIESSSerdesConfig(int32_t serdes, int32_t iface);
46SemaphoreP_Handle PlatformSetupMSIAndINTX (void *handle); 46SemaphoreP_Handle PlatformSetupMSIAndINTX (void *handle);
47 47
48#endif 48#endif
diff --git a/example/sample/src/pcie_sample.c b/example/sample/src/pcie_sample.c
index a17cc82..bae5608 100644
--- a/example/sample/src/pcie_sample.c
+++ b/example/sample/src/pcie_sample.c
@@ -548,9 +548,10 @@ pcieRet_e pcieSerdesCfg(void)
548 PlatformPCIESS2PhyConfig(); 548 PlatformPCIESS2PhyConfig();
549#elif defined(SOC_AM65XX) 549#elif defined(SOC_AM65XX)
550#ifdef am65xx_idk 550#ifdef am65xx_idk
551 PlatformPCIESSSerdesConfig(0); 551 PlatformPCIESSSerdesConfig(0, 0);
552 PlatformPCIESSSerdesConfig(1, 0);
552#else 553#else
553 PlatformPCIESSSerdesConfig(1); 554 PlatformPCIESSSerdesConfig(1, 1);
554#endif 555#endif
555#else 556#else
556#ifndef SIMULATOR_SUPPORT 557#ifndef SIMULATOR_SUPPORT
@@ -1763,7 +1764,6 @@ void pcieRcWaitInts (Pcie_Handle handle, SemaphoreP_Handle sem, void *pcieBase)
1763void pcieSetLanes (Pcie_Handle handle) 1764void pcieSetLanes (Pcie_Handle handle)
1764{ 1765{
1765#ifdef PCIE_REV2_HW 1766#ifdef PCIE_REV2_HW
1766 /* Request just 1 lane -- this would work on all HW */
1767 pcieLnkCtrlReg_t lnkCtrlReg; 1767 pcieLnkCtrlReg_t lnkCtrlReg;
1768 pcieRegisters_t regs; 1768 pcieRegisters_t regs;
1769 uint8_t origLanes; 1769 uint8_t origLanes;
@@ -1776,7 +1776,11 @@ void pcieSetLanes (Pcie_Handle handle)
1776 exit(1); 1776 exit(1);
1777 } 1777 }
1778 origLanes = lnkCtrlReg.lnkMode; 1778 origLanes = lnkCtrlReg.lnkMode;
1779#ifdef am65xx_idk
1780 lnkCtrlReg.lnkMode = 3; /* bitfield enabling both lanes */
1781#else
1779 lnkCtrlReg.lnkMode = 1; 1782 lnkCtrlReg.lnkMode = 1;
1783#endif
1780 if (Pcie_writeRegs (handle, pcie_LOCATION_LOCAL, &regs) != pcie_RET_OK) 1784 if (Pcie_writeRegs (handle, pcie_LOCATION_LOCAL, &regs) != pcie_RET_OK)
1781 { 1785 {
1782 PCIE_logPrintf ("Write LnkCtrl register failed!\n"); 1786 PCIE_logPrintf ("Write LnkCtrl register failed!\n");