summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorJohn Dowdal2018-08-14 16:24:40 -0500
committerJohn Dowdal2018-09-12 16:40:18 -0500
commitfabfa8a7d1e58725e33ec0647b4789c0f00c5115 (patch)
treefd6fc7d96022f0c36146e0724be6b5c514b3e399 /example
parentbf8d3a22c03a5f273321c284fa1737072eca3f77 (diff)
downloadpcie-lld-fabfa8a7d1e58725e33ec0647b4789c0f00c5115.tar.gz
pcie-lld-fabfa8a7d1e58725e33ec0647b4789c0f00c5115.tar.xz
pcie-lld-fabfa8a7d1e58725e33ec0647b4789c0f00c5115.zip
PRSDK-3849 rev 2 (am65xx) tested with makefile example. Other revs library builds.
Diffstat (limited to 'example')
-rw-r--r--example/sample/am65xx/pciesample_a53.cfg150
-rw-r--r--example/sample/am65xx/pciesample_r5.cfg161
-rw-r--r--example/sample/am65xx/r5_MPU.xs126
-rw-r--r--example/sample/am65xx/src/pcie_sample_board.c529
-rw-r--r--example/sample/am65xx/src/pcie_sample_board.h49
-rw-r--r--example/sample/makefile47
-rw-r--r--example/sample/src/pcie_sample.c370
-rw-r--r--example/sample/src/pcie_sample.h28
8 files changed, 1302 insertions, 158 deletions
diff --git a/example/sample/am65xx/pciesample_a53.cfg b/example/sample/am65xx/pciesample_a53.cfg
new file mode 100644
index 0000000..b721263
--- /dev/null
+++ b/example/sample/am65xx/pciesample_a53.cfg
@@ -0,0 +1,150 @@
1
2/* =============================================================================
3 * Copyright (c) Texas Instruments Incorporated 2018
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the
15 * distribution.
16 *
17 * Neither the name of Texas Instruments Incorporated nor the names of
18 * its contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 */
33var Defaults = xdc.useModule('xdc.runtime.Defaults');
34var Diags = xdc.useModule('xdc.runtime.Diags');
35var Error = xdc.useModule('xdc.runtime.Error');
36var Log = xdc.useModule('xdc.runtime.Log');
37var LoggerBuf = xdc.useModule('xdc.runtime.LoggerBuf');
38var Main = xdc.useModule('xdc.runtime.Main');
39var Memory = xdc.useModule('xdc.runtime.Memory')
40var System = xdc.useModule('xdc.runtime.System');
41var Text = xdc.useModule('xdc.runtime.Text');
42var Clock = xdc.useModule('ti.sysbios.knl.Clock');
43var Task = xdc.useModule('ti.sysbios.knl.Task');
44var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
45
46var BIOS = xdc.useModule('ti.sysbios.BIOS');
47var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');
48var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
49var SysMin = xdc.useModule('xdc.runtime.SysMin');
50
51
52var Cache = xdc.module("ti.sysbios.hal.Cache");
53Cache.CacheProxy = xdc.useModule("ti.sysbios.family.arm.v8a.Cache");
54/*
55 * Direct CIO to UART
56 */
57/* System.SupportProxy = SysUart; */
58System.SupportProxy = SysMin;
59
60/*
61 * Program.argSize sets the size of the .args section.
62 * The examples don't use command line args so argSize is set to 0.
63 */
64Program.argSize = 0x0;
65
66/*
67 * Uncomment this line to globally disable Asserts.
68 * All modules inherit the default from the 'Defaults' module. You
69 * can override these defaults on a per-module basis using Module.common$.
70 * Disabling Asserts will save code space and improve runtime performance.
71Defaults.common$.diags_ASSERT = Diags.ALWAYS_OFF;
72 */
73
74/*
75 * Uncomment this line to keep module names from being loaded on the target.
76 * The module name strings are placed in the .const section. Setting this
77 * parameter to false will save space in the .const section. Error and
78 * Assert messages will contain an "unknown module" prefix instead
79 * of the actual module name.
80Defaults.common$.namedModule = false;
81 */
82
83
84/* Create default heap and hook it into Memory */
85var heapMemParams = new HeapMem.Params;
86heapMemParams.size = 0x10000;
87var heap0 = HeapMem.create(heapMemParams);
88
89Memory.defaultHeapInstance = heap0;
90
91/*
92 * Minimize exit handler array in System. The System module includes
93 * an array of functions that are registered with System_atexit() to be
94 * called by System_exit().
95 */
96System.maxAtexitHandlers = 4;
97
98/*
99 * Uncomment this line to disable the Error print function.
100 * We lose error information when this is disabled since the errors are
101 * not printed. Disabling the raiseHook will save some code space if
102 * your app is not using System_printf() since the Error_print() function
103 * calls System_printf().
104Error.raiseHook = null;
105 */
106
107/*
108 * Uncomment this line to keep Error, Assert, and Log strings from being
109 * loaded on the target. These strings are placed in the .const section.
110 * Setting this parameter to false will save space in the .const section.
111 * Error, Assert and Log message will print raw ids and args instead of
112 * a formatted message.
113Text.isLoaded = false;
114 */
115
116/*
117 * Uncomment this line to disable the output of characters by SysMin
118 * when the program exits. SysMin writes characters to a circular buffer.
119 * This buffer can be viewed using the SysMin Output view in ROV.
120SysMin.flushAtExit = false;
121 */
122
123/* System stack size (used by ISRs and Swis) */
124Program.stack = 0x10000;
125
126Task.defaultStackSize = 0x4000;
127/*
128 * Create and install logger for the whole system
129 */
130var loggerBufParams = new LoggerBuf.Params();
131loggerBufParams.numEntries = 32;
132var logger0 = LoggerBuf.create(loggerBufParams);
133Defaults.common$.logger = logger0;
134Main.common$.diags_INFO = Diags.ALWAYS_ON;
135
136BIOS.libType = BIOS.LibType_Custom;
137
138
139
140/* Disable Timer frequency check, workaround for QT test */
141var Timer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');
142Timer.checkFrequency = false;
143
144
145var Mmu = xdc.useModule('ti.sysbios.family.arm.v8a.Mmu');
146Mmu.tableArrayLen = 24;
147Mmu.initFunc = "&InitMmu";
148
149Program.sectMap[".ti_sysbios_family_arm_v8a_Mmu_tableArray"] = "MSMC_SRAM";
150Program.sectMap[".dstBufSec"] = "MSMC_SRAM";
diff --git a/example/sample/am65xx/pciesample_r5.cfg b/example/sample/am65xx/pciesample_r5.cfg
new file mode 100644
index 0000000..3a95a3c
--- /dev/null
+++ b/example/sample/am65xx/pciesample_r5.cfg
@@ -0,0 +1,161 @@
1
2/* =============================================================================
3 * Copyright (c) Texas Instruments Incorporated 2018
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the
15 * distribution.
16 *
17 * Neither the name of Texas Instruments Incorporated nor the names of
18 * its contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 */
33var Defaults = xdc.useModule('xdc.runtime.Defaults');
34var Diags = xdc.useModule('xdc.runtime.Diags');
35var Error = xdc.useModule('xdc.runtime.Error');
36var Log = xdc.useModule('xdc.runtime.Log');
37var LoggerBuf = xdc.useModule('xdc.runtime.LoggerBuf');
38var Main = xdc.useModule('xdc.runtime.Main');
39var Memory = xdc.useModule('xdc.runtime.Memory')
40var System = xdc.useModule('xdc.runtime.System');
41var Text = xdc.useModule('xdc.runtime.Text');
42var Clock = xdc.useModule('ti.sysbios.knl.Clock');
43var Task = xdc.useModule('ti.sysbios.knl.Task');
44var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
45
46var BIOS = xdc.useModule('ti.sysbios.BIOS');
47var Hwi = xdc.useModule('ti.sysbios.family.arm.v7r.keystone3.Hwi');
48var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
49var SysMin = xdc.useModule('xdc.runtime.SysMin');
50
51
52var Load = xdc.useModule('ti.sysbios.utils.Load');
53/*
54 * CPU Load
55 */
56Load.swiEnabled = true;
57Load.hwiEnabled = true;
58Load.taskEnabled = true;
59/* Enable cache */
60var Cache = xdc.useModule('ti.sysbios.family.arm.v7r.Cache');
61Cache.enableCache = true;
62
63/*
64 * Direct CIO to UART
65 */
66/* System.SupportProxy = SysUart; */
67System.SupportProxy = SysMin;
68
69/*
70 * Program.argSize sets the size of the .args section.
71 * The examples don't use command line args so argSize is set to 0.
72 */
73Program.argSize = 0x0;
74
75/*
76 * Uncomment this line to globally disable Asserts.
77 * All modules inherit the default from the 'Defaults' module. You
78 * can override these defaults on a per-module basis using Module.common$.
79 * Disabling Asserts will save code space and improve runtime performance.
80Defaults.common$.diags_ASSERT = Diags.ALWAYS_OFF;
81 */
82
83/*
84 * Uncomment this line to keep module names from being loaded on the target.
85 * The module name strings are placed in the .const section. Setting this
86 * parameter to false will save space in the .const section. Error and
87 * Assert messages will contain an "unknown module" prefix instead
88 * of the actual module name.
89Defaults.common$.namedModule = false;
90 */
91
92/* Create default heap and hook it into Memory */
93var heapMemParams = new HeapMem.Params;
94heapMemParams.size = 0x10000;
95var heap0 = HeapMem.create(heapMemParams);
96
97Memory.defaultHeapInstance = heap0;
98
99/*
100 * Minimize exit handler array in System. The System module includes
101 * an array of functions that are registered with System_atexit() to be
102 * called by System_exit().
103 */
104System.maxAtexitHandlers = 4;
105
106/*
107 * Uncomment this line to disable the Error print function.
108 * We lose error information when this is disabled since the errors are
109 * not printed. Disabling the raiseHook will save some code space if
110 * your app is not using System_printf() since the Error_print() function
111 * calls System_printf().
112Error.raiseHook = null;
113 */
114
115/*
116 * Uncomment this line to keep Error, Assert, and Log strings from being
117 * loaded on the target. These strings are placed in the .const section.
118 * Setting this parameter to false will save space in the .const section.
119 * Error, Assert and Log message will print raw ids and args instead of
120 * a formatted message.
121Text.isLoaded = false;
122 */
123
124/*
125 * Uncomment this line to disable the output of characters by SysMin
126 * when the program exits. SysMin writes characters to a circular buffer.
127 * This buffer can be viewed using the SysMin Output view in ROV.
128SysMin.flushAtExit = false;
129 */
130
131/* System stack size (used by ISRs and Swis) */
132Program.stack = 0x10000;
133
134Task.defaultStackSize = 0x4000;
135
136/*
137 * Create and install logger for the whole system
138 */
139var loggerBufParams = new LoggerBuf.Params();
140loggerBufParams.numEntries = 32;
141var logger0 = LoggerBuf.create(loggerBufParams);
142Defaults.common$.logger = logger0;
143Main.common$.diags_INFO = Diags.ALWAYS_ON;
144
145BIOS.libType = BIOS.LibType_Custom;
146
147/* Disable Timer frequency check, workaround for QT test */
148var Timer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');
149Timer.checkFrequency = false;
150
151
152/*
153 * Initialize MPU and enable it
154 *
155 * Note: MPU must be enabled and properly configured for caching to work.
156 */
157xdc.loadCapsule("r5_MPU.xs");
158
159Program.sectMap[".dstBufSec"] = "OCMRAM";
160
161
diff --git a/example/sample/am65xx/r5_MPU.xs b/example/sample/am65xx/r5_MPU.xs
new file mode 100644
index 0000000..4db47a1
--- /dev/null
+++ b/example/sample/am65xx/r5_MPU.xs
@@ -0,0 +1,126 @@
1/*
2 * Copyright (c) 2018, Texas Instruments Incorporated
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32/*
33 * ======== event_MPU.xs ========
34 * MPU Settings for SIMMAXWELL device's Cortex-R5F
35 */
36
37/*
38 * -------------------------------------------------------------------------------------------------------------
39 * | Id | Base Address | Size | En | Cacheable | XN | AccPerm | Mask |
40 * |-------------------------------------------------------------------------------------------------------------|
41 * | 0 | 0x00000000 | 4GB | T | Strongly Ordered, Shareable | T | RW at PL 1 | 0x0 |
42 * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
43 * | 1 | 0x00000000 | 1K | T | Write-Back, Write-Allocate, Non-Shareable | F | RW at PL 1 | 0x0 |
44 * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
45 * | 2 | 0x41000000 | 32K | T | Write-Back, Write-Allocate, Non-Shareable | F | RW at PL 1 | 0x0 |
46 * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
47 * | 3 | 0x41010000 | 32K | T | Write-Back, Write-Allocate, Non-Shareable | F | RW at PL 1 | 0x0 |
48 * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
49 * | 4 | 0x41C00000 | 512K | T | Write-Back, Write-Allocate, Non-Shareable | F | RW at PL 1 | 0x0 |
50 * -------------------------------------------------------------------------------------------------------------
51 */
52
53/*
54 * Note: Marking a region as shareable will cause the region to behave as outer shareable with write through
55 * no write-allocate caching policy irrespective of the actual cache policy set. Therefore, only select
56 * regions that are actually shared outside the R5 CPUSS must be marked as shared.
57 */
58
59var MPU = xdc.useModule('ti.sysbios.family.arm.MPU');
60MPU.enableMPU = true;
61MPU.enableBackgroundRegion = true;
62
63var attrs = new MPU.RegionAttrs();
64MPU.initRegionAttrsMeta(attrs);
65
66attrs.enable = true;
67attrs.bufferable = false;
68attrs.cacheable = false;
69attrs.shareable = true;
70attrs.noExecute = true;
71attrs.accPerm = 1; /* RW at PL1 */
72attrs.tex = 0;
73attrs.subregionDisableMask = 0;
74MPU.setRegionMeta(0, 0x00000000, MPU.RegionSize_4G, attrs);
75
76attrs.enable = true;
77attrs.bufferable = true;
78attrs.cacheable = true;
79attrs.shareable = false;
80attrs.noExecute = false;
81attrs.accPerm = 1; /* RW at PL1 */
82attrs.tex = 1;
83attrs.subregionDisableMask = 0;
84MPU.setRegionMeta(1, 0x00000000, MPU.RegionSize_1K, attrs);
85
86attrs.enable = true;
87attrs.bufferable = true;
88attrs.cacheable = true;
89attrs.shareable = false;
90attrs.noExecute = false;
91attrs.accPerm = 1; /* RW at PL1 */
92attrs.tex = 1;
93attrs.subregionDisableMask = 0;
94MPU.setRegionMeta(2, 0x41000000, MPU.RegionSize_32K, attrs);
95
96attrs.enable = true;
97attrs.bufferable = true;
98attrs.cacheable = true;
99attrs.shareable = false;
100attrs.noExecute = false;
101attrs.accPerm = 1; /* RW at PL1 */
102attrs.tex = 1;
103attrs.subregionDisableMask = 0x0;
104MPU.setRegionMeta(3, 0x41010000, MPU.RegionSize_32K, attrs);
105
106attrs.enable = true;
107attrs.bufferable = true;
108attrs.cacheable = true;
109attrs.shareable = false;
110attrs.noExecute = false;
111attrs.accPerm = 1; /* RW at PL1 */
112attrs.tex = 1;
113attrs.subregionDisableMask = 0;
114MPU.setRegionMeta(4, 0x41C00000, MPU.RegionSize_512K, attrs);
115
116attrs.enable = true;
117attrs.bufferable = true;
118attrs.cacheable = true;
119attrs.shareable = false;
120attrs.noExecute = false;
121attrs.accPerm = 1; /* RW at PL1 */
122attrs.tex = 1;
123attrs.subregionDisableMask = 0;
124MPU.setRegionMeta(5, 0x70000000, MPU.RegionSize_2M, attrs);
125
126
diff --git a/example/sample/am65xx/src/pcie_sample_board.c b/example/sample/am65xx/src/pcie_sample_board.c
new file mode 100644
index 0000000..a822708
--- /dev/null
+++ b/example/sample/am65xx/src/pcie_sample_board.c
@@ -0,0 +1,529 @@
1/* ============================================================================
2 * Copyright (c) Texas Instruments Incorporated 2018
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 *
8 * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 *
11 * Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the
14 * distribution.
15 *
16 * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32*/
33
34
35/**
36 * @file pcie_example_board.h
37 *
38 */
39
40#include "pcie_sample.h"
41#include "pcie_sample_board.h"
42#include <ti/csl/soc.h>
43#include <ti/csl/csl_serdes.h>
44#include <ti/csl/cslr_device.h>
45#include <ti/csl/csl_serdes_pcie.h>
46#include <ti/csl/cslr_pcie.h>
47
48#include <ti/osal/osal.h>
49#include <ti/drv/pcie/pcie.h>
50#include <string.h>
51
52#include <stdint.h>
53#include <stdbool.h>
54
55/* UART Header files */
56#include <ti/drv/uart/UART.h>
57#include <ti/drv/uart/UART_stdio.h>
58
59#if defined (__aarch64__)
60/* XDCtools Header files */
61#include <xdc/std.h>
62#include <xdc/runtime/Error.h>
63
64/* BIOS Header files */
65#include <ti/sysbios/BIOS.h>
66#include <ti/sysbios/family/arm/v8a/Mmu.h>
67
68struct MmuCfg_t {
69 uint64_t vaddr;
70 uint64_t paddr;
71 size_t size;
72 int attrInd;
73} MmuCfgTbl[] = {
74 { 0x00100000, 0x00100000, 0x00900000, 0 }, /* Main MMR0 */
75 { 0x00400000, 0x00400000, 0x00001000, 0 }, /* PSC0 */
76 { 0x01800000, 0x01800000, 0x00100000, 0 }, /* gicv3 */
77 { 0x02400000, 0x02400000, 0x000c0000, 0 }, /* dmtimer */
78 { 0x02800000, 0x02800000, 0x00001000, 0 }, /* uart */
79 { 0x02000000, 0x02000000, 0x00100000, 0 }, /* I2C */
80 { 0x02100000, 0x02100000, 0x00080000, 0 }, /* McSPI */
81 { 0x05500000, 0x05500000, 0x00100000, 0 }, /* PCIE ctrl */
82 { 0x10000000, 0x10000000, 0x10000000, 0 }, /* PCIE data */
83 { 0x40F00000, 0x40F00000, 0x00020000, 0 }, /* MCU MMR0 */
84 { 0x40d00000, 0x40d00000, 0x00002000, 0 }, /* PLL0 */
85 { 0x43000000, 0x43000000, 0x00020000, 0 }, /* WKUP MMR0 */
86 { 0x02C40000, 0x02C40000, 0x00100000, 0 }, /* pinmux ctrl */
87 { 0x30800000, 0x30800000, 0x0C000000, 0 }, /* main navss */
88 { 0x28380000, 0x28380000, 0x03880000, 0 }, /* mcu navss */
89 { 0x30000000, 0x30000000, 0x0F000000, 0 }, /* ctrcontrol0 */
90 { 0x42000000, 0x42000000, 0x00001000, 0 }, /* PSC WKUP */
91 { 0x70000000, 0x70000000, 0x04000000, 7 }, /* msmc */
92 { 0x41C00000, 0x41C00000, 0x00080000, 7 }, /* ocmc */
93 { 0, 0, 0, 8 } /* attrInd = 8 -> end of table */
94};
95
96void InitMmu(void)
97{
98 bool retVal = FALSE;
99 uint32_t j = 0;
100 Mmu_MapAttrs attrs;
101 Mmu_initMapAttrs(&attrs);
102 while (MmuCfgTbl[j].attrInd < 8) {
103 attrs.attrIndx = MmuCfgTbl[j].attrInd;
104 retVal = Mmu_map(MmuCfgTbl[j].vaddr, MmuCfgTbl[j].paddr, MmuCfgTbl[j].size, &attrs);
105 if(retVal == FALSE)
106 break;
107 j++;
108 }
109
110 if(retVal == FALSE) {
111 UART_printf("Mmu_map idx %d returned error %d", j, retVal);
112 while(1);
113 }
114}
115#endif
116
117#define KICK0 0x68EF3490ull
118#define KICK1 0xD172BC5Aull
119
120static void unlock_mmrs(void)
121{
122
123 /* Unlock Lock1 Kick Registers */
124 *(volatile uint32_t *) (CSL_CTRL_MMR0_CFG0_BASE
125 + CSL_MAIN_CTRL_MMR_CFG0_LOCK1_KICK0) = KICK0;
126 *(volatile uint32_t *) (CSL_CTRL_MMR0_CFG0_BASE
127 + CSL_MAIN_CTRL_MMR_CFG0_LOCK1_KICK1) = KICK1;
128
129 /* Unlock Lock2 Kick Registers */
130 *(volatile uint32_t *) (CSL_CTRL_MMR0_CFG0_BASE
131 + CSL_MAIN_CTRL_MMR_CFG0_LOCK2_KICK0) = KICK0;
132 *(volatile uint32_t *) (CSL_CTRL_MMR0_CFG0_BASE
133 + CSL_MAIN_CTRL_MMR_CFG0_LOCK2_KICK1) = KICK1;
134}
135
136#define PCIE_REF_CLOCK CSL_SERDES_REF_CLOCK_100M /* Ref clock of serdes */
137#define PCIE_LINK_RATE CSL_SERDES_LINK_RATE_8G /* Link rate of serdes */
138#define PCIE_NUM_LANES 1 /* Number of lanes to be tested */
139#define PCIE_LANE_MASK 0x1 /* All lanes are set */
140#define PCIE_PHY_TYPE CSL_SERDES_PHY_TYPE_PCIe /* For running PCIe tests */
141#define PCIE_LANE_RATE CSL_SERDES_LANE_FULL_RATE /* Set to run at full rate of the link rate */
142#define PCIE_LOOPBACK_MODE CSL_SERDES_LOOPBACK_DISABLED /* For internal near end serial loopback tests */
143#define PCIE_OPERATING_MODE CSL_SERDES_FUNCTIONAL_MODE_FAST_SIM /* Should always be set to Diagnostic Mode for BER, EYE and PRBS tests */
144#define PCIE_FORCEATTBOOST CSL_SERDES_FORCE_ATT_BOOST_DISABLED
145
146void CSL_serdesWaitForCMUOK(uint32_t baseAddr);
147
148void PlatformPCIESSSerdesConfig(int32_t serdes)
149{
150 uint32_t serdesBase;
151 uint32_t i;
152 CSL_SerdesResult status;
153 CSL_SerdesLaneEnableParams serdesLaneEnableParams;
154 CSL_SerdesLaneEnableStatus laneRetVal = CSL_SERDES_LANE_ENABLE_NO_ERR;
155
156 memset (&serdesLaneEnableParams, 0, sizeof(serdesLaneEnableParams));
157
158 unlock_mmrs();
159
160 if (serdes == 0)
161 {
162 serdesBase = CSL_SERDES0_BASE;
163 }
164 else
165 {
166 serdesBase = CSL_SERDES1_BASE;
167 }
168
169 /* CTRLMMR_SERDES0_CTRL Register 0x0010_4080
170 [1:0] LANE_FUNC_SEL: Input that selects which IP input is muxed into serdes output lane
171 00 : USB
172 01 : PCIE0 L0
173 10 : ICSS2 L0
174 11 : Reserved
175 [7:4] CLK_SEL
176 Bit0 - Select Right CML clock
177 Bit1 - Enable Chaining
178 Bit2 - Select Left CML clock
179 Bit3 - Right side chaining enable is inverted from Left side (Bit1)
180
181 CTRLMMR_SERDES1_CTRL Register 0x0010_4090
182 [1:0] LANE_FUNC_SEL: Input that selects which IP input is muxed into serdes output lane
183 00 : PCIE1 L0
184 01 : PCIE0 L1
185 10 : ICSS2 L1
186 11 : Reserved
187 [7:4] CLK_SEL
188 Bit0 - Select Right CML clock
189 Bit1 - Enable Chaining
190 Bit2 - Select Left CML clock
191 Bit3 - Right side chaining enable is inverted from Left side (Bit1)
192 */
193
194 CSL_FINSR(*(volatile uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_SERDES0_CTRL), 1, 0, 0x1);
195 CSL_FINSR(*(volatile uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_SERDES1_CTRL), 1, 0, 0x0);
196
197 /* CSL_MAIN_CTRL_MMR_CFG0_SERDES0/1_REFCLK_SEL (0x0010_8020/0x0010_8024)
198 * Internal reference clock:
199 * 0x0 WKUP_HFOSC0_CLK
200 * 0x1 HFOSC0_CLK
201 * 0x2 MAIN_PLL_CLKOUT
202 * 0x3 MAINHSDIV_CLKOUT4
203 */
204
205 if (serdes == 0)
206 {
207 CSL_FINSR(*(volatile uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_SERDES0_CTRL), 7, 4, 0x4); //Left CML
208 CSL_FINSR(*(volatile uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_SERDES0_REFCLK_SEL), 1, 0, 0x3);
209 }
210 else
211 {
212 CSL_FINSR(*(volatile uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_SERDES1_CTRL), 7, 4, 0x0); //Right CML
213 CSL_FINSR(*(volatile uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_SERDES1_REFCLK_SEL), 1, 0, 0x3);
214 }
215
216 //PUT SERDES PHY OUT OF RESET
217 CSL_serdesPorReset(serdesBase);
218
219 //Setup Serdes
220 serdesLaneEnableParams.baseAddr = serdesBase;
221 serdesLaneEnableParams.refClock = PCIE_REF_CLOCK;
222 serdesLaneEnableParams.linkRate = PCIE_LINK_RATE;
223 serdesLaneEnableParams.numLanes = PCIE_NUM_LANES;
224 serdesLaneEnableParams.laneMask = PCIE_LANE_MASK;
225 serdesLaneEnableParams.phyType = PCIE_PHY_TYPE;
226 serdesLaneEnableParams.operatingMode = PCIE_OPERATING_MODE;
227
228 for (i = 0; i < serdesLaneEnableParams.numLanes; i++)
229 {
230 serdesLaneEnableParams.laneCtrlRate[i] = PCIE_LANE_RATE;
231 serdesLaneEnableParams.loopbackMode[i] = PCIE_LOOPBACK_MODE;
232 }
233
234 status = CSL_serdesPCIeInit(serdesLaneEnableParams.baseAddr,
235 serdesLaneEnableParams.numLanes,
236 serdesLaneEnableParams.refClock,
237 serdesLaneEnableParams.linkRate); //Use this for PCIe serdes config load
238
239 /* Return error if input params are invalid */
240 if (status != CSL_SERDES_NO_ERR)
241 {
242 PCIE_logPrintf ("Invalid SERDES Init Params \n");
243 exit (1);
244 }
245
246 /* Common Lane Enable API for lane enable, pll enable etc */
247 laneRetVal = CSL_serdesLaneEnable(&serdesLaneEnableParams);
248
249 if (laneRetVal != 0)
250 {
251 PCIE_logPrintf ("Invalid Serdes Lane Enable\n");
252 exit (1);
253 }
254
255 PCIE_logPrintf ("Serdes Init Complete\n");
256
257 /* Check CMU_OK */
258 CSL_serdesWaitForCMUOK(serdesLaneEnableParams.baseAddr);
259}
260
261#if 0
262static uint32_t msi_ints = 0, intx_ints = 0, unknown_ints = 0;
263SemaphoreP_Handle semaphoreHandle;
264static void PlatformMsiIntxIsr (uintptr_t vhandle)
265{
266 pcieTiConfIrqStatusMsiReg_t pendingBits;
267 pciePlconfMsiCtrlIntStatusReg_t msiBits[8];
268 pciePlconfMsiCtrlIntStatusReg_t *clearMsiBits = NULL;
269 int32_t clearMsiBitsSize = 0;
270 Pcie_Handle handle = (Pcie_Handle)vhandle;
271 int32_t foundInt = 0;
272 /* Figure out which type if interrupt */
273 if (Pcie_getPendingFuncInts (handle, &pendingBits, sizeof(msiBits), msiBits) == pcie_RET_OK)
274 {
275 if (pendingBits.msi)
276 {
277 int32_t msiError = 0, i;
278 /* Check if its "right" msi */
279 for (i = 1; i < 8; i++)
280 {
281 if (msiBits[i].msiCtrlIntStatus)
282 {
283 msiError = 1; /* Unexpected MSI */
284 break;
285 }
286 }
287 if (msiBits[0].msiCtrlIntStatus != 1)
288 {
289 msiError = 1; /* Unexpected MSI */
290 }
291 if (! msiError)
292 {
293 /* Got "right" msi */
294 foundInt = 1;
295 msi_ints++;
296 /* clear it */
297 clearMsiBitsSize = sizeof(msiBits);
298 clearMsiBits = msiBits;
299 }
300 }
301 if (pendingBits.inta)
302 {
303 intx_ints++;
304 foundInt = 1;
305 }
306 if (pendingBits.intb)
307 {
308 intx_ints++;
309 foundInt = 1;
310 }
311 if (pendingBits.intc)
312 {
313 intx_ints++;
314 foundInt = 1;
315 }
316 if (pendingBits.intd)
317 {
318 intx_ints++;
319 foundInt = 1;
320 }
321 }
322 if (! foundInt)
323 {
324 /* Couldn't decode the interrupt */
325 unknown_ints ++;
326 }
327 else
328 {
329 /* Tell user task ISR happend */
330 SemaphoreP_postFromISR (semaphoreHandle);
331 }
332 /* Clear/acknowledge the interrupt */
333 Pcie_clrPendingFuncInts (handle, &pendingBits, clearMsiBitsSize, clearMsiBits);
334}
335
336
337HwiP_Handle pcieHwi;
338SemaphoreP_Handle PlatformSetupMSIAndINTX (Pcie_Handle handle)
339{
340 HwiP_Params hwiInputParams;
341 CSL_XbarIrqCpuId cpu;
342 uint32_t cpuEvent;
343 uint32_t xbarIndex;
344 int32_t vector;
345 pcieRet_e retVal;
346 pcieRegisters_t regs;
347 pcieRegisters_t epRegs;
348 pcieTiConfIrqStatusMsiReg_t rcMsiStat;
349 pcieTiConfIrqEnableSetMsiReg_t rcMsiEn;
350 pciePlconfMsiCtrlAddressReg_t rcMsiLowAddress;
351 pciePlconfMsiCtrlUpperAddressReg_t rcMsiUpAddress;
352 pciePlconfMsiCtrlIntEnableReg_t rcMsiIntEnable;
353 pciePlconfMsiCtrlIntStatusReg_t rcMsiBits[8];
354 pcieMsiCapReg_t epMsiCap;
355 pcieMsiLo32Reg_t epMsiLowAddress;
356 pcieMsiUp32Reg_t epMsiUpAddress;
357 pcieMsiDataReg_t epMsiDataVal;
358 int32_t i;
359
360 /* Create a semaphore for user task to wait for interrupt */
361 semaphoreHandle = SemaphoreP_create (0, NULL);
362 if (!semaphoreHandle)
363 {
364 PCIE_logPrintf("Failed to create semaphore\n");
365 exit(1);
366 }
367 memset (&regs, 0, sizeof(regs));
368 memset (&epRegs, 0, sizeof(epRegs));
369 memset (&rcMsiEn, 0, sizeof(rcMsiEn));
370 memset (&rcMsiLowAddress, 0, sizeof(rcMsiLowAddress));
371 memset (&rcMsiStat, 0, sizeof(rcMsiStat));
372 memset (&rcMsiUpAddress, 0, sizeof(rcMsiUpAddress));
373 memset (&rcMsiIntEnable, 0, sizeof(rcMsiIntEnable));
374 memset (&epMsiCap, 0, sizeof(epMsiCap));
375 memset (&epMsiLowAddress, 0, sizeof(epMsiLowAddress));
376 memset (&epMsiUpAddress, 0, sizeof(epMsiUpAddress));
377 memset (&epMsiDataVal, 0, sizeof(epMsiDataVal));
378
379 /* Read existing EP registers */
380 epRegs.msiCap = &epMsiCap;
381 epRegs.msiLo32 = &epMsiLowAddress;
382 epRegs.msiUp32 = &epMsiUpAddress;
383 epRegs.msiData = &epMsiDataVal;
384 retVal = Pcie_readRegs (handle, pcie_LOCATION_REMOTE, &epRegs);
385 if (retVal != pcie_RET_OK)
386 {
387 PCIE_logPrintf ("read of EP interrupt regs failed (%d)\n", retVal);
388 exit(1);
389 }
390
391 /* Enable MSI on EP */
392 epMsiCap.msiEn = 1;
393 epMsiDataVal.data = PCIE_WINDOW_MSI_DATA;
394 epMsiUpAddress.addr = 0;
395 epMsiLowAddress.addr = PCIE_WINDOW_MSI_ADDR>>2; /* because lld wants upper 30 bits only */
396 retVal = Pcie_writeRegs (handle, pcie_LOCATION_REMOTE, &epRegs);
397 if (retVal != pcie_RET_OK)
398 {
399 PCIE_logPrintf ("write of EP interrupt regs failed (%d)\n", retVal);
400 exit(1);
401 }
402
403 /* Clear any pending interrupts inside PCIE */
404 regs.tiConfIrqStatusMsi = &rcMsiStat;
405 rcMsiStat.inta = rcMsiStat.intb = rcMsiStat.intc = rcMsiStat.intd = 1;
406 rcMsiStat.msi = 1;
407 /* Clear any MSIs */
408 for (i = 0; i < 8; i++)
409 {
410 rcMsiBits[i].msiCtrlIntStatus = ~0U;
411 regs.plconfMsiCtrlIntStatus[i] = &rcMsiBits[i];
412 }
413 /* Enable the interrupts inside PCIE */
414 regs.tiConfIrqEnableSetMsi = &rcMsiEn;
415 rcMsiEn.inta = rcMsiEn.intb = rcMsiEn.intc = rcMsiEn.intd = 1;
416 rcMsiEn.msi = 1;
417 /* Set RC's data address */
418 regs.plconfMsiCtrlAddress = &rcMsiLowAddress;
419 regs.plconfMsiCtrlUpperAddress = &rcMsiUpAddress;
420 rcMsiLowAddress.msiCtrlAddress = PCIE_WINDOW_MSI_ADDR;
421 rcMsiUpAddress.msiCtrlUpperAddress = 0;
422 /* Set RC's interrupt enable in plconf */
423 regs.plconfMsiCtrlIntEnable[0] = &rcMsiIntEnable;
424 rcMsiIntEnable.msiCtrlIntEnable = 1;
425 retVal = Pcie_writeRegs (handle, pcie_LOCATION_LOCAL, &regs);
426 if (retVal != pcie_RET_OK)
427 {
428 PCIE_logPrintf ("write of RC interrupt regs failed (%d)\n", retVal);
429 exit(1);
430 }
431
432#ifdef _TMS320C6X
433 if (CSL_chipReadDNUM() == 0)
434 {
435 cpu = CSL_XBAR_IRQ_CPU_ID_DSP1;
436 }
437 else
438 {
439 cpu = CSL_XBAR_IRQ_CPU_ID_DSP2;
440 }
441 cpuEvent = 48;
442 xbarIndex = cpuEvent - 31;
443 vector = 12;
444#elif __ARM_ARCH_7A__
445 cpu = CSL_XBAR_IRQ_CPU_ID_MPU;
446 vector = 100;
447 cpuEvent = vector - 37;
448 xbarIndex = vector - 37;
449#else
450 /* Map IPU Intr 49 to PCIe_SS1_IRQ_INT1 event id 233 */
451 cpu = CSL_XBAR_IRQ_CPU_ID_IPU1;
452 vector = 49;
453 cpuEvent = 49;
454 xbarIndex = cpuEvent - 22;
455#endif
456
457 /* Configure xbar */
458 CSL_xbarIrqConfigure (cpu, xbarIndex, CSL_XBAR_PCIe_SS1_IRQ_INT1);
459
460 /* Construct Hwi object for this UART peripheral. */
461 HwiP_Params_init (&hwiInputParams);
462 hwiInputParams.name = "PCIE_MSI_AND_INTX";
463 hwiInputParams.arg = (uintptr_t)handle;
464#if defined (_TMS320C6X) || defined (__ARM_ARCH_7A__)
465 hwiInputParams.priority = 0;
466#else /* M4 */
467 hwiInputParams.priority = 0x20;
468#endif
469 hwiInputParams.evtId = cpuEvent;
470 pcieHwi = HwiP_create(vector, PlatformMsiIntxIsr, &hwiInputParams);
471
472 if (! pcieHwi)
473 {
474 PCIE_logPrintf("Hwi create failed\n");
475 exit(1);
476 }
477
478 return semaphoreHandle;
479}
480
481void PlatformGetInts (uint32_t *msis, uint32_t *intx, uint32_t *unknowns)
482{
483 if (msis)
484 {
485 *msis = msi_ints;
486 }
487 if (intx)
488 {
489 *intx = intx_ints;
490 }
491 if (unknowns)
492 {
493 *unknowns = unknown_ints;
494 }
495}
496
497void PlatformPCIE_GPIO_Init(void)
498{
499#if defined(SOC_AM572x) || defined(SOC_AM574x)
500 GPIO_init();
501#endif
502}
503
504/*
505 * API: PlatformPCIE_PERSTn_Reset
506 * Variable: resetOnOffF - Reset On/OFF Flag 1-ON/RESET , 0- OFF/Out of RESET
507 * Set PCIE_PERSTn to out of reset state
508 * GPIO_PCIE_RSTDRV - LOW to select the Reset driver
509 * GPIO_PCIE_SWRST - HIGH to set to out of RESET state
510 */
511void PlatformPCIE_PERSTn_Reset(uint32_t resetOnOffF)
512{
513#if defined(SOC_AM572x) || defined(SOC_AM574x)
514 GPIO_write(0, GPIO_PIN_VAL_HIGH); //Select Reset Driver
515
516 if(resetOnOffF)
517 {
518 GPIO_write(1, GPIO_PIN_VAL_LOW);
519 }
520 else
521 {
522 GPIO_write(1, GPIO_PIN_VAL_HIGH);
523 }
524
525#endif
526}
527#endif
528
529
diff --git a/example/sample/am65xx/src/pcie_sample_board.h b/example/sample/am65xx/src/pcie_sample_board.h
new file mode 100644
index 0000000..84e7be4
--- /dev/null
+++ b/example/sample/am65xx/src/pcie_sample_board.h
@@ -0,0 +1,49 @@
1/* ============================================================================
2 * Copyright (c) Texas Instruments Incorporated 2015-2018
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 *
8 * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 *
11 * Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the
14 * distribution.
15 *
16 * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32*/
33
34
35/**
36 * @file pcie_example_board.h
37 *
38 */
39
40#ifndef _PCIE_SAMPLE_BOARD_H_
41#define _PCIE_SAMPLE_BOARD_H_
42
43#include <ti/osal/osal.h>
44
45void PlatformPCIESSSerdesConfig(int32_t serdes);
46SemaphoreP_Handle PlatformSetupMSIAndINTX (void *handle);
47
48#endif
49
diff --git a/example/sample/makefile b/example/sample/makefile
new file mode 100644
index 0000000..895a6b3
--- /dev/null
+++ b/example/sample/makefile
@@ -0,0 +1,47 @@
1# Makefile for PCIE sample app
2include $(PDK_INSTALL_PATH)/ti/build/Rules.make
3
4#Name of the directory created under packages/ti/binary/
5APP_NAME = PCIE_sample_ExampleProject
6# Name of the binary if different from the default (APP_NAME)_$(BOARD_$(CORE)_<build_profile>
7LOCAL_APP_NAME = PCIE_sample__$(BOARD)_$(CORE)Example_Project
8
9
10ifeq ($(SOC),$(filter $(SOC), am65xx))
11SRCDIR = . src am65xx/src
12INCDIR = . src am65xx/src
13# Common source files across all platforms and cores
14SRCS_COMMON += pcie_sample.c pcie_sample_board.c
15endif
16
17# List all the external components/interfaces, whose interface header files
18# need to be included for this component
19INCLUDE_EXTERNAL_INTERFACES = bios xdc pdk
20
21# List all the components required by the application
22COMP_LIST_COMMON = pcie uart osal_tirtos csl board
23
24ifeq ($(CORE),$(filter $(CORE), mpu1_0))
25# Enable XDC build for application by providing XDC CFG File per core
26XDC_CFG_FILE_$(CORE) = ./am65xx/pciesample_a53.cfg
27endif
28
29ifeq ($(CORE),$(filter $(CORE), mcu1_0))
30# Enable XDC build for application by providing XDC CFG File per core
31XDC_CFG_FILE_$(CORE) = ./am65xx/pciesample_r5.cfg
32endif
33PACKAGE_SRCS_COMMON = .
34CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS)
35
36# Include common make files
37ifeq ($(MAKERULEDIR), )
38#Makerule path not defined, define this and assume relative path from ROOTDIR
39 MAKERULEDIR := $(ROOTDIR)/ti/build/makerules
40 export MAKERULEDIR
41endif
42include $(MAKERULEDIR)/common.mk
43
44# OBJs and libraries are built by using rule defined in rules_<target>.mk
45# and need not be explicitly specified here
46
47# Nothing beyond this point
diff --git a/example/sample/src/pcie_sample.c b/example/sample/src/pcie_sample.c
index 625f941..dae108b 100644
--- a/example/sample/src/pcie_sample.c
+++ b/example/sample/src/pcie_sample.c
@@ -1,5 +1,5 @@
1/* ============================================================================ 1/* ============================================================================
2 * Copyright (c) Texas Instruments Incorporated 2010-2017 2 * Copyright (c) Texas Instruments Incorporated 2010-2018
3 * 3 *
4 * Redistribution and use in source and binary forms, with or without 4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions 5 * modification, are permitted provided that the following conditions
@@ -62,13 +62,16 @@
62 * - EVM EP sends 10 MSI and 10 INTA's to EVM RC. 62 * - EVM EP sends 10 MSI and 10 INTA's to EVM RC.
63 * 63 *
64 */ 64 */
65 65
66 66
67#include "pcie_sample.h" 67#include "pcie_sample.h"
68#include <ti/drv/pcie/soc/pcie_soc.h> 68#include <ti/drv/pcie/soc/pcie_soc.h>
69 69
70#include <stdint.h> 70#include <stdint.h>
71 71
72#ifdef __TI_ARM_V7R4__
73#include <ti/sysbios/hal/Cache.h>
74#endif
72#ifdef __ARM_ARCH_7A__ 75#ifdef __ARM_ARCH_7A__
73#include <ti/sysbios/family/arm/a15/Cache.h> 76#include <ti/sysbios/family/arm/a15/Cache.h>
74#include <ti/sysbios/family/arm/a15/Mmu.h> 77#include <ti/sysbios/family/arm/a15/Mmu.h>
@@ -77,11 +80,15 @@
77#define COHERENT /* Cache ops unnecessary */ 80#define COHERENT /* Cache ops unnecessary */
78#endif 81#endif
79#endif 82#endif
80#if defined(SOC_AM574x) || defined(SOC_AM572x) || defined(SOC_AM571x) || defined(SOC_K2G) || (__ARM_ARCH_7A__) 83#ifdef __aarch64__
84#define COHERENT /* Cache ops unnecessary */
85#endif
86#if defined(SOC_AM574x) || defined(SOC_AM572x) || defined(SOC_AM571x) || \
87 defined(SOC_K2G) || defined(SOC_AM65XX) || defined(__ARM_ARCH_7A__)
81#include "ti/board/board.h" 88#include "ti/board/board.h"
82#endif 89#endif
83 90
84#if !defined(SOC_AM572x) && !defined(SOC_AM571x) && !defined(SOC_AM574x) 91#if !defined(SOC_AM572x) && !defined(SOC_AM571x) && !defined(SOC_AM574x) && !defined(SOC_AM65XX)
85#include <ti/csl/csl_bootcfgAux.h> 92#include <ti/csl/csl_bootcfgAux.h>
86#include <ti/csl/csl_xmcAux.h> 93#include <ti/csl/csl_xmcAux.h>
87#include <ti/csl/csl_serdes_pcie.h> 94#include <ti/csl/csl_serdes_pcie.h>
@@ -89,14 +96,18 @@
89#define PCIE_REV0_HW 96#define PCIE_REV0_HW
90#else 97#else
91#include "pcie_sample_board.h" 98#include "pcie_sample_board.h"
99#ifdef SOC_AM65XX
100#define PCIE_REV2_HW
101#else
92#define PCIE_REV1_HW 102#define PCIE_REV1_HW
93#endif 103#endif
104#endif
94#ifdef _TMS320C6X 105#ifdef _TMS320C6X
95#include <ti/csl/csl_cacheAux.h> 106#include <ti/csl/csl_cacheAux.h>
96#endif 107#endif
97#include <ti/csl/csl_chip.h> 108#include <ti/csl/csl_chip.h>
98 109
99#if (defined(_TMS320C6X) || defined (__TI_ARM_V7M4__)) 110#if (defined(_TMS320C6X) || defined (__TI_ARM_V7M4__)) || defined (__TI_ARM_V7R4__)
100#pragma DATA_SECTION(dstBuf, ".dstBufSec") 111#pragma DATA_SECTION(dstBuf, ".dstBufSec")
101/* Cache coherence: Align must be a multiple of cache line size (L2=128 bytes, L1=64 bytes) to operate with cache enabled. */ 112/* Cache coherence: Align must be a multiple of cache line size (L2=128 bytes, L1=64 bytes) to operate with cache enabled. */
102/* Aligning to 256 bytes because the PCIe inbound offset register masks the last 8bits of the buffer address */ 113/* Aligning to 256 bytes because the PCIe inbound offset register masks the last 8bits of the buffer address */
@@ -120,9 +131,9 @@ typedef struct dstBuf_s {
120#ifdef EDMA 131#ifdef EDMA
121 volatile uint32_t edma_buf[PCIE_EXAMPLE_LINE_SIZE]; 132 volatile uint32_t edma_buf[PCIE_EXAMPLE_LINE_SIZE];
122#endif 133#endif
123#ifdef EDMAPKTBENCH 134#ifdef EDMAPKTBENCH
124 edmaPktBenchBuf_t edmaPktBenchBuf; 135 edmaPktBenchBuf_t edmaPktBenchBuf;
125#endif 136#endif
126} dstBuf_t; 137} dstBuf_t;
127dstBuf_t dstBuf 138dstBuf_t dstBuf
128#ifdef __ARM_ARCH_7A__ 139#ifdef __ARM_ARCH_7A__
@@ -165,10 +176,10 @@ extern volatile unsigned int cregister TSCL;
165 the PCIe mode. It is global so it can be poked 176 the PCIe mode. It is global so it can be poked
166 from CCS. It should be set either to EP or RC. */ 177 from CCS. It should be set either to EP or RC. */
167pcieMode_e PcieModeGbl = pcie_EP_MODE; 178pcieMode_e PcieModeGbl = pcie_EP_MODE;
168#if defined(SOC_AM571x) 179#if defined(SOC_AM571x)
169Board_IDInfo boardId; 180Board_IDInfo boardId;
170Board_STATUS ret; 181Board_STATUS ret;
171#endif 182#endif
172 183
173#ifndef CSL_PSC_PD_PCIEX 184#ifndef CSL_PSC_PD_PCIEX
174#ifndef CSL_PSC_PD_PCIE 185#ifndef CSL_PSC_PD_PCIE
@@ -200,13 +211,13 @@ void cache_invalidate (void *ptr, int size)
200 211
201 /* Reenable Interrupts. */ 212 /* Reenable Interrupts. */
202 _restore_interrupts(key); 213 _restore_interrupts(key);
203#elif defined(__ARM_ARCH_7A__) 214#elif defined(__ARM_ARCH_7A__) || defined(__TI_ARM_V7R4__)
204#ifndef COHERENT 215#ifndef COHERENT
205 /* while bios could have been used on c66 that device chose csl */ 216 /* while bios could have been used on c66 that device chose csl */
206 Cache_inv (ptr, size, Cache_Type_ALLD, TRUE); 217 Cache_inv (ptr, size, Cache_Type_ALLD, TRUE);
207#endif 218#endif
208#else 219#else
209/* #error dont know how to invalidate the cache */ 220/* #error dont know how to invalidate the cache */
210#endif 221#endif
211} 222}
212 223
@@ -228,7 +239,7 @@ void cache_writeback (void *ptr, int size)
228 Cache_wb (ptr, size, Cache_Type_ALLD, TRUE); 239 Cache_wb (ptr, size, Cache_Type_ALLD, TRUE);
229#endif 240#endif
230#else 241#else
231/* #error dont know how to writeback the cache */ 242/* #error dont know how to writeback the cache */
232#endif 243#endif
233} 244}
234 245
@@ -436,7 +447,7 @@ pcieRet_e pcieCfgDbi(Pcie_Handle handle, uint8_t enable)
436 ****************************************************************************/ 447 ****************************************************************************/
437pcieRet_e pciePowerCfg(void) 448pcieRet_e pciePowerCfg(void)
438{ 449{
439#if !defined(SOC_AM572x) && !defined(SOC_AM571x) && !defined(SOC_AM574x) 450#if !defined(SOC_AM572x) && !defined(SOC_AM571x) && !defined(SOC_AM574x) && !defined(SOC_AM65XX)
440 /* Turn on the PCIe power domain */ 451 /* Turn on the PCIe power domain */
441 if (CSL_PSC_getPowerDomainState (CSL_PSC_PD_PCIE) != PSC_PDSTATE_ON) { 452 if (CSL_PSC_getPowerDomainState (CSL_PSC_PD_PCIE) != PSC_PDSTATE_ON) {
442 /* Enable the domain */ 453 /* Enable the domain */
@@ -464,13 +475,13 @@ static uint32_t readTime32(void)
464 475
465#if defined (_TMS320C6X) 476#if defined (_TMS320C6X)
466 timeVal = TSCL; 477 timeVal = TSCL;
467#elif __ARM_ARCH_7A__ 478#elif __ARM_ARCH_7A__
468 __asm__ __volatile__ ("MRC p15, 0, %0, c9, c13, 0\t\n": "=r"(timeVal)); 479 __asm__ __volatile__ ("MRC p15, 0, %0, c9, c13, 0\t\n": "=r"(timeVal));
469#else 480#else
470/* M4 specific implementation*/ 481/* M4 specific implementation*/
471 static uint32_t simuTimer = 0; 482 static uint32_t simuTimer = 0;
472 simuTimer++; 483 simuTimer++;
473 timeVal = simuTimer; 484 timeVal = simuTimer;
474#endif 485#endif
475 return timeVal; 486 return timeVal;
476} 487}
@@ -492,7 +503,8 @@ pcieRet_e pcieSerdesCfg(void)
492{ 503{
493#if !defined(DEVICE_K2K) && !defined(DEVICE_K2H) && !defined(DEVICE_K2E) && !defined(DEVICE_K2L) && \ 504#if !defined(DEVICE_K2K) && !defined(DEVICE_K2H) && !defined(DEVICE_K2E) && !defined(DEVICE_K2L) && \
494 !defined(SOC_K2K) && !defined(SOC_K2H) && !defined(SOC_K2L) && !defined(SOC_K2E) && !defined(SOC_K2G) && \ 505 !defined(SOC_K2K) && !defined(SOC_K2H) && !defined(SOC_K2L) && !defined(SOC_K2E) && !defined(SOC_K2G) && \
495 !defined(SOC_AM572x) && !defined(SOC_AM571x) && !defined(SOC_AM574x) 506 !defined(SOC_AM572x) && !defined(SOC_AM571x) && !defined(SOC_AM574x) && \
507 !defined(SOC_AM65XX)
496 uint16_t cfg; 508 uint16_t cfg;
497 509
498 /* Provide PLL reference clock to SERDES inside PCIESS 510 /* Provide PLL reference clock to SERDES inside PCIESS
@@ -510,7 +522,7 @@ pcieRet_e pcieSerdesCfg(void)
510 PlatformPCIESS1ClockEnable(); 522 PlatformPCIESS1ClockEnable();
511 PlatformPCIESS2ClockEnable(); 523 PlatformPCIESS2ClockEnable();
512 PlatformPCIESS1PllConfig(); 524 PlatformPCIESS1PllConfig();
513 PlatformPCIESSSetPhyMode(); 525 PlatformPCIESSSetPhyMode();
514 526
515 PlatformPCIESS1CtrlConfig(); 527 PlatformPCIESS1CtrlConfig();
516 PlatformPCIESS2CtrlConfig(); 528 PlatformPCIESS2CtrlConfig();
@@ -518,6 +530,8 @@ pcieRet_e pcieSerdesCfg(void)
518 PlatformPCIESS2Reset(); 530 PlatformPCIESS2Reset();
519 PlatformPCIESS1PhyConfig(); 531 PlatformPCIESS1PhyConfig();
520 PlatformPCIESS2PhyConfig(); 532 PlatformPCIESS2PhyConfig();
533#elif defined(SOC_AM65XX)
534 PlatformPCIESSSerdesConfig(0);
521#else 535#else
522#ifndef SIMULATOR_SUPPORT 536#ifndef SIMULATOR_SUPPORT
523 537
@@ -741,10 +755,10 @@ pcieRet_e pcieLtssmCtrl(Pcie_Handle handle, uint8_t enable)
741 return retVal; 755 return retVal;
742 } 756 }
743 } 757 }
744 758
745 if(enable) 759 if(enable)
746 deviceCmd.ltssmEn = cmdStatus.ltssmEn = 1; 760 deviceCmd.ltssmEn = cmdStatus.ltssmEn = 1;
747 else 761 else
748 deviceCmd.ltssmEn = cmdStatus.ltssmEn = 0; 762 deviceCmd.ltssmEn = cmdStatus.ltssmEn = 0;
749 763
750 if ((retVal = Pcie_writeRegs (handle, pcie_LOCATION_LOCAL, &regs)) != pcie_RET_OK) 764 if ((retVal = Pcie_writeRegs (handle, pcie_LOCATION_LOCAL, &regs)) != pcie_RET_OK)
@@ -769,7 +783,10 @@ pcieRet_e pcieSetGen2(Pcie_Handle handle)
769 783
770 uint8_t targetGen, dirSpd; 784 uint8_t targetGen, dirSpd;
771 785
772#ifdef GEN2 786#if defined(GEN3)
787 targetGen = 3;
788 dirSpd = 1;
789#elif defined(GEN2)
773 targetGen = 2; 790 targetGen = 2;
774 dirSpd = 1; 791 dirSpd = 1;
775#else 792#else
@@ -869,6 +886,7 @@ pcieRet_e pcieCfgRC(Pcie_Handle handle)
869 return retVal; 886 return retVal;
870 } 887 }
871 888
889#if !defined(PCIE_REV2_HW) /* RC does not support BAR */
872 /* Configure BAR Masks */ 890 /* Configure BAR Masks */
873 /* First need to enable writing on BAR mask registers */ 891 /* First need to enable writing on BAR mask registers */
874 if ((retVal = pcieCfgDbi (handle, 1)) != pcie_RET_OK) 892 if ((retVal = pcieCfgDbi (handle, 1)) != pcie_RET_OK)
@@ -904,6 +922,7 @@ pcieRet_e pcieCfgRC(Pcie_Handle handle)
904 { 922 {
905 return retVal; 923 return retVal;
906 } 924 }
925#endif
907 926
908 /* Enable memory access and mastership of the bus */ 927 /* Enable memory access and mastership of the bus */
909 memset (&setRegs, 0, sizeof(setRegs)); 928 memset (&setRegs, 0, sizeof(setRegs));
@@ -950,7 +969,7 @@ pcieRet_e pcieCfgRC(Pcie_Handle handle)
950 return retVal; 969 return retVal;
951 } 970 }
952 971
953#ifdef PCIE_REV0_HW 972#if defined(PCIE_REV0_HW) || defined(PCIE_REV2_HW)
954 /* Enable ECRC */ 973 /* Enable ECRC */
955 memset (&setRegs, 0, sizeof(setRegs)); 974 memset (&setRegs, 0, sizeof(setRegs));
956 975
@@ -1104,7 +1123,7 @@ pcieRet_e pcieCfgEP(Pcie_Handle handle)
1104 return retVal; 1123 return retVal;
1105 } 1124 }
1106 1125
1107#ifdef PCIE_REV0_HW 1126#if defined(PCIE_REV0_HW) || defined(PCIE_REV2_HW)
1108 /* Enable ECRC */ 1127 /* Enable ECRC */
1109 memset (&setRegs, 0, sizeof(setRegs)); 1128 memset (&setRegs, 0, sizeof(setRegs));
1110 1129
@@ -1188,7 +1207,7 @@ pcieRet_e pcieIbTransCfg(Pcie_Handle handle, pcieIbTransCfg_t *ibCfg)
1188 memset (&getRegs, 0, sizeof(getRegs)); 1207 memset (&getRegs, 0, sizeof(getRegs));
1189 memset (&cmdStatus, 0, sizeof(cmdStatus)); 1208 memset (&cmdStatus, 0, sizeof(cmdStatus));
1190 1209
1191 /* Set outbound offset registers */ 1210 /* Set inbound offset registers */
1192 if ((retVal = Pcie_cfgIbTrans(handle, ibCfg)) != pcie_RET_OK) 1211 if ((retVal = Pcie_cfgIbTrans(handle, ibCfg)) != pcie_RET_OK)
1193 { 1212 {
1194 PCIE_logPrintf ("Failed to configure Inbound Translation registers!\n"); 1213 PCIE_logPrintf ("Failed to configure Inbound Translation registers!\n");
@@ -1219,19 +1238,21 @@ pcieRet_e pcieIbTransCfg(Pcie_Handle handle, pcieIbTransCfg_t *ibCfg)
1219#else 1238#else
1220 1239
1221/***************************************************************************** 1240/*****************************************************************************
1222 * Function: Configure and enable Outbound Address Translation for rev 1 1241 * Function: Configure and enable Outbound Address Translation for rev 1/2
1223 ****************************************************************************/ 1242 ****************************************************************************/
1224pcieRet_e pcieObTransCfg(Pcie_Handle handle, uint32_t obAddrLo, uint32_t obAddrHi, uint8_t region) 1243pcieRet_e pcieObTransCfg(Pcie_Handle handle, uint32_t obAddrLo, uint32_t obAddrHi, uint8_t region)
1225{ 1244{
1226 pcieAtuRegionParams_t regionParams; 1245 pcieAtuRegionParams_t regionParams;
1227 pcieRet_e retVal; 1246 pcieRet_e retVal;
1228 uint32_t resSize; 1247 uint32_t resSize;
1248
1249 memset (&regionParams, 0, sizeof(regionParams));
1250
1251 if ((retVal = Pcie_getMemSpaceReserved (handle, &resSize)) != pcie_RET_OK) {
1252 PCIE_logPrintf ("getMemSpaceReserved failed (%d)\n", (int)retVal);
1253 return retVal;
1254 }
1229 1255
1230 if ((retVal = Pcie_getMemSpaceReserved (handle, &resSize)) != pcie_RET_OK) {
1231 PCIE_logPrintf ("getMemSpaceReserved failed (%d)\n", (int)retVal);
1232 return retVal;
1233 }
1234
1235 if(PcieModeGbl == pcie_RC_MODE) 1256 if(PcieModeGbl == pcie_RC_MODE)
1236 { 1257 {
1237 /*Configure OB region for remote configuration access space*/ 1258 /*Configure OB region for remote configuration access space*/
@@ -1276,12 +1297,14 @@ pcieRet_e pcieObTransCfg(Pcie_Handle handle, uint32_t obAddrLo, uint32_t obAddrH
1276} 1297}
1277 1298
1278/***************************************************************************** 1299/*****************************************************************************
1279 * Function: Configure and enable Inbound Address Translation for rev 1 1300 * Function: Configure and enable Inbound Address Translation for rev 1/2
1280 ****************************************************************************/ 1301 ****************************************************************************/
1281pcieRet_e pcieIbTransCfg(Pcie_Handle handle, pcieIbTransCfg_t *ibCfg) 1302pcieRet_e pcieIbTransCfg(Pcie_Handle handle, pcieIbTransCfg_t *ibCfg)
1282{ 1303{
1283 pcieAtuRegionParams_t regionParams; 1304 pcieAtuRegionParams_t regionParams;
1284 1305
1306 memset (&regionParams, 0, sizeof(regionParams));
1307
1285 /*Configure IB region for memory transfer*/ 1308 /*Configure IB region for memory transfer*/
1286 regionParams.regionDir = PCIE_ATU_REGION_DIR_INBOUND; 1309 regionParams.regionDir = PCIE_ATU_REGION_DIR_INBOUND;
1287 regionParams.tlpType = PCIE_TLP_TYPE_MEM; 1310 regionParams.tlpType = PCIE_TLP_TYPE_MEM;
@@ -1340,7 +1363,7 @@ void pcieWaitLinkUp(Pcie_Handle handle)
1340 1363
1341 memset (&getRegs, 0, sizeof(getRegs)); 1364 memset (&getRegs, 0, sizeof(getRegs));
1342 1365
1343#ifdef PCIE_REV0_HW 1366#if defined(PCIE_REV0_HW) || defined(PCIE_REV2_HW)
1344 pcieDebug0Reg_t ltssmStateReg; 1367 pcieDebug0Reg_t ltssmStateReg;
1345 getRegs.debug0 = &ltssmStateReg; 1368 getRegs.debug0 = &ltssmStateReg;
1346#else 1369#else
@@ -1363,70 +1386,70 @@ void pcieWaitLinkUp(Pcie_Handle handle)
1363 ltssmState = ltssmStateReg.ltssmState; 1386 ltssmState = ltssmStateReg.ltssmState;
1364 } 1387 }
1365} 1388}
1366 1389
1367pcieRet_e pcieCheckLinkParams(Pcie_Handle handle) 1390pcieRet_e pcieCheckLinkParams(Pcie_Handle handle)
1368{ 1391{
1369#if defined(SOC_K2G) || defined(SOC_AM572x) || defined(SOC_AM571x) || defined(SOC_AM574x) 1392#if defined(SOC_K2G) || defined(SOC_AM572x) || defined(SOC_AM571x) || defined(SOC_AM574x)
1370 pcieRet_e retVal = pcie_RET_OK; 1393 pcieRet_e retVal = pcie_RET_OK;
1371 pcieRegisters_t regs; 1394 pcieRegisters_t regs;
1372 pcieLinkStatCtrlReg_t linkStatCtrl; 1395 pcieLinkStatCtrlReg_t linkStatCtrl;
1373 int32_t expLanes = 1, expSpeed = 1; 1396 int32_t expLanes = 1, expSpeed = 1;
1374 const char *pass = "PASS", *fail = "FAIL"; 1397 const char *pass = "PASS", *fail = "FAIL";
1375 const char *result = pass; 1398 const char *result = pass;
1376 1399
1377#ifdef GEN2 1400#ifdef GEN2
1378 expSpeed = 2; 1401 expSpeed = 2;
1379#endif 1402#endif
1380#ifdef PCIESS1_X2 1403#ifdef PCIESS1_X2
1381 expLanes = 2; 1404 expLanes = 2;
1382#endif 1405#endif
1383/* the following code distinguishes between AM571x & AM570x, 1406/* the following code distinguishes between AM571x & AM570x,
1384 AM570x is addressed name DRA71x */ 1407 AM570x is addressed name DRA71x */
1385#if defined(SOC_AM571x) 1408#if defined(SOC_AM571x)
1386 if ((boardId.boardName[0] == 'D') && 1409 if ((boardId.boardName[0] == 'D') &&
1387 (boardId.boardName[1] == 'R') && 1410 (boardId.boardName[1] == 'R') &&
1388 (boardId.boardName[2] == 'A')) 1411 (boardId.boardName[2] == 'A'))
1389 { 1412 {
1390 expLanes = 1; 1413 expLanes = 1;
1391 } 1414 }
1392#endif 1415#endif
1393 1416
1394 /* Get link status */ 1417 /* Get link status */
1395 memset (&regs, 0, sizeof(regs)); 1418 memset (&regs, 0, sizeof(regs));
1396 regs.linkStatCtrl = &linkStatCtrl; 1419 regs.linkStatCtrl = &linkStatCtrl;
1397 1420
1398 PCIE_logPrintf ("Checking link speed and # of lanes\n"); 1421 PCIE_logPrintf ("Checking link speed and # of lanes\n");
1399 retVal = Pcie_readRegs (handle, pcie_LOCATION_LOCAL, &regs); 1422 retVal = Pcie_readRegs (handle, pcie_LOCATION_LOCAL, &regs);
1400 if (retVal != pcie_RET_OK) { 1423 if (retVal != pcie_RET_OK) {
1401 PCIE_logPrintf ("Failed to read linkStatCtrl: %d\n", retVal); 1424 PCIE_logPrintf ("Failed to read linkStatCtrl: %d\n", retVal);
1402 } else { 1425 } else {
1403 /* Check number of lanes */ 1426 /* Check number of lanes */
1404 if (expLanes != linkStatCtrl.negotiatedLinkWd) { 1427 if (expLanes != linkStatCtrl.negotiatedLinkWd) {
1405 result = fail; 1428 result = fail;
1406 retVal = pcie_RET_UNSUPPORTED; 1429 retVal = pcie_RET_UNSUPPORTED;
1407 } else { 1430 } else {
1408 result = pass; 1431 result = pass;
1409 } 1432 }
1410 PCIE_logPrintf ("Expect %d lanes, found %d lanes (%s)\n", 1433 PCIE_logPrintf ("Expect %d lanes, found %d lanes (%s)\n",
1411 (int)expLanes, (int)linkStatCtrl.negotiatedLinkWd, result); 1434 (int)expLanes, (int)linkStatCtrl.negotiatedLinkWd, result);
1412 1435
1413 /* Check speed */ 1436 /* Check speed */
1414 if (expSpeed != linkStatCtrl.linkSpeed) { 1437 if (expSpeed != linkStatCtrl.linkSpeed) {
1415 result = fail; 1438 result = fail;
1416 retVal = pcie_RET_UNSUPPORTED; 1439 retVal = pcie_RET_UNSUPPORTED;
1417 } else { 1440 } else {
1418 result = pass; 1441 result = pass;
1419 } 1442 }
1420 PCIE_logPrintf ("Expect gen %d speed, found gen %d speed (%s)\n", 1443 PCIE_logPrintf ("Expect gen %d speed, found gen %d speed (%s)\n",
1421 (int)expSpeed, (int)linkStatCtrl.linkSpeed, result); 1444 (int)expSpeed, (int)linkStatCtrl.linkSpeed, result);
1422 } 1445 }
1423 1446
1424 return retVal; 1447 return retVal;
1425#else 1448#else
1426 return pcie_RET_OK; 1449 return pcie_RET_OK;
1427#endif 1450#endif
1428} 1451}
1429 1452
1430 1453
1431#ifdef PCIE_REV1_HW 1454#ifdef PCIE_REV1_HW
1432void pcieEpSendInts (Pcie_Handle handle) 1455void pcieEpSendInts (Pcie_Handle handle)
@@ -1569,10 +1592,38 @@ void pcieRcWaitInts (Pcie_Handle handle, SemaphoreP_Handle sem, void *pcieBase)
1569} 1592}
1570#endif 1593#endif
1571 1594
1595void pcieSetLanes (Pcie_Handle handle)
1596{
1597#ifdef PCIE_REV2_HW
1598 /* Request just 1 lane -- this would work on all HW */
1599 pcieLnkCtrlReg_t lnkCtrlReg;
1600 pcieRegisters_t regs;
1601 uint8_t origLanes;
1602
1603 memset (&regs, 0, sizeof(regs));
1604 regs.lnkCtrl = &lnkCtrlReg;
1605 if (Pcie_readRegs (handle, pcie_LOCATION_LOCAL, &regs) != pcie_RET_OK)
1606 {
1607 PCIE_logPrintf ("Read LnkCtrl register failed!\n");
1608 exit(1);
1609 }
1610 origLanes = lnkCtrlReg.lnkMode;
1611 lnkCtrlReg.lnkMode = 1;
1612 if (Pcie_writeRegs (handle, pcie_LOCATION_LOCAL, &regs) != pcie_RET_OK)
1613 {
1614 PCIE_logPrintf ("Write LnkCtrl register failed!\n");
1615 exit(1);
1616 }
1617 PCIE_logPrintf ("Set lanes from %d to %d\n", (int)origLanes, (int)lnkCtrlReg.lnkMode);
1618#endif
1619}
1572 1620
1573/***************************************************************************** 1621/*****************************************************************************
1574 * Function: Main 1622 * Function: pcie main task
1575 ****************************************************************************/ 1623 ****************************************************************************/
1624uint32_t OFFSET = 0;
1625uint32_t base_address = 0x5500000;
1626int i;
1576void pcie (void) 1627void pcie (void)
1577{ 1628{
1578#ifdef _TMS320C6X 1629#ifdef _TMS320C6X
@@ -1580,7 +1631,8 @@ void pcie (void)
1580#endif 1631#endif
1581#if !defined(DEVICE_K2K) && !defined(DEVICE_K2H) && !defined(DEVICE_K2E) && !defined(DEVICE_K2L) && \ 1632#if !defined(DEVICE_K2K) && !defined(DEVICE_K2H) && !defined(DEVICE_K2E) && !defined(DEVICE_K2L) && \
1582 !defined(SOC_K2K) && !defined(SOC_K2H) && !defined(SOC_K2L) && !defined(SOC_K2E) && !defined(SOC_K2G) && \ 1633 !defined(SOC_K2K) && !defined(SOC_K2H) && !defined(SOC_K2L) && !defined(SOC_K2E) && !defined(SOC_K2G) && \
1583 !defined(SOC_AM572x) && !defined(SOC_AM571x) && !defined(SOC_AM574x) 1634 !defined(SOC_AM572x) && !defined(SOC_AM571x) && !defined(SOC_AM574x) && \
1635 !defined(SOC_AM65XX)
1584 uint16_t lock=0; 1636 uint16_t lock=0;
1585#endif 1637#endif
1586 pcieRet_e retVal; 1638 pcieRet_e retVal;
@@ -1590,15 +1642,15 @@ void pcie (void)
1590 void *pcieBase; 1642 void *pcieBase;
1591 dstBuf_t *pciedstBufBase; 1643 dstBuf_t *pciedstBufBase;
1592 uint32_t i; 1644 uint32_t i;
1593 char pcieModeResponse; 1645 char pcieModeResponse;
1594#ifdef PCIE_REV1_HW 1646#ifdef PCIE_REV1_HW
1595 SemaphoreP_Handle sem = NULL; 1647 SemaphoreP_Handle sem = NULL;
1596#endif 1648#endif
1597 1649
1598 /* Get remote buffer out of cache */ 1650 /* Get remote buffer out of cache */
1599 cache_writeback ((void *)&dstBuf, sizeof(dstBuf)); 1651 cache_writeback ((void *)&dstBuf, sizeof(dstBuf));
1600 /* Unlock kicker once, and don't relock, because its not multicore safe */ 1652 /* Unlock kicker once, and don't relock, because its not multicore safe */
1601#if !defined(SOC_AM572x) && !defined(SOC_AM571x) && !defined(SOC_AM574x) 1653#if !defined(SOC_AM572x) && !defined(SOC_AM571x) && !defined(SOC_AM574x) && !defined(SOC_AM65XX)
1602 CSL_BootCfgUnlockKicker(); 1654 CSL_BootCfgUnlockKicker();
1603#endif 1655#endif
1604 1656
@@ -1614,27 +1666,27 @@ void pcie (void)
1614 1666
1615 PCIE_logPrintf ("**********************************************\n"); 1667 PCIE_logPrintf ("**********************************************\n");
1616 PCIE_logPrintf ("* PCIe Test Start *\n"); 1668 PCIE_logPrintf ("* PCIe Test Start *\n");
1617 1669
1618#if defined(SOC_K2G) || defined(SOC_AM572x) || defined(SOC_AM571x) || defined(SOC_AM574x) 1670#if defined(SOC_K2G) || defined(SOC_AM572x) || defined(SOC_AM571x) || defined(SOC_AM574x) || defined(SOC_AM65XX)
1619 PCIE_logPrintf ("Enter: E for Endpoint or R for Root Complex \n"); 1671 PCIE_logPrintf ("Enter: E for Endpoint or R for Root Complex \n");
1620 PCIE_logScanf ("%c", &pcieModeResponse); 1672 PCIE_logScanf ("%c", &pcieModeResponse);
1621 if ((pcieModeResponse == 'E') || (pcieModeResponse == 'e')) 1673 if ((pcieModeResponse == 'E') || (pcieModeResponse == 'e'))
1622 { 1674 {
1623 PcieModeGbl = pcie_EP_MODE; 1675 PcieModeGbl = pcie_EP_MODE;
1624 PCIE_logPrintf ("* EP mode *\n"); 1676 PCIE_logPrintf ("* EP mode *\n");
1625 } 1677 }
1626 else if ((pcieModeResponse == 'R') || (pcieModeResponse == 'r')) 1678 else if ((pcieModeResponse == 'R') || (pcieModeResponse == 'r'))
1627 { 1679 {
1628 PcieModeGbl = pcie_RC_MODE; 1680 PcieModeGbl = pcie_RC_MODE;
1629 PCIE_logPrintf ("* RC mode *\n"); 1681 PCIE_logPrintf ("* RC mode *\n");
1630 } 1682 }
1631 else 1683 else
1632 { 1684 {
1633 PCIE_logPrintf ("Wrong Mode Enter. Please enter E or R \n"); 1685 PCIE_logPrintf ("Wrong Mode Enter. Please enter E or R \n");
1634 exit(1); 1686 exit(1);
1635 } 1687 }
1636#endif 1688#endif
1637 1689
1638 if(PcieModeGbl == pcie_RC_MODE) 1690 if(PcieModeGbl == pcie_RC_MODE)
1639 PCIE_logPrintf ("* RC mode *\n"); 1691 PCIE_logPrintf ("* RC mode *\n");
1640 else 1692 else
@@ -1683,7 +1735,8 @@ void pcie (void)
1683 /* Wait until the PCIe SERDES PLL locks */ 1735 /* Wait until the PCIe SERDES PLL locks */
1684#if !defined(DEVICE_K2K) && !defined(DEVICE_K2H) && !defined(DEVICE_K2E) && !defined(DEVICE_K2L) && \ 1736#if !defined(DEVICE_K2K) && !defined(DEVICE_K2H) && !defined(DEVICE_K2E) && !defined(DEVICE_K2L) && \
1685 !defined(SOC_K2K) && !defined(SOC_K2H) && !defined(SOC_K2L) && !defined(SOC_K2E) && !defined(SOC_K2G) && \ 1737 !defined(SOC_K2K) && !defined(SOC_K2H) && !defined(SOC_K2L) && !defined(SOC_K2E) && !defined(SOC_K2G) && \
1686 !defined(SOC_AM572x) && !defined(SOC_AM571x) && !defined(SOC_AM574x) 1738 !defined(SOC_AM572x) && !defined(SOC_AM571x) && !defined(SOC_AM574x) && \
1739 !defined(SOC_AM65XX)
1687 while (!lock) 1740 while (!lock)
1688 { 1741 {
1689 CSL_BootCfgGetPCIEPLLLock(&lock); 1742 CSL_BootCfgGetPCIEPLLLock(&lock);
@@ -1702,6 +1755,7 @@ void pcie (void)
1702 exit(1); 1755 exit(1);
1703 } 1756 }
1704 1757
1758#if !defined(PCIE_REV2_HW) /* RC does not support BAR */
1705 /* Configure Address Translation */ 1759 /* Configure Address Translation */
1706 1760
1707 barCfg.location = pcie_LOCATION_LOCAL; 1761 barCfg.location = pcie_LOCATION_LOCAL;
@@ -1717,7 +1771,7 @@ void pcie (void)
1717 PCIE_logPrintf ("Failed to configure BAR (%d)\n", (int)retVal); 1771 PCIE_logPrintf ("Failed to configure BAR (%d)\n", (int)retVal);
1718 exit(1); 1772 exit(1);
1719 } 1773 }
1720 1774#endif
1721 1775
1722 ibCfg.ibBar = PCIE_BAR_IDX_RC; /* Match BAR that was configured above*/ 1776 ibCfg.ibBar = PCIE_BAR_IDX_RC; /* Match BAR that was configured above*/
1723 ibCfg.ibStartAddrLo = PCIE_IB_LO_ADDR_RC; 1777 ibCfg.ibStartAddrLo = PCIE_IB_LO_ADDR_RC;
@@ -1797,6 +1851,9 @@ void pcie (void)
1797 } 1851 }
1798 } 1852 }
1799 1853
1854 /* Configure/limit number of lanes */
1855 pcieSetLanes (handle);
1856
1800 PCIE_logPrintf ("Starting link training...\n"); 1857 PCIE_logPrintf ("Starting link training...\n");
1801 1858
1802 /*Enable link training*/ 1859 /*Enable link training*/
@@ -1810,25 +1867,31 @@ void pcie (void)
1810 pcieWaitLinkUp(handle); 1867 pcieWaitLinkUp(handle);
1811 1868
1812 PCIE_logPrintf ("Link is up.\n"); 1869 PCIE_logPrintf ("Link is up.\n");
1813 if ((retVal = pcieCheckLinkParams(handle)) != pcie_RET_OK) 1870 if ((retVal = pcieCheckLinkParams(handle)) != pcie_RET_OK)
1814 { 1871 {
1815 PCIE_logPrintf ("Link width/speed verification FAILed: %d\n", retVal); 1872 PCIE_logPrintf ("Link width/speed verification FAILed: %d\n", retVal);
1816 /* This exit() can be removed if this example is being used as 1873 /* This exit() can be removed if this example is being used as
1817 * template with non TI card that supports slower or narrower connections 1874 * template with non TI card that supports slower or narrower connections
1818 */ 1875 */
1819 exit(1); 1876 exit(1);
1820 } 1877 }
1821 1878
1822 if ((retVal = Pcie_getMemSpaceRange (handle, &pcieBase, NULL)) != pcie_RET_OK) { 1879 if ((retVal = Pcie_getMemSpaceRange (handle, &pcieBase, NULL)) != pcie_RET_OK) {
1823 PCIE_logPrintf ("getMemSpaceRange failed (%d)\n", (int)retVal); 1880 PCIE_logPrintf ("getMemSpaceRange failed (%d)\n", (int)retVal);
1824 exit(1); 1881 exit(1);
1825 } 1882 }
1826 1883
1827#ifdef PCIE_REV1_HW 1884#if defined(PCIE_REV1_HW)
1828 /* Adjust PCIE base to point at remote target buffer */ 1885 /* Adjust PCIE base to point at remote target buffer */
1829 pcieBase = (char *)pcieBase + 1886 pcieBase = (char *)pcieBase +
1830 PCIE_WINDOW_MEM_BASE + /* data area doesn't start at low address */ 1887 PCIE_WINDOW_MEM_BASE + /* data area doesn't start at low address */
1831 (((uint32_t)&dstBuf) & 0xfff); /* dstBuf needs to be 4K aligned in addr tran */ 1888 (((uint32_t)&dstBuf) & 0xfff); /* dstBuf needs to be 4K aligned in addr tran */
1889#elif defined(PCIE_REV2_HW)
1890 /* Adjust PCIE base to point at remote target buffer */
1891 pcieBase = (char *) PCIE_WINDOW_MEM_BASE + /* data area doesn't start at low address */
1892 (((uint32_t)&dstBuf) & 0xffff); /* dstBuf needs to be 64K aligned in addr tran */
1893#else
1894 /* No adjustment needed */
1832#endif 1895#endif
1833 pciedstBufBase = (dstBuf_t *)pcieBase; 1896 pciedstBufBase = (dstBuf_t *)pcieBase;
1834 1897
@@ -1941,15 +2004,15 @@ PCIE_logPrintf ("Failed to pass token \n");
1941#ifdef EDMA 2004#ifdef EDMA
1942 edmaDeinit(hEdma); 2005 edmaDeinit(hEdma);
1943#endif 2006#endif
1944#ifdef EDMAPKTBENCH 2007#ifdef EDMAPKTBENCH
1945 if (PcieEdmaPktBench(&dstBuf.edmaPktBenchBuf.msiTracker[0], 2008 if (PcieEdmaPktBench(&dstBuf.edmaPktBenchBuf.msiTracker[0],
1946 &pciedstBufBase->edmaPktBenchBuf, 2009 &pciedstBufBase->edmaPktBenchBuf,
1947 PcieModeGbl, sem)) 2010 PcieModeGbl, sem))
1948 { 2011 {
1949 PCIE_logPrintf ("EDMA packet IO benchmark failed to execute correctly\n"); 2012 PCIE_logPrintf ("EDMA packet IO benchmark failed to execute correctly\n");
1950 exit(1); 2013 exit(1);
1951 } 2014 }
1952#endif 2015#endif
1953 PCIE_logPrintf ("Test passed.\n"); 2016 PCIE_logPrintf ("Test passed.\n");
1954#ifndef IO_CONSOLE 2017#ifndef IO_CONSOLE
1955 Console_printf ("Test passed.\n"); 2018 Console_printf ("Test passed.\n");
@@ -2021,7 +2084,8 @@ int main() {
2021 } 2084 }
2022#endif 2085#endif
2023 2086
2024#if defined(SOC_AM574x) || defined(SOC_AM572x) || defined(SOC_AM571x) || defined(SOC_K2G) || defined(__ARM_ARCH_7A__) 2087#if defined(SOC_AM574x) || defined(SOC_AM572x) || defined(SOC_AM571x) || \
2088 defined(SOC_K2G) || defined(SOC_AM65XX) || defined(__ARM_ARCH_7A__)
2025 Board_initCfg boardCfg; 2089 Board_initCfg boardCfg;
2026 boardCfg = BOARD_INIT_UNLOCK_MMR 2090 boardCfg = BOARD_INIT_UNLOCK_MMR
2027#ifndef IO_CONSOLE 2091#ifndef IO_CONSOLE
@@ -2033,13 +2097,13 @@ int main() {
2033#endif 2097#endif
2034 ; 2098 ;
2035 Board_init(boardCfg); 2099 Board_init(boardCfg);
2036#if defined(SOC_AM571x) 2100#if defined(SOC_AM571x)
2037 ret = Board_getIDInfo(&boardId); 2101 ret = Board_getIDInfo(&boardId);
2038 if (ret != BOARD_SOK) 2102 if (ret != BOARD_SOK)
2039 { 2103 {
2040 return 0; 2104 return 0;
2041 } 2105 }
2042#endif 2106#endif
2043#endif 2107#endif
2044 BIOS_start(); 2108 BIOS_start();
2045 return 0; 2109 return 0;
diff --git a/example/sample/src/pcie_sample.h b/example/sample/src/pcie_sample.h
index e861c08..eed69f8 100644
--- a/example/sample/src/pcie_sample.h
+++ b/example/sample/src/pcie_sample.h
@@ -1,5 +1,5 @@
1/* ============================================================================ 1/* ============================================================================
2 * Copyright (c) Texas Instruments Incorporated 2010-2017 2 * Copyright (c) Texas Instruments Incorporated 2010-2018
3 * 3 *
4 * Redistribution and use in source and binary forms, with or without 4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions 5 * modification, are permitted provided that the following conditions
@@ -63,7 +63,7 @@
63/* PCIE LLD include */ 63/* PCIE LLD include */
64#include <ti/drv/pcie/pcie.h> 64#include <ti/drv/pcie/pcie.h>
65 65
66#if !defined(__TI_ARM_V7M4__) && !defined(EDMAPKTBENCH) 66#if !defined(__TI_ARM_V7M4__) && !defined(EDMAPKTBENCH) && !defined(SOC_AM65XX)
67/* Only do EDMA on C6X and A15 */ 67/* Only do EDMA on C6X and A15 */
68#define EDMA 68#define EDMA
69#endif 69#endif
@@ -75,17 +75,24 @@
75#include "../../edmaPktBench/edmaPktBench.h" 75#include "../../edmaPktBench/edmaPktBench.h"
76#endif 76#endif
77 77
78/* Do gen2 on all devices -- remove or -U for GEN1 */ 78#if !defined(SOC_AM65XX)
79/* Do gen2 on all other devices -- remove or -U for GEN1 */
79#define GEN2 80#define GEN2
81#else
82/* AM6 is GEN3 */
83#define GEN3
84#endif
80 85
81/* Set up printf */ 86/* Set up printf */
82#include <xdc/runtime/System.h> 87#include <xdc/runtime/System.h>
83#define Console_printf System_printf 88#define Console_printf System_printf
84 89
85/* Enable the below macro to have prints on the IO Console */ 90/* Enable the below macro to have prints on the IO Console */
86#if !defined(SOC_AM574x) && !defined(SOC_AM572x) && !defined(SOC_AM571x) && !defined(SOC_K2G) && \ 91#if !defined(SOC_AM574x) && !defined(SOC_AM572x) && !defined(SOC_AM571x) && \
92 !defined(SOC_K2G) && \
93 !defined(SOC_AM65XX) && \
87 !defined(__ARM_ARCH_7A__) 94 !defined(__ARM_ARCH_7A__)
88/* AM57x and K2G always use UART for all cores. Also all ARM use UART */ 95/* AM57x, AM65x and K2G always use UART for all cores. Also all ARM use UART */
89#define IO_CONSOLE 96#define IO_CONSOLE
90#endif 97#endif
91 98
@@ -124,6 +131,16 @@
124#define PCIE_IB_LO_ADDR_EP PCIE_OB_LO_ADDR_RC 131#define PCIE_IB_LO_ADDR_EP PCIE_OB_LO_ADDR_RC
125#define PCIE_IB_HI_ADDR_EP 0 132#define PCIE_IB_HI_ADDR_EP 0
126 133
134#if defined(SOC_AM65XX)
135/* Data area offset absolute including PCIe base (only used rev 2) */
136#define PCIE_WINDOW_MEM_BASE 0x11000000U
137#define PCIE_WINDOW_MEM_MASK 0x00FFFFFFU
138
139/* Cfg area offset absolute including PCIe base (only used rev 2) */
140/* This MUST agree Pciev1_DeviceCfgBaseAddrs.bases! */
141#define PCIE_WINDOW_CFG_BASE 0x10010000U
142#define PCIE_WINDOW_CFG_MASK 0x0000FFFFU
143#else
127/* Data area offset relative to PCIe base (only used rev 1) */ 144/* Data area offset relative to PCIe base (only used rev 1) */
128#define PCIE_WINDOW_MEM_BASE 0x01000000U 145#define PCIE_WINDOW_MEM_BASE 0x01000000U
129#define PCIE_WINDOW_MEM_MASK 0x00FFFFFFU 146#define PCIE_WINDOW_MEM_MASK 0x00FFFFFFU
@@ -132,6 +149,7 @@
132/* This MUST agree Pciev1_DeviceCfgBaseAddrs.bases! */ 149/* This MUST agree Pciev1_DeviceCfgBaseAddrs.bases! */
133#define PCIE_WINDOW_CFG_BASE 0x00001000U 150#define PCIE_WINDOW_CFG_BASE 0x00001000U
134#define PCIE_WINDOW_CFG_MASK 0x00000FFFU 151#define PCIE_WINDOW_CFG_MASK 0x00000FFFU
152#endif
135 153
136/* MSI address in PCIE data window */ 154/* MSI address in PCIE data window */
137#define PCIE_WINDOW_MSI_ADDR 0x02000000U 155#define PCIE_WINDOW_MSI_ADDR 0x02000000U