refactor for v0/v1 and run on k2h

7 files changed, 684 insertions, 0 deletions

diff --git a/soc/Module.xs b/soc/Module.xs
new file mode 100644
index 0000000..1a4baff
--- /dev/null
+++ b/soc/Module.xs
@@ -0,0 +1,33 @@
+/******************************************************************************
+ * FILE PURPOSE: PCIE LLD soc specific files.
+ ******************************************************************************
+ * FILE NAME: Module.xs
+ *
+ * DESCRIPTION: 
+ *  This file contains the module specification for PCIE LLD soc specific files.
+ *
+ * Copyright (C) 2013-2015, Texas Instruments, Inc.
+ *****************************************************************************/
+
+/* Load the library utility. */
+var libUtility = xdc.loadCapsule ("../build/buildlib.xs");
+
+/**************************************************************************
+ * FUNCTION NAME : modBuild
+ **************************************************************************
+ * DESCRIPTION   :
+ *  The function is used to add all the source files in the soc 
+ *  directory into the package.
+ **************************************************************************/
+function modBuild() 
+{
+    /* Add all the .c files to the release package. */
+    var configFiles = libUtility.listAllFiles (".c", "soc", true);
+    for (var k = 0 ; k < configFiles.length; k++)
+        Pkg.otherFiles[Pkg.otherFiles.length++] = configFiles[k];
+
+    /* Add all the .h files to the release package. */
+    var configFiles = libUtility.listAllFiles (".h", "soc", true);
+    for (var k = 0 ; k < configFiles.length; k++)
+        Pkg.otherFiles[Pkg.otherFiles.length++] = configFiles[k];
+}
diff --git a/soc/am572x/src/pcie_soc.c b/soc/am572x/src/pcie_soc.c
new file mode 100644
index 0000000..ca3ff61
--- /dev/null
+++ b/soc/am572x/src/pcie_soc.c
@@ -0,0 +1,105 @@
+/**
+ *   @file  am572x/src/pcie_soc.c
+ *
+ *   @brief   
+ *      This file contains the device specific configuration and initialization routines
+ *      for pcie Low Level Driver.
+ *
+ *  \par
+ *  ============================================================================
+ *  @n   (C) Copyright 2015, Texas Instruments, Inc.
+ * 
+ *  Redistribution and use in source and binary forms, with or without 
+ *  modification, are permitted provided that the following conditions 
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the   
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  \par
+*/
+
+/** 
+ * This file contains an example device configuration for the pcie LLD.
+ * It is not precompiled to facilitate user modification of the file.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+
+/* CSL RL includes */
+#include <ti/csl/cslr_device.h>
+#include <ti/csl/cslr_bootcfg.h>
+
+#include <ti/csl/csl_bootcfg.h>
+
+/* pcie LLD includes */
+#include <ti/drv/pcie/device/pcie_device.h>
+#include <ti/drv/pcie/pcie.h>
+
+/** @addtogroup PCIE_LLD_DATASTRUCT
+@{ 
+*/
+
+/** @brief PCIE LLD initialization parameters */
+const Pcie_InitCfg pcieInitCfg =
+{
+  {
+    {
+      {
+        (void *)CSL_PCIE_SLV_CFG_REGS,
+        (void *)CSL_PCIE_SLV_DATA,
+        (volatile uint32_t *)&hBootCfg->DEVCFG,
+        CSL_BOOTCFG_DEVCFG_PCIESSMODE_MASK,
+        CSL_BOOTCFG_DEVCFG_PCIESSMODE_SHIFT
+      },
+      {
+        NULL,
+        NULL,
+        NULL,
+        0,
+        0
+      },
+      {
+        NULL,
+        NULL,
+        NULL,
+        0,
+        0
+      },
+      {
+        NULL,
+        NULL,
+        NULL,
+        0,
+        0
+      }
+    } 
+  }
+};
+
+/**
+@}
+*/
+
diff --git a/soc/k2e/src/pcie_soc.c b/soc/k2e/src/pcie_soc.c
new file mode 100644
index 0000000..11c54ea
--- /dev/null
+++ b/soc/k2e/src/pcie_soc.c
@@ -0,0 +1,125 @@
+/**
+ *   @file  k2e/src/pcie_soc.c
+ *
+ *   @brief   
+ *      This file contains the device specific configuration and initialization routines
+ *      for pcie Low Level Driver.
+ *
+ *  \par
+ *  ============================================================================
+ *  @n   (C) Copyright 2013-2015, Texas Instruments, Inc.
+ * 
+ *  Redistribution and use in source and binary forms, with or without 
+ *  modification, are permitted provided that the following conditions 
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the   
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  \par
+*/
+
+/** 
+ * This file contains an example device configuration for the pcie LLD.
+ * It is not precompiled to facilitate user modification of the file.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+
+/* CSL RL includes */
+#include <ti/csl/cslr_device.h>
+#include <ti/csl/cslr_bootcfg.h>
+
+#include <ti/csl/csl_bootcfg.h>
+
+/* pcie LLD includes */
+#include <ti/drv/pcie/soc/pcie_soc.h>
+#include <ti/drv/pcie/pcie.h>
+#include <ti/drv/pcie/src/v0/pcie.h>
+
+/** @addtogroup PCIE_LLD_DATASTRUCT
+@{ 
+*/
+
+/** @brief PCIE v0 calltable */
+Pcie_FxnTable fxnTablev0 =
+{
+  /*! Function to set PCIE to EP or RC for one device */
+  Pciev0_setInterfaceMode,
+  /*! Function to get the PCIE data area base address & size */
+  Pciev0_getMemSpaceRange,
+  /*! Function to read any PCIE register(s) */
+  Pciev0_readRegs,
+  /*! Function to write any PCIE register(s) */
+  Pciev0_writeRegs,
+  /*! Function to configure outbound translation registers */
+  Pciev0_cfgObOffset,
+  /*! Function to configure inbound translation registers */
+  Pciev0_cfgIbTrans,
+  /*! Function to configure a BAR register */
+  Pciev0_cfgBar
+};
+
+Pcie_DeviceCfgBaseAddr baseAddrDev0 = 
+{
+  (void *)CSL_PCIE_0_SLV_CFG_REGS,
+  (void *)CSL_PCIE_0_SLV_DATA,
+  (volatile uint32_t *)&hBootCfg->DEVCFG,
+  CSL_BOOTCFG_DEVCFG_PCIE_DEV_TYPE_MASK,
+  CSL_BOOTCFG_DEVCFG_PCIE_DEV_TYPE_SHIFT
+};
+
+Pcie_DeviceCfgBaseAddr baseAddrDev1 = 
+{
+  (void *)CSL_PCIE_1_SLV_CFG_REGS,
+  (void *)CSL_PCIE_1_SLV_DATA,
+  (volatile uint32_t *)&hBootCfg->DEVCFG,
+  CSL_BOOTCFG_DEVCFG_PCIE1_DEV_TYPE_MASK,
+  CSL_BOOTCFG_DEVCFG_PCIE1_DEV_TYPE_SHIFT
+};
+
+/** @brief PCIE LLD initialization parameters */
+const Pcie_InitCfg pcieInitCfg =
+{
+  {
+    {
+      &baseAddrDev0,
+      &baseAddrDev1,
+      NULL,
+      NULL
+    },
+    {
+      &fxnTablev0,
+      &fxnTablev0,
+      NULL,
+      NULL
+    }
+  }
+};
+
+/**
+@}
+*/
+
diff --git a/soc/k2h/src/pcie_soc.c b/soc/k2h/src/pcie_soc.c
new file mode 100644
index 0000000..c5ddfce
--- /dev/null
+++ b/soc/k2h/src/pcie_soc.c
@@ -0,0 +1,116 @@
+/**
+ *   @file  k2h/src/pcie_soc.c
+ *
+ *   @brief   
+ *      This file contains the device specific configuration and initialization routines
+ *      for pcie Low Level Driver.
+ *
+ *  \par
+ *  ============================================================================
+ *  @n   (C) Copyright 2013-2015, Texas Instruments, Inc.
+ * 
+ *  Redistribution and use in source and binary forms, with or without 
+ *  modification, are permitted provided that the following conditions 
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the   
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  \par
+*/
+
+/** 
+ * This file contains an example device configuration for the pcie LLD.
+ * It is not precompiled to facilitate user modification of the file.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+
+/* CSL RL includes */
+#include <ti/csl/cslr_device.h>
+#include <ti/csl/cslr_bootcfg.h>
+
+#include <ti/csl/csl_bootcfg.h>
+
+/* pcie LLD includes */
+#include <ti/drv/pcie/soc/pcie_soc.h>
+#include <ti/drv/pcie/pcie.h>
+#include <ti/drv/pcie/src/v0/pcie.h>
+
+/** @addtogroup PCIE_LLD_DATASTRUCT
+@{ 
+*/
+
+/** @brief PCIE v0 calltable */
+Pcie_FxnTable fxnTablev0 =
+{
+  /*! Function to set PCIE to EP or RC for one device */
+  Pciev0_setInterfaceMode,
+  /*! Function to get the PCIE data area base address & size */
+  Pciev0_getMemSpaceRange,
+  /*! Function to read any PCIE register(s) */
+  Pciev0_readRegs,
+  /*! Function to write any PCIE register(s) */
+  Pciev0_writeRegs,
+  /*! Function to configure outbound translation registers */
+  Pciev0_cfgObOffset,
+  /*! Function to configure inbound translation registers */
+  Pciev0_cfgIbTrans,
+  /*! Function to configure a BAR register */
+  Pciev0_cfgBar
+};
+
+Pcie_DeviceCfgBaseAddr baseAddrDev0 = 
+{
+  (void *)CSL_PCIE_SLV_CFG_REGS,
+  (void *)CSL_PCIE_SLV_DATA,
+  (volatile uint32_t *)&hBootCfg->DEVCFG,
+  CSL_BOOTCFG_DEVCFG_PCIESSMODE_MASK,
+  CSL_BOOTCFG_DEVCFG_PCIESSMODE_SHIFT
+};
+
+/** @brief PCIE LLD initialization parameters */
+const Pcie_InitCfg pcieInitCfg =
+{
+  {
+    {
+      &baseAddrDev0,
+      NULL,
+      NULL,
+      NULL
+    },
+    {
+      &fxnTablev0,
+      NULL,
+      NULL,
+      NULL
+    }
+  }
+};
+
+/**
+@}
+*/
+
diff --git a/soc/k2k/src/pcie_soc.c b/soc/k2k/src/pcie_soc.c
new file mode 100644
index 0000000..6a1efa5
--- /dev/null
+++ b/soc/k2k/src/pcie_soc.c
@@ -0,0 +1,116 @@
+/**
+ *   @file  k2k/src/pcie_soc.c
+ *
+ *   @brief   
+ *      This file contains the device specific configuration and initialization routines
+ *      for pcie Low Level Driver.
+ *
+ *  \par
+ *  ============================================================================
+ *  @n   (C) Copyright 2013-2015, Texas Instruments, Inc.
+ * 
+ *  Redistribution and use in source and binary forms, with or without 
+ *  modification, are permitted provided that the following conditions 
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the   
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  \par
+*/
+
+/** 
+ * This file contains an example device configuration for the pcie LLD.
+ * It is not precompiled to facilitate user modification of the file.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+
+/* CSL RL includes */
+#include <ti/csl/cslr_device.h>
+#include <ti/csl/cslr_bootcfg.h>
+
+#include <ti/csl/csl_bootcfg.h>
+
+/* pcie LLD includes */
+#include <ti/drv/pcie/soc/pcie_soc.h>
+#include <ti/drv/pcie/pcie.h>
+#include <ti/drv/pcie/src/v0/pcie.h>
+
+/** @addtogroup PCIE_LLD_DATASTRUCT
+@{ 
+*/
+
+/** @brief PCIE v0 calltable */
+Pcie_FxnTable fxnTablev0 =
+{
+  /*! Function to set PCIE to EP or RC for one device */
+  Pciev0_setInterfaceMode,
+  /*! Function to get the PCIE data area base address & size */
+  Pciev0_getMemSpaceRange,
+  /*! Function to read any PCIE register(s) */
+  Pciev0_readRegs,
+  /*! Function to write any PCIE register(s) */
+  Pciev0_writeRegs,
+  /*! Function to configure outbound translation registers */
+  Pciev0_cfgObOffset,
+  /*! Function to configure inbound translation registers */
+  Pciev0_cfgIbTrans,
+  /*! Function to configure a BAR register */
+  Pciev0_cfgBar
+};
+
+Pcie_DeviceCfgBaseAddr baseAddrDev0 = 
+{
+  (void *)CSL_PCIE_SLV_CFG_REGS,
+  (void *)CSL_PCIE_SLV_DATA,
+  (volatile uint32_t *)&hBootCfg->DEVCFG,
+  CSL_BOOTCFG_DEVCFG_PCIESSMODE_MASK,
+  CSL_BOOTCFG_DEVCFG_PCIESSMODE_SHIFT
+};
+
+/** @brief PCIE LLD initialization parameters */
+const Pcie_InitCfg pcieInitCfg =
+{
+  {
+    {
+      &baseAddrDev0,
+      NULL,
+      NULL,
+      NULL
+    },
+    {
+      &fxnTablev0,
+      NULL,
+      NULL,
+      NULL
+    }
+  }
+};
+
+/**
+@}
+*/
+
diff --git a/soc/k2l/src/pcie_soc.c b/soc/k2l/src/pcie_soc.c
new file mode 100644
index 0000000..3f42191
--- /dev/null
+++ b/soc/k2l/src/pcie_soc.c
@@ -0,0 +1,125 @@
+/**
+ *   @file  k2l/src/pcie_soc.c
+ *
+ *   @brief   
+ *      This file contains the device specific configuration and initialization routines
+ *      for pcie Low Level Driver.
+ *
+ *  \par
+ *  ============================================================================
+ *  @n   (C) Copyright 2013-2015, Texas Instruments, Inc.
+ * 
+ *  Redistribution and use in source and binary forms, with or without 
+ *  modification, are permitted provided that the following conditions 
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the   
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  \par
+*/
+
+/** 
+ * This file contains an example device configuration for the pcie LLD.
+ * It is not precompiled to facilitate user modification of the file.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+
+/* CSL RL includes */
+#include <ti/csl/cslr_device.h>
+#include <ti/csl/cslr_bootcfg.h>
+
+#include <ti/csl/csl_bootcfg.h>
+
+/* pcie LLD includes */
+#include <ti/drv/pcie/soc/pcie_soc.h>
+#include <ti/drv/pcie/pcie.h>
+#include <ti/drv/pcie/src/v0/pcie.h>
+
+/** @addtogroup PCIE_LLD_DATASTRUCT
+@{ 
+*/
+
+/** @brief PCIE v0 calltable */
+Pcie_FxnTable fxnTablev0 =
+{
+  /*! Function to set PCIE to EP or RC for one device */
+  Pciev0_setInterfaceMode,
+  /*! Function to get the PCIE data area base address & size */
+  Pciev0_getMemSpaceRange,
+  /*! Function to read any PCIE register(s) */
+  Pciev0_readRegs,
+  /*! Function to write any PCIE register(s) */
+  Pciev0_writeRegs,
+  /*! Function to configure outbound translation registers */
+  Pciev0_cfgObOffset,
+  /*! Function to configure inbound translation registers */
+  Pciev0_cfgIbTrans,
+  /*! Function to configure a BAR register */
+  Pciev0_cfgBar
+};
+
+Pcie_DeviceCfgBaseAddr baseAddrDev0 = 
+{
+  (void *)CSL_PCIE_0_SLV_CFG_REGS,
+  (void *)CSL_PCIE_0_SLV_DATA,
+  (volatile uint32_t *)&hBootCfg->DEVCFG,
+  CSL_BOOTCFG_DEVCFG_PCIESS_0_MODE_MASK,
+  CSL_BOOTCFG_DEVCFG_PCIESS_0_MODE_SHIFT
+};
+
+Pcie_DeviceCfgBaseAddr baseAddrDev1 = 
+{
+  (void *)CSL_PCIE_1_SLV_CFG_REGS,
+  (void *)CSL_PCIE_1_SLV_DATA,
+  (volatile uint32_t *)&hBootCfg->DEVCFG,
+  CSL_BOOTCFG_DEVCFG_PCIESS_1_MODE_MASK,
+  CSL_BOOTCFG_DEVCFG_PCIESS_1_MODE_SHIFT
+};
+
+/** @brief PCIE LLD initialization parameters */
+const Pcie_InitCfg pcieInitCfg =
+{
+  {
+    {
+      &baseAddrDev0,
+      &baseAddrDev1,
+      NULL,
+      NULL
+    },
+    {
+      &fxnTablev0,
+      &fxnTablev0,
+      NULL,
+      NULL
+    }
+  }
+};
+
+/**
+@}
+*/
+
diff --git a/soc/pcie_soc.h b/soc/pcie_soc.h
new file mode 100644
index 0000000..916a5af
--- /dev/null
+++ b/soc/pcie_soc.h
@@ -0,0 +1,64 @@
+/**
+ *   @file  pcie_soc.h
+ *
+ *   @brief   
+ *      
+ *      Extern for device definition in platform/src/pcie_device.h
+ *
+ *  \par
+ *  ============================================================================
+ *  @n   (C) Copyright 2013-2015, Texas Instruments, Inc.
+ * 
+ *  Redistribution and use in source and binary forms, with or without 
+ *  modification, are permitted provided that the following conditions 
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the   
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  \par
+*/
+
+#ifndef __PCIE_DEVICE_H__
+#define __PCIE_DEVICE_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* System level header files */
+#include <stdint.h>
+#include <stdlib.h>
+
+/* pcie LLD includes */
+#include <ti/drv/pcie/pcie.h>
+
+extern const Pcie_InitCfg pcieInitCfg;
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* __PCIE_DEVICE_H__ */
+
+/* Nothing past this point */