diff options
author | Suraj Das | 2016-09-14 16:45:57 -0500 |
---|---|---|
committer | Suraj Das | 2016-09-14 16:45:57 -0500 |
commit | 929bb66bd1e9e85337d1d3f76bdfa9864505d77c (patch) | |
tree | 95c64120b76fffdca5097a1ea81bd46bc0c8cd5e /src | |
parent | 4d8b37bb19e83af7c832cbc1e81da62d838a4596 (diff) | |
download | pcie-lld-929bb66bd1e9e85337d1d3f76bdfa9864505d77c.tar.gz pcie-lld-929bb66bd1e9e85337d1d3f76bdfa9864505d77c.tar.xz pcie-lld-929bb66bd1e9e85337d1d3f76bdfa9864505d77c.zip |
klocwork fix 1 for misra_return_not_last PRSDK-1201
Diffstat (limited to 'src')
-rw-r--r-- | src/pcieinit.c | 4 | ||||
-rw-r--r-- | src/v0/pciev0.c | 2668 | ||||
-rw-r--r-- | src/v1/pciev1.c | 1508 |
3 files changed, 2112 insertions, 2068 deletions
diff --git a/src/pcieinit.c b/src/pcieinit.c index dd6b59d..69d85a8 100644 --- a/src/pcieinit.c +++ b/src/pcieinit.c | |||
@@ -136,7 +136,9 @@ pcieRet_e Pcie_close | |||
136 | }else { | 136 | }else { |
137 | if (pHandle) { | 137 | if (pHandle) { |
138 | handle = *pHandle; | 138 | handle = *pHandle; |
139 | pcie_check_handle(handle); | 139 | if (pcie_check_handle_fcn(handle) == 0) { |
140 | ret_val = pcie_RET_INV_HANDLE; | ||
141 | } | ||
140 | *pHandle = NULL; | 142 | *pHandle = NULL; |
141 | ret_val = pcie_RET_OK; | 143 | ret_val = pcie_RET_OK; |
142 | }else { | 144 | }else { |
diff --git a/src/v0/pciev0.c b/src/v0/pciev0.c index 36c2bee..a855e7b 100644 --- a/src/v0/pciev0.c +++ b/src/v0/pciev0.c | |||
@@ -108,20 +108,23 @@ pcieRet_e Pciev0_getMemSpaceReserved | |||
108 | pcieRet_e retVal = pcie_RET_OK; | 108 | pcieRet_e retVal = pcie_RET_OK; |
109 | 109 | ||
110 | if (pcieLObjIsValid == 0) { | 110 | if (pcieLObjIsValid == 0) { |
111 | return pcie_RET_NO_INIT; | 111 | retVal = pcie_RET_NO_INIT; |
112 | } | 112 | } |
113 | 113 | else { | |
114 | pcie_check_handle(handle); | 114 | if (pcie_check_handle_fcn(handle) == 0) { |
115 | |||
116 | if (resSize) { | ||
117 | Pcie_DeviceCfgBaseAddr *bases = pcie_handle_to_cfg (handle); | ||
118 | if (bases) { | ||
119 | *resSize = bases->dataReserved; | ||
120 | } else { | ||
121 | retVal = pcie_RET_INV_HANDLE; | 115 | retVal = pcie_RET_INV_HANDLE; |
122 | } | 116 | } |
117 | else { | ||
118 | if (resSize) { | ||
119 | Pcie_DeviceCfgBaseAddr *bases = pcie_handle_to_cfg (handle); | ||
120 | if (bases) { | ||
121 | *resSize = bases->dataReserved; | ||
122 | } else { | ||
123 | retVal = pcie_RET_INV_HANDLE; | ||
124 | } | ||
125 | } | ||
126 | } | ||
123 | } | 127 | } |
124 | |||
125 | return retVal; | 128 | return retVal; |
126 | } /* Pciev0_getMemSpaceReserved */ | 129 | } /* Pciev0_getMemSpaceReserved */ |
127 | 130 | ||
@@ -140,24 +143,27 @@ pcieRet_e Pciev0_getMemSpaceRange | |||
140 | pcieRet_e retVal = pcie_RET_OK; | 143 | pcieRet_e retVal = pcie_RET_OK; |
141 | 144 | ||
142 | if (pcieLObjIsValid == 0) { | 145 | if (pcieLObjIsValid == 0) { |
143 | return pcie_RET_NO_INIT; | 146 | retVal = pcie_RET_NO_INIT; |
144 | } | 147 | } |
145 | 148 | else { | |
146 | pcie_check_handle(handle); | 149 | if (pcie_check_handle_fcn(handle) == 0) { |
147 | |||
148 | if (base) { | ||
149 | Pcie_DeviceCfgBaseAddr *cfg = pcie_handle_to_cfg (handle); | ||
150 | if (cfg) { | ||
151 | *base = cfg->dataBase; | ||
152 | } else { | ||
153 | retVal = pcie_RET_INV_HANDLE; | 150 | retVal = pcie_RET_INV_HANDLE; |
154 | } | 151 | } |
152 | else { | ||
153 | if (base) { | ||
154 | Pcie_DeviceCfgBaseAddr *cfg = pcie_handle_to_cfg (handle); | ||
155 | if (cfg) { | ||
156 | *base = cfg->dataBase; | ||
157 | } else { | ||
158 | retVal = pcie_RET_INV_HANDLE; | ||
159 | } | ||
160 | } | ||
161 | |||
162 | if (size) { | ||
163 | *size = (uint32_t)0x10000000; /* 256 MB */ | ||
164 | } | ||
165 | } | ||
155 | } | 166 | } |
156 | |||
157 | if (size) { | ||
158 | *size = (uint32_t)0x10000000; /* 256 MB */ | ||
159 | } | ||
160 | |||
161 | return retVal; | 167 | return retVal; |
162 | } /* Pciev0_getMemSpaceRange */ | 168 | } /* Pciev0_getMemSpaceRange */ |
163 | 169 | ||
@@ -184,630 +190,634 @@ pcieRet_e Pciev0_readRegs | |||
184 | int32_t i; | 190 | int32_t i; |
185 | 191 | ||
186 | if (pcieLObjIsValid == 0) { | 192 | if (pcieLObjIsValid == 0) { |
187 | return pcie_RET_NO_INIT; | 193 | retVal = pcie_RET_NO_INIT; |
188 | } | ||
189 | |||
190 | pcie_check_handle(handle); | ||
191 | |||
192 | baseAppRegs = cfg->cfgBase; | ||
193 | |||
194 | /* Get base address for Local or Remote config space */ | ||
195 | if (location == pcie_LOCATION_LOCAL) | ||
196 | { | ||
197 | pcie_get_loc_cfg_base(baseAppRegs, baseCfgEpRegs, baseCfgRcRegs) | ||
198 | } | ||
199 | else | ||
200 | { | ||
201 | pcie_get_rem_cfg_base(baseAppRegs, baseCfgEpRegs, baseCfgRcRegs) | ||
202 | } | ||
203 | |||
204 | /***************************************************************************************** | ||
205 | *Application Registers | ||
206 | *****************************************************************************************/ | ||
207 | if (readRegs->pid) { | ||
208 | pcie_check_result(retVal, pciev0_read_pid_reg (baseAppRegs, readRegs->pid)); | ||
209 | } | ||
210 | if (readRegs->cmdStatus) { | ||
211 | pcie_check_result(retVal, pciev0_read_cmdStatus_reg (baseAppRegs, readRegs->cmdStatus)); | ||
212 | } | ||
213 | if (readRegs->cfgTrans) { | ||
214 | pcie_check_result(retVal, pciev0_read_cfgTrans_reg (baseAppRegs, readRegs->cfgTrans)); | ||
215 | } | ||
216 | if (readRegs->ioBase) { | ||
217 | pcie_check_result(retVal, pciev0_read_ioBase_reg (baseAppRegs, readRegs->ioBase)); | ||
218 | } | ||
219 | if (readRegs->tlpCfg) { | ||
220 | pcie_check_result(retVal, pciev0_read_tlpCfg_reg (baseAppRegs, readRegs->tlpCfg)); | ||
221 | } | ||
222 | if (readRegs->rstCmd) { | ||
223 | pcie_check_result(retVal, pciev0_read_rstCmd_reg (baseAppRegs, readRegs->rstCmd)); | ||
224 | } | ||
225 | if (readRegs->pmCmd) { | ||
226 | pcie_check_result(retVal, pciev0_read_pmCmd_reg (baseAppRegs, readRegs->pmCmd)); | ||
227 | } | ||
228 | if (readRegs->pmCfg) { | ||
229 | pcie_check_result(retVal, pciev0_read_pmCfg_reg (baseAppRegs, readRegs->pmCfg)); | ||
230 | } | ||
231 | if (readRegs->actStatus) { | ||
232 | pcie_check_result(retVal, pciev0_read_actStatus_reg (baseAppRegs, readRegs->actStatus)); | ||
233 | } | ||
234 | if (readRegs->obSize) { | ||
235 | pcie_check_result(retVal, pciev0_read_obSize_reg (baseAppRegs, readRegs->obSize)); | ||
236 | } | ||
237 | if (readRegs->diagCtrl) { | ||
238 | pcie_check_result(retVal, pciev0_read_diagCtrl_reg (baseAppRegs, readRegs->diagCtrl)); | ||
239 | } | ||
240 | if (readRegs->endian) { | ||
241 | pcie_check_result(retVal, pciev0_read_endian_reg (baseAppRegs, readRegs->endian)); | ||
242 | } | ||
243 | if (readRegs->priority) { | ||
244 | pcie_check_result(retVal, pciev0_read_priority_reg (baseAppRegs, readRegs->priority)); | ||
245 | } | ||
246 | if (readRegs->irqEOI) { | ||
247 | pcie_check_result(retVal, pciev0_read_irqEOI_reg (baseAppRegs, readRegs->irqEOI)); | ||
248 | } | ||
249 | if (readRegs->msiIrq) { | ||
250 | pcie_check_result(retVal, pciev0_read_msiIrq_reg (baseAppRegs, readRegs->msiIrq)); | ||
251 | } | ||
252 | if (readRegs->epIrqSet) { | ||
253 | pcie_check_result(retVal, pciev0_read_epIrqSet_reg (baseAppRegs, readRegs->epIrqSet)); | ||
254 | } | ||
255 | if (readRegs->epIrqClr) { | ||
256 | pcie_check_result(retVal, pciev0_read_epIrqClr_reg (baseAppRegs, readRegs->epIrqClr)); | ||
257 | } | ||
258 | if (readRegs->epIrqStatus) { | ||
259 | pcie_check_result(retVal, pciev0_read_epIrqStatus_reg (baseAppRegs, readRegs->epIrqStatus)); | ||
260 | } | ||
261 | for (i = 0; i < 4; i++) { | ||
262 | if (readRegs->genPurpose[i]) { | ||
263 | pcie_check_result(retVal, pciev0_read_genPurpose_reg (baseAppRegs, readRegs->genPurpose[i], i)); | ||
264 | } | ||
265 | } | ||
266 | for (i = 0; i < 8; i++) { | ||
267 | if (readRegs->msiIrqStatusRaw[i]) { | ||
268 | pcie_check_result(retVal, pciev0_read_msiIrqStatusRaw_reg (baseAppRegs, readRegs->msiIrqStatusRaw[i], i)); | ||
269 | } | ||
270 | if (readRegs->msiIrqStatus[i]) { | ||
271 | pcie_check_result(retVal, pciev0_read_msiIrqStatus_reg (baseAppRegs, readRegs->msiIrqStatus[i], i)); | ||
272 | } | ||
273 | if (readRegs->msiIrqEnableSet[i]) { | ||
274 | pcie_check_result(retVal, pciev0_read_msiIrqEnableSet_reg (baseAppRegs, readRegs->msiIrqEnableSet[i], i)); | ||
275 | } | ||
276 | if (readRegs->msiIrqEnableClr[i]) { | ||
277 | pcie_check_result(retVal, pciev0_read_msiIrqEnableClr_reg (baseAppRegs, readRegs->msiIrqEnableClr[i], i)); | ||
278 | } | ||
279 | } | ||
280 | for (i = 0; i < 4; i++) { | ||
281 | if (readRegs->legacyIrqStatusRaw[i]) { | ||
282 | pcie_check_result(retVal, pciev0_read_legacyIrqStatusRaw_reg (baseAppRegs, readRegs->legacyIrqStatusRaw[i], i)); | ||
283 | } | ||
284 | if (readRegs->legacyIrqStatus[i]) { | ||
285 | pcie_check_result(retVal, pciev0_read_legacyIrqStatus_reg (baseAppRegs, readRegs->legacyIrqStatus[i], i)); | ||
286 | } | ||
287 | if (readRegs->legacyIrqEnableSet[i]) { | ||
288 | pcie_check_result(retVal, pciev0_read_legacyIrqEnableSet_reg (baseAppRegs, readRegs->legacyIrqEnableSet[i], i)); | ||
289 | } | ||
290 | if (readRegs->legacyIrqEnableClr[i]) { | ||
291 | pcie_check_result(retVal, pciev0_read_legacyIrqEnableClr_reg (baseAppRegs, readRegs->legacyIrqEnableClr[i], i)); | ||
292 | } | ||
293 | } | ||
294 | if (readRegs->errIrqStatusRaw) { | ||
295 | pcie_check_result(retVal, pciev0_read_errIrqStatusRaw_reg (baseAppRegs, readRegs->errIrqStatusRaw)); | ||
296 | } | ||
297 | if (readRegs->errIrqStatus) { | ||
298 | pcie_check_result(retVal, pciev0_read_errIrqStatus_reg (baseAppRegs, readRegs->errIrqStatus)); | ||
299 | } | ||
300 | if (readRegs->errIrqEnableSet) { | ||
301 | pcie_check_result(retVal, pciev0_read_errIrqEnableSet_reg (baseAppRegs, readRegs->errIrqEnableSet)); | ||
302 | } | ||
303 | if (readRegs->errIrqEnableClr) { | ||
304 | pcie_check_result(retVal, pciev0_read_errIrqEnableClr_reg (baseAppRegs, readRegs->errIrqEnableClr)); | ||
305 | } | ||
306 | |||
307 | if (readRegs->pmRstIrqStatusRaw) { | ||
308 | pcie_check_result(retVal, pciev0_read_pmRstIrqStatusRaw_reg (baseAppRegs, readRegs->pmRstIrqStatusRaw)); | ||
309 | } | ||
310 | if (readRegs->pmRstIrqStatus) { | ||
311 | pcie_check_result(retVal, pciev0_read_pmRstIrqStatus_reg (baseAppRegs, readRegs->pmRstIrqStatus)); | ||
312 | } | ||
313 | if (readRegs->pmRstIrqEnableSet) { | ||
314 | pcie_check_result(retVal, pciev0_read_pmRstIrqEnableSet_reg (baseAppRegs, readRegs->pmRstIrqEnableSet)); | ||
315 | } | ||
316 | if (readRegs->pmRstIrqEnableClr) { | ||
317 | pcie_check_result(retVal, pciev0_read_pmRstIrqEnableClr_reg (baseAppRegs, readRegs->pmRstIrqEnableClr)); | ||
318 | } | ||
319 | |||
320 | for (i = 0; i < 8; i ++) { | ||
321 | if (readRegs->obOffsetLo[i]) { | ||
322 | pcie_check_result(retVal, pciev0_read_obOffsetLo_reg (baseAppRegs, readRegs->obOffsetLo[i], i)); | ||
323 | } | ||
324 | if (readRegs->obOffsetHi[i]) { | ||
325 | pcie_check_result(retVal, pciev0_read_obOffsetHi_reg (baseAppRegs, readRegs->obOffsetHi[i], i)); | ||
326 | } | ||
327 | } | ||
328 | |||
329 | for (i = 0; i < 4; i ++) { | ||
330 | if (readRegs->ibBar[i]) { | ||
331 | pcie_check_result(retVal, pciev0_read_ibBar_reg (baseAppRegs, readRegs->ibBar[i], i)); | ||
332 | } | ||
333 | if (readRegs->ibStartLo[i]) { | ||
334 | pcie_check_result(retVal, pciev0_read_ibStartLo_reg (baseAppRegs, readRegs->ibStartLo[i], i)); | ||
335 | } | ||
336 | if (readRegs->ibStartHi[i]) { | ||
337 | pcie_check_result(retVal, pciev0_read_ibStartHi_reg (baseAppRegs, readRegs->ibStartHi[i], i)); | ||
338 | } | ||
339 | if (readRegs->ibOffset[i]) { | ||
340 | pcie_check_result(retVal, pciev0_read_ibOffset_reg (baseAppRegs, readRegs->ibOffset[i], i)); | ||
341 | } | ||
342 | } | ||
343 | |||
344 | if (readRegs->pcsCfg0) { | ||
345 | pcie_check_result(retVal, pciev0_read_pcsCfg0_reg (baseAppRegs, readRegs->pcsCfg0)); | ||
346 | } | ||
347 | if (readRegs->pcsCfg1) { | ||
348 | pcie_check_result(retVal, pciev0_read_pcsCfg1_reg (baseAppRegs, readRegs->pcsCfg1)); | ||
349 | } | ||
350 | if (readRegs->pcsStatus) { | ||
351 | pcie_check_result(retVal, pciev0_read_pcsStatus_reg (baseAppRegs, readRegs->pcsStatus)); | ||
352 | } | ||
353 | |||
354 | if (readRegs->serdesCfg0) { | ||
355 | pcie_check_result(retVal, pciev0_read_serdesCfg0_reg (baseAppRegs, readRegs->serdesCfg0)); | ||
356 | } | ||
357 | if (readRegs->serdesCfg1) { | ||
358 | pcie_check_result(retVal, pciev0_read_serdesCfg1_reg (baseAppRegs, readRegs->serdesCfg1)); | ||
359 | } | ||
360 | |||
361 | /***************************************************************************************** | ||
362 | *Configuration Registers | ||
363 | *****************************************************************************************/ | ||
364 | |||
365 | /*Type 0, Type1 Common Registers*/ | ||
366 | |||
367 | if (readRegs->vndDevId) { | ||
368 | pcie_check_result(retVal, pciev0_read_vndDevId_reg (baseCfgEpRegs, readRegs->vndDevId)); | ||
369 | } | ||
370 | if (readRegs->statusCmd) { | ||
371 | pcie_check_result(retVal, pciev0_read_statusCmd_reg (baseCfgEpRegs, readRegs->statusCmd)); | ||
372 | } | ||
373 | if (readRegs->revId) { | ||
374 | pcie_check_result(retVal, pciev0_read_revId_reg (baseCfgEpRegs, readRegs->revId)); | ||
375 | } | ||
376 | |||
377 | /*Type 0 Registers*/ | ||
378 | if (readRegs->bist) { | ||
379 | pcie_check_result(retVal, pciev0_read_bist_reg (baseCfgEpRegs, readRegs->bist)); | ||
380 | } | ||
381 | if (readRegs->type0BarIdx) { | ||
382 | pcie_check_result(retVal, pciev0_read_type0Bar_reg (baseCfgEpRegs, &(readRegs->type0BarIdx->reg), | ||
383 | readRegs->type0BarIdx->idx)); | ||
384 | } | ||
385 | if (readRegs->type0Bar32bitIdx) { | ||
386 | pcie_check_result(retVal, pciev0_read_type0Bar32bit_reg (baseCfgEpRegs, &(readRegs->type0Bar32bitIdx->reg), | ||
387 | readRegs->type0Bar32bitIdx->idx)); | ||
388 | } | ||
389 | if (readRegs->type0BarMask32bitIdx) { | ||
390 | pcie_check_result(retVal, pciev0_read_type0Bar32bit_reg (baseCfgEpRegs, &(readRegs->type0BarMask32bitIdx->reg), | ||
391 | readRegs->type0BarMask32bitIdx->idx)); | ||
392 | } | ||
393 | if (readRegs->subId) { | ||
394 | pcie_check_result(retVal, pciev0_read_subId_reg (baseCfgEpRegs, readRegs->subId)); | ||
395 | } | ||
396 | if (readRegs->cardbusCisPointer) { | ||
397 | /* Not supported on rev 0 */ | ||
398 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
399 | } | ||
400 | if (readRegs->expRom) { | ||
401 | pcie_check_result(retVal, pciev0_read_expRom_reg (baseCfgEpRegs, readRegs->expRom)); | ||
402 | } | ||
403 | if (readRegs->capPtr) { | ||
404 | pcie_check_result(retVal, pciev0_read_capPtr_reg (baseCfgEpRegs, readRegs->capPtr)); | ||
405 | } | ||
406 | if (readRegs->intPin) { | ||
407 | pcie_check_result(retVal, pciev0_read_intPin_reg (baseCfgEpRegs, readRegs->intPin)); | ||
408 | } | ||
409 | |||
410 | /*Type 1 Registers*/ | ||
411 | if (readRegs->type1BistHeader) { | ||
412 | pcie_check_result(retVal, pciev0_read_type1BistHeader_reg (baseCfgRcRegs, readRegs->type1BistHeader)); | ||
413 | } | ||
414 | if (readRegs->type1BarIdx) { | ||
415 | pcie_check_result(retVal, pciev0_read_type1Bar_reg (baseCfgRcRegs, &(readRegs->type1BarIdx->reg), | ||
416 | readRegs->type1BarIdx->idx)); | ||
417 | } | ||
418 | if (readRegs->type1Bar32bitIdx) { | ||
419 | pcie_check_result(retVal, pciev0_read_type1Bar32bit_reg (baseCfgRcRegs, &(readRegs->type1Bar32bitIdx->reg), | ||
420 | readRegs->type1Bar32bitIdx->idx)); | ||
421 | } | ||
422 | if (readRegs->type1BarMask32bitIdx) { | ||
423 | pcie_check_result(retVal, pciev0_read_type1Bar32bit_reg (baseCfgRcRegs, &(readRegs->type1BarMask32bitIdx->reg), | ||
424 | readRegs->type1BarMask32bitIdx->idx)); | ||
425 | } | ||
426 | if (readRegs->type1BusNum) { | ||
427 | pcie_check_result(retVal, pciev0_read_type1BusNum_reg (baseCfgRcRegs, readRegs->type1BusNum)); | ||
428 | } | ||
429 | if (readRegs->type1SecStat) { | ||
430 | pcie_check_result(retVal, pciev0_read_type1SecStat_reg (baseCfgRcRegs, readRegs->type1SecStat)); | ||
431 | } | ||
432 | if (readRegs->type1Memspace) { | ||
433 | pcie_check_result(retVal, pciev0_read_type1Memspace_reg (baseCfgRcRegs, readRegs->type1Memspace)); | ||
434 | } | ||
435 | if (readRegs->prefMem) { | ||
436 | pcie_check_result(retVal, pciev0_read_prefMem_reg (baseCfgRcRegs, readRegs->prefMem)); | ||
437 | } | ||
438 | if (readRegs->prefBaseUpper) { | ||
439 | pcie_check_result(retVal, pciev0_read_prefBaseUpper_reg (baseCfgRcRegs, readRegs->prefBaseUpper)); | ||
440 | } | ||
441 | if (readRegs->prefLimitUpper) { | ||
442 | pcie_check_result(retVal, pciev0_read_prefLimitUpper_reg (baseCfgRcRegs, readRegs->prefLimitUpper)); | ||
443 | } | ||
444 | if (readRegs->type1IOSpace) { | ||
445 | pcie_check_result(retVal, pciev0_read_type1IOSpace_reg (baseCfgRcRegs, readRegs->type1IOSpace)); | ||
446 | } | ||
447 | if (readRegs->type1CapPtr) { | ||
448 | pcie_check_result(retVal, pciev0_read_type1CapPtr_reg (baseCfgRcRegs, readRegs->type1CapPtr)); | ||
449 | } | ||
450 | if (readRegs->type1ExpnsnRom) { | ||
451 | pcie_check_result(retVal, pciev0_read_type1ExpnsnRom_reg (baseCfgRcRegs, readRegs->type1ExpnsnRom)); | ||
452 | } | ||
453 | if (readRegs->type1BridgeInt) { | ||
454 | pcie_check_result(retVal, pciev0_read_type1BridgeInt_reg (baseCfgRcRegs, readRegs->type1BridgeInt)); | ||
455 | } | ||
456 | |||
457 | /* Power Management Capabilities Registers */ | ||
458 | if (readRegs->pmCap) { | ||
459 | pcie_check_result(retVal, pciev0_read_pmCap_reg (baseCfgEpRegs, readRegs->pmCap)); | ||
460 | } | ||
461 | if (readRegs->pmCapCtlStat) { | ||
462 | pcie_check_result(retVal, pciev0_read_pmCapCtlStat_reg (baseCfgEpRegs, readRegs->pmCapCtlStat)); | ||
463 | } | ||
464 | |||
465 | /*MSI Registers*/ | ||
466 | if (readRegs->msiCap) { | ||
467 | pcie_check_result(retVal, pciev0_read_msiCap_reg (baseCfgEpRegs, readRegs->msiCap)); | ||
468 | } | 194 | } |
469 | if (readRegs->msiLo32) { | 195 | else { |
470 | pcie_check_result(retVal, pciev0_read_msiLo32_reg (baseCfgEpRegs, readRegs->msiLo32)); | 196 | if (pcie_check_handle_fcn(handle) == 0) { |
471 | } | 197 | retVal = pcie_RET_INV_HANDLE; |
472 | if (readRegs->msiUp32) { | ||
473 | pcie_check_result(retVal, pciev0_read_msiUp32_reg (baseCfgEpRegs, readRegs->msiUp32)); | ||
474 | } | ||
475 | if (readRegs->msiData) { | ||
476 | pcie_check_result(retVal, pciev0_read_msiData_reg (baseCfgEpRegs, readRegs->msiData)); | ||
477 | } | ||
478 | |||
479 | /*Capabilities Registers*/ | ||
480 | if (readRegs->pciesCap) { | ||
481 | pcie_check_result(retVal, pciev0_read_pciesCap_reg (baseCfgEpRegs, readRegs->pciesCap)); | ||
482 | } | ||
483 | if (readRegs->deviceCap) { | ||
484 | pcie_check_result(retVal, pciev0_read_deviceCap_reg (baseCfgEpRegs, readRegs->deviceCap)); | ||
485 | } | ||
486 | if (readRegs->devStatCtrl) { | ||
487 | pcie_check_result(retVal, pciev0_read_devStatCtrl_reg (baseCfgEpRegs, readRegs->devStatCtrl)); | ||
488 | } | ||
489 | if (readRegs->linkCap) { | ||
490 | pcie_check_result(retVal, pciev0_read_linkCap_reg (baseCfgEpRegs, readRegs->linkCap)); | ||
491 | } | ||
492 | if (readRegs->linkStatCtrl) { | ||
493 | pcie_check_result(retVal, pciev0_read_linkStatCtrl_reg (baseCfgEpRegs, readRegs->linkStatCtrl)); | ||
494 | } | ||
495 | if (readRegs->slotCap) { | ||
496 | pcie_check_result(retVal, pciev0_read_slotCap_reg (baseCfgRcRegs, readRegs->slotCap)); | ||
497 | } | ||
498 | if (readRegs->slotStatCtrl) { | ||
499 | pcie_check_result(retVal, pciev0_read_slotStatCtrl_reg (baseCfgRcRegs, readRegs->slotStatCtrl)); | ||
500 | } | ||
501 | if (readRegs->rootCtrlCap) { | ||
502 | pcie_check_result(retVal, pciev0_read_rootCtrlCap_reg (baseCfgRcRegs, readRegs->rootCtrlCap)); | ||
503 | } | ||
504 | if (readRegs->rootStatus) { | ||
505 | pcie_check_result(retVal, pciev0_read_rootStatus_reg (baseCfgRcRegs, readRegs->rootStatus)); | ||
506 | } | ||
507 | if (readRegs->devCap2) { | ||
508 | pcie_check_result(retVal, pciev0_read_devCap2_reg (baseCfgEpRegs, readRegs->devCap2)); | ||
509 | } | ||
510 | if (readRegs->devStatCtrl2) { | ||
511 | pcie_check_result(retVal, pciev0_read_devStatCtrl2_reg (baseCfgEpRegs, readRegs->devStatCtrl2)); | ||
512 | } | ||
513 | if (readRegs->linkCap2) { | ||
514 | /* Not supported on rev 0 */ | ||
515 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
516 | } | ||
517 | if (readRegs->linkCtrl2) { | ||
518 | pcie_check_result(retVal, pciev0_read_linkCtrl2_reg (baseCfgEpRegs, readRegs->linkCtrl2)); | ||
519 | } | ||
520 | |||
521 | |||
522 | /*Capabilities Extended Registers*/ | ||
523 | if (readRegs->extCap) { | ||
524 | pcie_check_result(retVal, pciev0_read_extCap_reg (baseCfgEpRegs, readRegs->extCap)); | ||
525 | } | ||
526 | if (readRegs->uncErr) { | ||
527 | pcie_check_result(retVal, pciev0_read_uncErr_reg (baseCfgEpRegs, readRegs->uncErr)); | ||
528 | } | ||
529 | if (readRegs->uncErrMask) { | ||
530 | pcie_check_result(retVal, pciev0_read_uncErrMask_reg (baseCfgEpRegs, readRegs->uncErrMask)); | ||
531 | } | ||
532 | if (readRegs->uncErrSvrty) { | ||
533 | pcie_check_result(retVal, pciev0_read_uncErrSvrty_reg (baseCfgEpRegs, readRegs->uncErrSvrty)); | ||
534 | } | ||
535 | if (readRegs->corErr) { | ||
536 | pcie_check_result(retVal, pciev0_read_corErr_reg (baseCfgEpRegs, readRegs->corErr)); | ||
537 | } | ||
538 | if (readRegs->corErrMask) { | ||
539 | pcie_check_result(retVal, pciev0_read_corErrMask_reg (baseCfgEpRegs, readRegs->corErrMask)); | ||
540 | } | ||
541 | if (readRegs->accr) { | ||
542 | pcie_check_result(retVal, pciev0_read_accr_reg (baseCfgEpRegs, readRegs->accr)); | ||
543 | } | ||
544 | for (i = 0; i < 4; i ++) { | ||
545 | if (readRegs->hdrLog[i]) { | ||
546 | pcie_check_result(retVal, pciev0_read_hdrLog_reg (baseCfgEpRegs, readRegs->hdrLog[i], i)); | ||
547 | } | ||
548 | } | ||
549 | if (readRegs->rootErrCmd) { | ||
550 | pcie_check_result(retVal, pciev0_read_rootErrCmd_reg (baseCfgEpRegs, readRegs->rootErrCmd)); | ||
551 | } | ||
552 | if (readRegs->rootErrSt) { | ||
553 | pcie_check_result(retVal, pciev0_read_rootErrSt_reg (baseCfgEpRegs, readRegs->rootErrSt)); | ||
554 | } | ||
555 | if (readRegs->errSrcID) { | ||
556 | pcie_check_result(retVal, pciev0_read_errSrcID_reg (baseCfgEpRegs, readRegs->errSrcID)); | ||
557 | } | ||
558 | |||
559 | /*Port Logic Registers*/ | ||
560 | if (readRegs->plAckTimer) { | ||
561 | pcie_check_result(retVal, pciev0_read_plAckTimer_reg (baseCfgEpRegs, readRegs->plAckTimer)); | ||
562 | } | ||
563 | if (readRegs->plOMsg) { | ||
564 | pcie_check_result(retVal, pciev0_read_plOMsg_reg (baseCfgEpRegs, readRegs->plOMsg)); | ||
565 | } | ||
566 | if (readRegs->plForceLink) { | ||
567 | pcie_check_result(retVal, pciev0_read_plForceLink_reg (baseCfgEpRegs, readRegs->plForceLink)); | ||
568 | } | ||
569 | if (readRegs->ackFreq) { | ||
570 | pcie_check_result(retVal, pciev0_read_ackFreq_reg (baseCfgEpRegs, readRegs->ackFreq)); | ||
571 | } | ||
572 | if (readRegs->lnkCtrl) { | ||
573 | pcie_check_result(retVal, pciev0_read_lnkCtrl_reg (baseCfgEpRegs, readRegs->lnkCtrl)); | ||
574 | } | ||
575 | if (readRegs->laneSkew) { | ||
576 | pcie_check_result(retVal, pciev0_read_laneSkew_reg (baseCfgEpRegs, readRegs->laneSkew)); | ||
577 | } | ||
578 | if (readRegs->symNum) { | ||
579 | pcie_check_result(retVal, pciev0_read_symNum_reg (baseCfgEpRegs, readRegs->symNum)); | ||
580 | } | ||
581 | if (readRegs->symTimerFltMask) { | ||
582 | pcie_check_result(retVal, pciev0_read_symTimerFltMask_reg (baseCfgEpRegs, readRegs->symTimerFltMask)); | ||
583 | } | ||
584 | if (readRegs->fltMask2) { | ||
585 | pcie_check_result(retVal, pciev0_read_fltMask2_reg (baseCfgEpRegs, readRegs->fltMask2)); | ||
586 | } | ||
587 | if (readRegs->debug0) { | ||
588 | pcie_check_result(retVal, pciev0_read_debug0_reg (baseCfgEpRegs, readRegs->debug0)); | ||
589 | } | ||
590 | if (readRegs->debug1) { | ||
591 | pcie_check_result(retVal, pciev0_read_debug1_reg (baseCfgEpRegs, readRegs->debug1)); | ||
592 | } | ||
593 | if (readRegs->gen2) { | ||
594 | pcie_check_result(retVal, pciev0_read_gen2_reg (baseCfgEpRegs, readRegs->gen2)); | ||
595 | } | ||
596 | |||
597 | /* Reject hw rev 1 PLCONF registers */ | ||
598 | if (readRegs->plconfObnpSubreqCtrl) { | ||
599 | /* Not supported on rev 0 */ | ||
600 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
601 | } | ||
602 | if (readRegs->plconfTrPStsR) { | ||
603 | /* Not supported on rev 0 */ | ||
604 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
605 | } | ||
606 | if (readRegs->plconfTrNpStsR) { | ||
607 | /* Not supported on rev 0 */ | ||
608 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
609 | } | ||
610 | if (readRegs->plconfTrCStsR) { | ||
611 | /* Not supported on rev 0 */ | ||
612 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
613 | } | ||
614 | if (readRegs->plconfQStsR) { | ||
615 | /* Not supported on rev 0 */ | ||
616 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
617 | } | ||
618 | if (readRegs->plconfVcTrAR1) { | ||
619 | /* Not supported on rev 0 */ | ||
620 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
621 | } | ||
622 | if (readRegs->plconfVcTrAR2) { | ||
623 | /* Not supported on rev 0 */ | ||
624 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
625 | } | ||
626 | if (readRegs->plconfVc0PrQC) { | ||
627 | /* Not supported on rev 0 */ | ||
628 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
629 | } | ||
630 | if (readRegs->plconfVc0NprQC) { | ||
631 | /* Not supported on rev 0 */ | ||
632 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
633 | } | ||
634 | if (readRegs->plconfVc0CrQC) { | ||
635 | /* Not supported on rev 0 */ | ||
636 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
637 | } | ||
638 | if (readRegs->plconfPhyStsR) { | ||
639 | /* Not supported on rev 0 */ | ||
640 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
641 | } | ||
642 | if (readRegs->plconfPhyCtrlR) { | ||
643 | /* Not supported on rev 0 */ | ||
644 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
645 | } | ||
646 | if (readRegs->plconfMsiCtrlAddress) { | ||
647 | /* Not supported on rev 0 */ | ||
648 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
649 | } | ||
650 | if (readRegs->plconfMsiCtrlUpperAddress) { | ||
651 | /* Not supported on rev 0 */ | ||
652 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
653 | } | ||
654 | for (i = 0; i < 8; i++) { | ||
655 | if (readRegs->plconfMsiCtrlIntEnable[i]) { | ||
656 | /* Not supported on rev 0 */ | ||
657 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
658 | } | ||
659 | if (readRegs->plconfMsiCtrlIntMask[i]) { | ||
660 | /* Not supported on rev 0 */ | ||
661 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
662 | } | 198 | } |
663 | if (readRegs->plconfMsiCtrlIntStatus[i]) { | 199 | else { |
664 | /* Not supported on rev 0 */ | 200 | baseAppRegs = cfg->cfgBase; |
665 | pcie_check_result(retVal, pcie_RET_INV_REG); | 201 | |
202 | /* Get base address for Local or Remote config space */ | ||
203 | if (location == pcie_LOCATION_LOCAL) | ||
204 | { | ||
205 | pcie_get_loc_cfg_base(baseAppRegs, baseCfgEpRegs, baseCfgRcRegs) | ||
206 | } | ||
207 | else | ||
208 | { | ||
209 | pcie_get_rem_cfg_base(baseAppRegs, baseCfgEpRegs, baseCfgRcRegs) | ||
210 | } | ||
211 | |||
212 | /***************************************************************************************** | ||
213 | *Application Registers | ||
214 | *****************************************************************************************/ | ||
215 | if ((retVal == pcie_RET_OK) && (readRegs->pid != NULL)) { | ||
216 | retVal = pciev0_read_pid_reg (baseAppRegs, readRegs->pid); | ||
217 | } | ||
218 | if ((retVal == pcie_RET_OK) && (readRegs->cmdStatus != NULL)) { | ||
219 | retVal = pciev0_read_cmdStatus_reg (baseAppRegs, readRegs->cmdStatus); | ||
220 | } | ||
221 | if ((retVal == pcie_RET_OK) && (readRegs->cfgTrans != NULL)) { | ||
222 | retVal = pciev0_read_cfgTrans_reg (baseAppRegs, readRegs->cfgTrans); | ||
223 | } | ||
224 | if ((retVal == pcie_RET_OK) && (readRegs->ioBase != NULL)) { | ||
225 | retVal = pciev0_read_ioBase_reg (baseAppRegs, readRegs->ioBase); | ||
226 | } | ||
227 | if ((retVal == pcie_RET_OK) && (readRegs->tlpCfg != NULL)) { | ||
228 | retVal = pciev0_read_tlpCfg_reg (baseAppRegs, readRegs->tlpCfg); | ||
229 | } | ||
230 | if ((retVal == pcie_RET_OK) && (readRegs->rstCmd != NULL)) { | ||
231 | retVal = pciev0_read_rstCmd_reg (baseAppRegs, readRegs->rstCmd); | ||
232 | } | ||
233 | if ((retVal == pcie_RET_OK) && (readRegs->pmCmd != NULL)) { | ||
234 | retVal = pciev0_read_pmCmd_reg (baseAppRegs, readRegs->pmCmd); | ||
235 | } | ||
236 | if ((retVal == pcie_RET_OK) && (readRegs->pmCfg != NULL)) { | ||
237 | retVal = pciev0_read_pmCfg_reg (baseAppRegs, readRegs->pmCfg); | ||
238 | } | ||
239 | if ((retVal == pcie_RET_OK) && (readRegs->actStatus != NULL)) { | ||
240 | retVal = pciev0_read_actStatus_reg (baseAppRegs, readRegs->actStatus); | ||
241 | } | ||
242 | if ((retVal == pcie_RET_OK) && (readRegs->obSize != NULL)) { | ||
243 | retVal = pciev0_read_obSize_reg (baseAppRegs, readRegs->obSize); | ||
244 | } | ||
245 | if ((retVal == pcie_RET_OK) && (readRegs->diagCtrl != NULL)) { | ||
246 | retVal = pciev0_read_diagCtrl_reg (baseAppRegs, readRegs->diagCtrl); | ||
247 | } | ||
248 | if ((retVal == pcie_RET_OK) && (readRegs->endian != NULL)) { | ||
249 | retVal = pciev0_read_endian_reg (baseAppRegs, readRegs->endian); | ||
250 | } | ||
251 | if ((retVal == pcie_RET_OK) && (readRegs->priority != NULL)) { | ||
252 | retVal = pciev0_read_priority_reg (baseAppRegs, readRegs->priority); | ||
253 | } | ||
254 | if ((retVal == pcie_RET_OK) && (readRegs->irqEOI != NULL)) { | ||
255 | retVal = pciev0_read_irqEOI_reg (baseAppRegs, readRegs->irqEOI); | ||
256 | } | ||
257 | if ((retVal == pcie_RET_OK) && (readRegs->msiIrq != NULL)) { | ||
258 | retVal = pciev0_read_msiIrq_reg (baseAppRegs, readRegs->msiIrq); | ||
259 | } | ||
260 | if ((retVal == pcie_RET_OK) && (readRegs->epIrqSet != NULL)) { | ||
261 | retVal = pciev0_read_epIrqSet_reg (baseAppRegs, readRegs->epIrqSet); | ||
262 | } | ||
263 | if ((retVal == pcie_RET_OK) && (readRegs->epIrqClr != NULL)) { | ||
264 | retVal = pciev0_read_epIrqClr_reg (baseAppRegs, readRegs->epIrqClr); | ||
265 | } | ||
266 | if ((retVal == pcie_RET_OK) && (readRegs->epIrqStatus != NULL)) { | ||
267 | retVal = pciev0_read_epIrqStatus_reg (baseAppRegs, readRegs->epIrqStatus); | ||
268 | } | ||
269 | for (i = 0; i < 4; i++) { | ||
270 | if ((retVal == pcie_RET_OK) && (readRegs->genPurpose[i] != NULL)) { | ||
271 | retVal = pciev0_read_genPurpose_reg (baseAppRegs, readRegs->genPurpose[i], i); | ||
272 | } | ||
273 | } | ||
274 | for (i = 0; i < 8; i++) { | ||
275 | if ((retVal == pcie_RET_OK) && (readRegs->msiIrqStatusRaw[i] != NULL)) { | ||
276 | retVal = pciev0_read_msiIrqStatusRaw_reg (baseAppRegs, readRegs->msiIrqStatusRaw[i], i); | ||
277 | } | ||
278 | if ((retVal == pcie_RET_OK) && (readRegs->msiIrqStatus[i] != NULL)) { | ||
279 | retVal = pciev0_read_msiIrqStatus_reg (baseAppRegs, readRegs->msiIrqStatus[i], i); | ||
280 | } | ||
281 | if ((retVal == pcie_RET_OK) && (readRegs->msiIrqEnableSet[i] != NULL)) { | ||
282 | retVal = pciev0_read_msiIrqEnableSet_reg (baseAppRegs, readRegs->msiIrqEnableSet[i], i); | ||
283 | } | ||
284 | if ((retVal == pcie_RET_OK) && (readRegs->msiIrqEnableClr[i] != NULL)) { | ||
285 | retVal = pciev0_read_msiIrqEnableClr_reg (baseAppRegs, readRegs->msiIrqEnableClr[i], i); | ||
286 | } | ||
287 | } | ||
288 | for (i = 0; i < 4; i++) { | ||
289 | if ((retVal == pcie_RET_OK) && (readRegs->legacyIrqStatusRaw[i] != NULL)) { | ||
290 | retVal = pciev0_read_legacyIrqStatusRaw_reg (baseAppRegs, readRegs->legacyIrqStatusRaw[i], i); | ||
291 | } | ||
292 | if ((retVal == pcie_RET_OK) && (readRegs->legacyIrqStatus[i] != NULL)) { | ||
293 | retVal = pciev0_read_legacyIrqStatus_reg (baseAppRegs, readRegs->legacyIrqStatus[i], i); | ||
294 | } | ||
295 | if ((retVal == pcie_RET_OK) && (readRegs->legacyIrqEnableSet[i] != NULL)) { | ||
296 | retVal = pciev0_read_legacyIrqEnableSet_reg (baseAppRegs, readRegs->legacyIrqEnableSet[i], i); | ||
297 | } | ||
298 | if ((retVal == pcie_RET_OK) && (readRegs->legacyIrqEnableClr[i] != NULL)) { | ||
299 | retVal = pciev0_read_legacyIrqEnableClr_reg (baseAppRegs, readRegs->legacyIrqEnableClr[i], i); | ||
300 | } | ||
301 | } | ||
302 | if ((retVal == pcie_RET_OK) && (readRegs->errIrqStatusRaw != NULL)) { | ||
303 | retVal = pciev0_read_errIrqStatusRaw_reg (baseAppRegs, readRegs->errIrqStatusRaw); | ||
304 | } | ||
305 | if ((retVal == pcie_RET_OK) && (readRegs->errIrqStatus != NULL)) { | ||
306 | retVal = pciev0_read_errIrqStatus_reg (baseAppRegs, readRegs->errIrqStatus); | ||
307 | } | ||
308 | if ((retVal == pcie_RET_OK) && (readRegs->errIrqEnableSet != NULL)) { | ||
309 | retVal = pciev0_read_errIrqEnableSet_reg (baseAppRegs, readRegs->errIrqEnableSet); | ||
310 | } | ||
311 | if ((retVal == pcie_RET_OK) && (readRegs->errIrqEnableClr != NULL)) { | ||
312 | retVal = pciev0_read_errIrqEnableClr_reg (baseAppRegs, readRegs->errIrqEnableClr); | ||
313 | } | ||
314 | |||
315 | if ((retVal == pcie_RET_OK) && (readRegs->pmRstIrqStatusRaw != NULL)) { | ||
316 | retVal = pciev0_read_pmRstIrqStatusRaw_reg (baseAppRegs, readRegs->pmRstIrqStatusRaw); | ||
317 | } | ||
318 | if ((retVal == pcie_RET_OK) && (readRegs->pmRstIrqStatus != NULL)) { | ||
319 | retVal = pciev0_read_pmRstIrqStatus_reg (baseAppRegs, readRegs->pmRstIrqStatus); | ||
320 | } | ||
321 | if ((retVal == pcie_RET_OK) && (readRegs->pmRstIrqEnableSet != NULL)) { | ||
322 | retVal = pciev0_read_pmRstIrqEnableSet_reg (baseAppRegs, readRegs->pmRstIrqEnableSet); | ||
323 | } | ||
324 | if ((retVal == pcie_RET_OK) && (readRegs->pmRstIrqEnableClr != NULL)) { | ||
325 | retVal = pciev0_read_pmRstIrqEnableClr_reg (baseAppRegs, readRegs->pmRstIrqEnableClr); | ||
326 | } | ||
327 | |||
328 | for (i = 0; i < 8; i ++) { | ||
329 | if ((retVal == pcie_RET_OK) && (readRegs->obOffsetLo[i] != NULL)) { | ||
330 | retVal = pciev0_read_obOffsetLo_reg (baseAppRegs, readRegs->obOffsetLo[i], i); | ||
331 | } | ||
332 | if ((retVal == pcie_RET_OK) && (readRegs->obOffsetHi[i] != NULL)) { | ||
333 | retVal = pciev0_read_obOffsetHi_reg (baseAppRegs, readRegs->obOffsetHi[i], i); | ||
334 | } | ||
335 | } | ||
336 | |||
337 | for (i = 0; i < 4; i ++) { | ||
338 | if ((retVal == pcie_RET_OK) && (readRegs->ibBar[i] != NULL)) { | ||
339 | retVal = pciev0_read_ibBar_reg (baseAppRegs, readRegs->ibBar[i], i); | ||
340 | } | ||
341 | if ((retVal == pcie_RET_OK) && (readRegs->ibStartLo[i] != NULL)) { | ||
342 | retVal = pciev0_read_ibStartLo_reg (baseAppRegs, readRegs->ibStartLo[i], i); | ||
343 | } | ||
344 | if ((retVal == pcie_RET_OK) && (readRegs->ibStartHi[i] != NULL)) { | ||
345 | retVal = pciev0_read_ibStartHi_reg (baseAppRegs, readRegs->ibStartHi[i], i); | ||
346 | } | ||
347 | if ((retVal == pcie_RET_OK) && (readRegs->ibOffset[i] != NULL)) { | ||
348 | retVal = pciev0_read_ibOffset_reg (baseAppRegs, readRegs->ibOffset[i], i); | ||
349 | } | ||
350 | } | ||
351 | |||
352 | if ((retVal == pcie_RET_OK) && (readRegs->pcsCfg0 != NULL)) { | ||
353 | retVal = pciev0_read_pcsCfg0_reg (baseAppRegs, readRegs->pcsCfg0); | ||
354 | } | ||
355 | if ((retVal == pcie_RET_OK) && (readRegs->pcsCfg1 != NULL)) { | ||
356 | retVal = pciev0_read_pcsCfg1_reg (baseAppRegs, readRegs->pcsCfg1); | ||
357 | } | ||
358 | if ((retVal == pcie_RET_OK) && (readRegs->pcsStatus != NULL)) { | ||
359 | retVal = pciev0_read_pcsStatus_reg (baseAppRegs, readRegs->pcsStatus); | ||
360 | } | ||
361 | |||
362 | if ((retVal == pcie_RET_OK) && (readRegs->serdesCfg0 != NULL)) { | ||
363 | retVal = pciev0_read_serdesCfg0_reg (baseAppRegs, readRegs->serdesCfg0); | ||
364 | } | ||
365 | if ((retVal == pcie_RET_OK) && (readRegs->serdesCfg1 != NULL)) { | ||
366 | retVal = pciev0_read_serdesCfg1_reg (baseAppRegs, readRegs->serdesCfg1); | ||
367 | } | ||
368 | |||
369 | /***************************************************************************************** | ||
370 | *Configuration Registers | ||
371 | *****************************************************************************************/ | ||
372 | |||
373 | /*Type 0, Type1 Common Registers*/ | ||
374 | |||
375 | if ((retVal == pcie_RET_OK) && (readRegs->vndDevId != NULL)) { | ||
376 | retVal = pciev0_read_vndDevId_reg (baseCfgEpRegs, readRegs->vndDevId); | ||
377 | } | ||
378 | if ((retVal == pcie_RET_OK) && (readRegs->statusCmd != NULL)) { | ||
379 | retVal = pciev0_read_statusCmd_reg (baseCfgEpRegs, readRegs->statusCmd); | ||
380 | } | ||
381 | if ((retVal == pcie_RET_OK) && (readRegs->revId != NULL)) { | ||
382 | retVal = pciev0_read_revId_reg (baseCfgEpRegs, readRegs->revId); | ||
383 | } | ||
384 | |||
385 | /*Type 0 Registers*/ | ||
386 | if ((retVal == pcie_RET_OK) && (readRegs->bist != NULL)) { | ||
387 | retVal = pciev0_read_bist_reg (baseCfgEpRegs, readRegs->bist); | ||
388 | } | ||
389 | if ((retVal == pcie_RET_OK) && (readRegs->type0BarIdx != NULL)) { | ||
390 | retVal = pciev0_read_type0Bar_reg (baseCfgEpRegs, &(readRegs->type0BarIdx->reg), | ||
391 | readRegs->type0BarIdx->idx); | ||
392 | } | ||
393 | if ((retVal == pcie_RET_OK) && (readRegs->type0Bar32bitIdx != NULL)) { | ||
394 | retVal = pciev0_read_type0Bar32bit_reg (baseCfgEpRegs, &(readRegs->type0Bar32bitIdx->reg), | ||
395 | readRegs->type0Bar32bitIdx->idx); | ||
396 | } | ||
397 | if ((retVal == pcie_RET_OK) && (readRegs->type0BarMask32bitIdx != NULL)) { | ||
398 | retVal = pciev0_read_type0Bar32bit_reg (baseCfgEpRegs, &(readRegs->type0BarMask32bitIdx->reg), | ||
399 | readRegs->type0BarMask32bitIdx->idx); | ||
400 | } | ||
401 | if ((retVal == pcie_RET_OK) && (readRegs->subId != NULL)) { | ||
402 | retVal = pciev0_read_subId_reg (baseCfgEpRegs, readRegs->subId); | ||
403 | } | ||
404 | if ((retVal == pcie_RET_OK) && (readRegs->cardbusCisPointer != NULL)) { | ||
405 | /* Not supported on rev 0 */ | ||
406 | retVal = pcie_RET_INV_REG; | ||
407 | } | ||
408 | if ((retVal == pcie_RET_OK) && (readRegs->expRom != NULL)) { | ||
409 | retVal = pciev0_read_expRom_reg (baseCfgEpRegs, readRegs->expRom); | ||
410 | } | ||
411 | if ((retVal == pcie_RET_OK) && (readRegs->capPtr != NULL)) { | ||
412 | retVal = pciev0_read_capPtr_reg (baseCfgEpRegs, readRegs->capPtr); | ||
413 | } | ||
414 | if ((retVal == pcie_RET_OK) && (readRegs->intPin != NULL)) { | ||
415 | retVal = pciev0_read_intPin_reg (baseCfgEpRegs, readRegs->intPin); | ||
416 | } | ||
417 | |||
418 | /*Type 1 Registers*/ | ||
419 | if ((retVal == pcie_RET_OK) && (readRegs->type1BistHeader != NULL)) { | ||
420 | retVal = pciev0_read_type1BistHeader_reg (baseCfgRcRegs, readRegs->type1BistHeader); | ||
421 | } | ||
422 | if ((retVal == pcie_RET_OK) && (readRegs->type1BarIdx != NULL)) { | ||
423 | retVal = pciev0_read_type1Bar_reg (baseCfgRcRegs, &(readRegs->type1BarIdx->reg), | ||
424 | readRegs->type1BarIdx->idx); | ||
425 | } | ||
426 | if ((retVal == pcie_RET_OK) && (readRegs->type1Bar32bitIdx != NULL)) { | ||
427 | retVal = pciev0_read_type1Bar32bit_reg (baseCfgRcRegs, &(readRegs->type1Bar32bitIdx->reg), | ||
428 | readRegs->type1Bar32bitIdx->idx); | ||
429 | } | ||
430 | if ((retVal == pcie_RET_OK) && (readRegs->type1BarMask32bitIdx != NULL)) { | ||
431 | retVal = pciev0_read_type1Bar32bit_reg (baseCfgRcRegs, &(readRegs->type1BarMask32bitIdx->reg), | ||
432 | readRegs->type1BarMask32bitIdx->idx); | ||
433 | } | ||
434 | if ((retVal == pcie_RET_OK) && (readRegs->type1BusNum != NULL)) { | ||
435 | retVal = pciev0_read_type1BusNum_reg (baseCfgRcRegs, readRegs->type1BusNum); | ||
436 | } | ||
437 | if ((retVal == pcie_RET_OK) && (readRegs->type1SecStat != NULL)) { | ||
438 | retVal = pciev0_read_type1SecStat_reg (baseCfgRcRegs, readRegs->type1SecStat); | ||
439 | } | ||
440 | if ((retVal == pcie_RET_OK) && (readRegs->type1Memspace != NULL)) { | ||
441 | retVal = pciev0_read_type1Memspace_reg (baseCfgRcRegs, readRegs->type1Memspace); | ||
442 | } | ||
443 | if ((retVal == pcie_RET_OK) && (readRegs->prefMem != NULL)) { | ||
444 | retVal = pciev0_read_prefMem_reg (baseCfgRcRegs, readRegs->prefMem); | ||
445 | } | ||
446 | if ((retVal == pcie_RET_OK) && (readRegs->prefBaseUpper != NULL)) { | ||
447 | retVal = pciev0_read_prefBaseUpper_reg (baseCfgRcRegs, readRegs->prefBaseUpper); | ||
448 | } | ||
449 | if ((retVal == pcie_RET_OK) && (readRegs->prefLimitUpper != NULL)) { | ||
450 | retVal = pciev0_read_prefLimitUpper_reg (baseCfgRcRegs, readRegs->prefLimitUpper); | ||
451 | } | ||
452 | if ((retVal == pcie_RET_OK) && (readRegs->type1IOSpace != NULL)) { | ||
453 | retVal = pciev0_read_type1IOSpace_reg (baseCfgRcRegs, readRegs->type1IOSpace); | ||
454 | } | ||
455 | if ((retVal == pcie_RET_OK) && (readRegs->type1CapPtr != NULL)) { | ||
456 | retVal = pciev0_read_type1CapPtr_reg (baseCfgRcRegs, readRegs->type1CapPtr); | ||
457 | } | ||
458 | if ((retVal == pcie_RET_OK) && (readRegs->type1ExpnsnRom != NULL)) { | ||
459 | retVal = pciev0_read_type1ExpnsnRom_reg (baseCfgRcRegs, readRegs->type1ExpnsnRom); | ||
460 | } | ||
461 | if ((retVal == pcie_RET_OK) && (readRegs->type1BridgeInt != NULL)) { | ||
462 | retVal = pciev0_read_type1BridgeInt_reg (baseCfgRcRegs, readRegs->type1BridgeInt); | ||
463 | } | ||
464 | |||
465 | /* Power Management Capabilities Registers */ | ||
466 | if ((retVal == pcie_RET_OK) && (readRegs->pmCap != NULL)) { | ||
467 | retVal = pciev0_read_pmCap_reg (baseCfgEpRegs, readRegs->pmCap); | ||
468 | } | ||
469 | if ((retVal == pcie_RET_OK) && (readRegs->pmCapCtlStat != NULL)) { | ||
470 | retVal = pciev0_read_pmCapCtlStat_reg (baseCfgEpRegs, readRegs->pmCapCtlStat); | ||
471 | } | ||
472 | |||
473 | /*MSI Registers*/ | ||
474 | if ((retVal == pcie_RET_OK) && (readRegs->msiCap != NULL)) { | ||
475 | retVal = pciev0_read_msiCap_reg (baseCfgEpRegs, readRegs->msiCap); | ||
476 | } | ||
477 | if ((retVal == pcie_RET_OK) && (readRegs->msiLo32 != NULL)) { | ||
478 | retVal = pciev0_read_msiLo32_reg (baseCfgEpRegs, readRegs->msiLo32); | ||
479 | } | ||
480 | if ((retVal == pcie_RET_OK) && (readRegs->msiUp32 != NULL)) { | ||
481 | retVal = pciev0_read_msiUp32_reg (baseCfgEpRegs, readRegs->msiUp32); | ||
482 | } | ||
483 | if ((retVal == pcie_RET_OK) && (readRegs->msiData != NULL)) { | ||
484 | retVal = pciev0_read_msiData_reg (baseCfgEpRegs, readRegs->msiData); | ||
485 | } | ||
486 | |||
487 | /*Capabilities Registers*/ | ||
488 | if ((retVal == pcie_RET_OK) && (readRegs->pciesCap != NULL)) { | ||
489 | retVal = pciev0_read_pciesCap_reg (baseCfgEpRegs, readRegs->pciesCap); | ||
490 | } | ||
491 | if ((retVal == pcie_RET_OK) && (readRegs->deviceCap != NULL)) { | ||
492 | retVal = pciev0_read_deviceCap_reg (baseCfgEpRegs, readRegs->deviceCap); | ||
493 | } | ||
494 | if ((retVal == pcie_RET_OK) && (readRegs->devStatCtrl != NULL)) { | ||
495 | retVal = pciev0_read_devStatCtrl_reg (baseCfgEpRegs, readRegs->devStatCtrl); | ||
496 | } | ||
497 | if ((retVal == pcie_RET_OK) && (readRegs->linkCap != NULL)) { | ||
498 | retVal = pciev0_read_linkCap_reg (baseCfgEpRegs, readRegs->linkCap); | ||
499 | } | ||
500 | if ((retVal == pcie_RET_OK) && (readRegs->linkStatCtrl != NULL)) { | ||
501 | retVal = pciev0_read_linkStatCtrl_reg (baseCfgEpRegs, readRegs->linkStatCtrl); | ||
502 | } | ||
503 | if ((retVal == pcie_RET_OK) && (readRegs->slotCap != NULL)) { | ||
504 | retVal = pciev0_read_slotCap_reg (baseCfgRcRegs, readRegs->slotCap); | ||
505 | } | ||
506 | if ((retVal == pcie_RET_OK) && (readRegs->slotStatCtrl != NULL)) { | ||
507 | retVal = pciev0_read_slotStatCtrl_reg (baseCfgRcRegs, readRegs->slotStatCtrl); | ||
508 | } | ||
509 | if ((retVal == pcie_RET_OK) && (readRegs->rootCtrlCap != NULL)) { | ||
510 | retVal = pciev0_read_rootCtrlCap_reg (baseCfgRcRegs, readRegs->rootCtrlCap); | ||
511 | } | ||
512 | if ((retVal == pcie_RET_OK) && (readRegs->rootStatus != NULL)) { | ||
513 | retVal = pciev0_read_rootStatus_reg (baseCfgRcRegs, readRegs->rootStatus); | ||
514 | } | ||
515 | if ((retVal == pcie_RET_OK) && (readRegs->devCap2 != NULL)) { | ||
516 | retVal = pciev0_read_devCap2_reg (baseCfgEpRegs, readRegs->devCap2); | ||
517 | } | ||
518 | if ((retVal == pcie_RET_OK) && (readRegs->devStatCtrl2 != NULL)) { | ||
519 | retVal = pciev0_read_devStatCtrl2_reg (baseCfgEpRegs, readRegs->devStatCtrl2); | ||
520 | } | ||
521 | if ((retVal == pcie_RET_OK) && (readRegs->linkCap2 != NULL)) { | ||
522 | /* Not supported on rev 0 */ | ||
523 | retVal = pcie_RET_INV_REG; | ||
524 | } | ||
525 | if ((retVal == pcie_RET_OK) && (readRegs->linkCtrl2 != NULL)) { | ||
526 | retVal = pciev0_read_linkCtrl2_reg (baseCfgEpRegs, readRegs->linkCtrl2); | ||
527 | } | ||
528 | |||
529 | |||
530 | /*Capabilities Extended Registers*/ | ||
531 | if ((retVal == pcie_RET_OK) && (readRegs->extCap != NULL)) { | ||
532 | retVal = pciev0_read_extCap_reg (baseCfgEpRegs, readRegs->extCap); | ||
533 | } | ||
534 | if ((retVal == pcie_RET_OK) && (readRegs->uncErr != NULL)) { | ||
535 | retVal = pciev0_read_uncErr_reg (baseCfgEpRegs, readRegs->uncErr); | ||
536 | } | ||
537 | if ((retVal == pcie_RET_OK) && (readRegs->uncErrMask != NULL)) { | ||
538 | retVal = pciev0_read_uncErrMask_reg (baseCfgEpRegs, readRegs->uncErrMask); | ||
539 | } | ||
540 | if ((retVal == pcie_RET_OK) && (readRegs->uncErrSvrty != NULL)) { | ||
541 | retVal = pciev0_read_uncErrSvrty_reg (baseCfgEpRegs, readRegs->uncErrSvrty); | ||
542 | } | ||
543 | if ((retVal == pcie_RET_OK) && (readRegs->corErr != NULL)) { | ||
544 | retVal = pciev0_read_corErr_reg (baseCfgEpRegs, readRegs->corErr); | ||
545 | } | ||
546 | if ((retVal == pcie_RET_OK) && (readRegs->corErrMask != NULL)) { | ||
547 | retVal = pciev0_read_corErrMask_reg (baseCfgEpRegs, readRegs->corErrMask); | ||
548 | } | ||
549 | if ((retVal == pcie_RET_OK) && (readRegs->accr != NULL)) { | ||
550 | retVal = pciev0_read_accr_reg (baseCfgEpRegs, readRegs->accr); | ||
551 | } | ||
552 | for (i = 0; i < 4; i ++) { | ||
553 | if ((retVal == pcie_RET_OK) && (readRegs->hdrLog[i] != NULL)) { | ||
554 | retVal = pciev0_read_hdrLog_reg (baseCfgEpRegs, readRegs->hdrLog[i], i); | ||
555 | } | ||
556 | } | ||
557 | if ((retVal == pcie_RET_OK) && (readRegs->rootErrCmd != NULL)) { | ||
558 | retVal = pciev0_read_rootErrCmd_reg (baseCfgEpRegs, readRegs->rootErrCmd); | ||
559 | } | ||
560 | if ((retVal == pcie_RET_OK) && (readRegs->rootErrSt != NULL)) { | ||
561 | retVal = pciev0_read_rootErrSt_reg (baseCfgEpRegs, readRegs->rootErrSt); | ||
562 | } | ||
563 | if ((retVal == pcie_RET_OK) && (readRegs->errSrcID != NULL)) { | ||
564 | retVal = pciev0_read_errSrcID_reg (baseCfgEpRegs, readRegs->errSrcID); | ||
565 | } | ||
566 | |||
567 | /*Port Logic Registers*/ | ||
568 | if ((retVal == pcie_RET_OK) && (readRegs->plAckTimer != NULL)) { | ||
569 | retVal = pciev0_read_plAckTimer_reg (baseCfgEpRegs, readRegs->plAckTimer); | ||
570 | } | ||
571 | if ((retVal == pcie_RET_OK) && (readRegs->plOMsg != NULL)) { | ||
572 | retVal = pciev0_read_plOMsg_reg (baseCfgEpRegs, readRegs->plOMsg); | ||
573 | } | ||
574 | if ((retVal == pcie_RET_OK) && (readRegs->plForceLink != NULL)) { | ||
575 | retVal = pciev0_read_plForceLink_reg (baseCfgEpRegs, readRegs->plForceLink); | ||
576 | } | ||
577 | if ((retVal == pcie_RET_OK) && (readRegs->ackFreq != NULL)) { | ||
578 | retVal = pciev0_read_ackFreq_reg (baseCfgEpRegs, readRegs->ackFreq); | ||
579 | } | ||
580 | if ((retVal == pcie_RET_OK) && (readRegs->lnkCtrl != NULL)) { | ||
581 | retVal = pciev0_read_lnkCtrl_reg (baseCfgEpRegs, readRegs->lnkCtrl); | ||
582 | } | ||
583 | if ((retVal == pcie_RET_OK) && (readRegs->laneSkew != NULL)) { | ||
584 | retVal = pciev0_read_laneSkew_reg (baseCfgEpRegs, readRegs->laneSkew); | ||
585 | } | ||
586 | if ((retVal == pcie_RET_OK) && (readRegs->symNum != NULL)) { | ||
587 | retVal = pciev0_read_symNum_reg (baseCfgEpRegs, readRegs->symNum); | ||
588 | } | ||
589 | if ((retVal == pcie_RET_OK) && (readRegs->symTimerFltMask != NULL)) { | ||
590 | retVal = pciev0_read_symTimerFltMask_reg (baseCfgEpRegs, readRegs->symTimerFltMask); | ||
591 | } | ||
592 | if ((retVal == pcie_RET_OK) && (readRegs->fltMask2 != NULL)) { | ||
593 | retVal = pciev0_read_fltMask2_reg (baseCfgEpRegs, readRegs->fltMask2); | ||
594 | } | ||
595 | if ((retVal == pcie_RET_OK) && (readRegs->debug0 != NULL)) { | ||
596 | retVal = pciev0_read_debug0_reg (baseCfgEpRegs, readRegs->debug0); | ||
597 | } | ||
598 | if ((retVal == pcie_RET_OK) && (readRegs->debug1 != NULL)) { | ||
599 | retVal = pciev0_read_debug1_reg (baseCfgEpRegs, readRegs->debug1); | ||
600 | } | ||
601 | if ((retVal == pcie_RET_OK) && (readRegs->gen2 != NULL)) { | ||
602 | retVal = pciev0_read_gen2_reg (baseCfgEpRegs, readRegs->gen2); | ||
603 | } | ||
604 | |||
605 | /* Reject hw rev 1 PLCONF registers */ | ||
606 | if ((retVal == pcie_RET_OK) && (readRegs->plconfObnpSubreqCtrl != NULL)) { | ||
607 | /* Not supported on rev 0 */ | ||
608 | retVal = pcie_RET_INV_REG; | ||
609 | } | ||
610 | if ((retVal == pcie_RET_OK) && (readRegs->plconfTrPStsR != NULL)) { | ||
611 | /* Not supported on rev 0 */ | ||
612 | retVal = pcie_RET_INV_REG; | ||
613 | } | ||
614 | if ((retVal == pcie_RET_OK) && (readRegs->plconfTrNpStsR != NULL)) { | ||
615 | /* Not supported on rev 0 */ | ||
616 | retVal = pcie_RET_INV_REG; | ||
617 | } | ||
618 | if ((retVal == pcie_RET_OK) && (readRegs->plconfTrCStsR != NULL)) { | ||
619 | /* Not supported on rev 0 */ | ||
620 | retVal = pcie_RET_INV_REG; | ||
621 | } | ||
622 | if ((retVal == pcie_RET_OK) && (readRegs->plconfQStsR != NULL)) { | ||
623 | /* Not supported on rev 0 */ | ||
624 | retVal = pcie_RET_INV_REG; | ||
625 | } | ||
626 | if ((retVal == pcie_RET_OK) && (readRegs->plconfVcTrAR1 != NULL)) { | ||
627 | /* Not supported on rev 0 */ | ||
628 | retVal = pcie_RET_INV_REG; | ||
629 | } | ||
630 | if ((retVal == pcie_RET_OK) && (readRegs->plconfVcTrAR2 != NULL)) { | ||
631 | /* Not supported on rev 0 */ | ||
632 | retVal = pcie_RET_INV_REG; | ||
633 | } | ||
634 | if ((retVal == pcie_RET_OK) && (readRegs->plconfVc0PrQC != NULL)) { | ||
635 | /* Not supported on rev 0 */ | ||
636 | retVal = pcie_RET_INV_REG; | ||
637 | } | ||
638 | if ((retVal == pcie_RET_OK) && (readRegs->plconfVc0NprQC != NULL)) { | ||
639 | /* Not supported on rev 0 */ | ||
640 | retVal = pcie_RET_INV_REG; | ||
641 | } | ||
642 | if ((retVal == pcie_RET_OK) && (readRegs->plconfVc0CrQC != NULL)) { | ||
643 | /* Not supported on rev 0 */ | ||
644 | retVal = pcie_RET_INV_REG; | ||
645 | } | ||
646 | if ((retVal == pcie_RET_OK) && (readRegs->plconfPhyStsR != NULL)) { | ||
647 | /* Not supported on rev 0 */ | ||
648 | retVal = pcie_RET_INV_REG; | ||
649 | } | ||
650 | if ((retVal == pcie_RET_OK) && (readRegs->plconfPhyCtrlR != NULL)) { | ||
651 | /* Not supported on rev 0 */ | ||
652 | retVal = pcie_RET_INV_REG; | ||
653 | } | ||
654 | if ((retVal == pcie_RET_OK) && (readRegs->plconfMsiCtrlAddress != NULL)) { | ||
655 | /* Not supported on rev 0 */ | ||
656 | retVal = pcie_RET_INV_REG; | ||
657 | } | ||
658 | if ((retVal == pcie_RET_OK) && (readRegs->plconfMsiCtrlUpperAddress != NULL)) { | ||
659 | /* Not supported on rev 0 */ | ||
660 | retVal = pcie_RET_INV_REG; | ||
661 | } | ||
662 | for (i = 0; i < 8; i++) { | ||
663 | if ((retVal == pcie_RET_OK) && (readRegs->plconfMsiCtrlIntEnable[i] != NULL)) { | ||
664 | /* Not supported on rev 0 */ | ||
665 | retVal = pcie_RET_INV_REG; | ||
666 | } | ||
667 | if ((retVal == pcie_RET_OK) && (readRegs->plconfMsiCtrlIntMask[i] != NULL)) { | ||
668 | /* Not supported on rev 0 */ | ||
669 | retVal = pcie_RET_INV_REG; | ||
670 | } | ||
671 | if ((retVal == pcie_RET_OK) && (readRegs->plconfMsiCtrlIntStatus[i] != NULL)) { | ||
672 | /* Not supported on rev 0 */ | ||
673 | retVal = pcie_RET_INV_REG; | ||
674 | } | ||
675 | } | ||
676 | if ((retVal == pcie_RET_OK) && (readRegs->plconfMsiCtrlGpio != NULL)) { | ||
677 | /* Not supported on rev 0 */ | ||
678 | retVal = pcie_RET_INV_REG; | ||
679 | } | ||
680 | if ((retVal == pcie_RET_OK) && (readRegs->plconfPipeLoopback != NULL)) { | ||
681 | /* Not supported on rev 0 */ | ||
682 | retVal = pcie_RET_INV_REG; | ||
683 | } | ||
684 | if ((retVal == pcie_RET_OK) && (readRegs->plconfDbiRoWrEn != NULL)) { | ||
685 | /* Not supported on rev 0 */ | ||
686 | retVal = pcie_RET_INV_REG; | ||
687 | } | ||
688 | if ((retVal == pcie_RET_OK) && (readRegs->plconfAxiSlvErrResp != NULL)) { | ||
689 | /* Not supported on rev 0 */ | ||
690 | retVal = pcie_RET_INV_REG; | ||
691 | } | ||
692 | if ((retVal == pcie_RET_OK) && (readRegs->plconfAxiSlvTimeout != NULL)) { | ||
693 | /* Not supported on rev 0 */ | ||
694 | retVal = pcie_RET_INV_REG; | ||
695 | } | ||
696 | if ((retVal == pcie_RET_OK) && (readRegs->plconfIatuIndex != NULL)) { | ||
697 | /* Not supported on rev 0 */ | ||
698 | retVal = pcie_RET_INV_REG; | ||
699 | } | ||
700 | if ((retVal == pcie_RET_OK) && (readRegs->plconfIatuRegCtrl1 != NULL)) { | ||
701 | /* Not supported on rev 0 */ | ||
702 | retVal = pcie_RET_INV_REG; | ||
703 | } | ||
704 | if ((retVal == pcie_RET_OK) && (readRegs->plconfIatuRegCtrl2 != NULL)) { | ||
705 | /* Not supported on rev 0 */ | ||
706 | retVal = pcie_RET_INV_REG; | ||
707 | } | ||
708 | if ((retVal == pcie_RET_OK) && (readRegs->plconfIatuRegLowerBase != NULL)) { | ||
709 | /* Not supported on rev 0 */ | ||
710 | retVal = pcie_RET_INV_REG; | ||
711 | } | ||
712 | if ((retVal == pcie_RET_OK) && (readRegs->plconfIatuRegUpperBase != NULL)) { | ||
713 | /* Not supported on rev 0 */ | ||
714 | retVal = pcie_RET_INV_REG; | ||
715 | } | ||
716 | if ((retVal == pcie_RET_OK) && (readRegs->plconfIatuRegLimit != NULL)) { | ||
717 | /* Not supported on rev 0 */ | ||
718 | retVal = pcie_RET_INV_REG; | ||
719 | } | ||
720 | if ((retVal == pcie_RET_OK) && (readRegs->plconfIatuRegLowerTarget != NULL)) { | ||
721 | /* Not supported on rev 0 */ | ||
722 | retVal = pcie_RET_INV_REG; | ||
723 | } | ||
724 | if ((retVal == pcie_RET_OK) && (readRegs->plconfIatuRegUpperTarget != NULL)) { | ||
725 | /* Not supported on rev 0 */ | ||
726 | retVal = pcie_RET_INV_REG; | ||
727 | } | ||
728 | if ((retVal == pcie_RET_OK) && (readRegs->plconfIatuRegCtrl3 != NULL)) { | ||
729 | /* Not supported on rev 0 */ | ||
730 | retVal = pcie_RET_INV_REG; | ||
731 | } | ||
732 | |||
733 | |||
734 | /* reject hw rev 1 TI CONF registers */ | ||
735 | if ((retVal == pcie_RET_OK) && (readRegs->tiConfRevision != NULL)) { | ||
736 | /* Not supported on rev 0 */ | ||
737 | retVal = pcie_RET_INV_REG; | ||
738 | } | ||
739 | if ((retVal == pcie_RET_OK) && (readRegs->tiConfSysConfig != NULL)) { | ||
740 | /* Not supported on rev 0 */ | ||
741 | retVal = pcie_RET_INV_REG; | ||
742 | } | ||
743 | if ((retVal == pcie_RET_OK) && (readRegs->tiConfIrqEoi != NULL)) { | ||
744 | /* Not supported on rev 0 */ | ||
745 | retVal = pcie_RET_INV_REG; | ||
746 | } | ||
747 | if ((retVal == pcie_RET_OK) && (readRegs->tiConfIrqStatusRawMain != NULL)) { | ||
748 | /* Not supported on rev 0 */ | ||
749 | retVal = pcie_RET_INV_REG; | ||
750 | } | ||
751 | if ((retVal == pcie_RET_OK) && (readRegs->tiConfIrqStatusMain != NULL)) { | ||
752 | /* Not supported on rev 0 */ | ||
753 | retVal = pcie_RET_INV_REG; | ||
754 | } | ||
755 | if ((retVal == pcie_RET_OK) && (readRegs->tiConfIrqEnableSetMain != NULL)) { | ||
756 | /* Not supported on rev 0 */ | ||
757 | retVal = pcie_RET_INV_REG; | ||
758 | } | ||
759 | if ((retVal == pcie_RET_OK) && (readRegs->tiConfIrqEnableClrMain != NULL)) { | ||
760 | /* Not supported on rev 0 */ | ||
761 | retVal = pcie_RET_INV_REG; | ||
762 | } | ||
763 | if ((retVal == pcie_RET_OK) && (readRegs->tiConfIrqStatusRawMsi != NULL)) { | ||
764 | /* Not supported on rev 0 */ | ||
765 | retVal = pcie_RET_INV_REG; | ||
766 | } | ||
767 | if ((retVal == pcie_RET_OK) && (readRegs->tiConfIrqStatusMsi != NULL)) { | ||
768 | /* Not supported on rev 0 */ | ||
769 | retVal = pcie_RET_INV_REG; | ||
770 | } | ||
771 | if ((retVal == pcie_RET_OK) && (readRegs->tiConfIrqEnableSetMsi != NULL)) { | ||
772 | /* Not supported on rev 0 */ | ||
773 | retVal = pcie_RET_INV_REG; | ||
774 | } | ||
775 | if ((retVal == pcie_RET_OK) && (readRegs->tiConfIrqEnableClrMsi != NULL)) { | ||
776 | /* Not supported on rev 0 */ | ||
777 | retVal = pcie_RET_INV_REG; | ||
778 | } | ||
779 | if ((retVal == pcie_RET_OK) && (readRegs->tiConfDeviceType != NULL)) { | ||
780 | /* Not supported on rev 0 */ | ||
781 | retVal = pcie_RET_INV_REG; | ||
782 | } | ||
783 | if ((retVal == pcie_RET_OK) && (readRegs->tiConfDeviceCmd != NULL)) { | ||
784 | /* Not supported on rev 0 */ | ||
785 | retVal = pcie_RET_INV_REG; | ||
786 | } | ||
787 | if ((retVal == pcie_RET_OK) && (readRegs->tiConfPmCtrl != NULL)) { | ||
788 | /* Not supported on rev 0 */ | ||
789 | retVal = pcie_RET_INV_REG; | ||
790 | } | ||
791 | if ((retVal == pcie_RET_OK) && (readRegs->tiConfPhyCs != NULL)) { | ||
792 | /* Not supported on rev 0 */ | ||
793 | retVal = pcie_RET_INV_REG; | ||
794 | } | ||
795 | if ((retVal == pcie_RET_OK) && (readRegs->tiConfIntxAssert != NULL)) { | ||
796 | /* Not supported on rev 0 */ | ||
797 | retVal = pcie_RET_INV_REG; | ||
798 | } | ||
799 | if ((retVal == pcie_RET_OK) && (readRegs->tiConfIntxDeassert != NULL)) { | ||
800 | /* Not supported on rev 0 */ | ||
801 | retVal = pcie_RET_INV_REG; | ||
802 | } | ||
803 | if ((retVal == pcie_RET_OK) && (readRegs->tiConfMsiXmt != NULL)) { | ||
804 | /* Not supported on rev 0 */ | ||
805 | retVal = pcie_RET_INV_REG; | ||
806 | } | ||
807 | if ((retVal == pcie_RET_OK) && (readRegs->tiConfDebugCfg != NULL)) { | ||
808 | /* Not supported on rev 0 */ | ||
809 | retVal = pcie_RET_INV_REG; | ||
810 | } | ||
811 | if ((retVal == pcie_RET_OK) && (readRegs->tiConfDebugData != NULL)) { | ||
812 | /* Not supported on rev 0 */ | ||
813 | retVal = pcie_RET_INV_REG; | ||
814 | } | ||
815 | if ((retVal == pcie_RET_OK) && (readRegs->tiConfDiagCtrl != NULL)) { | ||
816 | /* Not supported on rev 0 */ | ||
817 | retVal = pcie_RET_INV_REG; | ||
818 | } | ||
666 | } | 819 | } |
667 | } | 820 | } |
668 | if (readRegs->plconfMsiCtrlGpio) { | ||
669 | /* Not supported on rev 0 */ | ||
670 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
671 | } | ||
672 | if (readRegs->plconfPipeLoopback) { | ||
673 | /* Not supported on rev 0 */ | ||
674 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
675 | } | ||
676 | if (readRegs->plconfDbiRoWrEn) { | ||
677 | /* Not supported on rev 0 */ | ||
678 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
679 | } | ||
680 | if (readRegs->plconfAxiSlvErrResp) { | ||
681 | /* Not supported on rev 0 */ | ||
682 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
683 | } | ||
684 | if (readRegs->plconfAxiSlvTimeout) { | ||
685 | /* Not supported on rev 0 */ | ||
686 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
687 | } | ||
688 | if (readRegs->plconfIatuIndex) { | ||
689 | /* Not supported on rev 0 */ | ||
690 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
691 | } | ||
692 | if (readRegs->plconfIatuRegCtrl1) { | ||
693 | /* Not supported on rev 0 */ | ||
694 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
695 | } | ||
696 | if (readRegs->plconfIatuRegCtrl2) { | ||
697 | /* Not supported on rev 0 */ | ||
698 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
699 | } | ||
700 | if (readRegs->plconfIatuRegLowerBase) { | ||
701 | /* Not supported on rev 0 */ | ||
702 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
703 | } | ||
704 | if (readRegs->plconfIatuRegUpperBase) { | ||
705 | /* Not supported on rev 0 */ | ||
706 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
707 | } | ||
708 | if (readRegs->plconfIatuRegLimit) { | ||
709 | /* Not supported on rev 0 */ | ||
710 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
711 | } | ||
712 | if (readRegs->plconfIatuRegLowerTarget) { | ||
713 | /* Not supported on rev 0 */ | ||
714 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
715 | } | ||
716 | if (readRegs->plconfIatuRegUpperTarget) { | ||
717 | /* Not supported on rev 0 */ | ||
718 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
719 | } | ||
720 | if (readRegs->plconfIatuRegCtrl3) { | ||
721 | /* Not supported on rev 0 */ | ||
722 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
723 | } | ||
724 | |||
725 | |||
726 | /* reject hw rev 1 TI CONF registers */ | ||
727 | if (readRegs->tiConfRevision) { | ||
728 | /* Not supported on rev 0 */ | ||
729 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
730 | } | ||
731 | if (readRegs->tiConfSysConfig) { | ||
732 | /* Not supported on rev 0 */ | ||
733 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
734 | } | ||
735 | if (readRegs->tiConfIrqEoi) { | ||
736 | /* Not supported on rev 0 */ | ||
737 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
738 | } | ||
739 | if (readRegs->tiConfIrqStatusRawMain) { | ||
740 | /* Not supported on rev 0 */ | ||
741 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
742 | } | ||
743 | if (readRegs->tiConfIrqStatusMain) { | ||
744 | /* Not supported on rev 0 */ | ||
745 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
746 | } | ||
747 | if (readRegs->tiConfIrqEnableSetMain) { | ||
748 | /* Not supported on rev 0 */ | ||
749 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
750 | } | ||
751 | if (readRegs->tiConfIrqEnableClrMain) { | ||
752 | /* Not supported on rev 0 */ | ||
753 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
754 | } | ||
755 | if (readRegs->tiConfIrqStatusRawMsi) { | ||
756 | /* Not supported on rev 0 */ | ||
757 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
758 | } | ||
759 | if (readRegs->tiConfIrqStatusMsi) { | ||
760 | /* Not supported on rev 0 */ | ||
761 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
762 | } | ||
763 | if (readRegs->tiConfIrqEnableSetMsi) { | ||
764 | /* Not supported on rev 0 */ | ||
765 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
766 | } | ||
767 | if (readRegs->tiConfIrqEnableClrMsi) { | ||
768 | /* Not supported on rev 0 */ | ||
769 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
770 | } | ||
771 | if (readRegs->tiConfDeviceType) { | ||
772 | /* Not supported on rev 0 */ | ||
773 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
774 | } | ||
775 | if (readRegs->tiConfDeviceCmd) { | ||
776 | /* Not supported on rev 0 */ | ||
777 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
778 | } | ||
779 | if (readRegs->tiConfPmCtrl) { | ||
780 | /* Not supported on rev 0 */ | ||
781 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
782 | } | ||
783 | if (readRegs->tiConfPhyCs) { | ||
784 | /* Not supported on rev 0 */ | ||
785 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
786 | } | ||
787 | if (readRegs->tiConfIntxAssert) { | ||
788 | /* Not supported on rev 0 */ | ||
789 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
790 | } | ||
791 | if (readRegs->tiConfIntxDeassert) { | ||
792 | /* Not supported on rev 0 */ | ||
793 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
794 | } | ||
795 | if (readRegs->tiConfMsiXmt) { | ||
796 | /* Not supported on rev 0 */ | ||
797 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
798 | } | ||
799 | if (readRegs->tiConfDebugCfg) { | ||
800 | /* Not supported on rev 0 */ | ||
801 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
802 | } | ||
803 | if (readRegs->tiConfDebugData) { | ||
804 | /* Not supported on rev 0 */ | ||
805 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
806 | } | ||
807 | if (readRegs->tiConfDiagCtrl) { | ||
808 | /* Not supported on rev 0 */ | ||
809 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
810 | } | ||
811 | 821 | ||
812 | return retVal; | 822 | return retVal; |
813 | } /* Pciev0_readRegs */ | 823 | } /* Pciev0_readRegs */ |
@@ -836,604 +846,607 @@ pcieRet_e Pciev0_writeRegs | |||
836 | int32_t i; | 846 | int32_t i; |
837 | 847 | ||
838 | if (pcieLObjIsValid == 0) { | 848 | if (pcieLObjIsValid == 0) { |
839 | return pcie_RET_NO_INIT; | 849 | retVal = pcie_RET_NO_INIT; |
840 | } | ||
841 | |||
842 | pcie_check_handle(handle); | ||
843 | |||
844 | baseAppRegs = cfg->cfgBase; | ||
845 | |||
846 | /* Get base address for Local or Remote config space */ | ||
847 | if (location == pcie_LOCATION_LOCAL) | ||
848 | { | ||
849 | pcie_get_loc_cfg_base(baseAppRegs, baseCfgEpRegs, baseCfgRcRegs) | ||
850 | } | ||
851 | else | ||
852 | { | ||
853 | pcie_get_rem_cfg_base(baseAppRegs, baseCfgEpRegs, baseCfgRcRegs) | ||
854 | } | ||
855 | |||
856 | /***************************************************************************************** | ||
857 | *Application Registers | ||
858 | *****************************************************************************************/ | ||
859 | if (writeRegs->cmdStatus) { | ||
860 | pcie_check_result(retVal, pciev0_write_cmdStatus_reg (baseAppRegs, writeRegs->cmdStatus)); | ||
861 | } | ||
862 | if (writeRegs->cfgTrans) { | ||
863 | pcie_check_result(retVal, pciev0_write_cfgTrans_reg (baseAppRegs, writeRegs->cfgTrans)); | ||
864 | } | ||
865 | if (writeRegs->ioBase) { | ||
866 | pcie_check_result(retVal, pciev0_write_ioBase_reg (baseAppRegs, writeRegs->ioBase)); | ||
867 | } | ||
868 | if (writeRegs->tlpCfg) { | ||
869 | pcie_check_result(retVal, pciev0_write_tlpCfg_reg (baseAppRegs, writeRegs->tlpCfg)); | ||
870 | } | 850 | } |
871 | if (writeRegs->rstCmd) { | 851 | else { |
872 | pcie_check_result(retVal, pciev0_write_rstCmd_reg (baseAppRegs, writeRegs->rstCmd)); | 852 | if (pcie_check_handle_fcn(handle) == 0) { |
873 | } | 853 | retVal = pcie_RET_INV_HANDLE; |
874 | if (writeRegs->pmCmd) { | ||
875 | pcie_check_result(retVal, pciev0_write_pmCmd_reg (baseAppRegs, writeRegs->pmCmd)); | ||
876 | } | ||
877 | if (writeRegs->pmCfg) { | ||
878 | pcie_check_result(retVal, pciev0_write_pmCfg_reg (baseAppRegs, writeRegs->pmCfg)); | ||
879 | } | ||
880 | if (writeRegs->obSize) { | ||
881 | pcie_check_result(retVal, pciev0_write_obSize_reg (baseAppRegs, writeRegs->obSize)); | ||
882 | } | ||
883 | if (writeRegs->diagCtrl) { | ||
884 | pcie_check_result(retVal, pciev0_write_diagCtrl_reg (baseAppRegs, writeRegs->diagCtrl)); | ||
885 | } | ||
886 | if (writeRegs->endian) { | ||
887 | pcie_check_result(retVal, pciev0_write_endian_reg (baseAppRegs, writeRegs->endian)); | ||
888 | } | ||
889 | if (writeRegs->priority) { | ||
890 | pcie_check_result(retVal, pciev0_write_priority_reg (baseAppRegs, writeRegs->priority)); | ||
891 | } | ||
892 | if (writeRegs->irqEOI) { | ||
893 | pcie_check_result(retVal, pciev0_write_irqEOI_reg (baseAppRegs, writeRegs->irqEOI)); | ||
894 | } | ||
895 | if (writeRegs->msiIrq) { | ||
896 | pcie_check_result(retVal, pciev0_write_msiIrq_reg (baseAppRegs, writeRegs->msiIrq)); | ||
897 | } | ||
898 | if (writeRegs->epIrqSet) { | ||
899 | pcie_check_result(retVal, pciev0_write_epIrqSet_reg (baseAppRegs, writeRegs->epIrqSet)); | ||
900 | } | ||
901 | if (writeRegs->epIrqClr) { | ||
902 | pcie_check_result(retVal, pciev0_write_epIrqClr_reg (baseAppRegs, writeRegs->epIrqClr)); | ||
903 | } | ||
904 | if (writeRegs->epIrqStatus) { | ||
905 | pcie_check_result(retVal, pciev0_write_epIrqStatus_reg (baseAppRegs, writeRegs->epIrqStatus)); | ||
906 | } | ||
907 | for (i = 0; i < 4; i++) { | ||
908 | if (writeRegs->genPurpose[i]) { | ||
909 | pcie_check_result(retVal, pciev0_write_genPurpose_reg (baseAppRegs, writeRegs->genPurpose[i], i)); | ||
910 | } | ||
911 | } | ||
912 | for (i = 0; i < 8; i++) { | ||
913 | if (writeRegs->msiIrqStatusRaw[i]) { | ||
914 | pcie_check_result(retVal, pciev0_write_msiIrqStatusRaw_reg (baseAppRegs, writeRegs->msiIrqStatusRaw[i], i)); | ||
915 | } | ||
916 | if (writeRegs->msiIrqStatus[i]) { | ||
917 | pcie_check_result(retVal, pciev0_write_msiIrqStatus_reg (baseAppRegs, writeRegs->msiIrqStatus[i], i)); | ||
918 | } | ||
919 | if (writeRegs->msiIrqEnableSet[i]) { | ||
920 | pcie_check_result(retVal, pciev0_write_msiIrqEnableSet_reg (baseAppRegs, writeRegs->msiIrqEnableSet[i], i)); | ||
921 | } | ||
922 | if (writeRegs->msiIrqEnableClr[i]) { | ||
923 | pcie_check_result(retVal, pciev0_write_msiIrqEnableClr_reg (baseAppRegs, writeRegs->msiIrqEnableClr[i], i)); | ||
924 | } | ||
925 | } | ||
926 | for (i = 0; i < 4; i++) { | ||
927 | if (writeRegs->legacyIrqStatusRaw[i]) { | ||
928 | pcie_check_result(retVal, pciev0_write_legacyIrqStatusRaw_reg (baseAppRegs, writeRegs->legacyIrqStatusRaw[i], i)); | ||
929 | } | ||
930 | if (writeRegs->legacyIrqStatus[i]) { | ||
931 | pcie_check_result(retVal, pciev0_write_legacyIrqStatus_reg (baseAppRegs, writeRegs->legacyIrqStatus[i], i)); | ||
932 | } | ||
933 | if (writeRegs->legacyIrqEnableSet[i]) { | ||
934 | pcie_check_result(retVal, pciev0_write_legacyIrqEnableSet_reg (baseAppRegs, writeRegs->legacyIrqEnableSet[i], i)); | ||
935 | } | ||
936 | if (writeRegs->legacyIrqEnableClr[i]) { | ||
937 | pcie_check_result(retVal, pciev0_write_legacyIrqEnableClr_reg (baseAppRegs, writeRegs->legacyIrqEnableClr[i], i)); | ||
938 | } | ||
939 | } | ||
940 | if (writeRegs->errIrqStatusRaw) { | ||
941 | pcie_check_result(retVal, pciev0_write_errIrqStatusRaw_reg (baseAppRegs, writeRegs->errIrqStatusRaw)); | ||
942 | } | ||
943 | if (writeRegs->errIrqStatus) { | ||
944 | pcie_check_result(retVal, pciev0_write_errIrqStatus_reg (baseAppRegs, writeRegs->errIrqStatus)); | ||
945 | } | ||
946 | if (writeRegs->errIrqEnableSet) { | ||
947 | pcie_check_result(retVal, pciev0_write_errIrqEnableSet_reg (baseAppRegs, writeRegs->errIrqEnableSet)); | ||
948 | } | ||
949 | if (writeRegs->errIrqEnableClr) { | ||
950 | pcie_check_result(retVal, pciev0_write_errIrqEnableClr_reg (baseAppRegs, writeRegs->errIrqEnableClr)); | ||
951 | } | ||
952 | |||
953 | if (writeRegs->pmRstIrqStatusRaw) { | ||
954 | pcie_check_result(retVal, pciev0_write_pmRstIrqStatusRaw_reg (baseAppRegs, writeRegs->pmRstIrqStatusRaw)); | ||
955 | } | ||
956 | if (writeRegs->pmRstIrqStatus) { | ||
957 | pcie_check_result(retVal, pciev0_write_pmRstIrqStatus_reg (baseAppRegs, writeRegs->pmRstIrqStatus)); | ||
958 | } | ||
959 | if (writeRegs->pmRstIrqEnableSet) { | ||
960 | pcie_check_result(retVal, pciev0_write_pmRstIrqEnableSet_reg (baseAppRegs, writeRegs->pmRstIrqEnableSet)); | ||
961 | } | ||
962 | if (writeRegs->pmRstIrqEnableClr) { | ||
963 | pcie_check_result(retVal, pciev0_write_pmRstIrqEnableClr_reg (baseAppRegs, writeRegs->pmRstIrqEnableClr)); | ||
964 | } | ||
965 | |||
966 | for (i = 0; i < 8; i ++) { | ||
967 | if (writeRegs->obOffsetLo[i]) { | ||
968 | pcie_check_result(retVal, pciev0_write_obOffsetLo_reg (baseAppRegs, writeRegs->obOffsetLo[i], i)); | ||
969 | } | ||
970 | if (writeRegs->obOffsetHi[i]) { | ||
971 | pcie_check_result(retVal, pciev0_write_obOffsetHi_reg (baseAppRegs, writeRegs->obOffsetHi[i], i)); | ||
972 | } | ||
973 | } | ||
974 | |||
975 | for (i = 0; i < 4; i ++) { | ||
976 | if (writeRegs->ibBar[i]) { | ||
977 | pcie_check_result(retVal, pciev0_write_ibBar_reg (baseAppRegs, writeRegs->ibBar[i], i)); | ||
978 | } | ||
979 | if (writeRegs->ibStartLo[i]) { | ||
980 | pcie_check_result(retVal, pciev0_write_ibStartLo_reg (baseAppRegs, writeRegs->ibStartLo[i], i)); | ||
981 | } | ||
982 | if (writeRegs->ibStartHi[i]) { | ||
983 | pcie_check_result(retVal, pciev0_write_ibStartHi_reg (baseAppRegs, writeRegs->ibStartHi[i], i)); | ||
984 | } | ||
985 | if (writeRegs->ibOffset[i]) { | ||
986 | pcie_check_result(retVal, pciev0_write_ibOffset_reg (baseAppRegs, writeRegs->ibOffset[i], i)); | ||
987 | } | ||
988 | } | ||
989 | |||
990 | if (writeRegs->pcsCfg0) { | ||
991 | pcie_check_result(retVal, pciev0_write_pcsCfg0_reg (baseAppRegs, writeRegs->pcsCfg0)); | ||
992 | } | ||
993 | if (writeRegs->pcsCfg1) { | ||
994 | pcie_check_result(retVal, pciev0_write_pcsCfg1_reg (baseAppRegs, writeRegs->pcsCfg1)); | ||
995 | } | ||
996 | |||
997 | if (writeRegs->serdesCfg0) { | ||
998 | pcie_check_result(retVal, pciev0_write_serdesCfg0_reg (baseAppRegs, writeRegs->serdesCfg0)); | ||
999 | } | ||
1000 | if (writeRegs->serdesCfg1) { | ||
1001 | pcie_check_result(retVal, pciev0_write_serdesCfg1_reg (baseAppRegs, writeRegs->serdesCfg1)); | ||
1002 | } | ||
1003 | |||
1004 | /***************************************************************************************** | ||
1005 | *Configuration Registers | ||
1006 | *****************************************************************************************/ | ||
1007 | |||
1008 | /*Type 0, Type1 Common Registers*/ | ||
1009 | |||
1010 | if (writeRegs->vndDevId) { | ||
1011 | pcie_check_result(retVal, pciev0_write_vndDevId_reg (baseCfgEpRegs, writeRegs->vndDevId)); | ||
1012 | } | ||
1013 | if (writeRegs->statusCmd) { | ||
1014 | pcie_check_result(retVal, pciev0_write_statusCmd_reg (baseCfgEpRegs, writeRegs->statusCmd)); | ||
1015 | } | ||
1016 | if (writeRegs->revId) { | ||
1017 | pcie_check_result(retVal, pciev0_write_revId_reg (baseCfgEpRegs, writeRegs->revId)); | ||
1018 | } | ||
1019 | |||
1020 | /*Type 0 Registers*/ | ||
1021 | if (writeRegs->bist) { | ||
1022 | pcie_check_result(retVal, pciev0_write_bist_reg (baseCfgEpRegs, writeRegs->bist)); | ||
1023 | } | ||
1024 | if (writeRegs->type0BarIdx) { | ||
1025 | pcie_check_result(retVal, pciev0_write_type0Bar_reg (baseCfgEpRegs, &(writeRegs->type0BarIdx->reg), | ||
1026 | writeRegs->type0BarIdx->idx)); | ||
1027 | } | ||
1028 | if (writeRegs->type0Bar32bitIdx) { | ||
1029 | pcie_check_result(retVal, pciev0_write_type0Bar32bit_reg (baseCfgEpRegs, &(writeRegs->type0Bar32bitIdx->reg), | ||
1030 | writeRegs->type0Bar32bitIdx->idx)); | ||
1031 | } | ||
1032 | if (writeRegs->type0BarMask32bitIdx) { | ||
1033 | pcie_check_result(retVal, pciev0_write_type0Bar32bit_reg (baseCfgEpRegs, &(writeRegs->type0BarMask32bitIdx->reg), | ||
1034 | writeRegs->type0BarMask32bitIdx->idx)); | ||
1035 | } | ||
1036 | if (writeRegs->subId) { | ||
1037 | pcie_check_result(retVal, pciev0_write_subId_reg (baseCfgEpRegs, writeRegs->subId)); | ||
1038 | } | ||
1039 | if (writeRegs->cardbusCisPointer) { | ||
1040 | /* Not supported on rev 0 */ | ||
1041 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
1042 | } | ||
1043 | if (writeRegs->expRom) { | ||
1044 | pcie_check_result(retVal, pciev0_write_expRom_reg (baseCfgEpRegs, writeRegs->expRom)); | ||
1045 | } | ||
1046 | if (writeRegs->capPtr) { | ||
1047 | pcie_check_result(retVal, pciev0_write_capPtr_reg (baseCfgEpRegs, writeRegs->capPtr)); | ||
1048 | } | ||
1049 | if (writeRegs->intPin) { | ||
1050 | pcie_check_result(retVal, pciev0_write_intPin_reg (baseCfgEpRegs, writeRegs->intPin)); | ||
1051 | } | ||
1052 | |||
1053 | /*Type 1 Registers*/ | ||
1054 | if (writeRegs->type1BistHeader) { | ||
1055 | pcie_check_result(retVal, pciev0_write_type1BistHeader_reg (baseCfgRcRegs, writeRegs->type1BistHeader)); | ||
1056 | } | ||
1057 | if (writeRegs->type1BarIdx) { | ||
1058 | pcie_check_result(retVal, pciev0_write_type1Bar_reg (baseCfgRcRegs, &(writeRegs->type1BarIdx->reg), | ||
1059 | writeRegs->type1BarIdx->idx)); | ||
1060 | } | ||
1061 | if (writeRegs->type1Bar32bitIdx) { | ||
1062 | pcie_check_result(retVal, pciev0_write_type1Bar32bit_reg (baseCfgRcRegs, &(writeRegs->type1Bar32bitIdx->reg), | ||
1063 | writeRegs->type1Bar32bitIdx->idx)); | ||
1064 | } | ||
1065 | if (writeRegs->type1BarMask32bitIdx) { | ||
1066 | pcie_check_result(retVal, pciev0_write_type1Bar32bit_reg (baseCfgRcRegs, &(writeRegs->type1BarMask32bitIdx->reg), | ||
1067 | writeRegs->type1BarMask32bitIdx->idx)); | ||
1068 | } | ||
1069 | if (writeRegs->type1BusNum) { | ||
1070 | pcie_check_result(retVal, pciev0_write_type1BusNum_reg (baseCfgRcRegs, writeRegs->type1BusNum)); | ||
1071 | } | ||
1072 | if (writeRegs->type1SecStat) { | ||
1073 | pcie_check_result(retVal, pciev0_write_type1SecStat_reg (baseCfgRcRegs, writeRegs->type1SecStat)); | ||
1074 | } | ||
1075 | if (writeRegs->type1Memspace) { | ||
1076 | pcie_check_result(retVal, pciev0_write_type1Memspace_reg (baseCfgRcRegs, writeRegs->type1Memspace)); | ||
1077 | } | ||
1078 | if (writeRegs->prefMem) { | ||
1079 | pcie_check_result(retVal, pciev0_write_prefMem_reg (baseCfgRcRegs, writeRegs->prefMem)); | ||
1080 | } | ||
1081 | if (writeRegs->prefBaseUpper) { | ||
1082 | pcie_check_result(retVal, pciev0_write_prefBaseUpper_reg (baseCfgRcRegs, writeRegs->prefBaseUpper)); | ||
1083 | } | ||
1084 | if (writeRegs->prefLimitUpper) { | ||
1085 | pcie_check_result(retVal, pciev0_write_prefLimitUpper_reg (baseCfgRcRegs, writeRegs->prefLimitUpper)); | ||
1086 | } | ||
1087 | if (writeRegs->type1IOSpace) { | ||
1088 | pcie_check_result(retVal, pciev0_write_type1IOSpace_reg (baseCfgRcRegs, writeRegs->type1IOSpace)); | ||
1089 | } | ||
1090 | if (writeRegs->type1CapPtr) { | ||
1091 | pcie_check_result(retVal, pciev0_write_type1CapPtr_reg (baseCfgRcRegs, writeRegs->type1CapPtr)); | ||
1092 | } | ||
1093 | if (writeRegs->type1ExpnsnRom) { | ||
1094 | pcie_check_result(retVal, pciev0_write_type1ExpnsnRom_reg (baseCfgRcRegs, writeRegs->type1ExpnsnRom)); | ||
1095 | } | ||
1096 | if (writeRegs->type1BridgeInt) { | ||
1097 | pcie_check_result(retVal, pciev0_write_type1BridgeInt_reg (baseCfgRcRegs, writeRegs->type1BridgeInt)); | ||
1098 | } | ||
1099 | |||
1100 | /* Power Management Capabilities Registers */ | ||
1101 | if (writeRegs->pmCap) { | ||
1102 | pcie_check_result(retVal, pciev0_write_pmCap_reg (baseCfgEpRegs, writeRegs->pmCap)); | ||
1103 | } | ||
1104 | if (writeRegs->pmCapCtlStat) { | ||
1105 | pcie_check_result(retVal, pciev0_write_pmCapCtlStat_reg (baseCfgEpRegs, writeRegs->pmCapCtlStat)); | ||
1106 | } | ||
1107 | |||
1108 | /*MSI Registers*/ | ||
1109 | if (writeRegs->msiCap) { | ||
1110 | pcie_check_result(retVal, pciev0_write_msiCap_reg (baseCfgEpRegs, writeRegs->msiCap)); | ||
1111 | } | ||
1112 | if (writeRegs->msiLo32) { | ||
1113 | pcie_check_result(retVal, pciev0_write_msiLo32_reg (baseCfgEpRegs, writeRegs->msiLo32)); | ||
1114 | } | ||
1115 | if (writeRegs->msiUp32) { | ||
1116 | pcie_check_result(retVal, pciev0_write_msiUp32_reg (baseCfgEpRegs, writeRegs->msiUp32)); | ||
1117 | } | ||
1118 | if (writeRegs->msiData) { | ||
1119 | pcie_check_result(retVal, pciev0_write_msiData_reg (baseCfgEpRegs, writeRegs->msiData)); | ||
1120 | } | ||
1121 | |||
1122 | /*Capabilities Registers*/ | ||
1123 | if (writeRegs->pciesCap) { | ||
1124 | pcie_check_result(retVal, pciev0_write_pciesCap_reg (baseCfgEpRegs, writeRegs->pciesCap)); | ||
1125 | } | ||
1126 | if (writeRegs->deviceCap) { | ||
1127 | pcie_check_result(retVal, pciev0_write_deviceCap_reg (baseCfgEpRegs, writeRegs->deviceCap)); | ||
1128 | } | ||
1129 | |||
1130 | if (writeRegs->devStatCtrl) { | ||
1131 | pcie_check_result(retVal, pciev0_write_devStatCtrl_reg (baseCfgEpRegs, writeRegs->devStatCtrl)); | ||
1132 | } | ||
1133 | if (writeRegs->linkCap) { | ||
1134 | pcie_check_result(retVal, pciev0_write_linkCap_reg (baseCfgEpRegs, writeRegs->linkCap)); | ||
1135 | } | ||
1136 | if (writeRegs->linkStatCtrl) { | ||
1137 | pcie_check_result(retVal, pciev0_write_linkStatCtrl_reg (baseCfgEpRegs, writeRegs->linkStatCtrl)); | ||
1138 | } | ||
1139 | if (writeRegs->slotCap) { | ||
1140 | pcie_check_result(retVal, pciev0_write_slotCap_reg (baseCfgRcRegs, writeRegs->slotCap)); | ||
1141 | } | ||
1142 | if (writeRegs->slotStatCtrl) { | ||
1143 | pcie_check_result(retVal, pciev0_write_slotStatCtrl_reg (baseCfgRcRegs, writeRegs->slotStatCtrl)); | ||
1144 | } | ||
1145 | if (writeRegs->rootCtrlCap) { | ||
1146 | pcie_check_result(retVal, pciev0_write_rootCtrlCap_reg (baseCfgRcRegs, writeRegs->rootCtrlCap)); | ||
1147 | } | ||
1148 | if (writeRegs->rootStatus) { | ||
1149 | pcie_check_result(retVal, pciev0_write_rootStatus_reg (baseCfgRcRegs, writeRegs->rootStatus)); | ||
1150 | } | ||
1151 | if (writeRegs->devCap2) { | ||
1152 | pcie_check_result(retVal, pciev0_write_devCap2_reg (baseCfgEpRegs, writeRegs->devCap2)); | ||
1153 | } | ||
1154 | if (writeRegs->devStatCtrl2) { | ||
1155 | pcie_check_result(retVal, pciev0_write_devStatCtrl2_reg (baseCfgEpRegs, writeRegs->devStatCtrl2)); | ||
1156 | } | ||
1157 | if (writeRegs->linkCap2) { | ||
1158 | /* Not supported on rev 0 */ | ||
1159 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
1160 | } | ||
1161 | if (writeRegs->linkCtrl2) { | ||
1162 | pcie_check_result(retVal, pciev0_write_linkCtrl2_reg (baseCfgEpRegs, writeRegs->linkCtrl2)); | ||
1163 | } | ||
1164 | |||
1165 | /*Capabilities Extended Registers*/ | ||
1166 | if (writeRegs->uncErr) { | ||
1167 | pcie_check_result(retVal, pciev0_write_uncErr_reg (baseCfgEpRegs, writeRegs->uncErr)); | ||
1168 | } | ||
1169 | if (writeRegs->uncErrMask) { | ||
1170 | pcie_check_result(retVal, pciev0_write_uncErrMask_reg (baseCfgEpRegs, writeRegs->uncErrMask)); | ||
1171 | } | ||
1172 | if (writeRegs->uncErrSvrty) { | ||
1173 | pcie_check_result(retVal, pciev0_write_uncErrSvrty_reg (baseCfgEpRegs, writeRegs->uncErrSvrty)); | ||
1174 | } | ||
1175 | if (writeRegs->corErr) { | ||
1176 | pcie_check_result(retVal, pciev0_write_corErr_reg (baseCfgEpRegs, writeRegs->corErr)); | ||
1177 | } | ||
1178 | if (writeRegs->corErrMask) { | ||
1179 | pcie_check_result(retVal, pciev0_write_corErrMask_reg (baseCfgEpRegs, writeRegs->corErrMask)); | ||
1180 | } | ||
1181 | if (writeRegs->accr) { | ||
1182 | pcie_check_result(retVal, pciev0_write_accr_reg (baseCfgEpRegs, writeRegs->accr)); | ||
1183 | } | ||
1184 | if (writeRegs->rootErrCmd) { | ||
1185 | pcie_check_result(retVal, pciev0_write_rootErrCmd_reg (baseCfgEpRegs, writeRegs->rootErrCmd)); | ||
1186 | } | ||
1187 | if (writeRegs->rootErrSt) { | ||
1188 | pcie_check_result(retVal, pciev0_write_rootErrSt_reg (baseCfgEpRegs, writeRegs->rootErrSt)); | ||
1189 | } | ||
1190 | |||
1191 | /*Port Logic Registers*/ | ||
1192 | if (writeRegs->plAckTimer) { | ||
1193 | pcie_check_result(retVal, pciev0_write_plAckTimer_reg (baseCfgEpRegs, writeRegs->plAckTimer)); | ||
1194 | } | ||
1195 | if (writeRegs->plOMsg) { | ||
1196 | pcie_check_result(retVal, pciev0_write_plOMsg_reg (baseCfgEpRegs, writeRegs->plOMsg)); | ||
1197 | } | ||
1198 | if (writeRegs->plForceLink) { | ||
1199 | pcie_check_result(retVal, pciev0_write_plForceLink_reg (baseCfgEpRegs, writeRegs->plForceLink)); | ||
1200 | } | ||
1201 | if (writeRegs->ackFreq) { | ||
1202 | pcie_check_result(retVal, pciev0_write_ackFreq_reg (baseCfgEpRegs, writeRegs->ackFreq)); | ||
1203 | } | ||
1204 | if (writeRegs->lnkCtrl) { | ||
1205 | pcie_check_result(retVal, pciev0_write_lnkCtrl_reg (baseCfgEpRegs, writeRegs->lnkCtrl)); | ||
1206 | } | ||
1207 | if (writeRegs->laneSkew) { | ||
1208 | pcie_check_result(retVal, pciev0_write_laneSkew_reg (baseCfgEpRegs, writeRegs->laneSkew)); | ||
1209 | } | ||
1210 | if (writeRegs->symNum) { | ||
1211 | pcie_check_result(retVal, pciev0_write_symNum_reg (baseCfgEpRegs, writeRegs->symNum)); | ||
1212 | } | ||
1213 | if (writeRegs->symTimerFltMask) { | ||
1214 | pcie_check_result(retVal, pciev0_write_symTimerFltMask_reg (baseCfgEpRegs, writeRegs->symTimerFltMask)); | ||
1215 | } | ||
1216 | if (writeRegs->fltMask2) { | ||
1217 | pcie_check_result(retVal, pciev0_write_fltMask2_reg (baseCfgEpRegs, writeRegs->fltMask2)); | ||
1218 | } | ||
1219 | if (writeRegs->gen2) { | ||
1220 | pcie_check_result(retVal, pciev0_write_gen2_reg (baseCfgEpRegs, writeRegs->gen2)); | ||
1221 | } | ||
1222 | |||
1223 | /* Reject hw rev 1 PL CONF registers */ | ||
1224 | if (writeRegs->plconfObnpSubreqCtrl) { | ||
1225 | /* Not supported on rev 0 */ | ||
1226 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
1227 | } | ||
1228 | if (writeRegs->plconfTrPStsR) { | ||
1229 | /* Not supported on rev 0 */ | ||
1230 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
1231 | } | ||
1232 | if (writeRegs->plconfTrNpStsR) { | ||
1233 | /* Not supported on rev 0 */ | ||
1234 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
1235 | } | ||
1236 | if (writeRegs->plconfTrCStsR) { | ||
1237 | /* Not supported on rev 0 */ | ||
1238 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
1239 | } | ||
1240 | if (writeRegs->plconfQStsR) { | ||
1241 | /* Not supported on rev 0 */ | ||
1242 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
1243 | } | ||
1244 | if (writeRegs->plconfVcTrAR1) { | ||
1245 | /* Not supported on rev 0 */ | ||
1246 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
1247 | } | ||
1248 | if (writeRegs->plconfVcTrAR2) { | ||
1249 | /* Not supported on rev 0 */ | ||
1250 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
1251 | } | ||
1252 | if (writeRegs->plconfVc0PrQC) { | ||
1253 | /* Not supported on rev 0 */ | ||
1254 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
1255 | } | ||
1256 | if (writeRegs->plconfVc0NprQC) { | ||
1257 | /* Not supported on rev 0 */ | ||
1258 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
1259 | } | ||
1260 | if (writeRegs->plconfVc0CrQC) { | ||
1261 | /* Not supported on rev 0 */ | ||
1262 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
1263 | } | ||
1264 | if (writeRegs->plconfPhyStsR) { | ||
1265 | /* Not supported on rev 0 */ | ||
1266 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
1267 | } | ||
1268 | if (writeRegs->plconfPhyCtrlR) { | ||
1269 | /* Not supported on rev 0 */ | ||
1270 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
1271 | } | ||
1272 | if (writeRegs->plconfMsiCtrlAddress) { | ||
1273 | /* Not supported on rev 0 */ | ||
1274 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
1275 | } | ||
1276 | if (writeRegs->plconfMsiCtrlUpperAddress) { | ||
1277 | /* Not supported on rev 0 */ | ||
1278 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
1279 | } | ||
1280 | for (i = 0; i < 8; i++) { | ||
1281 | if (writeRegs->plconfMsiCtrlIntEnable[i]) { | ||
1282 | /* Not supported on rev 0 */ | ||
1283 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
1284 | } | ||
1285 | if (writeRegs->plconfMsiCtrlIntMask[i]) { | ||
1286 | /* Not supported on rev 0 */ | ||
1287 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
1288 | } | 854 | } |
1289 | if (writeRegs->plconfMsiCtrlIntStatus[i]) { | 855 | else { |
1290 | /* Not supported on rev 0 */ | 856 | baseAppRegs = cfg->cfgBase; |
1291 | pcie_check_result(retVal, pcie_RET_INV_REG); | 857 | |
858 | /* Get base address for Local or Remote config space */ | ||
859 | if (location == pcie_LOCATION_LOCAL) | ||
860 | { | ||
861 | pcie_get_loc_cfg_base(baseAppRegs, baseCfgEpRegs, baseCfgRcRegs) | ||
862 | } | ||
863 | else | ||
864 | { | ||
865 | pcie_get_rem_cfg_base(baseAppRegs, baseCfgEpRegs, baseCfgRcRegs) | ||
866 | } | ||
867 | /***************************************************************************************** | ||
868 | *Application Registers | ||
869 | *****************************************************************************************/ | ||
870 | if ((retVal == pcie_RET_OK) && (writeRegs->cmdStatus != NULL)) { | ||
871 | retVal = pciev0_write_cmdStatus_reg (baseAppRegs, writeRegs->cmdStatus); | ||
872 | } | ||
873 | if ((retVal == pcie_RET_OK) && (writeRegs->cfgTrans != NULL)) { | ||
874 | retVal = pciev0_write_cfgTrans_reg (baseAppRegs, writeRegs->cfgTrans); | ||
875 | } | ||
876 | if ((retVal == pcie_RET_OK) && (writeRegs->ioBase != NULL)) { | ||
877 | retVal = pciev0_write_ioBase_reg (baseAppRegs, writeRegs->ioBase); | ||
878 | } | ||
879 | if ((retVal == pcie_RET_OK) && (writeRegs->tlpCfg != NULL)) { | ||
880 | retVal = pciev0_write_tlpCfg_reg (baseAppRegs, writeRegs->tlpCfg); | ||
881 | } | ||
882 | if ((retVal == pcie_RET_OK) && (writeRegs->rstCmd != NULL)) { | ||
883 | retVal = pciev0_write_rstCmd_reg (baseAppRegs, writeRegs->rstCmd); | ||
884 | } | ||
885 | if ((retVal == pcie_RET_OK) && (writeRegs->pmCmd != NULL)) { | ||
886 | retVal = pciev0_write_pmCmd_reg (baseAppRegs, writeRegs->pmCmd); | ||
887 | } | ||
888 | if ((retVal == pcie_RET_OK) && (writeRegs->pmCfg != NULL)) { | ||
889 | retVal = pciev0_write_pmCfg_reg (baseAppRegs, writeRegs->pmCfg); | ||
890 | } | ||
891 | if ((retVal == pcie_RET_OK) && (writeRegs->obSize != NULL)) { | ||
892 | retVal = pciev0_write_obSize_reg (baseAppRegs, writeRegs->obSize); | ||
893 | } | ||
894 | if ((retVal == pcie_RET_OK) && (writeRegs->diagCtrl != NULL)) { | ||
895 | retVal = pciev0_write_diagCtrl_reg (baseAppRegs, writeRegs->diagCtrl); | ||
896 | } | ||
897 | if ((retVal == pcie_RET_OK) && (writeRegs->endian != NULL)) { | ||
898 | retVal = pciev0_write_endian_reg (baseAppRegs, writeRegs->endian); | ||
899 | } | ||
900 | if ((retVal == pcie_RET_OK) && (writeRegs->priority != NULL)) { | ||
901 | retVal = pciev0_write_priority_reg (baseAppRegs, writeRegs->priority); | ||
902 | } | ||
903 | if ((retVal == pcie_RET_OK) && (writeRegs->irqEOI != NULL)) { | ||
904 | retVal = pciev0_write_irqEOI_reg (baseAppRegs, writeRegs->irqEOI); | ||
905 | } | ||
906 | if ((retVal == pcie_RET_OK) && (writeRegs->msiIrq != NULL)) { | ||
907 | retVal = pciev0_write_msiIrq_reg (baseAppRegs, writeRegs->msiIrq); | ||
908 | } | ||
909 | if ((retVal == pcie_RET_OK) && (writeRegs->epIrqSet != NULL)) { | ||
910 | retVal = pciev0_write_epIrqSet_reg (baseAppRegs, writeRegs->epIrqSet); | ||
911 | } | ||
912 | if ((retVal == pcie_RET_OK) && (writeRegs->epIrqClr != NULL)) { | ||
913 | retVal = pciev0_write_epIrqClr_reg (baseAppRegs, writeRegs->epIrqClr); | ||
914 | } | ||
915 | if ((retVal == pcie_RET_OK) && (writeRegs->epIrqStatus != NULL)) { | ||
916 | retVal = pciev0_write_epIrqStatus_reg (baseAppRegs, writeRegs->epIrqStatus); | ||
917 | } | ||
918 | for (i = 0; i < 4; i++) { | ||
919 | if ((retVal == pcie_RET_OK) && (writeRegs->genPurpose[i] != NULL)) { | ||
920 | retVal = pciev0_write_genPurpose_reg (baseAppRegs, writeRegs->genPurpose[i], i); | ||
921 | } | ||
922 | } | ||
923 | for (i = 0; i < 8; i++) { | ||
924 | if ((retVal == pcie_RET_OK) && (writeRegs->msiIrqStatusRaw[i] != NULL)) { | ||
925 | retVal = pciev0_write_msiIrqStatusRaw_reg (baseAppRegs, writeRegs->msiIrqStatusRaw[i], i); | ||
926 | } | ||
927 | if ((retVal == pcie_RET_OK) && (writeRegs->msiIrqStatus[i] != NULL)) { | ||
928 | retVal = pciev0_write_msiIrqStatus_reg (baseAppRegs, writeRegs->msiIrqStatus[i], i); | ||
929 | } | ||
930 | if ((retVal == pcie_RET_OK) && (writeRegs->msiIrqEnableSet[i] != NULL)) { | ||
931 | retVal = pciev0_write_msiIrqEnableSet_reg (baseAppRegs, writeRegs->msiIrqEnableSet[i], i); | ||
932 | } | ||
933 | if ((retVal == pcie_RET_OK) && (writeRegs->msiIrqEnableClr[i] != NULL)) { | ||
934 | retVal = pciev0_write_msiIrqEnableClr_reg (baseAppRegs, writeRegs->msiIrqEnableClr[i], i); | ||
935 | } | ||
936 | } | ||
937 | for (i = 0; i < 4; i++) { | ||
938 | if ((retVal == pcie_RET_OK) && (writeRegs->legacyIrqStatusRaw[i] != NULL)) { | ||
939 | retVal = pciev0_write_legacyIrqStatusRaw_reg (baseAppRegs, writeRegs->legacyIrqStatusRaw[i], i); | ||
940 | } | ||
941 | if ((retVal == pcie_RET_OK) && (writeRegs->legacyIrqStatus[i] != NULL)) { | ||
942 | retVal = pciev0_write_legacyIrqStatus_reg (baseAppRegs, writeRegs->legacyIrqStatus[i], i); | ||
943 | } | ||
944 | if ((retVal == pcie_RET_OK) && (writeRegs->legacyIrqEnableSet[i] != NULL)) { | ||
945 | retVal = pciev0_write_legacyIrqEnableSet_reg (baseAppRegs, writeRegs->legacyIrqEnableSet[i], i); | ||
946 | } | ||
947 | if ((retVal == pcie_RET_OK) && (writeRegs->legacyIrqEnableClr[i] != NULL)) { | ||
948 | retVal = pciev0_write_legacyIrqEnableClr_reg (baseAppRegs, writeRegs->legacyIrqEnableClr[i], i); | ||
949 | } | ||
950 | } | ||
951 | if ((retVal == pcie_RET_OK) && (writeRegs->errIrqStatusRaw != NULL)) { | ||
952 | retVal = pciev0_write_errIrqStatusRaw_reg (baseAppRegs, writeRegs->errIrqStatusRaw); | ||
953 | } | ||
954 | if ((retVal == pcie_RET_OK) && (writeRegs->errIrqStatus != NULL)) { | ||
955 | retVal = pciev0_write_errIrqStatus_reg (baseAppRegs, writeRegs->errIrqStatus); | ||
956 | } | ||
957 | if ((retVal == pcie_RET_OK) && (writeRegs->errIrqEnableSet != NULL)) { | ||
958 | retVal = pciev0_write_errIrqEnableSet_reg (baseAppRegs, writeRegs->errIrqEnableSet); | ||
959 | } | ||
960 | if ((retVal == pcie_RET_OK) && (writeRegs->errIrqEnableClr != NULL)) { | ||
961 | retVal = pciev0_write_errIrqEnableClr_reg (baseAppRegs, writeRegs->errIrqEnableClr); | ||
962 | } | ||
963 | |||
964 | if ((retVal == pcie_RET_OK) && (writeRegs->pmRstIrqStatusRaw != NULL)) { | ||
965 | retVal = pciev0_write_pmRstIrqStatusRaw_reg (baseAppRegs, writeRegs->pmRstIrqStatusRaw); | ||
966 | } | ||
967 | if ((retVal == pcie_RET_OK) && (writeRegs->pmRstIrqStatus != NULL)) { | ||
968 | retVal = pciev0_write_pmRstIrqStatus_reg (baseAppRegs, writeRegs->pmRstIrqStatus); | ||
969 | } | ||
970 | if ((retVal == pcie_RET_OK) && (writeRegs->pmRstIrqEnableSet != NULL)) { | ||
971 | retVal = pciev0_write_pmRstIrqEnableSet_reg (baseAppRegs, writeRegs->pmRstIrqEnableSet); | ||
972 | } | ||
973 | if ((retVal == pcie_RET_OK) && (writeRegs->pmRstIrqEnableClr != NULL)) { | ||
974 | retVal = pciev0_write_pmRstIrqEnableClr_reg (baseAppRegs, writeRegs->pmRstIrqEnableClr); | ||
975 | } | ||
976 | |||
977 | for (i = 0; i < 8; i ++) { | ||
978 | if ((retVal == pcie_RET_OK) && (writeRegs->obOffsetLo[i] != NULL)) { | ||
979 | retVal = pciev0_write_obOffsetLo_reg (baseAppRegs, writeRegs->obOffsetLo[i], i); | ||
980 | } | ||
981 | if ((retVal == pcie_RET_OK) && (writeRegs->obOffsetHi[i] != NULL)) { | ||
982 | retVal = pciev0_write_obOffsetHi_reg (baseAppRegs, writeRegs->obOffsetHi[i], i); | ||
983 | } | ||
984 | } | ||
985 | |||
986 | for (i = 0; i < 4; i ++) { | ||
987 | if ((retVal == pcie_RET_OK) && (writeRegs->ibBar[i] != NULL)) { | ||
988 | retVal = pciev0_write_ibBar_reg (baseAppRegs, writeRegs->ibBar[i], i); | ||
989 | } | ||
990 | if ((retVal == pcie_RET_OK) && (writeRegs->ibStartLo[i] != NULL)) { | ||
991 | retVal = pciev0_write_ibStartLo_reg (baseAppRegs, writeRegs->ibStartLo[i], i); | ||
992 | } | ||
993 | if ((retVal == pcie_RET_OK) && (writeRegs->ibStartHi[i] != NULL)) { | ||
994 | retVal = pciev0_write_ibStartHi_reg (baseAppRegs, writeRegs->ibStartHi[i], i); | ||
995 | } | ||
996 | if ((retVal == pcie_RET_OK) && (writeRegs->ibOffset[i] != NULL)) { | ||
997 | retVal = pciev0_write_ibOffset_reg (baseAppRegs, writeRegs->ibOffset[i], i); | ||
998 | } | ||
999 | } | ||
1000 | |||
1001 | if ((retVal == pcie_RET_OK) && (writeRegs->pcsCfg0 != NULL)) { | ||
1002 | retVal = pciev0_write_pcsCfg0_reg (baseAppRegs, writeRegs->pcsCfg0); | ||
1003 | } | ||
1004 | if ((retVal == pcie_RET_OK) && (writeRegs->pcsCfg1 != NULL)) { | ||
1005 | retVal = pciev0_write_pcsCfg1_reg (baseAppRegs, writeRegs->pcsCfg1); | ||
1006 | } | ||
1007 | |||
1008 | if ((retVal == pcie_RET_OK) && (writeRegs->serdesCfg0 != NULL)) { | ||
1009 | retVal = pciev0_write_serdesCfg0_reg (baseAppRegs, writeRegs->serdesCfg0); | ||
1010 | } | ||
1011 | if ((retVal == pcie_RET_OK) && (writeRegs->serdesCfg1 != NULL)) { | ||
1012 | retVal = pciev0_write_serdesCfg1_reg (baseAppRegs, writeRegs->serdesCfg1); | ||
1013 | } | ||
1014 | |||
1015 | /***************************************************************************************** | ||
1016 | *Configuration Registers | ||
1017 | *****************************************************************************************/ | ||
1018 | |||
1019 | /*Type 0, Type1 Common Registers*/ | ||
1020 | |||
1021 | if ((retVal == pcie_RET_OK) && (writeRegs->vndDevId != NULL)) { | ||
1022 | retVal = pciev0_write_vndDevId_reg (baseCfgEpRegs, writeRegs->vndDevId); | ||
1023 | } | ||
1024 | if ((retVal == pcie_RET_OK) && (writeRegs->statusCmd != NULL)) { | ||
1025 | retVal = pciev0_write_statusCmd_reg (baseCfgEpRegs, writeRegs->statusCmd); | ||
1026 | } | ||
1027 | if ((retVal == pcie_RET_OK) && (writeRegs->revId != NULL)) { | ||
1028 | retVal = pciev0_write_revId_reg (baseCfgEpRegs, writeRegs->revId); | ||
1029 | } | ||
1030 | |||
1031 | /*Type 0 Registers*/ | ||
1032 | if ((retVal == pcie_RET_OK) && (writeRegs->bist != NULL)) { | ||
1033 | retVal = pciev0_write_bist_reg (baseCfgEpRegs, writeRegs->bist); | ||
1034 | } | ||
1035 | if ((retVal == pcie_RET_OK) && (writeRegs->type0BarIdx != NULL)) { | ||
1036 | retVal = pciev0_write_type0Bar_reg (baseCfgEpRegs, &(writeRegs->type0BarIdx->reg), | ||
1037 | writeRegs->type0BarIdx->idx); | ||
1038 | } | ||
1039 | if ((retVal == pcie_RET_OK) && (writeRegs->type0Bar32bitIdx != NULL)) { | ||
1040 | retVal = pciev0_write_type0Bar32bit_reg (baseCfgEpRegs, &(writeRegs->type0Bar32bitIdx->reg), | ||
1041 | writeRegs->type0Bar32bitIdx->idx); | ||
1042 | } | ||
1043 | if ((retVal == pcie_RET_OK) && (writeRegs->type0BarMask32bitIdx != NULL)) { | ||
1044 | retVal = pciev0_write_type0Bar32bit_reg (baseCfgEpRegs, &(writeRegs->type0BarMask32bitIdx->reg), | ||
1045 | writeRegs->type0BarMask32bitIdx->idx); | ||
1046 | } | ||
1047 | if ((retVal == pcie_RET_OK) && (writeRegs->subId != NULL)) { | ||
1048 | retVal = pciev0_write_subId_reg (baseCfgEpRegs, writeRegs->subId); | ||
1049 | } | ||
1050 | if ((retVal == pcie_RET_OK) && (writeRegs->cardbusCisPointer != NULL)) { | ||
1051 | /* Not supported on rev 0 */ | ||
1052 | retVal = pcie_RET_INV_REG; | ||
1053 | } | ||
1054 | if ((retVal == pcie_RET_OK) && (writeRegs->expRom != NULL)) { | ||
1055 | retVal = pciev0_write_expRom_reg (baseCfgEpRegs, writeRegs->expRom); | ||
1056 | } | ||
1057 | if ((retVal == pcie_RET_OK) && (writeRegs->capPtr != NULL)) { | ||
1058 | retVal = pciev0_write_capPtr_reg (baseCfgEpRegs, writeRegs->capPtr); | ||
1059 | } | ||
1060 | if ((retVal == pcie_RET_OK) && (writeRegs->intPin != NULL)) { | ||
1061 | retVal = pciev0_write_intPin_reg (baseCfgEpRegs, writeRegs->intPin); | ||
1062 | } | ||
1063 | |||
1064 | /*Type 1 Registers*/ | ||
1065 | if ((retVal == pcie_RET_OK) && (writeRegs->type1BistHeader != NULL)) { | ||
1066 | retVal = pciev0_write_type1BistHeader_reg (baseCfgRcRegs, writeRegs->type1BistHeader); | ||
1067 | } | ||
1068 | if ((retVal == pcie_RET_OK) && (writeRegs->type1BarIdx != NULL)) { | ||
1069 | retVal = pciev0_write_type1Bar_reg (baseCfgRcRegs, &(writeRegs->type1BarIdx->reg), | ||
1070 | writeRegs->type1BarIdx->idx); | ||
1071 | } | ||
1072 | if ((retVal == pcie_RET_OK) && (writeRegs->type1Bar32bitIdx != NULL)) { | ||
1073 | retVal = pciev0_write_type1Bar32bit_reg (baseCfgRcRegs, &(writeRegs->type1Bar32bitIdx->reg), | ||
1074 | writeRegs->type1Bar32bitIdx->idx); | ||
1075 | } | ||
1076 | if ((retVal == pcie_RET_OK) && (writeRegs->type1BarMask32bitIdx != NULL)) { | ||
1077 | retVal = pciev0_write_type1Bar32bit_reg (baseCfgRcRegs, &(writeRegs->type1BarMask32bitIdx->reg), | ||
1078 | writeRegs->type1BarMask32bitIdx->idx); | ||
1079 | } | ||
1080 | if ((retVal == pcie_RET_OK) && (writeRegs->type1BusNum != NULL)) { | ||
1081 | retVal = pciev0_write_type1BusNum_reg (baseCfgRcRegs, writeRegs->type1BusNum); | ||
1082 | } | ||
1083 | if ((retVal == pcie_RET_OK) && (writeRegs->type1SecStat != NULL)) { | ||
1084 | retVal = pciev0_write_type1SecStat_reg (baseCfgRcRegs, writeRegs->type1SecStat); | ||
1085 | } | ||
1086 | if ((retVal == pcie_RET_OK) && (writeRegs->type1Memspace != NULL)) { | ||
1087 | retVal = pciev0_write_type1Memspace_reg (baseCfgRcRegs, writeRegs->type1Memspace); | ||
1088 | } | ||
1089 | if ((retVal == pcie_RET_OK) && (writeRegs->prefMem != NULL)) { | ||
1090 | retVal = pciev0_write_prefMem_reg (baseCfgRcRegs, writeRegs->prefMem); | ||
1091 | } | ||
1092 | if ((retVal == pcie_RET_OK) && (writeRegs->prefBaseUpper != NULL)) { | ||
1093 | retVal = pciev0_write_prefBaseUpper_reg (baseCfgRcRegs, writeRegs->prefBaseUpper); | ||
1094 | } | ||
1095 | if ((retVal == pcie_RET_OK) && (writeRegs->prefLimitUpper != NULL)) { | ||
1096 | retVal = pciev0_write_prefLimitUpper_reg (baseCfgRcRegs, writeRegs->prefLimitUpper); | ||
1097 | } | ||
1098 | if ((retVal == pcie_RET_OK) && (writeRegs->type1IOSpace != NULL)) { | ||
1099 | retVal = pciev0_write_type1IOSpace_reg (baseCfgRcRegs, writeRegs->type1IOSpace); | ||
1100 | } | ||
1101 | if ((retVal == pcie_RET_OK) && (writeRegs->type1CapPtr != NULL)) { | ||
1102 | retVal = pciev0_write_type1CapPtr_reg (baseCfgRcRegs, writeRegs->type1CapPtr); | ||
1103 | } | ||
1104 | if ((retVal == pcie_RET_OK) && (writeRegs->type1ExpnsnRom != NULL)) { | ||
1105 | retVal = pciev0_write_type1ExpnsnRom_reg (baseCfgRcRegs, writeRegs->type1ExpnsnRom); | ||
1106 | } | ||
1107 | if ((retVal == pcie_RET_OK) && (writeRegs->type1BridgeInt != NULL)) { | ||
1108 | retVal = pciev0_write_type1BridgeInt_reg (baseCfgRcRegs, writeRegs->type1BridgeInt); | ||
1109 | } | ||
1110 | |||
1111 | /* Power Management Capabilities Registers */ | ||
1112 | if ((retVal == pcie_RET_OK) && (writeRegs->pmCap != NULL)) { | ||
1113 | retVal = pciev0_write_pmCap_reg (baseCfgEpRegs, writeRegs->pmCap); | ||
1114 | } | ||
1115 | if ((retVal == pcie_RET_OK) && (writeRegs->pmCapCtlStat != NULL)) { | ||
1116 | retVal = pciev0_write_pmCapCtlStat_reg (baseCfgEpRegs, writeRegs->pmCapCtlStat); | ||
1117 | } | ||
1118 | |||
1119 | /*MSI Registers*/ | ||
1120 | if ((retVal == pcie_RET_OK) && (writeRegs->msiCap != NULL)) { | ||
1121 | retVal = pciev0_write_msiCap_reg (baseCfgEpRegs, writeRegs->msiCap); | ||
1122 | } | ||
1123 | if ((retVal == pcie_RET_OK) && (writeRegs->msiLo32 != NULL)) { | ||
1124 | retVal = pciev0_write_msiLo32_reg (baseCfgEpRegs, writeRegs->msiLo32); | ||
1125 | } | ||
1126 | if ((retVal == pcie_RET_OK) && (writeRegs->msiUp32 != NULL)) { | ||
1127 | retVal = pciev0_write_msiUp32_reg (baseCfgEpRegs, writeRegs->msiUp32); | ||
1128 | } | ||
1129 | if ((retVal == pcie_RET_OK) && (writeRegs->msiData != NULL)) { | ||
1130 | retVal = pciev0_write_msiData_reg (baseCfgEpRegs, writeRegs->msiData); | ||
1131 | } | ||
1132 | |||
1133 | /*Capabilities Registers*/ | ||
1134 | if ((retVal == pcie_RET_OK) && (writeRegs->pciesCap != NULL)) { | ||
1135 | retVal = pciev0_write_pciesCap_reg (baseCfgEpRegs, writeRegs->pciesCap); | ||
1136 | } | ||
1137 | if ((retVal == pcie_RET_OK) && (writeRegs->deviceCap != NULL)) { | ||
1138 | retVal = pciev0_write_deviceCap_reg (baseCfgEpRegs, writeRegs->deviceCap); | ||
1139 | } | ||
1140 | |||
1141 | if ((retVal == pcie_RET_OK) && (writeRegs->devStatCtrl != NULL)) { | ||
1142 | retVal = pciev0_write_devStatCtrl_reg (baseCfgEpRegs, writeRegs->devStatCtrl); | ||
1143 | } | ||
1144 | if ((retVal == pcie_RET_OK) && (writeRegs->linkCap != NULL)) { | ||
1145 | retVal = pciev0_write_linkCap_reg (baseCfgEpRegs, writeRegs->linkCap); | ||
1146 | } | ||
1147 | if ((retVal == pcie_RET_OK) && (writeRegs->linkStatCtrl != NULL)) { | ||
1148 | retVal = pciev0_write_linkStatCtrl_reg (baseCfgEpRegs, writeRegs->linkStatCtrl); | ||
1149 | } | ||
1150 | if ((retVal == pcie_RET_OK) && (writeRegs->slotCap != NULL)) { | ||
1151 | retVal = pciev0_write_slotCap_reg (baseCfgRcRegs, writeRegs->slotCap); | ||
1152 | } | ||
1153 | if ((retVal == pcie_RET_OK) && (writeRegs->slotStatCtrl != NULL)) { | ||
1154 | retVal = pciev0_write_slotStatCtrl_reg (baseCfgRcRegs, writeRegs->slotStatCtrl); | ||
1155 | } | ||
1156 | if ((retVal == pcie_RET_OK) && (writeRegs->rootCtrlCap != NULL)) { | ||
1157 | retVal = pciev0_write_rootCtrlCap_reg (baseCfgRcRegs, writeRegs->rootCtrlCap); | ||
1158 | } | ||
1159 | if ((retVal == pcie_RET_OK) && (writeRegs->rootStatus != NULL)) { | ||
1160 | retVal = pciev0_write_rootStatus_reg (baseCfgRcRegs, writeRegs->rootStatus); | ||
1161 | } | ||
1162 | if ((retVal == pcie_RET_OK) && (writeRegs->devCap2 != NULL)) { | ||
1163 | retVal = pciev0_write_devCap2_reg (baseCfgEpRegs, writeRegs->devCap2); | ||
1164 | } | ||
1165 | if ((retVal == pcie_RET_OK) && (writeRegs->devStatCtrl2 != NULL)) { | ||
1166 | retVal = pciev0_write_devStatCtrl2_reg (baseCfgEpRegs, writeRegs->devStatCtrl2); | ||
1167 | } | ||
1168 | if ((retVal == pcie_RET_OK) && (writeRegs->linkCap2 != NULL)) { | ||
1169 | /* Not supported on rev 0 */ | ||
1170 | retVal = pcie_RET_INV_REG; | ||
1171 | } | ||
1172 | if ((retVal == pcie_RET_OK) && (writeRegs->linkCtrl2 != NULL)) { | ||
1173 | retVal = pciev0_write_linkCtrl2_reg (baseCfgEpRegs, writeRegs->linkCtrl2); | ||
1174 | } | ||
1175 | |||
1176 | /*Capabilities Extended Registers*/ | ||
1177 | if ((retVal == pcie_RET_OK) && (writeRegs->uncErr != NULL)) { | ||
1178 | retVal = pciev0_write_uncErr_reg (baseCfgEpRegs, writeRegs->uncErr); | ||
1179 | } | ||
1180 | if ((retVal == pcie_RET_OK) && (writeRegs->uncErrMask != NULL)) { | ||
1181 | retVal = pciev0_write_uncErrMask_reg (baseCfgEpRegs, writeRegs->uncErrMask); | ||
1182 | } | ||
1183 | if ((retVal == pcie_RET_OK) && (writeRegs->uncErrSvrty != NULL)) { | ||
1184 | retVal = pciev0_write_uncErrSvrty_reg (baseCfgEpRegs, writeRegs->uncErrSvrty); | ||
1185 | } | ||
1186 | if ((retVal == pcie_RET_OK) && (writeRegs->corErr != NULL)) { | ||
1187 | retVal = pciev0_write_corErr_reg (baseCfgEpRegs, writeRegs->corErr); | ||
1188 | } | ||
1189 | if ((retVal == pcie_RET_OK) && (writeRegs->corErrMask != NULL)) { | ||
1190 | retVal = pciev0_write_corErrMask_reg (baseCfgEpRegs, writeRegs->corErrMask); | ||
1191 | } | ||
1192 | if ((retVal == pcie_RET_OK) && (writeRegs->accr != NULL)) { | ||
1193 | retVal = pciev0_write_accr_reg (baseCfgEpRegs, writeRegs->accr); | ||
1194 | } | ||
1195 | if ((retVal == pcie_RET_OK) && (writeRegs->rootErrCmd != NULL)) { | ||
1196 | retVal = pciev0_write_rootErrCmd_reg (baseCfgEpRegs, writeRegs->rootErrCmd); | ||
1197 | } | ||
1198 | if ((retVal == pcie_RET_OK) && (writeRegs->rootErrSt != NULL)) { | ||
1199 | retVal = pciev0_write_rootErrSt_reg (baseCfgEpRegs, writeRegs->rootErrSt); | ||
1200 | } | ||
1201 | |||
1202 | /*Port Logic Registers*/ | ||
1203 | if ((retVal == pcie_RET_OK) && (writeRegs->plAckTimer != NULL)) { | ||
1204 | retVal = pciev0_write_plAckTimer_reg (baseCfgEpRegs, writeRegs->plAckTimer); | ||
1205 | } | ||
1206 | if ((retVal == pcie_RET_OK) && (writeRegs->plOMsg != NULL)) { | ||
1207 | retVal = pciev0_write_plOMsg_reg (baseCfgEpRegs, writeRegs->plOMsg); | ||
1208 | } | ||
1209 | if ((retVal == pcie_RET_OK) && (writeRegs->plForceLink != NULL)) { | ||
1210 | retVal = pciev0_write_plForceLink_reg (baseCfgEpRegs, writeRegs->plForceLink); | ||
1211 | } | ||
1212 | if ((retVal == pcie_RET_OK) && (writeRegs->ackFreq != NULL)) { | ||
1213 | retVal = pciev0_write_ackFreq_reg (baseCfgEpRegs, writeRegs->ackFreq); | ||
1214 | } | ||
1215 | if ((retVal == pcie_RET_OK) && (writeRegs->lnkCtrl != NULL)) { | ||
1216 | retVal = pciev0_write_lnkCtrl_reg (baseCfgEpRegs, writeRegs->lnkCtrl); | ||
1217 | } | ||
1218 | if ((retVal == pcie_RET_OK) && (writeRegs->laneSkew != NULL)) { | ||
1219 | retVal = pciev0_write_laneSkew_reg (baseCfgEpRegs, writeRegs->laneSkew); | ||
1220 | } | ||
1221 | if ((retVal == pcie_RET_OK) && (writeRegs->symNum != NULL)) { | ||
1222 | retVal = pciev0_write_symNum_reg (baseCfgEpRegs, writeRegs->symNum); | ||
1223 | } | ||
1224 | if ((retVal == pcie_RET_OK) && (writeRegs->symTimerFltMask != NULL)) { | ||
1225 | retVal = pciev0_write_symTimerFltMask_reg (baseCfgEpRegs, writeRegs->symTimerFltMask); | ||
1226 | } | ||
1227 | if ((retVal == pcie_RET_OK) && (writeRegs->fltMask2 != NULL)) { | ||
1228 | retVal = pciev0_write_fltMask2_reg (baseCfgEpRegs, writeRegs->fltMask2); | ||
1229 | } | ||
1230 | if ((retVal == pcie_RET_OK) && (writeRegs->gen2 != NULL)) { | ||
1231 | retVal = pciev0_write_gen2_reg (baseCfgEpRegs, writeRegs->gen2); | ||
1232 | } | ||
1233 | |||
1234 | /* Reject hw rev 1 PL CONF registers */ | ||
1235 | if ((retVal == pcie_RET_OK) && (writeRegs->plconfObnpSubreqCtrl != NULL)) { | ||
1236 | /* Not supported on rev 0 */ | ||
1237 | retVal = pcie_RET_INV_REG; | ||
1238 | } | ||
1239 | if ((retVal == pcie_RET_OK) && (writeRegs->plconfTrPStsR != NULL)) { | ||
1240 | /* Not supported on rev 0 */ | ||
1241 | retVal = pcie_RET_INV_REG; | ||
1242 | } | ||
1243 | if ((retVal == pcie_RET_OK) && (writeRegs->plconfTrNpStsR != NULL)) { | ||
1244 | /* Not supported on rev 0 */ | ||
1245 | retVal = pcie_RET_INV_REG; | ||
1246 | } | ||
1247 | if ((retVal == pcie_RET_OK) && (writeRegs->plconfTrCStsR != NULL)) { | ||
1248 | /* Not supported on rev 0 */ | ||
1249 | retVal = pcie_RET_INV_REG; | ||
1250 | } | ||
1251 | if ((retVal == pcie_RET_OK) && (writeRegs->plconfQStsR != NULL)) { | ||
1252 | /* Not supported on rev 0 */ | ||
1253 | retVal = pcie_RET_INV_REG; | ||
1254 | } | ||
1255 | if ((retVal == pcie_RET_OK) && (writeRegs->plconfVcTrAR1 != NULL)) { | ||
1256 | /* Not supported on rev 0 */ | ||
1257 | retVal = pcie_RET_INV_REG; | ||
1258 | } | ||
1259 | if ((retVal == pcie_RET_OK) && (writeRegs->plconfVcTrAR2 != NULL)) { | ||
1260 | /* Not supported on rev 0 */ | ||
1261 | retVal = pcie_RET_INV_REG; | ||
1262 | } | ||
1263 | if ((retVal == pcie_RET_OK) && (writeRegs->plconfVc0PrQC != NULL)) { | ||
1264 | /* Not supported on rev 0 */ | ||
1265 | retVal = pcie_RET_INV_REG; | ||
1266 | } | ||
1267 | if ((retVal == pcie_RET_OK) && (writeRegs->plconfVc0NprQC != NULL)) { | ||
1268 | /* Not supported on rev 0 */ | ||
1269 | retVal = pcie_RET_INV_REG; | ||
1270 | } | ||
1271 | if ((retVal == pcie_RET_OK) && (writeRegs->plconfVc0CrQC != NULL)) { | ||
1272 | /* Not supported on rev 0 */ | ||
1273 | retVal = pcie_RET_INV_REG; | ||
1274 | } | ||
1275 | if ((retVal == pcie_RET_OK) && (writeRegs->plconfPhyStsR != NULL)) { | ||
1276 | /* Not supported on rev 0 */ | ||
1277 | retVal = pcie_RET_INV_REG; | ||
1278 | } | ||
1279 | if ((retVal == pcie_RET_OK) && (writeRegs->plconfPhyCtrlR != NULL)) { | ||
1280 | /* Not supported on rev 0 */ | ||
1281 | retVal = pcie_RET_INV_REG; | ||
1282 | } | ||
1283 | if ((retVal == pcie_RET_OK) && (writeRegs->plconfMsiCtrlAddress != NULL)) { | ||
1284 | /* Not supported on rev 0 */ | ||
1285 | retVal = pcie_RET_INV_REG; | ||
1286 | } | ||
1287 | if ((retVal == pcie_RET_OK) && (writeRegs->plconfMsiCtrlUpperAddress != NULL)) { | ||
1288 | /* Not supported on rev 0 */ | ||
1289 | retVal = pcie_RET_INV_REG; | ||
1290 | } | ||
1291 | for (i = 0; i < 8; i++) { | ||
1292 | if ((retVal == pcie_RET_OK) && (writeRegs->plconfMsiCtrlIntEnable[i] != NULL)) { | ||
1293 | /* Not supported on rev 0 */ | ||
1294 | retVal = pcie_RET_INV_REG; | ||
1295 | } | ||
1296 | if ((retVal == pcie_RET_OK) && (writeRegs->plconfMsiCtrlIntMask[i] != NULL)) { | ||
1297 | /* Not supported on rev 0 */ | ||
1298 | retVal = pcie_RET_INV_REG; | ||
1299 | } | ||
1300 | if ((retVal == pcie_RET_OK) && (writeRegs->plconfMsiCtrlIntStatus[i] != NULL)) { | ||
1301 | /* Not supported on rev 0 */ | ||
1302 | retVal = pcie_RET_INV_REG; | ||
1303 | } | ||
1304 | } | ||
1305 | if ((retVal == pcie_RET_OK) && (writeRegs->plconfMsiCtrlGpio != NULL)) { | ||
1306 | /* Not supported on rev 0 */ | ||
1307 | retVal = pcie_RET_INV_REG; | ||
1308 | } | ||
1309 | if ((retVal == pcie_RET_OK) && (writeRegs->plconfPipeLoopback != NULL)) { | ||
1310 | /* Not supported on rev 0 */ | ||
1311 | retVal = pcie_RET_INV_REG; | ||
1312 | } | ||
1313 | if ((retVal == pcie_RET_OK) && (writeRegs->plconfDbiRoWrEn != NULL)) { | ||
1314 | /* Not supported on rev 0 */ | ||
1315 | retVal = pcie_RET_INV_REG; | ||
1316 | } | ||
1317 | if ((retVal == pcie_RET_OK) && (writeRegs->plconfAxiSlvErrResp != NULL)) { | ||
1318 | /* Not supported on rev 0 */ | ||
1319 | retVal = pcie_RET_INV_REG; | ||
1320 | } | ||
1321 | if ((retVal == pcie_RET_OK) && (writeRegs->plconfAxiSlvTimeout != NULL)) { | ||
1322 | /* Not supported on rev 0 */ | ||
1323 | retVal = pcie_RET_INV_REG; | ||
1324 | } | ||
1325 | if ((retVal == pcie_RET_OK) && (writeRegs->plconfIatuIndex != NULL)) { | ||
1326 | /* Not supported on rev 0 */ | ||
1327 | retVal = pcie_RET_INV_REG; | ||
1328 | } | ||
1329 | if ((retVal == pcie_RET_OK) && (writeRegs->plconfIatuRegCtrl1 != NULL)) { | ||
1330 | /* Not supported on rev 0 */ | ||
1331 | retVal = pcie_RET_INV_REG; | ||
1332 | } | ||
1333 | if ((retVal == pcie_RET_OK) && (writeRegs->plconfIatuRegCtrl2 != NULL)) { | ||
1334 | /* Not supported on rev 0 */ | ||
1335 | retVal = pcie_RET_INV_REG; | ||
1336 | } | ||
1337 | if ((retVal == pcie_RET_OK) && (writeRegs->plconfIatuRegLowerBase != NULL)) { | ||
1338 | /* Not supported on rev 0 */ | ||
1339 | retVal = pcie_RET_INV_REG; | ||
1340 | } | ||
1341 | if ((retVal == pcie_RET_OK) && (writeRegs->plconfIatuRegUpperBase != NULL)) { | ||
1342 | /* Not supported on rev 0 */ | ||
1343 | retVal = pcie_RET_INV_REG; | ||
1344 | } | ||
1345 | if ((retVal == pcie_RET_OK) && (writeRegs->plconfIatuRegLimit != NULL)) { | ||
1346 | /* Not supported on rev 0 */ | ||
1347 | retVal = pcie_RET_INV_REG; | ||
1348 | } | ||
1349 | if ((retVal == pcie_RET_OK) && (writeRegs->plconfIatuRegLowerTarget != NULL)) { | ||
1350 | /* Not supported on rev 0 */ | ||
1351 | retVal = pcie_RET_INV_REG; | ||
1352 | } | ||
1353 | if ((retVal == pcie_RET_OK) && (writeRegs->plconfIatuRegUpperTarget != NULL)) { | ||
1354 | /* Not supported on rev 0 */ | ||
1355 | retVal = pcie_RET_INV_REG; | ||
1356 | } | ||
1357 | if ((retVal == pcie_RET_OK) && (writeRegs->plconfIatuRegCtrl3 != NULL)) { | ||
1358 | /* Not supported on rev 0 */ | ||
1359 | retVal = pcie_RET_INV_REG; | ||
1360 | } | ||
1361 | |||
1362 | |||
1363 | /* Reject hw rev 1 TI CONF registers */ | ||
1364 | if ((retVal == pcie_RET_OK) && (writeRegs->tiConfRevision != NULL)) { | ||
1365 | /* Not supported on rev 0 */ | ||
1366 | retVal = pcie_RET_INV_REG; | ||
1367 | } | ||
1368 | if ((retVal == pcie_RET_OK) && (writeRegs->tiConfSysConfig != NULL)) { | ||
1369 | /* Not supported on rev 0 */ | ||
1370 | retVal = pcie_RET_INV_REG; | ||
1371 | } | ||
1372 | if ((retVal == pcie_RET_OK) && (writeRegs->tiConfIrqEoi != NULL)) { | ||
1373 | /* Not supported on rev 0 */ | ||
1374 | retVal = pcie_RET_INV_REG; | ||
1375 | } | ||
1376 | if ((retVal == pcie_RET_OK) && (writeRegs->tiConfIrqStatusRawMain != NULL)) { | ||
1377 | /* Not supported on rev 0 */ | ||
1378 | retVal = pcie_RET_INV_REG; | ||
1379 | } | ||
1380 | if ((retVal == pcie_RET_OK) && (writeRegs->tiConfIrqStatusMain != NULL)) { | ||
1381 | /* Not supported on rev 0 */ | ||
1382 | retVal = pcie_RET_INV_REG; | ||
1383 | } | ||
1384 | if ((retVal == pcie_RET_OK) && (writeRegs->tiConfIrqEnableSetMain != NULL)) { | ||
1385 | /* Not supported on rev 0 */ | ||
1386 | retVal = pcie_RET_INV_REG; | ||
1387 | } | ||
1388 | if ((retVal == pcie_RET_OK) && (writeRegs->tiConfIrqEnableClrMain != NULL)) { | ||
1389 | /* Not supported on rev 0 */ | ||
1390 | retVal = pcie_RET_INV_REG; | ||
1391 | } | ||
1392 | if ((retVal == pcie_RET_OK) && (writeRegs->tiConfIrqStatusRawMsi != NULL)) { | ||
1393 | /* Not supported on rev 0 */ | ||
1394 | retVal = pcie_RET_INV_REG; | ||
1395 | } | ||
1396 | if ((retVal == pcie_RET_OK) && (writeRegs->tiConfIrqStatusMsi != NULL)) { | ||
1397 | /* Not supported on rev 0 */ | ||
1398 | retVal = pcie_RET_INV_REG; | ||
1399 | } | ||
1400 | if ((retVal == pcie_RET_OK) && (writeRegs->tiConfIrqEnableSetMsi != NULL)) { | ||
1401 | /* Not supported on rev 0 */ | ||
1402 | retVal = pcie_RET_INV_REG; | ||
1403 | } | ||
1404 | if ((retVal == pcie_RET_OK) && (writeRegs->tiConfIrqEnableClrMsi != NULL)) { | ||
1405 | /* Not supported on rev 0 */ | ||
1406 | retVal = pcie_RET_INV_REG; | ||
1407 | } | ||
1408 | if ((retVal == pcie_RET_OK) && (writeRegs->tiConfDeviceType != NULL)) { | ||
1409 | /* Not supported on rev 0 */ | ||
1410 | retVal = pcie_RET_INV_REG; | ||
1411 | } | ||
1412 | if ((retVal == pcie_RET_OK) && (writeRegs->tiConfDeviceCmd != NULL)) { | ||
1413 | /* Not supported on rev 0 */ | ||
1414 | retVal = pcie_RET_INV_REG; | ||
1415 | } | ||
1416 | if ((retVal == pcie_RET_OK) && (writeRegs->tiConfPmCtrl != NULL)) { | ||
1417 | /* Not supported on rev 0 */ | ||
1418 | retVal = pcie_RET_INV_REG; | ||
1419 | } | ||
1420 | if ((retVal == pcie_RET_OK) && (writeRegs->tiConfPhyCs != NULL)) { | ||
1421 | /* Not supported on rev 0 */ | ||
1422 | retVal = pcie_RET_INV_REG; | ||
1423 | } | ||
1424 | if ((retVal == pcie_RET_OK) && (writeRegs->tiConfIntxAssert != NULL)) { | ||
1425 | /* Not supported on rev 0 */ | ||
1426 | retVal = pcie_RET_INV_REG; | ||
1427 | } | ||
1428 | if ((retVal == pcie_RET_OK) && (writeRegs->tiConfIntxDeassert != NULL)) { | ||
1429 | /* Not supported on rev 0 */ | ||
1430 | retVal = pcie_RET_INV_REG; | ||
1431 | } | ||
1432 | if ((retVal == pcie_RET_OK) && (writeRegs->tiConfMsiXmt != NULL)) { | ||
1433 | /* Not supported on rev 0 */ | ||
1434 | retVal = pcie_RET_INV_REG; | ||
1435 | } | ||
1436 | if ((retVal == pcie_RET_OK) && (writeRegs->tiConfDebugCfg != NULL)) { | ||
1437 | /* Not supported on rev 0 */ | ||
1438 | retVal = pcie_RET_INV_REG; | ||
1439 | } | ||
1440 | if ((retVal == pcie_RET_OK) && (writeRegs->tiConfDebugData != NULL)) { | ||
1441 | /* Not supported on rev 0 */ | ||
1442 | retVal = pcie_RET_INV_REG; | ||
1443 | } | ||
1444 | if ((retVal == pcie_RET_OK) && (writeRegs->tiConfDiagCtrl != NULL)) { | ||
1445 | /* Not supported on rev 0 */ | ||
1446 | retVal = pcie_RET_INV_REG; | ||
1447 | } | ||
1292 | } | 1448 | } |
1293 | } | 1449 | } |
1294 | if (writeRegs->plconfMsiCtrlGpio) { | ||
1295 | /* Not supported on rev 0 */ | ||
1296 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
1297 | } | ||
1298 | if (writeRegs->plconfPipeLoopback) { | ||
1299 | /* Not supported on rev 0 */ | ||
1300 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
1301 | } | ||
1302 | if (writeRegs->plconfDbiRoWrEn) { | ||
1303 | /* Not supported on rev 0 */ | ||
1304 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
1305 | } | ||
1306 | if (writeRegs->plconfAxiSlvErrResp) { | ||
1307 | /* Not supported on rev 0 */ | ||
1308 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
1309 | } | ||
1310 | if (writeRegs->plconfAxiSlvTimeout) { | ||
1311 | /* Not supported on rev 0 */ | ||
1312 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
1313 | } | ||
1314 | if (writeRegs->plconfIatuIndex) { | ||
1315 | /* Not supported on rev 0 */ | ||
1316 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
1317 | } | ||
1318 | if (writeRegs->plconfIatuRegCtrl1) { | ||
1319 | /* Not supported on rev 0 */ | ||
1320 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
1321 | } | ||
1322 | if (writeRegs->plconfIatuRegCtrl2) { | ||
1323 | /* Not supported on rev 0 */ | ||
1324 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
1325 | } | ||
1326 | if (writeRegs->plconfIatuRegLowerBase) { | ||
1327 | /* Not supported on rev 0 */ | ||
1328 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
1329 | } | ||
1330 | if (writeRegs->plconfIatuRegUpperBase) { | ||
1331 | /* Not supported on rev 0 */ | ||
1332 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
1333 | } | ||
1334 | if (writeRegs->plconfIatuRegLimit) { | ||
1335 | /* Not supported on rev 0 */ | ||
1336 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
1337 | } | ||
1338 | if (writeRegs->plconfIatuRegLowerTarget) { | ||
1339 | /* Not supported on rev 0 */ | ||
1340 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
1341 | } | ||
1342 | if (writeRegs->plconfIatuRegUpperTarget) { | ||
1343 | /* Not supported on rev 0 */ | ||
1344 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
1345 | } | ||
1346 | if (writeRegs->plconfIatuRegCtrl3) { | ||
1347 | /* Not supported on rev 0 */ | ||
1348 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
1349 | } | ||
1350 | |||
1351 | |||
1352 | /* Reject hw rev 1 TI CONF registers */ | ||
1353 | if (writeRegs->tiConfRevision) { | ||
1354 | /* Not supported on rev 0 */ | ||
1355 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
1356 | } | ||
1357 | if (writeRegs->tiConfSysConfig) { | ||
1358 | /* Not supported on rev 0 */ | ||
1359 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
1360 | } | ||
1361 | if (writeRegs->tiConfIrqEoi) { | ||
1362 | /* Not supported on rev 0 */ | ||
1363 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
1364 | } | ||
1365 | if (writeRegs->tiConfIrqStatusRawMain) { | ||
1366 | /* Not supported on rev 0 */ | ||
1367 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
1368 | } | ||
1369 | if (writeRegs->tiConfIrqStatusMain) { | ||
1370 | /* Not supported on rev 0 */ | ||
1371 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
1372 | } | ||
1373 | if (writeRegs->tiConfIrqEnableSetMain) { | ||
1374 | /* Not supported on rev 0 */ | ||
1375 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
1376 | } | ||
1377 | if (writeRegs->tiConfIrqEnableClrMain) { | ||
1378 | /* Not supported on rev 0 */ | ||
1379 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
1380 | } | ||
1381 | if (writeRegs->tiConfIrqStatusRawMsi) { | ||
1382 | /* Not supported on rev 0 */ | ||
1383 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
1384 | } | ||
1385 | if (writeRegs->tiConfIrqStatusMsi) { | ||
1386 | /* Not supported on rev 0 */ | ||
1387 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
1388 | } | ||
1389 | if (writeRegs->tiConfIrqEnableSetMsi) { | ||
1390 | /* Not supported on rev 0 */ | ||
1391 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
1392 | } | ||
1393 | if (writeRegs->tiConfIrqEnableClrMsi) { | ||
1394 | /* Not supported on rev 0 */ | ||
1395 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
1396 | } | ||
1397 | if (writeRegs->tiConfDeviceType) { | ||
1398 | /* Not supported on rev 0 */ | ||
1399 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
1400 | } | ||
1401 | if (writeRegs->tiConfDeviceCmd) { | ||
1402 | /* Not supported on rev 0 */ | ||
1403 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
1404 | } | ||
1405 | if (writeRegs->tiConfPmCtrl) { | ||
1406 | /* Not supported on rev 0 */ | ||
1407 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
1408 | } | ||
1409 | if (writeRegs->tiConfPhyCs) { | ||
1410 | /* Not supported on rev 0 */ | ||
1411 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
1412 | } | ||
1413 | if (writeRegs->tiConfIntxAssert) { | ||
1414 | /* Not supported on rev 0 */ | ||
1415 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
1416 | } | ||
1417 | if (writeRegs->tiConfIntxDeassert) { | ||
1418 | /* Not supported on rev 0 */ | ||
1419 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
1420 | } | ||
1421 | if (writeRegs->tiConfMsiXmt) { | ||
1422 | /* Not supported on rev 0 */ | ||
1423 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
1424 | } | ||
1425 | if (writeRegs->tiConfDebugCfg) { | ||
1426 | /* Not supported on rev 0 */ | ||
1427 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
1428 | } | ||
1429 | if (writeRegs->tiConfDebugData) { | ||
1430 | /* Not supported on rev 0 */ | ||
1431 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
1432 | } | ||
1433 | if (writeRegs->tiConfDiagCtrl) { | ||
1434 | /* Not supported on rev 0 */ | ||
1435 | pcie_check_result(retVal, pcie_RET_INV_REG); | ||
1436 | } | ||
1437 | 1450 | ||
1438 | return retVal; | 1451 | return retVal; |
1439 | } /* Pciev0_writeRegs */ | 1452 | } /* Pciev0_writeRegs */ |
@@ -1459,27 +1472,31 @@ pcieRet_e Pciev0_cfgObOffset | |||
1459 | uint16_t obAddrLoField; | 1472 | uint16_t obAddrLoField; |
1460 | 1473 | ||
1461 | if (pcieLObjIsValid == 0) { | 1474 | if (pcieLObjIsValid == 0) { |
1462 | return pcie_RET_NO_INIT; | 1475 | retVal = pcie_RET_NO_INIT; |
1476 | } | ||
1477 | else { | ||
1478 | if (pcie_check_handle_fcn(handle) == 0) { | ||
1479 | retVal = pcie_RET_INV_HANDLE; | ||
1480 | } | ||
1481 | else { | ||
1482 | baseAppRegs = cfg->cfgBase; | ||
1483 | |||
1484 | memset (&obOffsetLo, 0, sizeof(obOffsetLo)); | ||
1485 | memset (&obOffsetHi, 0, sizeof(obOffsetHi)); | ||
1486 | |||
1487 | uint32_t temp_var = 0U; | ||
1488 | pcie_getbits(obAddrLo, CSL_PCIESS_APP_OB_OFFSET_INDEX_OB_OFFSET_LO, temp_var); | ||
1489 | obAddrLoField = (uint16_t)temp_var; | ||
1490 | |||
1491 | obOffsetLo.enable = 1; | ||
1492 | obOffsetLo.offsetLo = obAddrLoField; | ||
1493 | |||
1494 | obOffsetHi.offsetHi = obAddrHi; | ||
1495 | |||
1496 | retVal = pciev0_write_obOffsetLo_reg(baseAppRegs, &obOffsetLo, (int_fast32_t)region); | ||
1497 | retVal = pciev0_write_obOffsetHi_reg(baseAppRegs, &obOffsetHi, (int_fast32_t)region); | ||
1498 | } | ||
1463 | } | 1499 | } |
1464 | |||
1465 | pcie_check_handle(handle); | ||
1466 | baseAppRegs = cfg->cfgBase; | ||
1467 | |||
1468 | memset (&obOffsetLo, 0, sizeof(obOffsetLo)); | ||
1469 | memset (&obOffsetHi, 0, sizeof(obOffsetHi)); | ||
1470 | |||
1471 | uint32_t temp_var = 0U; | ||
1472 | pcie_getbits(obAddrLo, CSL_PCIESS_APP_OB_OFFSET_INDEX_OB_OFFSET_LO, temp_var); | ||
1473 | obAddrLoField = (uint16_t)temp_var; | ||
1474 | |||
1475 | obOffsetLo.enable = 1; | ||
1476 | obOffsetLo.offsetLo = obAddrLoField; | ||
1477 | |||
1478 | obOffsetHi.offsetHi = obAddrHi; | ||
1479 | |||
1480 | pcie_check_result(retVal, pciev0_write_obOffsetLo_reg(baseAppRegs, &obOffsetLo, (int_fast32_t)region)); | ||
1481 | pcie_check_result(retVal, pciev0_write_obOffsetHi_reg(baseAppRegs, &obOffsetHi, (int_fast32_t)region)); | ||
1482 | |||
1483 | return retVal; | 1500 | return retVal; |
1484 | } /* Pciev0_cfgObOffset */ | 1501 | } /* Pciev0_cfgObOffset */ |
1485 | 1502 | ||
@@ -1507,33 +1524,37 @@ pcieRet_e Pciev0_cfgIbTrans | |||
1507 | uint32_t ibOffsetField; | 1524 | uint32_t ibOffsetField; |
1508 | 1525 | ||
1509 | if (pcieLObjIsValid == 0) { | 1526 | if (pcieLObjIsValid == 0) { |
1510 | return pcie_RET_NO_INIT; | 1527 | retVal = pcie_RET_NO_INIT; |
1528 | } | ||
1529 | else { | ||
1530 | if (pcie_check_handle_fcn(handle) == 0) { | ||
1531 | retVal = pcie_RET_INV_HANDLE; | ||
1532 | } | ||
1533 | else { | ||
1534 | baseAppRegs = cfg->cfgBase; | ||
1535 | |||
1536 | memset (&ibBar, 0, sizeof(ibBar)); | ||
1537 | memset (&ibStartLo, 0, sizeof(ibStartLo)); | ||
1538 | memset (&ibStartHi, 0, sizeof(ibStartHi)); | ||
1539 | memset (&ibOffset, 0, sizeof(ibOffset)); | ||
1540 | |||
1541 | ibBar.ibBar = ibCfg->ibBar; | ||
1542 | |||
1543 | pcie_getbits(ibCfg->ibStartAddrLo, CSL_PCIESS_APP_IB_START_LO_IB_START_LO, ibStartLoField); | ||
1544 | ibStartLo.ibStartLo = ibStartLoField; | ||
1545 | |||
1546 | ibStartHi.ibStartHi = ibCfg->ibStartAddrHi; | ||
1547 | |||
1548 | pcie_getbits(ibCfg->ibOffsetAddr, CSL_PCIESS_APP_IB_OFFSET_IB_OFFSET, ibOffsetField); | ||
1549 | ibOffset.ibOffset = ibOffsetField; | ||
1550 | |||
1551 | |||
1552 | retVal = pciev0_write_ibBar_reg (baseAppRegs, &ibBar, ibCfg->region); | ||
1553 | retVal = pciev0_write_ibStartLo_reg(baseAppRegs, &ibStartLo, ibCfg->region); | ||
1554 | retVal = pciev0_write_ibStartHi_reg(baseAppRegs, &ibStartHi, ibCfg->region); | ||
1555 | retVal = pciev0_write_ibOffset_reg (baseAppRegs, &ibOffset, ibCfg->region); | ||
1556 | } | ||
1511 | } | 1557 | } |
1512 | |||
1513 | pcie_check_handle(handle); | ||
1514 | baseAppRegs = cfg->cfgBase; | ||
1515 | |||
1516 | memset (&ibBar, 0, sizeof(ibBar)); | ||
1517 | memset (&ibStartLo, 0, sizeof(ibStartLo)); | ||
1518 | memset (&ibStartHi, 0, sizeof(ibStartHi)); | ||
1519 | memset (&ibOffset, 0, sizeof(ibOffset)); | ||
1520 | |||
1521 | ibBar.ibBar = ibCfg->ibBar; | ||
1522 | |||
1523 | pcie_getbits(ibCfg->ibStartAddrLo, CSL_PCIESS_APP_IB_START_LO_IB_START_LO, ibStartLoField); | ||
1524 | ibStartLo.ibStartLo = ibStartLoField; | ||
1525 | |||
1526 | ibStartHi.ibStartHi = ibCfg->ibStartAddrHi; | ||
1527 | |||
1528 | pcie_getbits(ibCfg->ibOffsetAddr, CSL_PCIESS_APP_IB_OFFSET_IB_OFFSET, ibOffsetField); | ||
1529 | ibOffset.ibOffset = ibOffsetField; | ||
1530 | |||
1531 | |||
1532 | pcie_check_result(retVal, pciev0_write_ibBar_reg (baseAppRegs, &ibBar, ibCfg->region)); | ||
1533 | pcie_check_result(retVal, pciev0_write_ibStartLo_reg(baseAppRegs, &ibStartLo, ibCfg->region)); | ||
1534 | pcie_check_result(retVal, pciev0_write_ibStartHi_reg(baseAppRegs, &ibStartHi, ibCfg->region)); | ||
1535 | pcie_check_result(retVal, pciev0_write_ibOffset_reg (baseAppRegs, &ibOffset, ibCfg->region)); | ||
1536 | |||
1537 | return retVal; | 1558 | return retVal; |
1538 | } /* Pciev0_cfgIbTrans */ | 1559 | } /* Pciev0_cfgIbTrans */ |
1539 | 1560 | ||
@@ -1554,46 +1575,49 @@ pcieRet_e Pciev0_cfgBar | |||
1554 | pcieRet_e retVal = pcie_RET_OK; | 1575 | pcieRet_e retVal = pcie_RET_OK; |
1555 | 1576 | ||
1556 | if (pcieLObjIsValid == 0) { | 1577 | if (pcieLObjIsValid == 0) { |
1557 | return pcie_RET_NO_INIT; | 1578 | retVal = pcie_RET_NO_INIT; |
1558 | } | ||
1559 | |||
1560 | pcie_check_handle(handle); | ||
1561 | |||
1562 | memset (&setRegs, 0, sizeof(setRegs)); | ||
1563 | memset (&type0BarIdx, 0, sizeof(type0BarIdx)); | ||
1564 | memset (&type1BarIdx, 0, sizeof(type1BarIdx)); | ||
1565 | |||
1566 | if(barCfg->mode == pcie_RC_MODE) | ||
1567 | { | ||
1568 | pcie_getbits(barCfg->base, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BAR_BASE_ADDRESS, barAddrField); | ||
1569 | |||
1570 | type1BarIdx.reg.base = barAddrField; | ||
1571 | type1BarIdx.reg.prefetch = barCfg->prefetch; | ||
1572 | type1BarIdx.reg.type = barCfg->type; | ||
1573 | type1BarIdx.reg.memSpace = barCfg->memSpace; | ||
1574 | type1BarIdx.idx = barCfg->idx; | ||
1575 | |||
1576 | setRegs.type1BarIdx = &type1BarIdx; | ||
1577 | } | 1579 | } |
1578 | else | 1580 | else { |
1579 | { | 1581 | if (pcie_check_handle_fcn(handle) == 0) { |
1580 | pcie_getbits(barCfg->base, CSL_PCIE_CFG_SPACE_ENDPOINT_BAR_BASE_ADDRESS, barAddrField); | 1582 | retVal = pcie_RET_INV_HANDLE; |
1581 | 1583 | } | |
1582 | type0BarIdx.reg.base = barAddrField; | 1584 | else { |
1583 | type0BarIdx.reg.prefetch = barCfg->prefetch; | 1585 | memset (&setRegs, 0, sizeof(setRegs)); |
1584 | type0BarIdx.reg.type = barCfg->type; | 1586 | memset (&type0BarIdx, 0, sizeof(type0BarIdx)); |
1585 | type0BarIdx.reg.memSpace = barCfg->memSpace; | 1587 | memset (&type1BarIdx, 0, sizeof(type1BarIdx)); |
1586 | type0BarIdx.idx = barCfg->idx; | 1588 | |
1587 | 1589 | if(barCfg->mode == pcie_RC_MODE) | |
1588 | setRegs.type0BarIdx = &type0BarIdx; | 1590 | { |
1589 | } | 1591 | pcie_getbits(barCfg->base, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BAR_BASE_ADDRESS, barAddrField); |
1590 | 1592 | ||
1591 | pcieRet_e temp_var = Pcie_writeRegs (handle, barCfg->location, &setRegs); | 1593 | type1BarIdx.reg.base = barAddrField; |
1592 | if ((temp_var) != pcie_RET_OK) | 1594 | type1BarIdx.reg.prefetch = barCfg->prefetch; |
1593 | { | 1595 | type1BarIdx.reg.type = barCfg->type; |
1594 | retVal = temp_var; | 1596 | type1BarIdx.reg.memSpace = barCfg->memSpace; |
1597 | type1BarIdx.idx = barCfg->idx; | ||
1598 | |||
1599 | setRegs.type1BarIdx = &type1BarIdx; | ||
1600 | } | ||
1601 | else | ||
1602 | { | ||
1603 | pcie_getbits(barCfg->base, CSL_PCIE_CFG_SPACE_ENDPOINT_BAR_BASE_ADDRESS, barAddrField); | ||
1604 | |||
1605 | type0BarIdx.reg.base = barAddrField; | ||
1606 | type0BarIdx.reg.prefetch = barCfg->prefetch; | ||
1607 | type0BarIdx.reg.type = barCfg->type; | ||
1608 | type0BarIdx.reg.memSpace = barCfg->memSpace; | ||
1609 | type0BarIdx.idx = barCfg->idx; | ||
1610 | |||
1611 | setRegs.type0BarIdx = &type0BarIdx; | ||
1612 | } | ||
1613 | |||
1614 | pcieRet_e temp_var = Pcie_writeRegs (handle, barCfg->location, &setRegs); | ||
1615 | if ((temp_var) != pcie_RET_OK) | ||
1616 | { | ||
1617 | retVal = temp_var; | ||
1618 | } | ||
1619 | } | ||
1595 | } | 1620 | } |
1596 | |||
1597 | return retVal; | 1621 | return retVal; |
1598 | } /* Pciev0_cfgBar */ | 1622 | } /* Pciev0_cfgBar */ |
1599 | 1623 | ||
diff --git a/src/v1/pciev1.c b/src/v1/pciev1.c index dbe2a2b..997e574 100644 --- a/src/v1/pciev1.c +++ b/src/v1/pciev1.c | |||
@@ -93,13 +93,14 @@ pcieRet_e Pciev1_setInterfaceMode | |||
93 | { | 93 | { |
94 | Pcie_DeviceCfgBaseAddr *cfg = pcie_handle_to_cfg (handle); | 94 | Pcie_DeviceCfgBaseAddr *cfg = pcie_handle_to_cfg (handle); |
95 | Pciev1_DeviceCfgBaseAddrs *bases = cfg->cfgBase; | 95 | Pciev1_DeviceCfgBaseAddrs *bases = cfg->cfgBase; |
96 | pcieRet_e retVal = pcie_RET_INV_HANDLE; | ||
96 | 97 | ||
97 | if (bases) { | 98 | if (bases) { |
98 | pcie_set_mode (bases, mode); | 99 | pcie_set_mode (bases, mode); |
99 | return pcie_RET_OK; | 100 | retVal = pcie_RET_OK; |
100 | } | 101 | } |
101 | 102 | ||
102 | return pcie_RET_INV_HANDLE; | 103 | return retVal; |
103 | } /* Pciev1_setInterfaceMode */ | 104 | } /* Pciev1_setInterfaceMode */ |
104 | 105 | ||
105 | /********************************************************************* | 106 | /********************************************************************* |
@@ -117,18 +118,22 @@ pcieRet_e Pciev1_getMemSpaceReserved | |||
117 | pcieRet_e retVal = pcie_RET_OK; | 118 | pcieRet_e retVal = pcie_RET_OK; |
118 | 119 | ||
119 | if (pcieLObjIsValid == 0) { | 120 | if (pcieLObjIsValid == 0) { |
120 | return pcie_RET_NO_INIT; | 121 | retVal = pcie_RET_NO_INIT; |
121 | } | 122 | } |
122 | 123 | else { | |
123 | pcie_check_handle(handle); | 124 | if (pcie_check_handle_fcn(handle) == 0) { |
124 | |||
125 | if (resSize) { | ||
126 | Pcie_DeviceCfgBaseAddr *bases = pcie_handle_to_cfg (handle); | ||
127 | if (bases) { | ||
128 | *resSize = bases->dataReserved; | ||
129 | } else { | ||
130 | retVal = pcie_RET_INV_HANDLE; | 125 | retVal = pcie_RET_INV_HANDLE; |
131 | } | 126 | } |
127 | else { | ||
128 | if (resSize) { | ||
129 | Pcie_DeviceCfgBaseAddr *bases = pcie_handle_to_cfg (handle); | ||
130 | if (bases) { | ||
131 | *resSize = bases->dataReserved; | ||
132 | } else { | ||
133 | retVal = pcie_RET_INV_HANDLE; | ||
134 | } | ||
135 | } | ||
136 | } | ||
132 | } | 137 | } |
133 | 138 | ||
134 | return retVal; | 139 | return retVal; |
@@ -148,22 +153,26 @@ pcieRet_e Pciev1_getMemSpaceRange | |||
148 | pcieRet_e retVal = pcie_RET_OK; | 153 | pcieRet_e retVal = pcie_RET_OK; |
149 | 154 | ||
150 | if (pcieLObjIsValid == 0) { | 155 | if (pcieLObjIsValid == 0) { |
151 | return pcie_RET_NO_INIT; | 156 | retVal = pcie_RET_NO_INIT; |
152 | } | 157 | } |
153 | 158 | else { | |
154 | pcie_check_handle(handle); | 159 | if (pcie_check_handle_fcn(handle) == 0) { |
155 | |||
156 | if (base) { | ||
157 | Pcie_DeviceCfgBaseAddr *bases = pcie_handle_to_cfg (handle); | ||
158 | if (bases) { | ||
159 | *base = bases->dataBase; | ||
160 | } else { | ||
161 | retVal = pcie_RET_INV_HANDLE; | 160 | retVal = pcie_RET_INV_HANDLE; |
162 | } | 161 | } |
163 | } | 162 | else { |
163 | if (base) { | ||
164 | Pcie_DeviceCfgBaseAddr *bases = pcie_handle_to_cfg (handle); | ||
165 | if (bases) { | ||
166 | *base = bases->dataBase; | ||
167 | } else { | ||
168 | retVal = pcie_RET_INV_HANDLE; | ||
169 | } | ||
170 | } | ||
164 | 171 | ||
165 | if (size) { | 172 | if (size) { |
166 | *size = (uint32_t)0x10000000; /* 256 MB */ | 173 | *size = (uint32_t)0x10000000; /* 256 MB */ |
174 | } | ||
175 | } | ||
167 | } | 176 | } |
168 | 177 | ||
169 | return retVal; | 178 | return retVal; |
@@ -195,223 +204,226 @@ pcieRet_e Pciev1_readRegs | |||
195 | int32_t i; | 204 | int32_t i; |
196 | 205 | ||
197 | if (pcieLObjIsValid == 0) { | 206 | if (pcieLObjIsValid == 0) { |
198 | return pcie_RET_NO_INIT; | 207 | retVal = pcie_RET_NO_INIT; |
199 | } | 208 | } |
200 | 209 | else { | |
201 | pcie_check_handle(handle); | 210 | if (pcie_check_handle_fcn(handle) == 0) { |
202 | 211 | retVal = pcie_RET_INV_HANDLE; | |
203 | /* Get base address for Local or Remote config space */ | 212 | } |
204 | if (location != pcie_LOCATION_LOCAL) | 213 | else { |
205 | { | 214 | /* Get base address for Local or Remote config space */ |
206 | char *remoteBase = (char *)cfg->dataBase + bases->remoteOffset; | 215 | if (location != pcie_LOCATION_LOCAL) |
207 | uint32_t delta = 0; | 216 | { |
208 | baseCfgRcRegs = (CSL_RcCfgDbIcsRegs *)(remoteBase + delta); | 217 | char *remoteBase = (char *)cfg->dataBase + bases->remoteOffset; |
209 | baseCfgEpRegs = (CSL_EpCfgDbIcsRegs *)(remoteBase + delta); | 218 | uint32_t delta = 0; |
210 | delta = (char *)bases->plConf - (char *)bases->rcDbics; | 219 | baseCfgRcRegs = (CSL_RcCfgDbIcsRegs *)(remoteBase + delta); |
211 | baseCfgPlRegs = (CSL_PlConfRegs *) (remoteBase + delta); | 220 | baseCfgEpRegs = (CSL_EpCfgDbIcsRegs *)(remoteBase + delta); |
221 | delta = (char *)bases->plConf - (char *)bases->rcDbics; | ||
222 | baseCfgPlRegs = (CSL_PlConfRegs *) (remoteBase + delta); | ||
223 | } | ||
224 | } | ||
212 | } | 225 | } |
213 | |||
214 | /***************************************************************************************** | 226 | /***************************************************************************************** |
215 | * Reject hw rev 0 app registers (these are similar but not identical to TI CONF on rev 1) | 227 | * Reject hw rev 0 app registers (these are similar but not identical to TI CONF on rev 1) |
216 | *****************************************************************************************/ | 228 | *****************************************************************************************/ |
217 | if (readRegs->pid) { | 229 | if ((retVal == pcie_RET_OK) && (readRegs->pid != NULL)) { |
218 | /* Not supported on rev 1 */ | 230 | /* Not supported on rev 1 */ |
219 | pcie_check_result(retVal, pcie_RET_INV_REG); | 231 | retVal = pcie_RET_INV_REG; |
220 | } | 232 | } |
221 | if (readRegs->cmdStatus) { | 233 | if ((retVal == pcie_RET_OK) && (readRegs->cmdStatus != NULL)) { |
222 | /* Not supported on rev 1 */ | 234 | /* Not supported on rev 1 */ |
223 | pcie_check_result(retVal, pcie_RET_INV_REG); | 235 | retVal = pcie_RET_INV_REG; |
224 | } | 236 | } |
225 | if (readRegs->cfgTrans) { | 237 | if ((retVal == pcie_RET_OK) && (readRegs->cfgTrans != NULL)) { |
226 | /* Not supported on rev 1 */ | 238 | /* Not supported on rev 1 */ |
227 | pcie_check_result(retVal, pcie_RET_INV_REG); | 239 | retVal = pcie_RET_INV_REG; |
228 | } | 240 | } |
229 | if (readRegs->ioBase) { | 241 | if ((retVal == pcie_RET_OK) && (readRegs->ioBase != NULL)) { |
230 | /* Not supported on rev 1 */ | 242 | /* Not supported on rev 1 */ |
231 | pcie_check_result(retVal, pcie_RET_INV_REG); | 243 | retVal = pcie_RET_INV_REG; |
232 | } | 244 | } |
233 | if (readRegs->tlpCfg) { | 245 | if ((retVal == pcie_RET_OK) && (readRegs->tlpCfg != NULL)) { |
234 | /* Not supported on rev 1 */ | 246 | /* Not supported on rev 1 */ |
235 | pcie_check_result(retVal, pcie_RET_INV_REG); | 247 | retVal = pcie_RET_INV_REG; |
236 | } | 248 | } |
237 | if (readRegs->rstCmd) { | 249 | if ((retVal == pcie_RET_OK) && (readRegs->rstCmd != NULL)) { |
238 | /* Not supported on rev 1 */ | 250 | /* Not supported on rev 1 */ |
239 | pcie_check_result(retVal, pcie_RET_INV_REG); | 251 | retVal = pcie_RET_INV_REG; |
240 | } | 252 | } |
241 | if (readRegs->pmCmd) { | 253 | if ((retVal == pcie_RET_OK) && (readRegs->pmCmd != NULL)) { |
242 | /* Not supported on rev 1 */ | 254 | /* Not supported on rev 1 */ |
243 | pcie_check_result(retVal, pcie_RET_INV_REG); | 255 | retVal = pcie_RET_INV_REG; |
244 | } | 256 | } |
245 | if (readRegs->pmCfg) { | 257 | if ((retVal == pcie_RET_OK) && (readRegs->pmCfg != NULL)) { |
246 | /* Not supported on rev 1 */ | 258 | /* Not supported on rev 1 */ |
247 | pcie_check_result(retVal, pcie_RET_INV_REG); | 259 | retVal = pcie_RET_INV_REG; |
248 | } | 260 | } |
249 | if (readRegs->actStatus) { | 261 | if ((retVal == pcie_RET_OK) && (readRegs->actStatus != NULL)) { |
250 | /* Not supported on rev 1 */ | 262 | /* Not supported on rev 1 */ |
251 | pcie_check_result(retVal, pcie_RET_INV_REG); | 263 | retVal = pcie_RET_INV_REG; |
252 | } | 264 | } |
253 | if (readRegs->obSize) { | 265 | if ((retVal == pcie_RET_OK) && (readRegs->obSize != NULL)) { |
254 | /* Not supported on rev 1 */ | 266 | /* Not supported on rev 1 */ |
255 | pcie_check_result(retVal, pcie_RET_INV_REG); | 267 | retVal = pcie_RET_INV_REG; |
256 | } | 268 | } |
257 | if (readRegs->diagCtrl) { | 269 | if ((retVal == pcie_RET_OK) && (readRegs->diagCtrl != NULL)) { |
258 | /* Not supported on rev 1 */ | 270 | /* Not supported on rev 1 */ |
259 | pcie_check_result(retVal, pcie_RET_INV_REG); | 271 | retVal = pcie_RET_INV_REG; |
260 | } | 272 | } |
261 | if (readRegs->endian) { | 273 | if ((retVal == pcie_RET_OK) && (readRegs->endian != NULL)) { |
262 | /* Not supported on rev 1 */ | 274 | /* Not supported on rev 1 */ |
263 | pcie_check_result(retVal, pcie_RET_INV_REG); | 275 | retVal = pcie_RET_INV_REG; |
264 | } | 276 | } |
265 | if (readRegs->priority) { | 277 | if ((retVal == pcie_RET_OK) && (readRegs->priority != NULL)) { |
266 | /* Not supported on rev 1 */ | 278 | /* Not supported on rev 1 */ |
267 | pcie_check_result(retVal, pcie_RET_INV_REG); | 279 | retVal = pcie_RET_INV_REG; |
268 | } | 280 | } |
269 | if (readRegs->irqEOI) { | 281 | if ((retVal == pcie_RET_OK) && (readRegs->irqEOI != NULL)) { |
270 | /* Not supported on rev 1 */ | 282 | /* Not supported on rev 1 */ |
271 | pcie_check_result(retVal, pcie_RET_INV_REG); | 283 | retVal = pcie_RET_INV_REG; |
272 | } | 284 | } |
273 | if (readRegs->msiIrq) { | 285 | if ((retVal == pcie_RET_OK) && (readRegs->msiIrq != NULL)) { |
274 | /* Not supported on rev 1 */ | 286 | /* Not supported on rev 1 */ |
275 | pcie_check_result(retVal, pcie_RET_INV_REG); | 287 | retVal = pcie_RET_INV_REG; |
276 | } | 288 | } |
277 | if (readRegs->epIrqSet) { | 289 | if ((retVal == pcie_RET_OK) && (readRegs->epIrqSet != NULL)) { |
278 | /* Not supported on rev 1 */ | 290 | /* Not supported on rev 1 */ |
279 | pcie_check_result(retVal, pcie_RET_INV_REG); | 291 | retVal = pcie_RET_INV_REG; |
280 | } | 292 | } |
281 | if (readRegs->epIrqClr) { | 293 | if ((retVal == pcie_RET_OK) && (readRegs->epIrqClr != NULL)) { |
282 | /* Not supported on rev 1 */ | 294 | /* Not supported on rev 1 */ |
283 | pcie_check_result(retVal, pcie_RET_INV_REG); | 295 | retVal = pcie_RET_INV_REG; |
284 | } | 296 | } |
285 | if (readRegs->epIrqStatus) { | 297 | if ((retVal == pcie_RET_OK) && (readRegs->epIrqStatus != NULL)) { |
286 | /* Not supported on rev 1 */ | 298 | /* Not supported on rev 1 */ |
287 | pcie_check_result(retVal, pcie_RET_INV_REG); | 299 | retVal = pcie_RET_INV_REG; |
288 | } | 300 | } |
289 | for (i = 0; i < 4; i++) { | 301 | for (i = 0; i < 4; i++) { |
290 | if (readRegs->genPurpose[i]) { | 302 | if ((retVal == pcie_RET_OK) && (readRegs->genPurpose[i] != NULL)) { |
291 | /* Not supported on rev 1 */ | 303 | /* Not supported on rev 1 */ |
292 | pcie_check_result(retVal, pcie_RET_INV_REG); | 304 | retVal = pcie_RET_INV_REG; |
293 | } | 305 | } |
294 | } | 306 | } |
295 | for (i = 0; i < 8; i++) { | 307 | for (i = 0; i < 8; i++) { |
296 | if (readRegs->msiIrqStatusRaw[i]) { | 308 | if ((retVal == pcie_RET_OK) && (readRegs->msiIrqStatusRaw[i] != NULL)) { |
297 | /* Not supported on rev 1 */ | 309 | /* Not supported on rev 1 */ |
298 | pcie_check_result(retVal, pcie_RET_INV_REG); | 310 | retVal = pcie_RET_INV_REG; |
299 | } | 311 | } |
300 | if (readRegs->msiIrqStatus[i]) { | 312 | if ((retVal == pcie_RET_OK) && (readRegs->msiIrqStatus[i] != NULL)) { |
301 | /* Not supported on rev 1 */ | 313 | /* Not supported on rev 1 */ |
302 | pcie_check_result(retVal, pcie_RET_INV_REG); | 314 | retVal = pcie_RET_INV_REG; |
303 | } | 315 | } |
304 | if (readRegs->msiIrqEnableSet[i]) { | 316 | if ((retVal == pcie_RET_OK) && (readRegs->msiIrqEnableSet[i] != NULL)) { |
305 | /* Not supported on rev 1 */ | 317 | /* Not supported on rev 1 */ |
306 | pcie_check_result(retVal, pcie_RET_INV_REG); | 318 | retVal = pcie_RET_INV_REG; |
307 | } | 319 | } |
308 | if (readRegs->msiIrqEnableClr[i]) { | 320 | if ((retVal == pcie_RET_OK) && (readRegs->msiIrqEnableClr[i] != NULL)) { |
309 | /* Not supported on rev 1 */ | 321 | /* Not supported on rev 1 */ |
310 | pcie_check_result(retVal, pcie_RET_INV_REG); | 322 | retVal = pcie_RET_INV_REG; |
311 | } | 323 | } |
312 | } | 324 | } |
313 | for (i = 0; i < 4; i++) { | 325 | for (i = 0; i < 4; i++) { |
314 | if (readRegs->legacyIrqStatusRaw[i]) { | 326 | if ((retVal == pcie_RET_OK) && (readRegs->legacyIrqStatusRaw[i] != NULL)) { |
315 | /* Not supported on rev 1 */ | 327 | /* Not supported on rev 1 */ |
316 | pcie_check_result(retVal, pcie_RET_INV_REG); | 328 | retVal = pcie_RET_INV_REG; |
317 | } | 329 | } |
318 | if (readRegs->legacyIrqStatus[i]) { | 330 | if ((retVal == pcie_RET_OK) && (readRegs->legacyIrqStatus[i] != NULL)) { |
319 | /* Not supported on rev 1 */ | 331 | /* Not supported on rev 1 */ |
320 | pcie_check_result(retVal, pcie_RET_INV_REG); | 332 | retVal = pcie_RET_INV_REG; |
321 | } | 333 | } |
322 | if (readRegs->legacyIrqEnableSet[i]) { | 334 | if ((retVal == pcie_RET_OK) && (readRegs->legacyIrqEnableSet[i] != NULL)) { |
323 | /* Not supported on rev 1 */ | 335 | /* Not supported on rev 1 */ |
324 | pcie_check_result(retVal, pcie_RET_INV_REG); | 336 | retVal = pcie_RET_INV_REG; |
325 | } | 337 | } |
326 | if (readRegs->legacyIrqEnableClr[i]) { | 338 | if ((retVal == pcie_RET_OK) && (readRegs->legacyIrqEnableClr[i] != NULL)) { |
327 | /* Not supported on rev 1 */ | 339 | /* Not supported on rev 1 */ |
328 | pcie_check_result(retVal, pcie_RET_INV_REG); | 340 | retVal = pcie_RET_INV_REG; |
329 | } | 341 | } |
330 | } | 342 | } |
331 | if (readRegs->errIrqStatusRaw) { | 343 | if ((retVal == pcie_RET_OK) && (readRegs->errIrqStatusRaw != NULL)) { |
332 | /* Not supported on rev 1 */ | 344 | /* Not supported on rev 1 */ |
333 | pcie_check_result(retVal, pcie_RET_INV_REG); | 345 | retVal = pcie_RET_INV_REG; |
334 | } | 346 | } |
335 | if (readRegs->errIrqStatus) { | 347 | if ((retVal == pcie_RET_OK) && (readRegs->errIrqStatus != NULL)) { |
336 | /* Not supported on rev 1 */ | 348 | /* Not supported on rev 1 */ |
337 | pcie_check_result(retVal, pcie_RET_INV_REG); | 349 | retVal = pcie_RET_INV_REG; |
338 | } | 350 | } |
339 | if (readRegs->errIrqEnableSet) { | 351 | if ((retVal == pcie_RET_OK) && (readRegs->errIrqEnableSet != NULL)) { |
340 | /* Not supported on rev 1 */ | 352 | /* Not supported on rev 1 */ |
341 | pcie_check_result(retVal, pcie_RET_INV_REG); | 353 | retVal = pcie_RET_INV_REG; |
342 | } | 354 | } |
343 | if (readRegs->errIrqEnableClr) { | 355 | if ((retVal == pcie_RET_OK) && (readRegs->errIrqEnableClr != NULL)) { |
344 | /* Not supported on rev 1 */ | 356 | /* Not supported on rev 1 */ |
345 | pcie_check_result(retVal, pcie_RET_INV_REG); | 357 | retVal = pcie_RET_INV_REG; |
346 | } | 358 | } |
347 | 359 | ||
348 | if (readRegs->pmRstIrqStatusRaw) { | 360 | if ((retVal == pcie_RET_OK) && (readRegs->pmRstIrqStatusRaw != NULL)) { |
349 | /* Not supported on rev 1 */ | 361 | /* Not supported on rev 1 */ |
350 | pcie_check_result(retVal, pcie_RET_INV_REG); | 362 | retVal = pcie_RET_INV_REG; |
351 | } | 363 | } |
352 | if (readRegs->pmRstIrqStatus) { | 364 | if ((retVal == pcie_RET_OK) && (readRegs->pmRstIrqStatus != NULL)) { |
353 | /* Not supported on rev 1 */ | 365 | /* Not supported on rev 1 */ |
354 | pcie_check_result(retVal, pcie_RET_INV_REG); | 366 | retVal = pcie_RET_INV_REG; |
355 | } | 367 | } |
356 | if (readRegs->pmRstIrqEnableSet) { | 368 | if ((retVal == pcie_RET_OK) && (readRegs->pmRstIrqEnableSet != NULL)) { |
357 | /* Not supported on rev 1 */ | 369 | /* Not supported on rev 1 */ |
358 | pcie_check_result(retVal, pcie_RET_INV_REG); | 370 | retVal = pcie_RET_INV_REG; |
359 | } | 371 | } |
360 | if (readRegs->pmRstIrqEnableClr) { | 372 | if ((retVal == pcie_RET_OK) && (readRegs->pmRstIrqEnableClr != NULL)) { |
361 | /* Not supported on rev 1 */ | 373 | /* Not supported on rev 1 */ |
362 | pcie_check_result(retVal, pcie_RET_INV_REG); | 374 | retVal = pcie_RET_INV_REG; |
363 | } | 375 | } |
364 | 376 | ||
365 | for (i = 0; i < 8; i ++) { | 377 | for (i = 0; i < 8; i ++) { |
366 | if (readRegs->obOffsetLo[i]) { | 378 | if ((retVal == pcie_RET_OK) && (readRegs->obOffsetLo[i] != NULL)) { |
367 | /* Not supported on rev 1 */ | 379 | /* Not supported on rev 1 */ |
368 | pcie_check_result(retVal, pcie_RET_INV_REG); | 380 | retVal = pcie_RET_INV_REG; |
369 | } | 381 | } |
370 | if (readRegs->obOffsetHi[i]) { | 382 | if ((retVal == pcie_RET_OK) && (readRegs->obOffsetHi[i] != NULL)) { |
371 | /* Not supported on rev 1 */ | 383 | /* Not supported on rev 1 */ |
372 | pcie_check_result(retVal, pcie_RET_INV_REG); | 384 | retVal = pcie_RET_INV_REG; |
373 | } | 385 | } |
374 | } | 386 | } |
375 | 387 | ||
376 | for (i = 0; i < 4; i ++) { | 388 | for (i = 0; i < 4; i ++) { |
377 | if (readRegs->ibBar[i]) { | 389 | if ((retVal == pcie_RET_OK) && (readRegs->ibBar[i] != NULL)) { |
378 | /* Not supported on rev 1 */ | 390 | /* Not supported on rev 1 */ |
379 | pcie_check_result(retVal, pcie_RET_INV_REG); | 391 | retVal = pcie_RET_INV_REG; |
380 | } | 392 | } |
381 | if (readRegs->ibStartLo[i]) { | 393 | if ((retVal == pcie_RET_OK) && (readRegs->ibStartLo[i] != NULL)) { |
382 | /* Not supported on rev 1 */ | 394 | /* Not supported on rev 1 */ |
383 | pcie_check_result(retVal, pcie_RET_INV_REG); | 395 | retVal = pcie_RET_INV_REG; |
384 | } | 396 | } |
385 | if (readRegs->ibStartHi[i]) { | 397 | if ((retVal == pcie_RET_OK) && (readRegs->ibStartHi[i] != NULL)) { |
386 | /* Not supported on rev 1 */ | 398 | /* Not supported on rev 1 */ |
387 | pcie_check_result(retVal, pcie_RET_INV_REG); | 399 | retVal = pcie_RET_INV_REG; |
388 | } | 400 | } |
389 | if (readRegs->ibOffset[i]) { | 401 | if ((retVal == pcie_RET_OK) && (readRegs->ibOffset[i] != NULL)) { |
390 | /* Not supported on rev 1 */ | 402 | /* Not supported on rev 1 */ |
391 | pcie_check_result(retVal, pcie_RET_INV_REG); | 403 | retVal = pcie_RET_INV_REG; |
392 | } | 404 | } |
393 | } | 405 | } |
394 | 406 | ||
395 | if (readRegs->pcsCfg0) { | 407 | if ((retVal == pcie_RET_OK) && (readRegs->pcsCfg0 != NULL)) { |
396 | /* Not supported on rev 1 */ | 408 | /* Not supported on rev 1 */ |
397 | pcie_check_result(retVal, pcie_RET_INV_REG); | 409 | retVal = pcie_RET_INV_REG; |
398 | } | 410 | } |
399 | if (readRegs->pcsCfg1) { | 411 | if ((retVal == pcie_RET_OK) && (readRegs->pcsCfg1 != NULL)) { |
400 | /* Not supported on rev 1 */ | 412 | /* Not supported on rev 1 */ |
401 | pcie_check_result(retVal, pcie_RET_INV_REG); | 413 | retVal = pcie_RET_INV_REG; |
402 | } | 414 | } |
403 | if (readRegs->pcsStatus) { | 415 | if ((retVal == pcie_RET_OK) && (readRegs->pcsStatus != NULL)) { |
404 | /* Not supported on rev 1 */ | 416 | /* Not supported on rev 1 */ |
405 | pcie_check_result(retVal, pcie_RET_INV_REG); | 417 | retVal = pcie_RET_INV_REG; |
406 | } | 418 | } |
407 | 419 | ||
408 | if (readRegs->serdesCfg0) { | 420 | if ((retVal == pcie_RET_OK) && (readRegs->serdesCfg0 != NULL)) { |
409 | /* Not supported on rev 1 */ | 421 | /* Not supported on rev 1 */ |
410 | pcie_check_result(retVal, pcie_RET_INV_REG); | 422 | retVal = pcie_RET_INV_REG; |
411 | } | 423 | } |
412 | if (readRegs->serdesCfg1) { | 424 | if ((retVal == pcie_RET_OK) && (readRegs->serdesCfg1 != NULL)) { |
413 | /* Not supported on rev 1 */ | 425 | /* Not supported on rev 1 */ |
414 | pcie_check_result(retVal, pcie_RET_INV_REG); | 426 | retVal = pcie_RET_INV_REG; |
415 | } | 427 | } |
416 | 428 | ||
417 | /***************************************************************************************** | 429 | /***************************************************************************************** |
@@ -420,409 +432,409 @@ pcieRet_e Pciev1_readRegs | |||
420 | 432 | ||
421 | /*Type 0, Type1 Common Registers*/ | 433 | /*Type 0, Type1 Common Registers*/ |
422 | 434 | ||
423 | if (readRegs->vndDevId) { | 435 | if ((retVal == pcie_RET_OK) && (readRegs->vndDevId != NULL)) { |
424 | pcie_check_result(retVal, pciev1_read_vndDevId_reg (&baseCfgEpRegs->DEVICE_VENDORID, readRegs->vndDevId)); | 436 | retVal = pciev1_read_vndDevId_reg (&baseCfgEpRegs->DEVICE_VENDORID, readRegs->vndDevId); |
425 | } | 437 | } |
426 | if (readRegs->statusCmd) { | 438 | if ((retVal == pcie_RET_OK) && (readRegs->statusCmd != NULL)) { |
427 | pcie_check_result(retVal, pciev1_read_statusCmd_reg (&baseCfgEpRegs->STATUS_COMMAND_REGISTER, readRegs->statusCmd)); | 439 | retVal = pciev1_read_statusCmd_reg (&baseCfgEpRegs->STATUS_COMMAND_REGISTER, readRegs->statusCmd); |
428 | } | 440 | } |
429 | if (readRegs->revId) { | 441 | if ((retVal == pcie_RET_OK) && (readRegs->revId != NULL)) { |
430 | pcie_check_result(retVal, pciev1_read_revId_reg (&baseCfgEpRegs->CLASSCODE_REVISIONID, readRegs->revId)); | 442 | retVal = pciev1_read_revId_reg (&baseCfgEpRegs->CLASSCODE_REVISIONID, readRegs->revId); |
431 | } | 443 | } |
432 | 444 | ||
433 | if (readRegs->bist) { | 445 | if ((retVal == pcie_RET_OK) && (readRegs->bist != NULL)) { |
434 | pcie_check_result(retVal, pciev1_read_bist_reg (baseCfgEpRegs, readRegs->bist)); | 446 | retVal = pciev1_read_bist_reg (baseCfgEpRegs, readRegs->bist); |
435 | } | 447 | } |
436 | 448 | ||
437 | /*Type 0 Registers*/ | 449 | /*Type 0 Registers*/ |
438 | if (readRegs->type0BarIdx) { | 450 | if ((retVal == pcie_RET_OK) && (readRegs->type0BarIdx != NULL)) { |
439 | pcie_check_result(retVal, pciev1_read_type0Bar_reg (baseCfgEpRegs, &(readRegs->type0BarIdx->reg), | 451 | retVal = pciev1_read_type0Bar_reg (baseCfgEpRegs, &(readRegs->type0BarIdx->reg), |
440 | readRegs->type0BarIdx->idx)); | 452 | readRegs->type0BarIdx->idx); |
441 | } | 453 | } |
442 | if (readRegs->type0Bar32bitIdx) { | 454 | if ((retVal == pcie_RET_OK) && (readRegs->type0Bar32bitIdx != NULL)) { |
443 | pcie_check_result(retVal, pciev1_read_type0Bar32bit_reg (baseCfgEpRegs, &(readRegs->type0Bar32bitIdx->reg), | 455 | retVal = pciev1_read_type0Bar32bit_reg (baseCfgEpRegs, &(readRegs->type0Bar32bitIdx->reg), |
444 | readRegs->type0Bar32bitIdx->idx)); | 456 | readRegs->type0Bar32bitIdx->idx); |
445 | } | 457 | } |
446 | if (readRegs->type0BarMask32bitIdx) { | 458 | if ((retVal == pcie_RET_OK) && (readRegs->type0BarMask32bitIdx != NULL)) { |
447 | pcie_check_result(retVal, pciev1_read_type0Bar32bit_reg (baseCfgEpCS2Regs, &(readRegs->type0BarMask32bitIdx->reg), | 459 | retVal = pciev1_read_type0Bar32bit_reg (baseCfgEpCS2Regs, &(readRegs->type0BarMask32bitIdx->reg), |
448 | readRegs->type0BarMask32bitIdx->idx)); | 460 | readRegs->type0BarMask32bitIdx->idx); |
449 | } | 461 | } |
450 | if (readRegs->subId) { | 462 | if ((retVal == pcie_RET_OK) && (readRegs->subId != NULL)) { |
451 | pcie_check_result(retVal, pciev1_read_subId_reg (baseCfgEpRegs, readRegs->subId)); | 463 | retVal = pciev1_read_subId_reg (baseCfgEpRegs, readRegs->subId); |
452 | } | 464 | } |
453 | if (readRegs->cardbusCisPointer) { | 465 | if ((retVal == pcie_RET_OK) && (readRegs->cardbusCisPointer != NULL)) { |
454 | pcie_check_result(retVal, pciev1_read_cardbusCisPointer_reg (baseCfgEpRegs, readRegs->cardbusCisPointer)); | 466 | retVal = pciev1_read_cardbusCisPointer_reg (baseCfgEpRegs, readRegs->cardbusCisPointer); |
455 | } | 467 | } |
456 | if (readRegs->expRom) { | 468 | if ((retVal == pcie_RET_OK) && (readRegs->expRom != NULL)) { |
457 | pcie_check_result(retVal, pciev1_read_expRom_reg (baseCfgEpRegs, readRegs->expRom)); | 469 | retVal = pciev1_read_expRom_reg (baseCfgEpRegs, readRegs->expRom); |
458 | } | 470 | } |
459 | if (readRegs->capPtr) { | 471 | if ((retVal == pcie_RET_OK) && (readRegs->capPtr != NULL)) { |
460 | pcie_check_result(retVal, pciev1_read_capPtr_reg (baseCfgEpRegs, readRegs->capPtr)); | 472 | retVal = pciev1_read_capPtr_reg (baseCfgEpRegs, readRegs->capPtr); |
461 | } | 473 | } |
462 | if (readRegs->intPin) { | 474 | if ((retVal == pcie_RET_OK) && (readRegs->intPin != NULL)) { |
463 | pcie_check_result(retVal, pciev1_read_intPin_reg (baseCfgEpRegs, readRegs->intPin)); | 475 | retVal = pciev1_read_intPin_reg (baseCfgEpRegs, readRegs->intPin); |
464 | } | 476 | } |
465 | 477 | ||
466 | /*Type 1 Registers*/ | 478 | /*Type 1 Registers*/ |
467 | if (readRegs->type1BistHeader) { | 479 | if ((retVal == pcie_RET_OK) && (readRegs->type1BistHeader != NULL)) { |
468 | pcie_check_result(retVal, pciev1_read_type1BistHeader_reg (baseCfgRcRegs, readRegs->type1BistHeader)); | 480 | retVal = pciev1_read_type1BistHeader_reg (baseCfgRcRegs, readRegs->type1BistHeader); |
469 | } | 481 | } |
470 | if (readRegs->type1BarIdx) { | 482 | if ((retVal == pcie_RET_OK) && (readRegs->type1BarIdx != NULL)) { |
471 | pcie_check_result(retVal, pciev1_read_type1Bar_reg (baseCfgRcRegs, &(readRegs->type1BarIdx->reg), | 483 | retVal = pciev1_read_type1Bar_reg (baseCfgRcRegs, &(readRegs->type1BarIdx->reg), |
472 | readRegs->type1BarIdx->idx)); | 484 | readRegs->type1BarIdx->idx); |
473 | } | 485 | } |
474 | if (readRegs->type1Bar32bitIdx) { | 486 | if ((retVal == pcie_RET_OK) && (readRegs->type1Bar32bitIdx != NULL)) { |
475 | pcie_check_result(retVal, pciev1_read_type1Bar32bit_reg (baseCfgRcRegs, &(readRegs->type1Bar32bitIdx->reg), | 487 | retVal = pciev1_read_type1Bar32bit_reg (baseCfgRcRegs, &(readRegs->type1Bar32bitIdx->reg), |
476 | readRegs->type1Bar32bitIdx->idx)); | 488 | readRegs->type1Bar32bitIdx->idx); |
477 | } | 489 | } |
478 | if (readRegs->type1BarMask32bitIdx) { | 490 | if ((retVal == pcie_RET_OK) && (readRegs->type1BarMask32bitIdx != NULL)) { |
479 | pcie_check_result(retVal, pciev1_read_type1Bar32bit_reg (baseCfgRcCS2Regs, &(readRegs->type1BarMask32bitIdx->reg), | 491 | retVal = pciev1_read_type1Bar32bit_reg (baseCfgRcCS2Regs, &(readRegs->type1BarMask32bitIdx->reg), |
480 | readRegs->type1BarMask32bitIdx->idx)); | 492 | readRegs->type1BarMask32bitIdx->idx); |
481 | } | 493 | } |
482 | if (readRegs->type1BusNum) { | 494 | if ((retVal == pcie_RET_OK) && (readRegs->type1BusNum != NULL)) { |
483 | pcie_check_result(retVal, pciev1_read_type1BusNum_reg (baseCfgRcRegs, readRegs->type1BusNum)); | 495 | retVal = pciev1_read_type1BusNum_reg (baseCfgRcRegs, readRegs->type1BusNum); |
484 | } | 496 | } |
485 | if (readRegs->type1SecStat) { | 497 | if ((retVal == pcie_RET_OK) && (readRegs->type1SecStat != NULL)) { |
486 | pcie_check_result(retVal, pciev1_read_type1SecStat_reg (baseCfgRcRegs, readRegs->type1SecStat)); | 498 | retVal = pciev1_read_type1SecStat_reg (baseCfgRcRegs, readRegs->type1SecStat); |
487 | } | 499 | } |
488 | if (readRegs->type1Memspace) { | 500 | if ((retVal == pcie_RET_OK) && (readRegs->type1Memspace != NULL)) { |
489 | pcie_check_result(retVal, pciev1_read_type1Memspace_reg (baseCfgRcRegs, readRegs->type1Memspace)); | 501 | retVal = pciev1_read_type1Memspace_reg (baseCfgRcRegs, readRegs->type1Memspace); |
490 | } | 502 | } |
491 | if (readRegs->prefMem) { | 503 | if ((retVal == pcie_RET_OK) && (readRegs->prefMem != NULL)) { |
492 | pcie_check_result(retVal, pciev1_read_prefMem_reg (baseCfgRcRegs, readRegs->prefMem)); | 504 | retVal = pciev1_read_prefMem_reg (baseCfgRcRegs, readRegs->prefMem); |
493 | } | 505 | } |
494 | if (readRegs->prefBaseUpper) { | 506 | if ((retVal == pcie_RET_OK) && (readRegs->prefBaseUpper != NULL)) { |
495 | pcie_check_result(retVal, pciev1_read_prefBaseUpper_reg (baseCfgRcRegs, readRegs->prefBaseUpper)); | 507 | retVal = pciev1_read_prefBaseUpper_reg (baseCfgRcRegs, readRegs->prefBaseUpper); |
496 | } | 508 | } |
497 | if (readRegs->prefLimitUpper) { | 509 | if ((retVal == pcie_RET_OK) && (readRegs->prefLimitUpper != NULL)) { |
498 | pcie_check_result(retVal, pciev1_read_prefLimitUpper_reg (baseCfgRcRegs, readRegs->prefLimitUpper)); | 510 | retVal = pciev1_read_prefLimitUpper_reg (baseCfgRcRegs, readRegs->prefLimitUpper); |
499 | } | 511 | } |
500 | if (readRegs->type1IOSpace) { | 512 | if ((retVal == pcie_RET_OK) && (readRegs->type1IOSpace != NULL)) { |
501 | pcie_check_result(retVal, pciev1_read_type1IOSpace_reg (baseCfgRcRegs, readRegs->type1IOSpace)); | 513 | retVal = pciev1_read_type1IOSpace_reg (baseCfgRcRegs, readRegs->type1IOSpace); |
502 | } | 514 | } |
503 | if (readRegs->type1CapPtr) { | 515 | if ((retVal == pcie_RET_OK) && (readRegs->type1CapPtr != NULL)) { |
504 | pcie_check_result(retVal, pciev1_read_type1CapPtr_reg (baseCfgRcRegs, readRegs->type1CapPtr)); | 516 | retVal = pciev1_read_type1CapPtr_reg (baseCfgRcRegs, readRegs->type1CapPtr); |
505 | } | 517 | } |
506 | if (readRegs->type1ExpnsnRom) { | 518 | if ((retVal == pcie_RET_OK) && (readRegs->type1ExpnsnRom != NULL)) { |
507 | pcie_check_result(retVal, pciev1_read_type1ExpnsnRom_reg (baseCfgRcRegs, readRegs->type1ExpnsnRom)); | 519 | retVal = pciev1_read_type1ExpnsnRom_reg (baseCfgRcRegs, readRegs->type1ExpnsnRom); |
508 | } | 520 | } |
509 | if (readRegs->type1BridgeInt) { | 521 | if ((retVal == pcie_RET_OK) && (readRegs->type1BridgeInt != NULL)) { |
510 | pcie_check_result(retVal, pciev1_read_type1BridgeInt_reg (baseCfgRcRegs, readRegs->type1BridgeInt)); | 522 | retVal = pciev1_read_type1BridgeInt_reg (baseCfgRcRegs, readRegs->type1BridgeInt); |
511 | } | 523 | } |
512 | 524 | ||
513 | /* Power Management Capabilities Registers */ | 525 | /* Power Management Capabilities Registers */ |
514 | if (readRegs->pmCap) { | 526 | if ((retVal == pcie_RET_OK) && (readRegs->pmCap != NULL)) { |
515 | pcie_check_result(retVal, pciev1_read_pmCap_reg (baseCfgEpRegs, readRegs->pmCap)); | 527 | retVal = pciev1_read_pmCap_reg (baseCfgEpRegs, readRegs->pmCap); |
516 | } | 528 | } |
517 | if (readRegs->pmCapCtlStat) { | 529 | if ((retVal == pcie_RET_OK) && (readRegs->pmCapCtlStat != NULL)) { |
518 | pcie_check_result(retVal, pciev1_read_pmCapCtlStat_reg (baseCfgEpRegs, readRegs->pmCapCtlStat)); | 530 | retVal = pciev1_read_pmCapCtlStat_reg (baseCfgEpRegs, readRegs->pmCapCtlStat); |
519 | } | 531 | } |
520 | 532 | ||
521 | /*MSI Registers*/ | 533 | /*MSI Registers*/ |
522 | if (readRegs->msiCap) { | 534 | if ((retVal == pcie_RET_OK) && (readRegs->msiCap != NULL)) { |
523 | pcie_check_result(retVal, pciev1_read_msiCap_reg (baseCfgEpRegs, readRegs->msiCap)); | 535 | retVal = pciev1_read_msiCap_reg (baseCfgEpRegs, readRegs->msiCap); |
524 | } | 536 | } |
525 | if (readRegs->msiLo32) { | 537 | if ((retVal == pcie_RET_OK) && (readRegs->msiLo32 != NULL)) { |
526 | pcie_check_result(retVal, pciev1_read_msiLo32_reg (baseCfgEpRegs, readRegs->msiLo32)); | 538 | retVal = pciev1_read_msiLo32_reg (baseCfgEpRegs, readRegs->msiLo32); |
527 | } | 539 | } |
528 | if (readRegs->msiUp32) { | 540 | if ((retVal == pcie_RET_OK) && (readRegs->msiUp32 != NULL)) { |
529 | pcie_check_result(retVal, pciev1_read_msiUp32_reg (baseCfgEpRegs, readRegs->msiUp32)); | 541 | retVal = pciev1_read_msiUp32_reg (baseCfgEpRegs, readRegs->msiUp32); |
530 | } | 542 | } |
531 | if (readRegs->msiData) { | 543 | if ((retVal == pcie_RET_OK) && (readRegs->msiData != NULL)) { |
532 | pcie_check_result(retVal, pciev1_read_msiData_reg (baseCfgEpRegs, readRegs->msiData)); | 544 | retVal = pciev1_read_msiData_reg (baseCfgEpRegs, readRegs->msiData); |
533 | } | 545 | } |
534 | 546 | ||
535 | /*Capabilities Registers*/ | 547 | /*Capabilities Registers*/ |
536 | if (readRegs->pciesCap) { | 548 | if ((retVal == pcie_RET_OK) && (readRegs->pciesCap != NULL)) { |
537 | pcie_check_result(retVal, pciev1_read_pciesCap_reg (&baseCfgEpRegs->PCIE_CAP_STRUC.PCIE_CAP, readRegs->pciesCap)); | 549 | retVal = pciev1_read_pciesCap_reg (&baseCfgEpRegs->PCIE_CAP_STRUC.PCIE_CAP, readRegs->pciesCap); |
538 | } | 550 | } |
539 | if (readRegs->deviceCap) { | 551 | if ((retVal == pcie_RET_OK) && (readRegs->deviceCap != NULL)) { |
540 | pcie_check_result(retVal, pciev1_read_deviceCap_reg (&baseCfgEpRegs->PCIE_CAP_STRUC.DEV_CAP, readRegs->deviceCap)); | 552 | retVal = pciev1_read_deviceCap_reg (&baseCfgEpRegs->PCIE_CAP_STRUC.DEV_CAP, readRegs->deviceCap); |
541 | } | 553 | } |
542 | if (readRegs->devStatCtrl) { | 554 | if ((retVal == pcie_RET_OK) && (readRegs->devStatCtrl != NULL)) { |
543 | pcie_check_result(retVal, pciev1_read_devStatCtrl_reg (&baseCfgEpRegs->PCIE_CAP_STRUC.DEV_CAS, readRegs->devStatCtrl)); | 555 | retVal = pciev1_read_devStatCtrl_reg (&baseCfgEpRegs->PCIE_CAP_STRUC.DEV_CAS, readRegs->devStatCtrl); |
544 | } | 556 | } |
545 | if (readRegs->linkCap) { | 557 | if ((retVal == pcie_RET_OK) && (readRegs->linkCap != NULL)) { |
546 | pcie_check_result(retVal, pciev1_read_linkCap_reg (&baseCfgEpRegs->PCIE_CAP_STRUC.LNK_CAP, readRegs->linkCap)); | 558 | retVal = pciev1_read_linkCap_reg (&baseCfgEpRegs->PCIE_CAP_STRUC.LNK_CAP, readRegs->linkCap); |
547 | } | 559 | } |
548 | if (readRegs->linkStatCtrl) { | 560 | if ((retVal == pcie_RET_OK) && (readRegs->linkStatCtrl != NULL)) { |
549 | pcie_check_result(retVal, pciev1_read_linkStatCtrl_reg (&baseCfgEpRegs->PCIE_CAP_STRUC.LNK_CAS, readRegs->linkStatCtrl)); | 561 | retVal = pciev1_read_linkStatCtrl_reg (&baseCfgEpRegs->PCIE_CAP_STRUC.LNK_CAS, readRegs->linkStatCtrl); |
550 | } | 562 | } |
551 | if (readRegs->slotCap) { | 563 | if ((retVal == pcie_RET_OK) && (readRegs->slotCap != NULL)) { |
552 | pcie_check_result(retVal, pciev1_read_slotCap_reg (baseCfgRcRegs, readRegs->slotCap)); | 564 | retVal = pciev1_read_slotCap_reg (baseCfgRcRegs, readRegs->slotCap); |
553 | } | 565 | } |
554 | if (readRegs->slotStatCtrl) { | 566 | if ((retVal == pcie_RET_OK) && (readRegs->slotStatCtrl != NULL)) { |
555 | pcie_check_result(retVal, pciev1_read_slotStatCtrl_reg (baseCfgRcRegs, readRegs->slotStatCtrl)); | 567 | retVal = pciev1_read_slotStatCtrl_reg (baseCfgRcRegs, readRegs->slotStatCtrl); |
556 | } | 568 | } |
557 | if (readRegs->rootCtrlCap) { | 569 | if ((retVal == pcie_RET_OK) && (readRegs->rootCtrlCap != NULL)) { |
558 | pcie_check_result(retVal, pciev1_read_rootCtrlCap_reg (baseCfgRcRegs, readRegs->rootCtrlCap)); | 570 | retVal = pciev1_read_rootCtrlCap_reg (baseCfgRcRegs, readRegs->rootCtrlCap); |
559 | } | 571 | } |
560 | if (readRegs->rootStatus) { | 572 | if ((retVal == pcie_RET_OK) && (readRegs->rootStatus != NULL)) { |
561 | pcie_check_result(retVal, pciev1_read_rootStatus_reg (baseCfgRcRegs, readRegs->rootStatus)); | 573 | retVal = pciev1_read_rootStatus_reg (baseCfgRcRegs, readRegs->rootStatus); |
562 | } | 574 | } |
563 | if (readRegs->devCap2) { | 575 | if ((retVal == pcie_RET_OK) && (readRegs->devCap2 != NULL)) { |
564 | pcie_check_result(retVal, pciev1_read_devCap2_reg (&baseCfgEpRegs->PCIE_CAP_STRUC.DEV_CAP_2, readRegs->devCap2)); | 576 | retVal = pciev1_read_devCap2_reg (&baseCfgEpRegs->PCIE_CAP_STRUC.DEV_CAP_2, readRegs->devCap2); |
565 | } | 577 | } |
566 | if (readRegs->devStatCtrl2) { | 578 | if ((retVal == pcie_RET_OK) && (readRegs->devStatCtrl2 != NULL)) { |
567 | pcie_check_result(retVal, pciev1_read_devStatCtrl2_reg (&baseCfgEpRegs->PCIE_CAP_STRUC.DEV_CAS_2, readRegs->devStatCtrl2)); | 579 | retVal = pciev1_read_devStatCtrl2_reg (&baseCfgEpRegs->PCIE_CAP_STRUC.DEV_CAS_2, readRegs->devStatCtrl2); |
568 | } | 580 | } |
569 | if (readRegs->linkCap2) { | 581 | if ((retVal == pcie_RET_OK) && (readRegs->linkCap2 != NULL)) { |
570 | pcie_check_result(retVal, pciev1_read_linkCap2_reg (&baseCfgEpRegs->PCIE_CAP_STRUC.LNK_CAP_2, readRegs->linkCap2)); | 582 | retVal = pciev1_read_linkCap2_reg (&baseCfgEpRegs->PCIE_CAP_STRUC.LNK_CAP_2, readRegs->linkCap2); |
571 | } | 583 | } |
572 | if (readRegs->linkCtrl2) { | 584 | if ((retVal == pcie_RET_OK) && (readRegs->linkCtrl2 != NULL)) { |
573 | pcie_check_result(retVal, pciev1_read_linkCtrl2_reg (&baseCfgEpRegs->PCIE_CAP_STRUC.LNK_CAS_2, readRegs->linkCtrl2)); | 585 | retVal = pciev1_read_linkCtrl2_reg (&baseCfgEpRegs->PCIE_CAP_STRUC.LNK_CAS_2, readRegs->linkCtrl2); |
574 | } | 586 | } |
575 | 587 | ||
576 | 588 | ||
577 | /*Capabilities Extended Registers*/ | 589 | /*Capabilities Extended Registers*/ |
578 | if (readRegs->extCap) { | 590 | if ((retVal == pcie_RET_OK) && (readRegs->extCap != NULL)) { |
579 | /* Not supported on rev 1 */ | 591 | /* Not supported on rev 1 */ |
580 | pcie_check_result(retVal, pcie_RET_INV_REG); | 592 | retVal = pcie_RET_INV_REG; |
581 | } | 593 | } |
582 | if (readRegs->uncErr) { | 594 | if ((retVal == pcie_RET_OK) && (readRegs->uncErr != NULL)) { |
583 | /* Not supported on rev 1 */ | 595 | /* Not supported on rev 1 */ |
584 | pcie_check_result(retVal, pcie_RET_INV_REG); | 596 | retVal = pcie_RET_INV_REG; |
585 | } | 597 | } |
586 | if (readRegs->uncErrMask) { | 598 | if ((retVal == pcie_RET_OK) && (readRegs->uncErrMask != NULL)) { |
587 | /* Not supported on rev 1 */ | 599 | /* Not supported on rev 1 */ |
588 | pcie_check_result(retVal, pcie_RET_INV_REG); | 600 | retVal = pcie_RET_INV_REG; |
589 | } | 601 | } |
590 | if (readRegs->uncErrSvrty) { | 602 | if ((retVal == pcie_RET_OK) && (readRegs->uncErrSvrty != NULL)) { |
591 | /* Not supported on rev 1 */ | 603 | /* Not supported on rev 1 */ |
592 | pcie_check_result(retVal, pcie_RET_INV_REG); | 604 | retVal = pcie_RET_INV_REG; |
593 | } | 605 | } |
594 | if (readRegs->corErr) { | 606 | if ((retVal == pcie_RET_OK) && (readRegs->corErr != NULL)) { |
595 | /* Not supported on rev 1 */ | 607 | /* Not supported on rev 1 */ |
596 | pcie_check_result(retVal, pcie_RET_INV_REG); | 608 | retVal = pcie_RET_INV_REG; |
597 | } | 609 | } |
598 | if (readRegs->corErrMask) { | 610 | if ((retVal == pcie_RET_OK) && (readRegs->corErrMask != NULL)) { |
599 | /* Not supported on rev 1 */ | 611 | /* Not supported on rev 1 */ |
600 | pcie_check_result(retVal, pcie_RET_INV_REG); | 612 | retVal = pcie_RET_INV_REG; |
601 | } | 613 | } |
602 | if (readRegs->accr) { | 614 | if ((retVal == pcie_RET_OK) && (readRegs->accr != NULL)) { |
603 | /* Not supported on rev 1 */ | 615 | /* Not supported on rev 1 */ |
604 | pcie_check_result(retVal, pcie_RET_INV_REG); | 616 | retVal = pcie_RET_INV_REG; |
605 | } | 617 | } |
606 | for (i = 0; i < 4; i ++) { | 618 | for (i = 0; i < 4; i ++) { |
607 | if (readRegs->hdrLog[i]) { | 619 | if ((retVal == pcie_RET_OK) && (readRegs->hdrLog[i] != NULL)) { |
608 | /* Not supported on rev 1 */ | 620 | /* Not supported on rev 1 */ |
609 | pcie_check_result(retVal, pcie_RET_INV_REG); | 621 | retVal = pcie_RET_INV_REG; |
610 | } | 622 | } |
611 | } | 623 | } |
612 | if (readRegs->rootErrCmd) { | 624 | if ((retVal == pcie_RET_OK) && (readRegs->rootErrCmd != NULL)) { |
613 | /* Not supported on rev 1 */ | 625 | /* Not supported on rev 1 */ |
614 | pcie_check_result(retVal, pcie_RET_INV_REG); | 626 | retVal = pcie_RET_INV_REG; |
615 | } | 627 | } |
616 | if (readRegs->rootErrSt) { | 628 | if ((retVal == pcie_RET_OK) && (readRegs->rootErrSt != NULL)) { |
617 | /* Not supported on rev 1 */ | 629 | /* Not supported on rev 1 */ |
618 | pcie_check_result(retVal, pcie_RET_INV_REG); | 630 | retVal = pcie_RET_INV_REG; |
619 | } | 631 | } |
620 | if (readRegs->errSrcID) { | 632 | if ((retVal == pcie_RET_OK) && (readRegs->errSrcID != NULL)) { |
621 | /* Not supported on rev 1 */ | 633 | /* Not supported on rev 1 */ |
622 | pcie_check_result(retVal, pcie_RET_INV_REG); | 634 | retVal = pcie_RET_INV_REG; |
623 | } | 635 | } |
624 | 636 | ||
625 | /*Port Logic Registers*/ | 637 | /*Port Logic Registers*/ |
626 | if (readRegs->plAckTimer) { | 638 | if ((retVal == pcie_RET_OK) && (readRegs->plAckTimer != NULL)) { |
627 | pcie_check_result(retVal, pciev1_read_plAckTimer_reg (baseCfgPlRegs, readRegs->plAckTimer)); | 639 | retVal = pciev1_read_plAckTimer_reg (baseCfgPlRegs, readRegs->plAckTimer); |
628 | } | 640 | } |
629 | if (readRegs->plOMsg) { | 641 | if ((retVal == pcie_RET_OK) && (readRegs->plOMsg != NULL)) { |
630 | pcie_check_result(retVal, pciev1_read_plOMsg_reg (baseCfgPlRegs, readRegs->plOMsg)); | 642 | retVal = pciev1_read_plOMsg_reg (baseCfgPlRegs, readRegs->plOMsg); |
631 | } | 643 | } |
632 | if (readRegs->plForceLink) { | 644 | if ((retVal == pcie_RET_OK) && (readRegs->plForceLink != NULL)) { |
633 | pcie_check_result(retVal, pciev1_read_plForceLink_reg (baseCfgPlRegs, readRegs->plForceLink)); | 645 | retVal = pciev1_read_plForceLink_reg (baseCfgPlRegs, readRegs->plForceLink); |
634 | } | 646 | } |
635 | if (readRegs->ackFreq) { | 647 | if ((retVal == pcie_RET_OK) && (readRegs->ackFreq != NULL)) { |
636 | pcie_check_result(retVal, pciev1_read_ackFreq_reg (baseCfgPlRegs, readRegs->ackFreq)); | 648 | retVal = pciev1_read_ackFreq_reg (baseCfgPlRegs, readRegs->ackFreq); |
637 | } | 649 | } |
638 | if (readRegs->lnkCtrl) { | 650 | if ((retVal == pcie_RET_OK) && (readRegs->lnkCtrl != NULL)) { |
639 | pcie_check_result(retVal, pciev1_read_lnkCtrl_reg (baseCfgPlRegs, readRegs->lnkCtrl)); | 651 | retVal = pciev1_read_lnkCtrl_reg (baseCfgPlRegs, readRegs->lnkCtrl); |
640 | } | 652 | } |
641 | if (readRegs->laneSkew) { | 653 | if ((retVal == pcie_RET_OK) && (readRegs->laneSkew != NULL)) { |
642 | pcie_check_result(retVal, pciev1_read_laneSkew_reg (baseCfgPlRegs, readRegs->laneSkew)); | 654 | retVal = pciev1_read_laneSkew_reg (baseCfgPlRegs, readRegs->laneSkew); |
643 | } | 655 | } |
644 | if (readRegs->symNum) { | 656 | if ((retVal == pcie_RET_OK) && (readRegs->symNum != NULL)) { |
645 | pcie_check_result(retVal, pciev1_read_symNum_reg (baseCfgPlRegs, readRegs->symNum)); | 657 | retVal = pciev1_read_symNum_reg (baseCfgPlRegs, readRegs->symNum); |
646 | } | 658 | } |
647 | if (readRegs->symTimerFltMask) { | 659 | if ((retVal == pcie_RET_OK) && (readRegs->symTimerFltMask != NULL)) { |
648 | pcie_check_result(retVal, pciev1_read_symTimerFltMask_reg (baseCfgPlRegs, readRegs->symTimerFltMask)); | 660 | retVal = pciev1_read_symTimerFltMask_reg (baseCfgPlRegs, readRegs->symTimerFltMask); |
649 | } | 661 | } |
650 | if (readRegs->fltMask2) { | 662 | if ((retVal == pcie_RET_OK) && (readRegs->fltMask2 != NULL)) { |
651 | pcie_check_result(retVal, pciev1_read_fltMask2_reg (baseCfgPlRegs, readRegs->fltMask2)); | 663 | retVal = pciev1_read_fltMask2_reg (baseCfgPlRegs, readRegs->fltMask2); |
652 | } | 664 | } |
653 | if (readRegs->debug0) { | 665 | if ((retVal == pcie_RET_OK) && (readRegs->debug0 != NULL)) { |
654 | /* Not supported on rev 1 */ | 666 | /* Not supported on rev 1 */ |
655 | pcie_check_result(retVal, pcie_RET_INV_REG); | 667 | retVal = pcie_RET_INV_REG; |
656 | } | 668 | } |
657 | if (readRegs->debug1) { | 669 | if ((retVal == pcie_RET_OK) && (readRegs->debug1 != NULL)) { |
658 | /* Not supported on rev 1 */ | 670 | /* Not supported on rev 1 */ |
659 | pcie_check_result(retVal, pcie_RET_INV_REG); | 671 | retVal = pcie_RET_INV_REG; |
660 | } | 672 | } |
661 | if (readRegs->gen2) { | 673 | if ((retVal == pcie_RET_OK) && (readRegs->gen2 != NULL)) { |
662 | pcie_check_result(retVal, pciev1_read_gen2_reg (baseCfgPlRegs, readRegs->gen2)); | 674 | retVal = pciev1_read_gen2_reg (baseCfgPlRegs, readRegs->gen2); |
663 | } | 675 | } |
664 | 676 | ||
665 | /* hw rev 1 PLCONF registers */ | 677 | /* hw rev 1 PLCONF registers */ |
666 | if (readRegs->plconfObnpSubreqCtrl) { | 678 | if ((retVal == pcie_RET_OK) && (readRegs->plconfObnpSubreqCtrl != NULL)) { |
667 | pcie_check_result(retVal, pciev1_read_plconfObnpSubreqCtrl_reg (baseCfgPlRegs, readRegs->plconfObnpSubreqCtrl)); | 679 | retVal = pciev1_read_plconfObnpSubreqCtrl_reg (baseCfgPlRegs, readRegs->plconfObnpSubreqCtrl); |
668 | } | 680 | } |
669 | if (readRegs->plconfTrPStsR) { | 681 | if ((retVal == pcie_RET_OK) && (readRegs->plconfTrPStsR != NULL)) { |
670 | pcie_check_result(retVal, pciev1_read_plconfTrPStsR_reg (baseCfgPlRegs, readRegs->plconfTrPStsR)); | 682 | retVal = pciev1_read_plconfTrPStsR_reg (baseCfgPlRegs, readRegs->plconfTrPStsR); |
671 | } | 683 | } |
672 | if (readRegs->plconfTrNpStsR) { | 684 | if ((retVal == pcie_RET_OK) && (readRegs->plconfTrNpStsR != NULL)) { |
673 | pcie_check_result(retVal, pciev1_read_plconfTrNpStsR_reg (baseCfgPlRegs, readRegs->plconfTrNpStsR)); | 685 | retVal = pciev1_read_plconfTrNpStsR_reg (baseCfgPlRegs, readRegs->plconfTrNpStsR); |
674 | } | 686 | } |
675 | if (readRegs->plconfTrCStsR) { | 687 | if ((retVal == pcie_RET_OK) && (readRegs->plconfTrCStsR != NULL)) { |
676 | pcie_check_result(retVal, pciev1_read_plconfTrCStsR_reg (baseCfgPlRegs, readRegs->plconfTrCStsR)); | 688 | retVal = pciev1_read_plconfTrCStsR_reg (baseCfgPlRegs, readRegs->plconfTrCStsR); |
677 | } | 689 | } |
678 | if (readRegs->plconfQStsR) { | 690 | if ((retVal == pcie_RET_OK) && (readRegs->plconfQStsR != NULL)) { |
679 | pcie_check_result(retVal, pciev1_read_plconfQStsR_reg (baseCfgPlRegs, readRegs->plconfQStsR)); | 691 | retVal = pciev1_read_plconfQStsR_reg (baseCfgPlRegs, readRegs->plconfQStsR); |
680 | } | 692 | } |
681 | if (readRegs->plconfVcTrAR1) { | 693 | if ((retVal == pcie_RET_OK) && (readRegs->plconfVcTrAR1 != NULL)) { |
682 | pcie_check_result(retVal, pciev1_read_plconfVcTrAR1_reg (baseCfgPlRegs, readRegs->plconfVcTrAR1)); | 694 | retVal = pciev1_read_plconfVcTrAR1_reg (baseCfgPlRegs, readRegs->plconfVcTrAR1); |
683 | } | 695 | } |
684 | if (readRegs->plconfVcTrAR2) { | 696 | if ((retVal == pcie_RET_OK) && (readRegs->plconfVcTrAR2 != NULL)) { |
685 | pcie_check_result(retVal, pciev1_read_plconfVcTrAR2_reg (baseCfgPlRegs, readRegs->plconfVcTrAR2)); | 697 | retVal = pciev1_read_plconfVcTrAR2_reg (baseCfgPlRegs, readRegs->plconfVcTrAR2); |
686 | } | 698 | } |
687 | if (readRegs->plconfVc0PrQC) { | 699 | if ((retVal == pcie_RET_OK) && (readRegs->plconfVc0PrQC != NULL)) { |
688 | pcie_check_result(retVal, pciev1_read_plconfVc0PrQC_reg (baseCfgPlRegs, readRegs->plconfVc0PrQC)); | 700 | retVal = pciev1_read_plconfVc0PrQC_reg (baseCfgPlRegs, readRegs->plconfVc0PrQC); |
689 | } | 701 | } |
690 | if (readRegs->plconfVc0NprQC) { | 702 | if ((retVal == pcie_RET_OK) && (readRegs->plconfVc0NprQC != NULL)) { |
691 | pcie_check_result(retVal, pciev1_read_plconfVc0NprQC_reg (baseCfgPlRegs, readRegs->plconfVc0NprQC)); | 703 | retVal = pciev1_read_plconfVc0NprQC_reg (baseCfgPlRegs, readRegs->plconfVc0NprQC); |
692 | } | 704 | } |
693 | if (readRegs->plconfVc0CrQC) { | 705 | if ((retVal == pcie_RET_OK) && (readRegs->plconfVc0CrQC != NULL)) { |
694 | pcie_check_result(retVal, pciev1_read_plconfVc0CrQC_reg (baseCfgPlRegs, readRegs->plconfVc0CrQC)); | 706 | retVal = pciev1_read_plconfVc0CrQC_reg (baseCfgPlRegs, readRegs->plconfVc0CrQC); |
695 | } | 707 | } |
696 | if (readRegs->plconfPhyStsR) { | 708 | if ((retVal == pcie_RET_OK) && (readRegs->plconfPhyStsR != NULL)) { |
697 | pcie_check_result(retVal, pciev1_read_plconfPhyStsR_reg (baseCfgPlRegs, readRegs->plconfPhyStsR)); | 709 | retVal = pciev1_read_plconfPhyStsR_reg (baseCfgPlRegs, readRegs->plconfPhyStsR); |
698 | } | 710 | } |
699 | if (readRegs->plconfPhyCtrlR) { | 711 | if ((retVal == pcie_RET_OK) && (readRegs->plconfPhyCtrlR != NULL)) { |
700 | pcie_check_result(retVal, pciev1_read_plconfPhyCtrlR_reg (baseCfgPlRegs, readRegs->plconfPhyCtrlR)); | 712 | retVal = pciev1_read_plconfPhyCtrlR_reg (baseCfgPlRegs, readRegs->plconfPhyCtrlR); |
701 | } | 713 | } |
702 | if (readRegs->plconfMsiCtrlAddress) { | 714 | if ((retVal == pcie_RET_OK) && (readRegs->plconfMsiCtrlAddress != NULL)) { |
703 | pcie_check_result(retVal, pciev1_read_plconfMsiCtrlAddress_reg (baseCfgPlRegs, readRegs->plconfMsiCtrlAddress)); | 715 | retVal = pciev1_read_plconfMsiCtrlAddress_reg (baseCfgPlRegs, readRegs->plconfMsiCtrlAddress); |
704 | } | 716 | } |
705 | if (readRegs->plconfMsiCtrlUpperAddress) { | 717 | if ((retVal == pcie_RET_OK) && (readRegs->plconfMsiCtrlUpperAddress != NULL)) { |
706 | pcie_check_result(retVal, pciev1_read_plconfMsiCtrlUpperAddress_reg (baseCfgPlRegs, readRegs->plconfMsiCtrlUpperAddress)); | 718 | retVal = pciev1_read_plconfMsiCtrlUpperAddress_reg (baseCfgPlRegs, readRegs->plconfMsiCtrlUpperAddress); |
707 | } | 719 | } |
708 | for (i = 0; i < 8; i++) { | 720 | for (i = 0; i < 8; i++) { |
709 | if (readRegs->plconfMsiCtrlIntEnable[i]) { | 721 | if ((retVal == pcie_RET_OK) && (readRegs->plconfMsiCtrlIntEnable[i] != NULL)) { |
710 | pcie_check_result(retVal, pciev1_read_plconfMsiCtrlIntEnable_reg (baseCfgPlRegs, readRegs->plconfMsiCtrlIntEnable[i], i)); | 722 | retVal = pciev1_read_plconfMsiCtrlIntEnable_reg (baseCfgPlRegs, readRegs->plconfMsiCtrlIntEnable[i], i); |
711 | } | 723 | } |
712 | if (readRegs->plconfMsiCtrlIntMask[i]) { | 724 | if ((retVal == pcie_RET_OK) && (readRegs->plconfMsiCtrlIntMask[i] != NULL)) { |
713 | pcie_check_result(retVal, pciev1_read_plconfMsiCtrlIntMask_reg (baseCfgPlRegs, readRegs->plconfMsiCtrlIntMask[i], i)); | 725 | retVal = pciev1_read_plconfMsiCtrlIntMask_reg (baseCfgPlRegs, readRegs->plconfMsiCtrlIntMask[i], i); |
714 | } | 726 | } |
715 | if (readRegs->plconfMsiCtrlIntStatus[i]) { | 727 | if ((retVal == pcie_RET_OK) && (readRegs->plconfMsiCtrlIntStatus[i] != NULL)) { |
716 | pcie_check_result(retVal, pciev1_read_plconfMsiCtrlIntStatus_reg (baseCfgPlRegs, readRegs->plconfMsiCtrlIntStatus[i], i)); | 728 | retVal = pciev1_read_plconfMsiCtrlIntStatus_reg (baseCfgPlRegs, readRegs->plconfMsiCtrlIntStatus[i], i); |
717 | } | 729 | } |
718 | } | 730 | } |
719 | if (readRegs->plconfMsiCtrlGpio) { | 731 | if ((retVal == pcie_RET_OK) && (readRegs->plconfMsiCtrlGpio != NULL)) { |
720 | pcie_check_result(retVal, pciev1_read_plconfMsiCtrlGpio_reg (baseCfgPlRegs, readRegs->plconfMsiCtrlGpio)); | 732 | retVal = pciev1_read_plconfMsiCtrlGpio_reg (baseCfgPlRegs, readRegs->plconfMsiCtrlGpio); |
721 | } | 733 | } |
722 | if (readRegs->plconfPipeLoopback) { | 734 | if ((retVal == pcie_RET_OK) && (readRegs->plconfPipeLoopback != NULL)) { |
723 | pcie_check_result(retVal, pciev1_read_plconfPipeLoopback_reg (baseCfgPlRegs, readRegs->plconfPipeLoopback)); | 735 | retVal = pciev1_read_plconfPipeLoopback_reg (baseCfgPlRegs, readRegs->plconfPipeLoopback); |
724 | } | 736 | } |
725 | if (readRegs->plconfDbiRoWrEn) { | 737 | if ((retVal == pcie_RET_OK) && (readRegs->plconfDbiRoWrEn != NULL)) { |
726 | pcie_check_result(retVal, pciev1_read_plconfDbiRoWrEn_reg (baseCfgPlRegs, readRegs->plconfDbiRoWrEn)); | 738 | retVal = pciev1_read_plconfDbiRoWrEn_reg (baseCfgPlRegs, readRegs->plconfDbiRoWrEn); |
727 | } | 739 | } |
728 | if (readRegs->plconfAxiSlvErrResp) { | 740 | if ((retVal == pcie_RET_OK) && (readRegs->plconfAxiSlvErrResp != NULL)) { |
729 | pcie_check_result(retVal, pciev1_read_plconfAxiSlvErrResp_reg (baseCfgPlRegs, readRegs->plconfAxiSlvErrResp)); | 741 | retVal = pciev1_read_plconfAxiSlvErrResp_reg (baseCfgPlRegs, readRegs->plconfAxiSlvErrResp); |
730 | } | 742 | } |
731 | if (readRegs->plconfAxiSlvTimeout) { | 743 | if ((retVal == pcie_RET_OK) && (readRegs->plconfAxiSlvTimeout != NULL)) { |
732 | pcie_check_result(retVal, pciev1_read_plconfAxiSlvTimeout_reg (baseCfgPlRegs, readRegs->plconfAxiSlvTimeout)); | 744 | retVal = pciev1_read_plconfAxiSlvTimeout_reg (baseCfgPlRegs, readRegs->plconfAxiSlvTimeout); |
733 | } | 745 | } |
734 | if (readRegs->plconfIatuIndex) { | 746 | if ((retVal == pcie_RET_OK) && (readRegs->plconfIatuIndex != NULL)) { |
735 | pcie_check_result(retVal, pciev1_read_plconfIatuIndex_reg (baseCfgPlRegs, readRegs->plconfIatuIndex)); | 747 | retVal = pciev1_read_plconfIatuIndex_reg (baseCfgPlRegs, readRegs->plconfIatuIndex); |
736 | } | 748 | } |
737 | if (readRegs->plconfIatuRegCtrl1) { | 749 | if ((retVal == pcie_RET_OK) && (readRegs->plconfIatuRegCtrl1 != NULL)) { |
738 | pcie_check_result(retVal, pciev1_read_plconfIatuRegCtrl1_reg (baseCfgPlRegs, readRegs->plconfIatuRegCtrl1)); | 750 | retVal = pciev1_read_plconfIatuRegCtrl1_reg (baseCfgPlRegs, readRegs->plconfIatuRegCtrl1); |
739 | } | 751 | } |
740 | if (readRegs->plconfIatuRegCtrl2) { | 752 | if ((retVal == pcie_RET_OK) && (readRegs->plconfIatuRegCtrl2 != NULL)) { |
741 | pcie_check_result(retVal, pciev1_read_plconfIatuRegCtrl2_reg (baseCfgPlRegs, readRegs->plconfIatuRegCtrl2)); | 753 | retVal = pciev1_read_plconfIatuRegCtrl2_reg (baseCfgPlRegs, readRegs->plconfIatuRegCtrl2); |
742 | } | 754 | } |
743 | if (readRegs->plconfIatuRegLowerBase) { | 755 | if ((retVal == pcie_RET_OK) && (readRegs->plconfIatuRegLowerBase != NULL)) { |
744 | pcie_check_result(retVal, pciev1_read_plconfIatuRegLowerBase_reg (baseCfgPlRegs, readRegs->plconfIatuRegLowerBase)); | 756 | retVal = pciev1_read_plconfIatuRegLowerBase_reg (baseCfgPlRegs, readRegs->plconfIatuRegLowerBase); |
745 | } | 757 | } |
746 | if (readRegs->plconfIatuRegUpperBase) { | 758 | if ((retVal == pcie_RET_OK) && (readRegs->plconfIatuRegUpperBase != NULL)) { |
747 | pcie_check_result(retVal, pciev1_read_plconfIatuRegUpperBase_reg (baseCfgPlRegs, readRegs->plconfIatuRegUpperBase)); | 759 | retVal = pciev1_read_plconfIatuRegUpperBase_reg (baseCfgPlRegs, readRegs->plconfIatuRegUpperBase); |
748 | } | 760 | } |
749 | if (readRegs->plconfIatuRegLimit) { | 761 | if ((retVal == pcie_RET_OK) && (readRegs->plconfIatuRegLimit != NULL)) { |
750 | pcie_check_result(retVal, pciev1_read_plconfIatuRegLimit_reg (baseCfgPlRegs, readRegs->plconfIatuRegLimit)); | 762 | retVal = pciev1_read_plconfIatuRegLimit_reg (baseCfgPlRegs, readRegs->plconfIatuRegLimit); |
751 | } | 763 | } |
752 | if (readRegs->plconfIatuRegLowerTarget) { | 764 | if ((retVal == pcie_RET_OK) && (readRegs->plconfIatuRegLowerTarget != NULL)) { |
753 | pcie_check_result(retVal, pciev1_read_plconfIatuRegLowerTarget_reg (baseCfgPlRegs, readRegs->plconfIatuRegLowerTarget)); | 765 | retVal = pciev1_read_plconfIatuRegLowerTarget_reg (baseCfgPlRegs, readRegs->plconfIatuRegLowerTarget); |
754 | } | 766 | } |
755 | if (readRegs->plconfIatuRegUpperTarget) { | 767 | if ((retVal == pcie_RET_OK) && (readRegs->plconfIatuRegUpperTarget != NULL)) { |
756 | pcie_check_result(retVal, pciev1_read_plconfIatuRegUpperTarget_reg (baseCfgPlRegs, readRegs->plconfIatuRegUpperTarget)); | 768 | retVal = pciev1_read_plconfIatuRegUpperTarget_reg (baseCfgPlRegs, readRegs->plconfIatuRegUpperTarget); |
757 | } | 769 | } |
758 | if (readRegs->plconfIatuRegCtrl3) { | 770 | if ((retVal == pcie_RET_OK) && (readRegs->plconfIatuRegCtrl3 != NULL)) { |
759 | pcie_check_result(retVal, pciev1_read_plconfIatuRegCtrl3_reg (baseCfgPlRegs, readRegs->plconfIatuRegCtrl3)); | 771 | retVal = pciev1_read_plconfIatuRegCtrl3_reg (baseCfgPlRegs, readRegs->plconfIatuRegCtrl3); |
760 | } | 772 | } |
761 | 773 | ||
762 | 774 | ||
763 | /* TI CONF registers */ | 775 | /* TI CONF registers */ |
764 | if (readRegs->tiConfRevision) { | 776 | if ((retVal == pcie_RET_OK) && (readRegs->tiConfRevision != NULL)) { |
765 | pcie_check_result(retVal, pciev1_read_tiConfRevision_reg (baseCfgTiConfRegs, readRegs->tiConfRevision)); | 777 | retVal = pciev1_read_tiConfRevision_reg (baseCfgTiConfRegs, readRegs->tiConfRevision); |
766 | } | 778 | } |
767 | if (readRegs->tiConfSysConfig) { | 779 | if ((retVal == pcie_RET_OK) && (readRegs->tiConfSysConfig != NULL)) { |
768 | pcie_check_result(retVal, pciev1_read_tiConfSysConfig_reg (baseCfgTiConfRegs, readRegs->tiConfSysConfig)); | 780 | retVal = pciev1_read_tiConfSysConfig_reg (baseCfgTiConfRegs, readRegs->tiConfSysConfig); |
769 | } | 781 | } |
770 | if (readRegs->tiConfIrqEoi) { | 782 | if ((retVal == pcie_RET_OK) && (readRegs->tiConfIrqEoi != NULL)) { |
771 | pcie_check_result(retVal, pciev1_read_tiConfIrqEoi_reg (baseCfgTiConfRegs, readRegs->tiConfIrqEoi)); | 783 | retVal = pciev1_read_tiConfIrqEoi_reg (baseCfgTiConfRegs, readRegs->tiConfIrqEoi); |
772 | } | 784 | } |
773 | if (readRegs->tiConfIrqStatusRawMain) { | 785 | if ((retVal == pcie_RET_OK) && (readRegs->tiConfIrqStatusRawMain != NULL)) { |
774 | pcie_check_result(retVal, pciev1_read_tiConfIrqStatusRawMain_reg (baseCfgTiConfRegs, readRegs->tiConfIrqStatusRawMain)); | 786 | retVal = pciev1_read_tiConfIrqStatusRawMain_reg (baseCfgTiConfRegs, readRegs->tiConfIrqStatusRawMain); |
775 | } | 787 | } |
776 | if (readRegs->tiConfIrqStatusMain) { | 788 | if ((retVal == pcie_RET_OK) && (readRegs->tiConfIrqStatusMain != NULL)) { |
777 | pcie_check_result(retVal, pciev1_read_tiConfIrqStatusMain_reg (baseCfgTiConfRegs, readRegs->tiConfIrqStatusMain)); | 789 | retVal = pciev1_read_tiConfIrqStatusMain_reg (baseCfgTiConfRegs, readRegs->tiConfIrqStatusMain); |
778 | } | 790 | } |
779 | if (readRegs->tiConfIrqEnableSetMain) { | 791 | if ((retVal == pcie_RET_OK) && (readRegs->tiConfIrqEnableSetMain != NULL)) { |
780 | pcie_check_result(retVal, pciev1_read_tiConfIrqEnableSetMain_reg (baseCfgTiConfRegs, readRegs->tiConfIrqEnableSetMain)); | 792 | retVal = pciev1_read_tiConfIrqEnableSetMain_reg (baseCfgTiConfRegs, readRegs->tiConfIrqEnableSetMain); |
781 | } | 793 | } |
782 | if (readRegs->tiConfIrqEnableClrMain) { | 794 | if ((retVal == pcie_RET_OK) && (readRegs->tiConfIrqEnableClrMain != NULL)) { |
783 | pcie_check_result(retVal, pciev1_read_tiConfIrqEnableClrMain_reg (baseCfgTiConfRegs, readRegs->tiConfIrqEnableClrMain)); | 795 | retVal = pciev1_read_tiConfIrqEnableClrMain_reg (baseCfgTiConfRegs, readRegs->tiConfIrqEnableClrMain); |
784 | } | 796 | } |
785 | if (readRegs->tiConfIrqStatusRawMsi) { | 797 | if ((retVal == pcie_RET_OK) && (readRegs->tiConfIrqStatusRawMsi != NULL)) { |
786 | pcie_check_result(retVal, pciev1_read_tiConfIrqStatusRawMsi_reg (baseCfgTiConfRegs, readRegs->tiConfIrqStatusRawMsi)); | 798 | retVal = pciev1_read_tiConfIrqStatusRawMsi_reg (baseCfgTiConfRegs, readRegs->tiConfIrqStatusRawMsi); |
787 | } | 799 | } |
788 | if (readRegs->tiConfIrqStatusMsi) { | 800 | if ((retVal == pcie_RET_OK) && (readRegs->tiConfIrqStatusMsi != NULL)) { |
789 | pcie_check_result(retVal, pciev1_read_tiConfIrqStatusMsi_reg (baseCfgTiConfRegs, readRegs->tiConfIrqStatusMsi)); | 801 | retVal = pciev1_read_tiConfIrqStatusMsi_reg (baseCfgTiConfRegs, readRegs->tiConfIrqStatusMsi); |
790 | } | 802 | } |
791 | if (readRegs->tiConfIrqEnableSetMsi) { | 803 | if ((retVal == pcie_RET_OK) && (readRegs->tiConfIrqEnableSetMsi != NULL)) { |
792 | pcie_check_result(retVal, pciev1_read_tiConfIrqEnableSetMsi_reg (baseCfgTiConfRegs, readRegs->tiConfIrqEnableSetMsi)); | 804 | retVal = pciev1_read_tiConfIrqEnableSetMsi_reg (baseCfgTiConfRegs, readRegs->tiConfIrqEnableSetMsi); |
793 | } | 805 | } |
794 | if (readRegs->tiConfIrqEnableClrMsi) { | 806 | if ((retVal == pcie_RET_OK) && (readRegs->tiConfIrqEnableClrMsi != NULL)) { |
795 | pcie_check_result(retVal, pciev1_read_tiConfIrqEnableClrMsi_reg (baseCfgTiConfRegs, readRegs->tiConfIrqEnableClrMsi)); | 807 | retVal = pciev1_read_tiConfIrqEnableClrMsi_reg (baseCfgTiConfRegs, readRegs->tiConfIrqEnableClrMsi); |
796 | } | 808 | } |
797 | if (readRegs->tiConfDeviceType) { | 809 | if ((retVal == pcie_RET_OK) && (readRegs->tiConfDeviceType != NULL)) { |
798 | pcie_check_result(retVal, pciev1_read_tiConfDeviceType_reg (baseCfgTiConfRegs, readRegs->tiConfDeviceType)); | 810 | retVal = pciev1_read_tiConfDeviceType_reg (baseCfgTiConfRegs, readRegs->tiConfDeviceType); |
799 | } | 811 | } |
800 | if (readRegs->tiConfDeviceCmd) { | 812 | if ((retVal == pcie_RET_OK) && (readRegs->tiConfDeviceCmd != NULL)) { |
801 | pcie_check_result(retVal, pciev1_read_tiConfDeviceCmd_reg (baseCfgTiConfRegs, readRegs->tiConfDeviceCmd)); | 813 | retVal = pciev1_read_tiConfDeviceCmd_reg (baseCfgTiConfRegs, readRegs->tiConfDeviceCmd); |
802 | } | 814 | } |
803 | if (readRegs->tiConfPmCtrl) { | 815 | if ((retVal == pcie_RET_OK) && (readRegs->tiConfPmCtrl != NULL)) { |
804 | pcie_check_result(retVal, pciev1_read_tiConfPmCtrl_reg (baseCfgTiConfRegs, readRegs->tiConfPmCtrl)); | 816 | retVal = pciev1_read_tiConfPmCtrl_reg (baseCfgTiConfRegs, readRegs->tiConfPmCtrl); |
805 | } | 817 | } |
806 | if (readRegs->tiConfPhyCs) { | 818 | if ((retVal == pcie_RET_OK) && (readRegs->tiConfPhyCs != NULL)) { |
807 | pcie_check_result(retVal, pciev1_read_tiConfPhyCs_reg (baseCfgTiConfRegs, readRegs->tiConfPhyCs)); | 819 | retVal = pciev1_read_tiConfPhyCs_reg (baseCfgTiConfRegs, readRegs->tiConfPhyCs); |
808 | } | 820 | } |
809 | if (readRegs->tiConfIntxAssert) { | 821 | if ((retVal == pcie_RET_OK) && (readRegs->tiConfIntxAssert != NULL)) { |
810 | pcie_check_result(retVal, pciev1_read_tiConfIntxAssert_reg (baseCfgTiConfRegs, readRegs->tiConfIntxAssert)); | 822 | retVal = pciev1_read_tiConfIntxAssert_reg (baseCfgTiConfRegs, readRegs->tiConfIntxAssert); |
811 | } | 823 | } |
812 | if (readRegs->tiConfIntxDeassert) { | 824 | if ((retVal == pcie_RET_OK) && (readRegs->tiConfIntxDeassert != NULL)) { |
813 | pcie_check_result(retVal, pciev1_read_tiConfIntxDeassert_reg (baseCfgTiConfRegs, readRegs->tiConfIntxDeassert)); | 825 | retVal = pciev1_read_tiConfIntxDeassert_reg (baseCfgTiConfRegs, readRegs->tiConfIntxDeassert); |
814 | } | 826 | } |
815 | if (readRegs->tiConfMsiXmt) { | 827 | if ((retVal == pcie_RET_OK) && (readRegs->tiConfMsiXmt != NULL)) { |
816 | pcie_check_result(retVal, pciev1_read_tiConfMsiXmt_reg (baseCfgTiConfRegs, readRegs->tiConfMsiXmt)); | 828 | retVal = pciev1_read_tiConfMsiXmt_reg (baseCfgTiConfRegs, readRegs->tiConfMsiXmt); |
817 | } | 829 | } |
818 | if (readRegs->tiConfDebugCfg) { | 830 | if ((retVal == pcie_RET_OK) && (readRegs->tiConfDebugCfg != NULL)) { |
819 | pcie_check_result(retVal, pciev1_read_tiConfDebugCfg_reg (baseCfgTiConfRegs, readRegs->tiConfDebugCfg)); | 831 | retVal = pciev1_read_tiConfDebugCfg_reg (baseCfgTiConfRegs, readRegs->tiConfDebugCfg); |
820 | } | 832 | } |
821 | if (readRegs->tiConfDebugData) { | 833 | if ((retVal == pcie_RET_OK) && (readRegs->tiConfDebugData != NULL)) { |
822 | pcie_check_result(retVal, pciev1_read_tiConfDebugData_reg (baseCfgTiConfRegs, readRegs->tiConfDebugData)); | 834 | retVal = pciev1_read_tiConfDebugData_reg (baseCfgTiConfRegs, readRegs->tiConfDebugData); |
823 | } | 835 | } |
824 | if (readRegs->tiConfDiagCtrl) { | 836 | if ((retVal == pcie_RET_OK) && (readRegs->tiConfDiagCtrl != NULL)) { |
825 | pcie_check_result(retVal, pciev1_read_tiConfDiagCtrl_reg (baseCfgTiConfRegs, readRegs->tiConfDiagCtrl)); | 837 | retVal = pciev1_read_tiConfDiagCtrl_reg (baseCfgTiConfRegs, readRegs->tiConfDiagCtrl); |
826 | } | 838 | } |
827 | 839 | ||
828 | return retVal; | 840 | return retVal; |
@@ -855,211 +867,214 @@ pcieRet_e Pciev1_writeRegs | |||
855 | int32_t i; | 867 | int32_t i; |
856 | 868 | ||
857 | if (pcieLObjIsValid == 0) { | 869 | if (pcieLObjIsValid == 0) { |
858 | return pcie_RET_NO_INIT; | 870 | retVal = pcie_RET_NO_INIT; |
859 | } | 871 | } |
860 | 872 | else { | |
861 | pcie_check_handle(handle); | 873 | if (pcie_check_handle_fcn(handle) == 0) { |
862 | 874 | retVal = pcie_RET_INV_HANDLE; | |
863 | /* Get base address for Local/Remote config space */ | 875 | } |
864 | if (location != pcie_LOCATION_LOCAL) | 876 | else { |
865 | { | 877 | /* Get base address for Local/Remote config space */ |
866 | char *remoteBase = (char *)cfg->dataBase + bases->remoteOffset; | 878 | if (location != pcie_LOCATION_LOCAL) |
867 | uint32_t delta = 0; | 879 | { |
868 | baseCfgRcRegs = (CSL_RcCfgDbIcsRegs *)(remoteBase + delta); | 880 | char *remoteBase = (char *)cfg->dataBase + bases->remoteOffset; |
869 | baseCfgEpRegs = (CSL_EpCfgDbIcsRegs *)(remoteBase + delta); | 881 | uint32_t delta = 0; |
870 | delta = (char *)bases->plConf - (char *)bases->rcDbics; | 882 | baseCfgRcRegs = (CSL_RcCfgDbIcsRegs *)(remoteBase + delta); |
871 | baseCfgPlRegs = (CSL_PlConfRegs *) (remoteBase + delta); | 883 | baseCfgEpRegs = (CSL_EpCfgDbIcsRegs *)(remoteBase + delta); |
884 | delta = (char *)bases->plConf - (char *)bases->rcDbics; | ||
885 | baseCfgPlRegs = (CSL_PlConfRegs *) (remoteBase + delta); | ||
886 | } | ||
887 | } | ||
872 | } | 888 | } |
873 | |||
874 | /***************************************************************************************** | 889 | /***************************************************************************************** |
875 | * Reject hw rev 0 app registers (these are similar but not identical to TI CONF on rev 1) | 890 | * Reject hw rev 0 app registers (these are similar but not identical to TI CONF on rev 1) |
876 | *****************************************************************************************/ | 891 | *****************************************************************************************/ |
877 | if (writeRegs->cmdStatus) { | 892 | if ((retVal == pcie_RET_OK) && (writeRegs->cmdStatus != NULL)) { |
878 | /* Not supported on rev 1 */ | 893 | /* Not supported on rev 1 */ |
879 | pcie_check_result(retVal, pcie_RET_INV_REG); | 894 | retVal = pcie_RET_INV_REG; |
880 | } | 895 | } |
881 | if (writeRegs->cfgTrans) { | 896 | if ((retVal == pcie_RET_OK) && (writeRegs->cfgTrans != NULL)) { |
882 | /* Not supported on rev 1 */ | 897 | /* Not supported on rev 1 */ |
883 | pcie_check_result(retVal, pcie_RET_INV_REG); | 898 | retVal = pcie_RET_INV_REG; |
884 | } | 899 | } |
885 | if (writeRegs->ioBase) { | 900 | if ((retVal == pcie_RET_OK) && (writeRegs->ioBase != NULL)) { |
886 | /* Not supported on rev 1 */ | 901 | /* Not supported on rev 1 */ |
887 | pcie_check_result(retVal, pcie_RET_INV_REG); | 902 | retVal = pcie_RET_INV_REG; |
888 | } | 903 | } |
889 | if (writeRegs->tlpCfg) { | 904 | if ((retVal == pcie_RET_OK) && (writeRegs->tlpCfg != NULL)) { |
890 | /* Not supported on rev 1 */ | 905 | /* Not supported on rev 1 */ |
891 | pcie_check_result(retVal, pcie_RET_INV_REG); | 906 | retVal = pcie_RET_INV_REG; |
892 | } | 907 | } |
893 | if (writeRegs->rstCmd) { | 908 | if ((retVal == pcie_RET_OK) && (writeRegs->rstCmd != NULL)) { |
894 | /* Not supported on rev 1 */ | 909 | /* Not supported on rev 1 */ |
895 | pcie_check_result(retVal, pcie_RET_INV_REG); | 910 | retVal = pcie_RET_INV_REG; |
896 | } | 911 | } |
897 | if (writeRegs->pmCmd) { | 912 | if ((retVal == pcie_RET_OK) && (writeRegs->pmCmd != NULL)) { |
898 | /* Not supported on rev 1 */ | 913 | /* Not supported on rev 1 */ |
899 | pcie_check_result(retVal, pcie_RET_INV_REG); | 914 | retVal = pcie_RET_INV_REG; |
900 | } | 915 | } |
901 | if (writeRegs->pmCfg) { | 916 | if ((retVal == pcie_RET_OK) && (writeRegs->pmCfg != NULL)) { |
902 | /* Not supported on rev 1 */ | 917 | /* Not supported on rev 1 */ |
903 | pcie_check_result(retVal, pcie_RET_INV_REG); | 918 | retVal = pcie_RET_INV_REG; |
904 | } | 919 | } |
905 | if (writeRegs->obSize) { | 920 | if ((retVal == pcie_RET_OK) && (writeRegs->obSize != NULL)) { |
906 | /* Not supported on rev 1 */ | 921 | /* Not supported on rev 1 */ |
907 | pcie_check_result(retVal, pcie_RET_INV_REG); | 922 | retVal = pcie_RET_INV_REG; |
908 | } | 923 | } |
909 | if (writeRegs->diagCtrl) { | 924 | if ((retVal == pcie_RET_OK) && (writeRegs->diagCtrl != NULL)) { |
910 | /* Not supported on rev 1 */ | 925 | /* Not supported on rev 1 */ |
911 | pcie_check_result(retVal, pcie_RET_INV_REG); | 926 | retVal = pcie_RET_INV_REG; |
912 | } | 927 | } |
913 | if (writeRegs->endian) { | 928 | if ((retVal == pcie_RET_OK) && (writeRegs->endian != NULL)) { |
914 | /* Not supported on rev 1 */ | 929 | /* Not supported on rev 1 */ |
915 | pcie_check_result(retVal, pcie_RET_INV_REG); | 930 | retVal = pcie_RET_INV_REG; |
916 | } | 931 | } |
917 | if (writeRegs->priority) { | 932 | if ((retVal == pcie_RET_OK) && (writeRegs->priority != NULL)) { |
918 | /* Not supported on rev 1 */ | 933 | /* Not supported on rev 1 */ |
919 | pcie_check_result(retVal, pcie_RET_INV_REG); | 934 | retVal = pcie_RET_INV_REG; |
920 | } | 935 | } |
921 | if (writeRegs->irqEOI) { | 936 | if ((retVal == pcie_RET_OK) && (writeRegs->irqEOI != NULL)) { |
922 | /* Not supported on rev 1 */ | 937 | /* Not supported on rev 1 */ |
923 | pcie_check_result(retVal, pcie_RET_INV_REG); | 938 | retVal = pcie_RET_INV_REG; |
924 | } | 939 | } |
925 | if (writeRegs->msiIrq) { | 940 | if ((retVal == pcie_RET_OK) && (writeRegs->msiIrq != NULL)) { |
926 | /* Not supported on rev 1 */ | 941 | /* Not supported on rev 1 */ |
927 | pcie_check_result(retVal, pcie_RET_INV_REG); | 942 | retVal = pcie_RET_INV_REG; |
928 | } | 943 | } |
929 | if (writeRegs->epIrqSet) { | 944 | if ((retVal == pcie_RET_OK) && (writeRegs->epIrqSet != NULL)) { |
930 | /* Not supported on rev 1 */ | 945 | /* Not supported on rev 1 */ |
931 | pcie_check_result(retVal, pcie_RET_INV_REG); | 946 | retVal = pcie_RET_INV_REG; |
932 | } | 947 | } |
933 | if (writeRegs->epIrqClr) { | 948 | if ((retVal == pcie_RET_OK) && (writeRegs->epIrqClr != NULL)) { |
934 | /* Not supported on rev 1 */ | 949 | /* Not supported on rev 1 */ |
935 | pcie_check_result(retVal, pcie_RET_INV_REG); | 950 | retVal = pcie_RET_INV_REG; |
936 | } | 951 | } |
937 | if (writeRegs->epIrqStatus) { | 952 | if ((retVal == pcie_RET_OK) && (writeRegs->epIrqStatus != NULL)) { |
938 | /* Not supported on rev 1 */ | 953 | /* Not supported on rev 1 */ |
939 | pcie_check_result(retVal, pcie_RET_INV_REG); | 954 | retVal = pcie_RET_INV_REG; |
940 | } | 955 | } |
941 | for (i = 0; i < 4; i++) { | 956 | for (i = 0; i < 4; i++) { |
942 | if (writeRegs->genPurpose[i]) { | 957 | if ((retVal == pcie_RET_OK) && (writeRegs->genPurpose[i] != NULL)) { |
943 | /* Not supported on rev 1 */ | 958 | /* Not supported on rev 1 */ |
944 | pcie_check_result(retVal, pcie_RET_INV_REG); | 959 | retVal = pcie_RET_INV_REG; |
945 | } | 960 | } |
946 | } | 961 | } |
947 | for (i = 0; i < 8; i++) { | 962 | for (i = 0; i < 8; i++) { |
948 | if (writeRegs->msiIrqStatusRaw[i]) { | 963 | if ((retVal == pcie_RET_OK) && (writeRegs->msiIrqStatusRaw[i] != NULL)) { |
949 | /* Not supported on rev 1 */ | 964 | /* Not supported on rev 1 */ |
950 | pcie_check_result(retVal, pcie_RET_INV_REG); | 965 | retVal = pcie_RET_INV_REG; |
951 | } | 966 | } |
952 | if (writeRegs->msiIrqStatus[i]) { | 967 | if ((retVal == pcie_RET_OK) && (writeRegs->msiIrqStatus[i] != NULL)) { |
953 | /* Not supported on rev 1 */ | 968 | /* Not supported on rev 1 */ |
954 | pcie_check_result(retVal, pcie_RET_INV_REG); | 969 | retVal = pcie_RET_INV_REG; |
955 | } | 970 | } |
956 | if (writeRegs->msiIrqEnableSet[i]) { | 971 | if ((retVal == pcie_RET_OK) && (writeRegs->msiIrqEnableSet[i] != NULL)) { |
957 | /* Not supported on rev 1 */ | 972 | /* Not supported on rev 1 */ |
958 | pcie_check_result(retVal, pcie_RET_INV_REG); | 973 | retVal = pcie_RET_INV_REG; |
959 | } | 974 | } |
960 | if (writeRegs->msiIrqEnableClr[i]) { | 975 | if ((retVal == pcie_RET_OK) && (writeRegs->msiIrqEnableClr[i] != NULL)) { |
961 | /* Not supported on rev 1 */ | 976 | /* Not supported on rev 1 */ |
962 | pcie_check_result(retVal, pcie_RET_INV_REG); | 977 | retVal = pcie_RET_INV_REG; |
963 | } | 978 | } |
964 | } | 979 | } |
965 | for (i = 0; i < 4; i++) { | 980 | for (i = 0; i < 4; i++) { |
966 | if (writeRegs->legacyIrqStatusRaw[i]) { | 981 | if ((retVal == pcie_RET_OK) && (writeRegs->legacyIrqStatusRaw[i] != NULL)) { |
967 | /* Not supported on rev 1 */ | 982 | /* Not supported on rev 1 */ |
968 | pcie_check_result(retVal, pcie_RET_INV_REG); | 983 | retVal = pcie_RET_INV_REG; |
969 | } | 984 | } |
970 | if (writeRegs->legacyIrqStatus[i]) { | 985 | if ((retVal == pcie_RET_OK) && (writeRegs->legacyIrqStatus[i] != NULL)) { |
971 | /* Not supported on rev 1 */ | 986 | /* Not supported on rev 1 */ |
972 | pcie_check_result(retVal, pcie_RET_INV_REG); | 987 | retVal = pcie_RET_INV_REG; |
973 | } | 988 | } |
974 | if (writeRegs->legacyIrqEnableSet[i]) { | 989 | if ((retVal == pcie_RET_OK) && (writeRegs->legacyIrqEnableSet[i] != NULL)) { |
975 | /* Not supported on rev 1 */ | 990 | /* Not supported on rev 1 */ |
976 | pcie_check_result(retVal, pcie_RET_INV_REG); | 991 | retVal = pcie_RET_INV_REG; |
977 | } | 992 | } |
978 | if (writeRegs->legacyIrqEnableClr[i]) { | 993 | if ((retVal == pcie_RET_OK) && (writeRegs->legacyIrqEnableClr[i] != NULL)) { |
979 | /* Not supported on rev 1 */ | 994 | /* Not supported on rev 1 */ |
980 | pcie_check_result(retVal, pcie_RET_INV_REG); | 995 | retVal = pcie_RET_INV_REG; |
981 | } | 996 | } |
982 | } | 997 | } |
983 | if (writeRegs->errIrqStatusRaw) { | 998 | if ((retVal == pcie_RET_OK) && (writeRegs->errIrqStatusRaw != NULL)) { |
984 | /* Not supported on rev 1 */ | 999 | /* Not supported on rev 1 */ |
985 | pcie_check_result(retVal, pcie_RET_INV_REG); | 1000 | retVal = pcie_RET_INV_REG; |
986 | } | 1001 | } |
987 | if (writeRegs->errIrqStatus) { | 1002 | if ((retVal == pcie_RET_OK) && (writeRegs->errIrqStatus != NULL)) { |
988 | /* Not supported on rev 1 */ | 1003 | /* Not supported on rev 1 */ |
989 | pcie_check_result(retVal, pcie_RET_INV_REG); | 1004 | retVal = pcie_RET_INV_REG; |
990 | } | 1005 | } |
991 | if (writeRegs->errIrqEnableSet) { | 1006 | if ((retVal == pcie_RET_OK) && (writeRegs->errIrqEnableSet != NULL)) { |
992 | /* Not supported on rev 1 */ | 1007 | /* Not supported on rev 1 */ |
993 | pcie_check_result(retVal, pcie_RET_INV_REG); | 1008 | retVal = pcie_RET_INV_REG; |
994 | } | 1009 | } |
995 | if (writeRegs->errIrqEnableClr) { | 1010 | if ((retVal == pcie_RET_OK) && (writeRegs->errIrqEnableClr != NULL)) { |
996 | /* Not supported on rev 1 */ | 1011 | /* Not supported on rev 1 */ |
997 | pcie_check_result(retVal, pcie_RET_INV_REG); | 1012 | retVal = pcie_RET_INV_REG; |
998 | } | 1013 | } |
999 | 1014 | ||
1000 | if (writeRegs->pmRstIrqStatusRaw) { | 1015 | if ((retVal == pcie_RET_OK) && (writeRegs->pmRstIrqStatusRaw != NULL)) { |
1001 | /* Not supported on rev 1 */ | 1016 | /* Not supported on rev 1 */ |
1002 | pcie_check_result(retVal, pcie_RET_INV_REG); | 1017 | retVal = pcie_RET_INV_REG; |
1003 | } | 1018 | } |
1004 | if (writeRegs->pmRstIrqStatus) { | 1019 | if ((retVal == pcie_RET_OK) && (writeRegs->pmRstIrqStatus != NULL)) { |
1005 | /* Not supported on rev 1 */ | 1020 | /* Not supported on rev 1 */ |
1006 | pcie_check_result(retVal, pcie_RET_INV_REG); | 1021 | retVal = pcie_RET_INV_REG; |
1007 | } | 1022 | } |
1008 | if (writeRegs->pmRstIrqEnableSet) { | 1023 | if ((retVal == pcie_RET_OK) && (writeRegs->pmRstIrqEnableSet != NULL)) { |
1009 | /* Not supported on rev 1 */ | 1024 | /* Not supported on rev 1 */ |
1010 | pcie_check_result(retVal, pcie_RET_INV_REG); | 1025 | retVal = pcie_RET_INV_REG; |
1011 | } | 1026 | } |
1012 | if (writeRegs->pmRstIrqEnableClr) { | 1027 | if ((retVal == pcie_RET_OK) && (writeRegs->pmRstIrqEnableClr != NULL)) { |
1013 | /* Not supported on rev 1 */ | 1028 | /* Not supported on rev 1 */ |
1014 | pcie_check_result(retVal, pcie_RET_INV_REG); | 1029 | retVal = pcie_RET_INV_REG; |
1015 | } | 1030 | } |
1016 | 1031 | ||
1017 | for (i = 0; i < 8; i ++) { | 1032 | for (i = 0; i < 8; i ++) { |
1018 | if (writeRegs->obOffsetLo[i]) { | 1033 | if ((retVal == pcie_RET_OK) && (writeRegs->obOffsetLo[i] != NULL)) { |
1019 | /* Not supported on rev 1 */ | 1034 | /* Not supported on rev 1 */ |
1020 | pcie_check_result(retVal, pcie_RET_INV_REG); | 1035 | retVal = pcie_RET_INV_REG; |
1021 | } | 1036 | } |
1022 | if (writeRegs->obOffsetHi[i]) { | 1037 | if ((retVal == pcie_RET_OK) && (writeRegs->obOffsetHi[i] != NULL)) { |
1023 | /* Not supported on rev 1 */ | 1038 | /* Not supported on rev 1 */ |
1024 | pcie_check_result(retVal, pcie_RET_INV_REG); | 1039 | retVal = pcie_RET_INV_REG; |
1025 | } | 1040 | } |
1026 | } | 1041 | } |
1027 | 1042 | ||
1028 | for (i = 0; i < 4; i ++) { | 1043 | for (i = 0; i < 4; i ++) { |
1029 | if (writeRegs->ibBar[i]) { | 1044 | if ((retVal == pcie_RET_OK) && (writeRegs->ibBar[i] != NULL)) { |
1030 | /* Not supported on rev 1 */ | 1045 | /* Not supported on rev 1 */ |
1031 | pcie_check_result(retVal, pcie_RET_INV_REG); | 1046 | retVal = pcie_RET_INV_REG; |
1032 | } | 1047 | } |
1033 | if (writeRegs->ibStartLo[i]) { | 1048 | if ((retVal == pcie_RET_OK) && (writeRegs->ibStartLo[i] != NULL)) { |
1034 | /* Not supported on rev 1 */ | 1049 | /* Not supported on rev 1 */ |
1035 | pcie_check_result(retVal, pcie_RET_INV_REG); | 1050 | retVal = pcie_RET_INV_REG; |
1036 | } | 1051 | } |
1037 | if (writeRegs->ibStartHi[i]) { | 1052 | if ((retVal == pcie_RET_OK) && (writeRegs->ibStartHi[i] != NULL)) { |
1038 | /* Not supported on rev 1 */ | 1053 | /* Not supported on rev 1 */ |
1039 | pcie_check_result(retVal, pcie_RET_INV_REG); | 1054 | retVal = pcie_RET_INV_REG; |
1040 | } | 1055 | } |
1041 | if (writeRegs->ibOffset[i]) { | 1056 | if ((retVal == pcie_RET_OK) && (writeRegs->ibOffset[i] != NULL)) { |
1042 | /* Not supported on rev 1 */ | 1057 | /* Not supported on rev 1 */ |
1043 | pcie_check_result(retVal, pcie_RET_INV_REG); | 1058 | retVal = pcie_RET_INV_REG; |
1044 | } | 1059 | } |
1045 | } | 1060 | } |
1046 | 1061 | ||
1047 | if (writeRegs->pcsCfg0) { | 1062 | if ((retVal == pcie_RET_OK) && (writeRegs->pcsCfg0 != NULL)) { |
1048 | /* Not supported on rev 1 */ | 1063 | /* Not supported on rev 1 */ |
1049 | pcie_check_result(retVal, pcie_RET_INV_REG); | 1064 | retVal = pcie_RET_INV_REG; |
1050 | } | 1065 | } |
1051 | if (writeRegs->pcsCfg1) { | 1066 | if ((retVal == pcie_RET_OK) && (writeRegs->pcsCfg1 != NULL)) { |
1052 | /* Not supported on rev 1 */ | 1067 | /* Not supported on rev 1 */ |
1053 | pcie_check_result(retVal, pcie_RET_INV_REG); | 1068 | retVal = pcie_RET_INV_REG; |
1054 | } | 1069 | } |
1055 | 1070 | ||
1056 | if (writeRegs->serdesCfg0) { | 1071 | if ((retVal == pcie_RET_OK) && (writeRegs->serdesCfg0 != NULL)) { |
1057 | /* Not supported on rev 1 */ | 1072 | /* Not supported on rev 1 */ |
1058 | pcie_check_result(retVal, pcie_RET_INV_REG); | 1073 | retVal = pcie_RET_INV_REG; |
1059 | } | 1074 | } |
1060 | if (writeRegs->serdesCfg1) { | 1075 | if ((retVal == pcie_RET_OK) && (writeRegs->serdesCfg1 != NULL)) { |
1061 | /* Not supported on rev 1 */ | 1076 | /* Not supported on rev 1 */ |
1062 | pcie_check_result(retVal, pcie_RET_INV_REG); | 1077 | retVal = pcie_RET_INV_REG; |
1063 | } | 1078 | } |
1064 | 1079 | ||
1065 | /***************************************************************************************** | 1080 | /***************************************************************************************** |
@@ -1068,410 +1083,410 @@ pcieRet_e Pciev1_writeRegs | |||
1068 | 1083 | ||
1069 | /*Type 0, Type1 Common Registers*/ | 1084 | /*Type 0, Type1 Common Registers*/ |
1070 | 1085 | ||
1071 | if (writeRegs->vndDevId) { | 1086 | if ((retVal == pcie_RET_OK) && (writeRegs->vndDevId != NULL)) { |
1072 | pcie_check_result(retVal, pciev1_write_vndDevId_reg (&baseCfgEpRegs->DEVICE_VENDORID, writeRegs->vndDevId)); | 1087 | retVal = pciev1_write_vndDevId_reg (&baseCfgEpRegs->DEVICE_VENDORID, writeRegs->vndDevId); |
1073 | } | 1088 | } |
1074 | if (writeRegs->statusCmd) { | 1089 | if ((retVal == pcie_RET_OK) && (writeRegs->statusCmd != NULL)) { |
1075 | pcie_check_result(retVal, pciev1_write_statusCmd_reg (&baseCfgEpRegs->STATUS_COMMAND_REGISTER, writeRegs->statusCmd)); | 1090 | retVal = pciev1_write_statusCmd_reg (&baseCfgEpRegs->STATUS_COMMAND_REGISTER, writeRegs->statusCmd); |
1076 | } | 1091 | } |
1077 | if (writeRegs->revId) { | 1092 | if ((retVal == pcie_RET_OK) && (writeRegs->revId != NULL)) { |
1078 | pcie_check_result(retVal, pciev1_write_revId_reg (&baseCfgEpRegs->CLASSCODE_REVISIONID, writeRegs->revId)); | 1093 | retVal = pciev1_write_revId_reg (&baseCfgEpRegs->CLASSCODE_REVISIONID, writeRegs->revId); |
1079 | } | 1094 | } |
1080 | 1095 | ||
1081 | if (writeRegs->bist) { | 1096 | if ((retVal == pcie_RET_OK) && (writeRegs->bist != NULL)) { |
1082 | pcie_check_result(retVal, pciev1_write_bist_reg (baseCfgEpRegs, writeRegs->bist)); | 1097 | retVal = pciev1_write_bist_reg (baseCfgEpRegs, writeRegs->bist); |
1083 | } | 1098 | } |
1084 | 1099 | ||
1085 | /*Type 0 Registers*/ | 1100 | /*Type 0 Registers*/ |
1086 | if (writeRegs->type0BarIdx) { | 1101 | if ((retVal == pcie_RET_OK) && (writeRegs->type0BarIdx != NULL)) { |
1087 | pcie_check_result(retVal, pciev1_write_type0Bar_reg (baseCfgEpRegs, &(writeRegs->type0BarIdx->reg), | 1102 | retVal = pciev1_write_type0Bar_reg (baseCfgEpRegs, &(writeRegs->type0BarIdx->reg), |
1088 | writeRegs->type0BarIdx->idx)); | 1103 | writeRegs->type0BarIdx->idx); |
1089 | } | 1104 | } |
1090 | if (writeRegs->type0BarMask32bitIdx) { | 1105 | if ((retVal == pcie_RET_OK) && (writeRegs->type0BarMask32bitIdx != NULL)) { |
1091 | pcie_check_result(retVal, pciev1_write_type0Bar32bit_reg (baseCfgEpCS2Regs, &(writeRegs->type0BarMask32bitIdx->reg), | 1106 | retVal = pciev1_write_type0Bar32bit_reg (baseCfgEpCS2Regs, &(writeRegs->type0BarMask32bitIdx->reg), |
1092 | writeRegs->type0BarMask32bitIdx->idx)); | 1107 | writeRegs->type0BarMask32bitIdx->idx); |
1093 | } | 1108 | } |
1094 | if (writeRegs->type0Bar32bitIdx) { | 1109 | if ((retVal == pcie_RET_OK) && (writeRegs->type0Bar32bitIdx != NULL)) { |
1095 | pcie_check_result(retVal, pciev1_write_type0Bar32bit_reg (baseCfgEpRegs, &(writeRegs->type0Bar32bitIdx->reg), | 1110 | retVal = pciev1_write_type0Bar32bit_reg (baseCfgEpRegs, &(writeRegs->type0Bar32bitIdx->reg), |
1096 | writeRegs->type0Bar32bitIdx->idx)); | 1111 | writeRegs->type0Bar32bitIdx->idx); |
1097 | } | 1112 | } |
1098 | if (writeRegs->subId) { | 1113 | if ((retVal == pcie_RET_OK) && (writeRegs->subId != NULL)) { |
1099 | pcie_check_result(retVal, pciev1_write_subId_reg (baseCfgEpRegs, writeRegs->subId)); | 1114 | retVal = pciev1_write_subId_reg (baseCfgEpRegs, writeRegs->subId); |
1100 | } | 1115 | } |
1101 | if (writeRegs->cardbusCisPointer) { | 1116 | if ((retVal == pcie_RET_OK) && (writeRegs->cardbusCisPointer != NULL)) { |
1102 | pcie_check_result(retVal, pciev1_write_cardbusCisPointer_reg (baseCfgEpRegs, writeRegs->cardbusCisPointer)); | 1117 | retVal = pciev1_write_cardbusCisPointer_reg (baseCfgEpRegs, writeRegs->cardbusCisPointer); |
1103 | } | 1118 | } |
1104 | if (writeRegs->expRom) { | 1119 | if ((retVal == pcie_RET_OK) && (writeRegs->expRom != NULL)) { |
1105 | pcie_check_result(retVal, pciev1_write_expRom_reg (baseCfgEpRegs, writeRegs->expRom)); | 1120 | retVal = pciev1_write_expRom_reg (baseCfgEpRegs, writeRegs->expRom); |
1106 | } | 1121 | } |
1107 | if (writeRegs->capPtr) { | 1122 | if ((retVal == pcie_RET_OK) && (writeRegs->capPtr != NULL)) { |
1108 | pcie_check_result(retVal, pciev1_write_capPtr_reg (baseCfgEpRegs, writeRegs->capPtr)); | 1123 | retVal = pciev1_write_capPtr_reg (baseCfgEpRegs, writeRegs->capPtr); |
1109 | } | 1124 | } |
1110 | if (writeRegs->intPin) { | 1125 | if ((retVal == pcie_RET_OK) && (writeRegs->intPin != NULL)) { |
1111 | pcie_check_result(retVal, pciev1_write_intPin_reg (baseCfgEpRegs, writeRegs->intPin)); | 1126 | retVal = pciev1_write_intPin_reg (baseCfgEpRegs, writeRegs->intPin); |
1112 | } | 1127 | } |
1113 | 1128 | ||
1114 | /*Type 1 Registers*/ | 1129 | /*Type 1 Registers*/ |
1115 | if (writeRegs->type1BistHeader) { | 1130 | if ((retVal == pcie_RET_OK) && (writeRegs->type1BistHeader != NULL)) { |
1116 | pcie_check_result(retVal, pciev1_write_type1BistHeader_reg (baseCfgRcRegs, writeRegs->type1BistHeader)); | 1131 | retVal = pciev1_write_type1BistHeader_reg (baseCfgRcRegs, writeRegs->type1BistHeader); |
1117 | } | 1132 | } |
1118 | if (writeRegs->type1BarIdx) { | 1133 | if ((retVal == pcie_RET_OK) && (writeRegs->type1BarIdx != NULL)) { |
1119 | pcie_check_result(retVal, pciev1_write_type1Bar_reg (baseCfgRcRegs, &(writeRegs->type1BarIdx->reg), | 1134 | retVal = pciev1_write_type1Bar_reg (baseCfgRcRegs, &(writeRegs->type1BarIdx->reg), |
1120 | writeRegs->type1BarIdx->idx)); | 1135 | writeRegs->type1BarIdx->idx); |
1121 | } | 1136 | } |
1122 | if (writeRegs->type1BarMask32bitIdx) { | 1137 | if ((retVal == pcie_RET_OK) && (writeRegs->type1BarMask32bitIdx != NULL)) { |
1123 | pcie_check_result(retVal, pciev1_write_type1Bar32bit_reg (baseCfgRcCS2Regs, &(writeRegs->type1BarMask32bitIdx->reg), | 1138 | retVal = pciev1_write_type1Bar32bit_reg (baseCfgRcCS2Regs, &(writeRegs->type1BarMask32bitIdx->reg), |
1124 | writeRegs->type1BarMask32bitIdx->idx)); | 1139 | writeRegs->type1BarMask32bitIdx->idx); |
1125 | } | 1140 | } |
1126 | if (writeRegs->type1Bar32bitIdx) { | 1141 | if ((retVal == pcie_RET_OK) && (writeRegs->type1Bar32bitIdx != NULL)) { |
1127 | pcie_check_result(retVal, pciev1_write_type1Bar32bit_reg (baseCfgRcRegs, &(writeRegs->type1Bar32bitIdx->reg), | 1142 | retVal = pciev1_write_type1Bar32bit_reg (baseCfgRcRegs, &(writeRegs->type1Bar32bitIdx->reg), |
1128 | writeRegs->type1Bar32bitIdx->idx)); | 1143 | writeRegs->type1Bar32bitIdx->idx); |
1129 | } | 1144 | } |
1130 | if (writeRegs->type1BusNum) { | 1145 | if ((retVal == pcie_RET_OK) && (writeRegs->type1BusNum != NULL)) { |
1131 | pcie_check_result(retVal, pciev1_write_type1BusNum_reg (baseCfgRcRegs, writeRegs->type1BusNum)); | 1146 | retVal = pciev1_write_type1BusNum_reg (baseCfgRcRegs, writeRegs->type1BusNum); |
1132 | } | 1147 | } |
1133 | if (writeRegs->type1SecStat) { | 1148 | if ((retVal == pcie_RET_OK) && (writeRegs->type1SecStat != NULL)) { |
1134 | pcie_check_result(retVal, pciev1_write_type1SecStat_reg (baseCfgRcRegs, writeRegs->type1SecStat)); | 1149 | retVal = pciev1_write_type1SecStat_reg (baseCfgRcRegs, writeRegs->type1SecStat); |
1135 | } | 1150 | } |
1136 | if (writeRegs->type1Memspace) { | 1151 | if ((retVal == pcie_RET_OK) && (writeRegs->type1Memspace != NULL)) { |
1137 | pcie_check_result(retVal, pciev1_write_type1Memspace_reg (baseCfgRcRegs, writeRegs->type1Memspace)); | 1152 | retVal = pciev1_write_type1Memspace_reg (baseCfgRcRegs, writeRegs->type1Memspace); |
1138 | } | 1153 | } |
1139 | if (writeRegs->prefMem) { | 1154 | if ((retVal == pcie_RET_OK) && (writeRegs->prefMem != NULL)) { |
1140 | pcie_check_result(retVal, pciev1_write_prefMem_reg (baseCfgRcRegs, writeRegs->prefMem)); | 1155 | retVal = pciev1_write_prefMem_reg (baseCfgRcRegs, writeRegs->prefMem); |
1141 | } | 1156 | } |
1142 | if (writeRegs->prefBaseUpper) { | 1157 | if ((retVal == pcie_RET_OK) && (writeRegs->prefBaseUpper != NULL)) { |
1143 | pcie_check_result(retVal, pciev1_write_prefBaseUpper_reg (baseCfgRcRegs, writeRegs->prefBaseUpper)); | 1158 | retVal = pciev1_write_prefBaseUpper_reg (baseCfgRcRegs, writeRegs->prefBaseUpper); |
1144 | } | 1159 | } |
1145 | if (writeRegs->prefLimitUpper) { | 1160 | if ((retVal == pcie_RET_OK) && (writeRegs->prefLimitUpper != NULL)) { |
1146 | pcie_check_result(retVal, pciev1_write_prefLimitUpper_reg (baseCfgRcRegs, writeRegs->prefLimitUpper)); | 1161 | retVal = pciev1_write_prefLimitUpper_reg (baseCfgRcRegs, writeRegs->prefLimitUpper); |
1147 | } | 1162 | } |
1148 | if (writeRegs->type1IOSpace) { | 1163 | if ((retVal == pcie_RET_OK) && (writeRegs->type1IOSpace != NULL)) { |
1149 | pcie_check_result(retVal, pciev1_write_type1IOSpace_reg (baseCfgRcRegs, writeRegs->type1IOSpace)); | 1164 | retVal = pciev1_write_type1IOSpace_reg (baseCfgRcRegs, writeRegs->type1IOSpace); |
1150 | } | 1165 | } |
1151 | if (writeRegs->type1CapPtr) { | 1166 | if ((retVal == pcie_RET_OK) && (writeRegs->type1CapPtr != NULL)) { |
1152 | pcie_check_result(retVal, pciev1_write_type1CapPtr_reg (baseCfgRcRegs, writeRegs->type1CapPtr)); | 1167 | retVal = pciev1_write_type1CapPtr_reg (baseCfgRcRegs, writeRegs->type1CapPtr); |
1153 | } | 1168 | } |
1154 | if (writeRegs->type1ExpnsnRom) { | 1169 | if ((retVal == pcie_RET_OK) && (writeRegs->type1ExpnsnRom != NULL)) { |
1155 | pcie_check_result(retVal, pciev1_write_type1ExpnsnRom_reg (baseCfgRcRegs, writeRegs->type1ExpnsnRom)); | 1170 | retVal = pciev1_write_type1ExpnsnRom_reg (baseCfgRcRegs, writeRegs->type1ExpnsnRom); |
1156 | } | 1171 | } |
1157 | if (writeRegs->type1BridgeInt) { | 1172 | if ((retVal == pcie_RET_OK) && (writeRegs->type1BridgeInt != NULL)) { |
1158 | pcie_check_result(retVal, pciev1_write_type1BridgeInt_reg (baseCfgRcRegs, writeRegs->type1BridgeInt)); | 1173 | retVal = pciev1_write_type1BridgeInt_reg (baseCfgRcRegs, writeRegs->type1BridgeInt); |
1159 | } | 1174 | } |
1160 | 1175 | ||
1161 | /* Power Management Capabilities Registers */ | 1176 | /* Power Management Capabilities Registers */ |
1162 | if (writeRegs->pmCap) { | 1177 | if ((retVal == pcie_RET_OK) && (writeRegs->pmCap != NULL)) { |
1163 | pcie_check_result(retVal, pciev1_write_pmCap_reg (baseCfgEpRegs, writeRegs->pmCap)); | 1178 | retVal = pciev1_write_pmCap_reg (baseCfgEpRegs, writeRegs->pmCap); |
1164 | } | 1179 | } |
1165 | if (writeRegs->pmCapCtlStat) { | 1180 | if ((retVal == pcie_RET_OK) && (writeRegs->pmCapCtlStat != NULL)) { |
1166 | pcie_check_result(retVal, pciev1_write_pmCapCtlStat_reg (baseCfgEpRegs, writeRegs->pmCapCtlStat)); | 1181 | retVal = pciev1_write_pmCapCtlStat_reg (baseCfgEpRegs, writeRegs->pmCapCtlStat); |
1167 | } | 1182 | } |
1168 | 1183 | ||
1169 | /*MSI Registers*/ | 1184 | /*MSI Registers*/ |
1170 | if (writeRegs->msiCap) { | 1185 | if ((retVal == pcie_RET_OK) && (writeRegs->msiCap != NULL)) { |
1171 | pcie_check_result(retVal, pciev1_write_msiCap_reg (baseCfgEpRegs, writeRegs->msiCap)); | 1186 | retVal = pciev1_write_msiCap_reg (baseCfgEpRegs, writeRegs->msiCap); |
1172 | } | 1187 | } |
1173 | if (writeRegs->msiLo32) { | 1188 | if ((retVal == pcie_RET_OK) && (writeRegs->msiLo32 != NULL)) { |
1174 | pcie_check_result(retVal, pciev1_write_msiLo32_reg (baseCfgEpRegs, writeRegs->msiLo32)); | 1189 | retVal = pciev1_write_msiLo32_reg (baseCfgEpRegs, writeRegs->msiLo32); |
1175 | } | 1190 | } |
1176 | if (writeRegs->msiUp32) { | 1191 | if ((retVal == pcie_RET_OK) && (writeRegs->msiUp32 != NULL)) { |
1177 | pcie_check_result(retVal, pciev1_write_msiUp32_reg (baseCfgEpRegs, writeRegs->msiUp32)); | 1192 | retVal = pciev1_write_msiUp32_reg (baseCfgEpRegs, writeRegs->msiUp32); |
1178 | } | 1193 | } |
1179 | if (writeRegs->msiData) { | 1194 | if ((retVal == pcie_RET_OK) && (writeRegs->msiData != NULL)) { |
1180 | pcie_check_result(retVal, pciev1_write_msiData_reg (baseCfgEpRegs, writeRegs->msiData)); | 1195 | retVal = pciev1_write_msiData_reg (baseCfgEpRegs, writeRegs->msiData); |
1181 | } | 1196 | } |
1182 | 1197 | ||
1183 | /*Capabilities Registers*/ | 1198 | /*Capabilities Registers*/ |
1184 | if (writeRegs->pciesCap) { | 1199 | if ((retVal == pcie_RET_OK) && (writeRegs->pciesCap != NULL)) { |
1185 | pcie_check_result(retVal, pciev1_write_pciesCap_reg (&baseCfgEpRegs->PCIE_CAP_STRUC.PCIE_CAP, writeRegs->pciesCap)); | 1200 | retVal = pciev1_write_pciesCap_reg (&baseCfgEpRegs->PCIE_CAP_STRUC.PCIE_CAP, writeRegs->pciesCap); |
1186 | } | 1201 | } |
1187 | if (writeRegs->deviceCap) { | 1202 | if ((retVal == pcie_RET_OK) && (writeRegs->deviceCap != NULL)) { |
1188 | pcie_check_result(retVal, pciev1_write_deviceCap_reg (&baseCfgEpRegs->PCIE_CAP_STRUC.DEV_CAP, writeRegs->deviceCap)); | 1203 | retVal = pciev1_write_deviceCap_reg (&baseCfgEpRegs->PCIE_CAP_STRUC.DEV_CAP, writeRegs->deviceCap); |
1189 | } | 1204 | } |
1190 | 1205 | ||
1191 | if (writeRegs->devStatCtrl) { | 1206 | if ((retVal == pcie_RET_OK) && (writeRegs->devStatCtrl != NULL)) { |
1192 | pcie_check_result(retVal, pciev1_write_devStatCtrl_reg (&baseCfgEpRegs->PCIE_CAP_STRUC.DEV_CAS, writeRegs->devStatCtrl)); | 1207 | retVal = pciev1_write_devStatCtrl_reg (&baseCfgEpRegs->PCIE_CAP_STRUC.DEV_CAS, writeRegs->devStatCtrl); |
1193 | } | 1208 | } |
1194 | if (writeRegs->linkCap) { | 1209 | if ((retVal == pcie_RET_OK) && (writeRegs->linkCap != NULL)) { |
1195 | pcie_check_result(retVal, pciev1_write_linkCap_reg (&baseCfgEpRegs->PCIE_CAP_STRUC.LNK_CAP, writeRegs->linkCap)); | 1210 | retVal = pciev1_write_linkCap_reg (&baseCfgEpRegs->PCIE_CAP_STRUC.LNK_CAP, writeRegs->linkCap); |
1196 | } | 1211 | } |
1197 | if (writeRegs->linkStatCtrl) { | 1212 | if ((retVal == pcie_RET_OK) && (writeRegs->linkStatCtrl != NULL)) { |
1198 | pcie_check_result(retVal, pciev1_write_linkStatCtrl_reg (&baseCfgEpRegs->PCIE_CAP_STRUC.LNK_CAS, writeRegs->linkStatCtrl)); | 1213 | retVal = pciev1_write_linkStatCtrl_reg (&baseCfgEpRegs->PCIE_CAP_STRUC.LNK_CAS, writeRegs->linkStatCtrl); |
1199 | } | 1214 | } |
1200 | if (writeRegs->slotCap) { | 1215 | if ((retVal == pcie_RET_OK) && (writeRegs->slotCap != NULL)) { |
1201 | pcie_check_result(retVal, pciev1_write_slotCap_reg (baseCfgRcRegs, writeRegs->slotCap)); | 1216 | retVal = pciev1_write_slotCap_reg (baseCfgRcRegs, writeRegs->slotCap); |
1202 | } | 1217 | } |
1203 | if (writeRegs->slotStatCtrl) { | 1218 | if ((retVal == pcie_RET_OK) && (writeRegs->slotStatCtrl != NULL)) { |
1204 | pcie_check_result(retVal, pciev1_write_slotStatCtrl_reg (baseCfgRcRegs, writeRegs->slotStatCtrl)); | 1219 | retVal = pciev1_write_slotStatCtrl_reg (baseCfgRcRegs, writeRegs->slotStatCtrl); |
1205 | } | 1220 | } |
1206 | if (writeRegs->rootCtrlCap) { | 1221 | if ((retVal == pcie_RET_OK) && (writeRegs->rootCtrlCap != NULL)) { |
1207 | pcie_check_result(retVal, pciev1_write_rootCtrlCap_reg (baseCfgRcRegs, writeRegs->rootCtrlCap)); | 1222 | retVal = pciev1_write_rootCtrlCap_reg (baseCfgRcRegs, writeRegs->rootCtrlCap); |
1208 | } | 1223 | } |
1209 | if (writeRegs->rootStatus) { | 1224 | if ((retVal == pcie_RET_OK) && (writeRegs->rootStatus != NULL)) { |
1210 | pcie_check_result(retVal, pciev1_write_rootStatus_reg (baseCfgRcRegs, writeRegs->rootStatus)); | 1225 | retVal = pciev1_write_rootStatus_reg (baseCfgRcRegs, writeRegs->rootStatus); |
1211 | } | 1226 | } |
1212 | if (writeRegs->devCap2) { | 1227 | if ((retVal == pcie_RET_OK) && (writeRegs->devCap2 != NULL)) { |
1213 | pcie_check_result(retVal, pciev1_write_devCap2_reg (&baseCfgEpRegs->PCIE_CAP_STRUC.DEV_CAP_2, writeRegs->devCap2)); | 1228 | retVal = pciev1_write_devCap2_reg (&baseCfgEpRegs->PCIE_CAP_STRUC.DEV_CAP_2, writeRegs->devCap2); |
1214 | } | 1229 | } |
1215 | if (writeRegs->devStatCtrl2) { | 1230 | if ((retVal == pcie_RET_OK) && (writeRegs->devStatCtrl2 != NULL)) { |
1216 | pcie_check_result(retVal, pciev1_write_devStatCtrl2_reg (&baseCfgEpRegs->PCIE_CAP_STRUC.DEV_CAS_2, writeRegs->devStatCtrl2)); | 1231 | retVal = pciev1_write_devStatCtrl2_reg (&baseCfgEpRegs->PCIE_CAP_STRUC.DEV_CAS_2, writeRegs->devStatCtrl2); |
1217 | } | 1232 | } |
1218 | if (writeRegs->linkCap2) { | 1233 | if ((retVal == pcie_RET_OK) && (writeRegs->linkCap2 != NULL)) { |
1219 | pcie_check_result(retVal, pciev1_write_linkCap2_reg (&baseCfgEpRegs->PCIE_CAP_STRUC.LNK_CAP_2, writeRegs->linkCap2)); | 1234 | retVal = pciev1_write_linkCap2_reg (&baseCfgEpRegs->PCIE_CAP_STRUC.LNK_CAP_2, writeRegs->linkCap2); |
1220 | } | 1235 | } |
1221 | if (writeRegs->linkCtrl2) { | 1236 | if ((retVal == pcie_RET_OK) && (writeRegs->linkCtrl2 != NULL)) { |
1222 | pcie_check_result(retVal, pciev1_write_linkCtrl2_reg (&baseCfgEpRegs->PCIE_CAP_STRUC.LNK_CAS_2, writeRegs->linkCtrl2)); | 1237 | retVal = pciev1_write_linkCtrl2_reg (&baseCfgEpRegs->PCIE_CAP_STRUC.LNK_CAS_2, writeRegs->linkCtrl2); |
1223 | } | 1238 | } |
1224 | 1239 | ||
1225 | /*Capabilities Extended Registers*/ | 1240 | /*Capabilities Extended Registers*/ |
1226 | if (writeRegs->extCap) { | 1241 | if ((retVal == pcie_RET_OK) && (writeRegs->extCap != NULL)) { |
1227 | /* Not supported on rev 1 */ | 1242 | /* Not supported on rev 1 */ |
1228 | pcie_check_result(retVal, pcie_RET_INV_REG); | 1243 | retVal = pcie_RET_INV_REG; |
1229 | } | 1244 | } |
1230 | if (writeRegs->uncErr) { | 1245 | if ((retVal == pcie_RET_OK) && (writeRegs->uncErr != NULL)) { |
1231 | /* Not supported on rev 1 */ | 1246 | /* Not supported on rev 1 */ |
1232 | pcie_check_result(retVal, pcie_RET_INV_REG); | 1247 | retVal = pcie_RET_INV_REG; |
1233 | } | 1248 | } |
1234 | if (writeRegs->uncErrMask) { | 1249 | if ((retVal == pcie_RET_OK) && (writeRegs->uncErrMask != NULL)) { |
1235 | /* Not supported on rev 1 */ | 1250 | /* Not supported on rev 1 */ |
1236 | pcie_check_result(retVal, pcie_RET_INV_REG); | 1251 | retVal = pcie_RET_INV_REG; |
1237 | } | 1252 | } |
1238 | if (writeRegs->uncErrSvrty) { | 1253 | if ((retVal == pcie_RET_OK) && (writeRegs->uncErrSvrty != NULL)) { |
1239 | /* Not supported on rev 1 */ | 1254 | /* Not supported on rev 1 */ |
1240 | pcie_check_result(retVal, pcie_RET_INV_REG); | 1255 | retVal = pcie_RET_INV_REG; |
1241 | } | 1256 | } |
1242 | if (writeRegs->corErr) { | 1257 | if ((retVal == pcie_RET_OK) && (writeRegs->corErr != NULL)) { |
1243 | /* Not supported on rev 1 */ | 1258 | /* Not supported on rev 1 */ |
1244 | pcie_check_result(retVal, pcie_RET_INV_REG); | 1259 | retVal = pcie_RET_INV_REG; |
1245 | } | 1260 | } |
1246 | if (writeRegs->corErrMask) { | 1261 | if ((retVal == pcie_RET_OK) && (writeRegs->corErrMask != NULL)) { |
1247 | /* Not supported on rev 1 */ | 1262 | /* Not supported on rev 1 */ |
1248 | pcie_check_result(retVal, pcie_RET_INV_REG); | 1263 | retVal = pcie_RET_INV_REG; |
1249 | } | 1264 | } |
1250 | if (writeRegs->accr) { | 1265 | if ((retVal == pcie_RET_OK) && (writeRegs->accr != NULL)) { |
1251 | /* Not supported on rev 1 */ | 1266 | /* Not supported on rev 1 */ |
1252 | pcie_check_result(retVal, pcie_RET_INV_REG); | 1267 | retVal = pcie_RET_INV_REG; |
1253 | } | 1268 | } |
1254 | for (i = 0; i < 4; i ++) { | 1269 | for (i = 0; i < 4; i ++) { |
1255 | if (writeRegs->hdrLog[i]) { | 1270 | if ((retVal == pcie_RET_OK) && (writeRegs->hdrLog[i] != NULL)) { |
1256 | /* Not supported on rev 1 */ | 1271 | /* Not supported on rev 1 */ |
1257 | pcie_check_result(retVal, pcie_RET_INV_REG); | 1272 | retVal = pcie_RET_INV_REG; |
1258 | } | 1273 | } |
1259 | } | 1274 | } |
1260 | if (writeRegs->rootErrCmd) { | 1275 | if ((retVal == pcie_RET_OK) && (writeRegs->rootErrCmd != NULL)) { |
1261 | /* Not supported on rev 1 */ | 1276 | /* Not supported on rev 1 */ |
1262 | pcie_check_result(retVal, pcie_RET_INV_REG); | 1277 | retVal = pcie_RET_INV_REG; |
1263 | } | 1278 | } |
1264 | if (writeRegs->rootErrSt) { | 1279 | if ((retVal == pcie_RET_OK) && (writeRegs->rootErrSt != NULL)) { |
1265 | /* Not supported on rev 1 */ | 1280 | /* Not supported on rev 1 */ |
1266 | pcie_check_result(retVal, pcie_RET_INV_REG); | 1281 | retVal = pcie_RET_INV_REG; |
1267 | } | 1282 | } |
1268 | if (writeRegs->errSrcID) { | 1283 | if ((retVal == pcie_RET_OK) && (writeRegs->errSrcID != NULL)) { |
1269 | /* Not supported on rev 1 */ | 1284 | /* Not supported on rev 1 */ |
1270 | pcie_check_result(retVal, pcie_RET_INV_REG); | 1285 | retVal = pcie_RET_INV_REG; |
1271 | } | 1286 | } |
1272 | 1287 | ||
1273 | /*Port Logic Registers*/ | 1288 | /*Port Logic Registers*/ |
1274 | if (writeRegs->plAckTimer) { | 1289 | if ((retVal == pcie_RET_OK) && (writeRegs->plAckTimer != NULL)) { |
1275 | pcie_check_result(retVal, pciev1_write_plAckTimer_reg (baseCfgPlRegs, writeRegs->plAckTimer)); | 1290 | retVal = pciev1_write_plAckTimer_reg (baseCfgPlRegs, writeRegs->plAckTimer); |
1276 | } | 1291 | } |
1277 | if (writeRegs->plOMsg) { | 1292 | if ((retVal == pcie_RET_OK) && (writeRegs->plOMsg != NULL)) { |
1278 | pcie_check_result(retVal, pciev1_write_plOMsg_reg (baseCfgPlRegs, writeRegs->plOMsg)); | 1293 | retVal = pciev1_write_plOMsg_reg (baseCfgPlRegs, writeRegs->plOMsg); |
1279 | } | 1294 | } |
1280 | if (writeRegs->plForceLink) { | 1295 | if ((retVal == pcie_RET_OK) && (writeRegs->plForceLink != NULL)) { |
1281 | pcie_check_result(retVal, pciev1_write_plForceLink_reg (baseCfgPlRegs, writeRegs->plForceLink)); | 1296 | retVal = pciev1_write_plForceLink_reg (baseCfgPlRegs, writeRegs->plForceLink); |
1282 | } | 1297 | } |
1283 | if (writeRegs->ackFreq) { | 1298 | if ((retVal == pcie_RET_OK) && (writeRegs->ackFreq != NULL)) { |
1284 | pcie_check_result(retVal, pciev1_write_ackFreq_reg (baseCfgPlRegs, writeRegs->ackFreq)); | 1299 | retVal = pciev1_write_ackFreq_reg (baseCfgPlRegs, writeRegs->ackFreq); |
1285 | } | 1300 | } |
1286 | if (writeRegs->lnkCtrl) { | 1301 | if ((retVal == pcie_RET_OK) && (writeRegs->lnkCtrl != NULL)) { |
1287 | pcie_check_result(retVal, pciev1_write_lnkCtrl_reg (baseCfgPlRegs, writeRegs->lnkCtrl)); | 1302 | retVal = pciev1_write_lnkCtrl_reg (baseCfgPlRegs, writeRegs->lnkCtrl); |
1288 | } | 1303 | } |
1289 | if (writeRegs->laneSkew) { | 1304 | if ((retVal == pcie_RET_OK) && (writeRegs->laneSkew != NULL)) { |
1290 | pcie_check_result(retVal, pciev1_write_laneSkew_reg (baseCfgPlRegs, writeRegs->laneSkew)); | 1305 | retVal = pciev1_write_laneSkew_reg (baseCfgPlRegs, writeRegs->laneSkew); |
1291 | } | 1306 | } |
1292 | if (writeRegs->symNum) { | 1307 | if ((retVal == pcie_RET_OK) && (writeRegs->symNum != NULL)) { |
1293 | pcie_check_result(retVal, pciev1_write_symNum_reg (baseCfgPlRegs, writeRegs->symNum)); | 1308 | retVal = pciev1_write_symNum_reg (baseCfgPlRegs, writeRegs->symNum); |
1294 | } | 1309 | } |
1295 | if (writeRegs->symTimerFltMask) { | 1310 | if ((retVal == pcie_RET_OK) && (writeRegs->symTimerFltMask != NULL)) { |
1296 | pcie_check_result(retVal, pciev1_write_symTimerFltMask_reg (baseCfgPlRegs, writeRegs->symTimerFltMask)); | 1311 | retVal = pciev1_write_symTimerFltMask_reg (baseCfgPlRegs, writeRegs->symTimerFltMask); |
1297 | } | 1312 | } |
1298 | if (writeRegs->fltMask2) { | 1313 | if ((retVal == pcie_RET_OK) && (writeRegs->fltMask2 != NULL)) { |
1299 | pcie_check_result(retVal, pciev1_write_fltMask2_reg (baseCfgPlRegs, writeRegs->fltMask2)); | 1314 | retVal = pciev1_write_fltMask2_reg (baseCfgPlRegs, writeRegs->fltMask2); |
1300 | } | 1315 | } |
1301 | if (writeRegs->gen2) { | 1316 | if ((retVal == pcie_RET_OK) && (writeRegs->gen2 != NULL)) { |
1302 | pcie_check_result(retVal, pciev1_write_gen2_reg (baseCfgPlRegs, writeRegs->gen2)); | 1317 | retVal = pciev1_write_gen2_reg (baseCfgPlRegs, writeRegs->gen2); |
1303 | } | 1318 | } |
1304 | 1319 | ||
1305 | /* hw rev 1 PLCONF registers */ | 1320 | /* hw rev 1 PLCONF registers */ |
1306 | if (writeRegs->plconfObnpSubreqCtrl) { | 1321 | if ((retVal == pcie_RET_OK) && (writeRegs->plconfObnpSubreqCtrl != NULL)) { |
1307 | pcie_check_result(retVal, pciev1_write_plconfObnpSubreqCtrl_reg (baseCfgPlRegs, writeRegs->plconfObnpSubreqCtrl)); | 1322 | retVal = pciev1_write_plconfObnpSubreqCtrl_reg (baseCfgPlRegs, writeRegs->plconfObnpSubreqCtrl); |
1308 | } | 1323 | } |
1309 | if (writeRegs->plconfTrPStsR) { | 1324 | if ((retVal == pcie_RET_OK) && (writeRegs->plconfTrPStsR != NULL)) { |
1310 | /* Pure RO register */ | 1325 | /* Pure RO register */ |
1311 | pcie_check_result(retVal, pcie_RET_INV_REG); | 1326 | retVal = pcie_RET_INV_REG; |
1312 | } | 1327 | } |
1313 | if (writeRegs->plconfTrNpStsR) { | 1328 | if ((retVal == pcie_RET_OK) && (writeRegs->plconfTrNpStsR != NULL)) { |
1314 | /* Pure RO register */ | 1329 | /* Pure RO register */ |
1315 | pcie_check_result(retVal, pcie_RET_INV_REG); | 1330 | retVal = pcie_RET_INV_REG; |
1316 | } | 1331 | } |
1317 | if (writeRegs->plconfTrCStsR) { | 1332 | if ((retVal == pcie_RET_OK) && (writeRegs->plconfTrCStsR != NULL)) { |
1318 | /* Pure RO register */ | 1333 | /* Pure RO register */ |
1319 | pcie_check_result(retVal, pcie_RET_INV_REG); | 1334 | retVal = pcie_RET_INV_REG; |
1320 | } | 1335 | } |
1321 | if (writeRegs->plconfQStsR) { | 1336 | if ((retVal == pcie_RET_OK) && (writeRegs->plconfQStsR != NULL)) { |
1322 | pcie_check_result(retVal, pciev1_write_plconfQStsR_reg (baseCfgPlRegs, writeRegs->plconfQStsR)); | 1337 | retVal = pciev1_write_plconfQStsR_reg (baseCfgPlRegs, writeRegs->plconfQStsR); |
1323 | } | 1338 | } |
1324 | if (writeRegs->plconfVcTrAR1) { | 1339 | if ((retVal == pcie_RET_OK) && (writeRegs->plconfVcTrAR1 != NULL)) { |
1325 | /* Pure RO register */ | 1340 | /* Pure RO register */ |
1326 | pcie_check_result(retVal, pcie_RET_INV_REG); | 1341 | retVal = pcie_RET_INV_REG; |
1327 | } | 1342 | } |
1328 | if (writeRegs->plconfVcTrAR2) { | 1343 | if ((retVal == pcie_RET_OK) && (writeRegs->plconfVcTrAR2 != NULL)) { |
1329 | /* Pure RO register */ | 1344 | /* Pure RO register */ |
1330 | pcie_check_result(retVal, pcie_RET_INV_REG); | 1345 | retVal = pcie_RET_INV_REG; |
1331 | } | 1346 | } |
1332 | if (writeRegs->plconfVc0PrQC) { | 1347 | if ((retVal == pcie_RET_OK) && (writeRegs->plconfVc0PrQC != NULL)) { |
1333 | pcie_check_result(retVal, pciev1_write_plconfVc0PrQC_reg (baseCfgPlRegs, writeRegs->plconfVc0PrQC)); | 1348 | retVal = pciev1_write_plconfVc0PrQC_reg (baseCfgPlRegs, writeRegs->plconfVc0PrQC); |
1334 | } | 1349 | } |
1335 | if (writeRegs->plconfVc0NprQC) { | 1350 | if ((retVal == pcie_RET_OK) && (writeRegs->plconfVc0NprQC != NULL)) { |
1336 | pcie_check_result(retVal, pciev1_write_plconfVc0NprQC_reg (baseCfgPlRegs, writeRegs->plconfVc0NprQC)); | 1351 | retVal = pciev1_write_plconfVc0NprQC_reg (baseCfgPlRegs, writeRegs->plconfVc0NprQC); |
1337 | } | 1352 | } |
1338 | if (writeRegs->plconfVc0CrQC) { | 1353 | if ((retVal == pcie_RET_OK) && (writeRegs->plconfVc0CrQC != NULL)) { |
1339 | pcie_check_result(retVal, pciev1_write_plconfVc0CrQC_reg (baseCfgPlRegs, writeRegs->plconfVc0CrQC)); | 1354 | retVal = pciev1_write_plconfVc0CrQC_reg (baseCfgPlRegs, writeRegs->plconfVc0CrQC); |
1340 | } | 1355 | } |
1341 | if (writeRegs->plconfPhyStsR) { | 1356 | if ((retVal == pcie_RET_OK) && (writeRegs->plconfPhyStsR != NULL)) { |
1342 | /* Pure RO register */ | 1357 | /* Pure RO register */ |
1343 | pcie_check_result(retVal, pcie_RET_INV_REG); | 1358 | retVal = pcie_RET_INV_REG; |
1344 | } | 1359 | } |
1345 | if (writeRegs->plconfPhyCtrlR) { | 1360 | if ((retVal == pcie_RET_OK) && (writeRegs->plconfPhyCtrlR != NULL)) { |
1346 | pcie_check_result(retVal, pciev1_write_plconfPhyCtrlR_reg (baseCfgPlRegs, writeRegs->plconfPhyCtrlR)); | 1361 | retVal = pciev1_write_plconfPhyCtrlR_reg (baseCfgPlRegs, writeRegs->plconfPhyCtrlR); |
1347 | } | 1362 | } |
1348 | if (writeRegs->plconfMsiCtrlAddress) { | 1363 | if ((retVal == pcie_RET_OK) && (writeRegs->plconfMsiCtrlAddress != NULL)) { |
1349 | pcie_check_result(retVal, pciev1_write_plconfMsiCtrlAddress_reg (baseCfgPlRegs, writeRegs->plconfMsiCtrlAddress)); | 1364 | retVal = pciev1_write_plconfMsiCtrlAddress_reg (baseCfgPlRegs, writeRegs->plconfMsiCtrlAddress); |
1350 | } | 1365 | } |
1351 | if (writeRegs->plconfMsiCtrlUpperAddress) { | 1366 | if ((retVal == pcie_RET_OK) && (writeRegs->plconfMsiCtrlUpperAddress != NULL)) { |
1352 | pcie_check_result(retVal, pciev1_write_plconfMsiCtrlUpperAddress_reg (baseCfgPlRegs, writeRegs->plconfMsiCtrlUpperAddress)); | 1367 | retVal = pciev1_write_plconfMsiCtrlUpperAddress_reg (baseCfgPlRegs, writeRegs->plconfMsiCtrlUpperAddress); |
1353 | } | 1368 | } |
1354 | for (i = 0; i < 8; i++) { | 1369 | for (i = 0; i < 8; i++) { |
1355 | if (writeRegs->plconfMsiCtrlIntEnable[i]) { | 1370 | if ((retVal == pcie_RET_OK) && (writeRegs->plconfMsiCtrlIntEnable[i] != NULL)) { |
1356 | pcie_check_result(retVal, pciev1_write_plconfMsiCtrlIntEnable_reg (baseCfgPlRegs, writeRegs->plconfMsiCtrlIntEnable[i], i)); | 1371 | retVal = pciev1_write_plconfMsiCtrlIntEnable_reg (baseCfgPlRegs, writeRegs->plconfMsiCtrlIntEnable[i], i); |
1357 | } | 1372 | } |
1358 | if (writeRegs->plconfMsiCtrlIntMask[i]) { | 1373 | if ((retVal == pcie_RET_OK) && (writeRegs->plconfMsiCtrlIntMask[i] != NULL)) { |
1359 | pcie_check_result(retVal, pciev1_write_plconfMsiCtrlIntMask_reg (baseCfgPlRegs, writeRegs->plconfMsiCtrlIntMask[i], i)); | 1374 | retVal = pciev1_write_plconfMsiCtrlIntMask_reg (baseCfgPlRegs, writeRegs->plconfMsiCtrlIntMask[i], i); |
1360 | } | 1375 | } |
1361 | if (writeRegs->plconfMsiCtrlIntStatus[i]) { | 1376 | if ((retVal == pcie_RET_OK) && (writeRegs->plconfMsiCtrlIntStatus[i] != NULL)) { |
1362 | pcie_check_result(retVal, pciev1_write_plconfMsiCtrlIntStatus_reg (baseCfgPlRegs, writeRegs->plconfMsiCtrlIntStatus[i], i)); | 1377 | retVal = pciev1_write_plconfMsiCtrlIntStatus_reg (baseCfgPlRegs, writeRegs->plconfMsiCtrlIntStatus[i], i); |
1363 | } | 1378 | } |
1364 | } | 1379 | } |
1365 | if (writeRegs->plconfMsiCtrlGpio) { | 1380 | if ((retVal == pcie_RET_OK) && (writeRegs->plconfMsiCtrlGpio != NULL)) { |
1366 | pcie_check_result(retVal, pciev1_write_plconfMsiCtrlGpio_reg (baseCfgPlRegs, writeRegs->plconfMsiCtrlGpio)); | 1381 | retVal = pciev1_write_plconfMsiCtrlGpio_reg (baseCfgPlRegs, writeRegs->plconfMsiCtrlGpio); |
1367 | } | 1382 | } |
1368 | if (writeRegs->plconfPipeLoopback) { | 1383 | if ((retVal == pcie_RET_OK) && (writeRegs->plconfPipeLoopback != NULL)) { |
1369 | pcie_check_result(retVal, pciev1_write_plconfPipeLoopback_reg (baseCfgPlRegs, writeRegs->plconfPipeLoopback)); | 1384 | retVal = pciev1_write_plconfPipeLoopback_reg (baseCfgPlRegs, writeRegs->plconfPipeLoopback); |
1370 | } | 1385 | } |
1371 | if (writeRegs->plconfDbiRoWrEn) { | 1386 | if ((retVal == pcie_RET_OK) && (writeRegs->plconfDbiRoWrEn != NULL)) { |
1372 | pcie_check_result(retVal, pciev1_write_plconfDbiRoWrEn_reg (baseCfgPlRegs, writeRegs->plconfDbiRoWrEn)); | 1387 | retVal = pciev1_write_plconfDbiRoWrEn_reg (baseCfgPlRegs, writeRegs->plconfDbiRoWrEn); |
1373 | } | 1388 | } |
1374 | if (writeRegs->plconfAxiSlvErrResp) { | 1389 | if ((retVal == pcie_RET_OK) && (writeRegs->plconfAxiSlvErrResp != NULL)) { |
1375 | pcie_check_result(retVal, pciev1_write_plconfAxiSlvErrResp_reg (baseCfgPlRegs, writeRegs->plconfAxiSlvErrResp)); | 1390 | retVal = pciev1_write_plconfAxiSlvErrResp_reg (baseCfgPlRegs, writeRegs->plconfAxiSlvErrResp); |
1376 | } | 1391 | } |
1377 | if (writeRegs->plconfAxiSlvTimeout) { | 1392 | if ((retVal == pcie_RET_OK) && (writeRegs->plconfAxiSlvTimeout != NULL)) { |
1378 | pcie_check_result(retVal, pciev1_write_plconfAxiSlvTimeout_reg (baseCfgPlRegs, writeRegs->plconfAxiSlvTimeout)); | 1393 | retVal = pciev1_write_plconfAxiSlvTimeout_reg (baseCfgPlRegs, writeRegs->plconfAxiSlvTimeout); |
1379 | } | 1394 | } |
1380 | if (writeRegs->plconfIatuIndex) { | 1395 | if ((retVal == pcie_RET_OK) && (writeRegs->plconfIatuIndex != NULL)) { |
1381 | pcie_check_result(retVal, pciev1_write_plconfIatuIndex_reg (baseCfgPlRegs, writeRegs->plconfIatuIndex)); | 1396 | retVal = pciev1_write_plconfIatuIndex_reg (baseCfgPlRegs, writeRegs->plconfIatuIndex); |
1382 | } | 1397 | } |
1383 | if (writeRegs->plconfIatuRegCtrl2) { | 1398 | if ((retVal == pcie_RET_OK) && (writeRegs->plconfIatuRegCtrl2 != NULL)) { |
1384 | pcie_check_result(retVal, pciev1_write_plconfIatuRegCtrl2_reg (baseCfgPlRegs, writeRegs->plconfIatuRegCtrl2)); | 1399 | retVal = pciev1_write_plconfIatuRegCtrl2_reg (baseCfgPlRegs, writeRegs->plconfIatuRegCtrl2); |
1385 | } | 1400 | } |
1386 | if (writeRegs->plconfIatuRegLowerBase) { | 1401 | if ((retVal == pcie_RET_OK) && (writeRegs->plconfIatuRegLowerBase != NULL)) { |
1387 | pcie_check_result(retVal, pciev1_write_plconfIatuRegLowerBase_reg (baseCfgPlRegs, writeRegs->plconfIatuRegLowerBase)); | 1402 | retVal = pciev1_write_plconfIatuRegLowerBase_reg (baseCfgPlRegs, writeRegs->plconfIatuRegLowerBase); |
1388 | } | 1403 | } |
1389 | if (writeRegs->plconfIatuRegUpperBase) { | 1404 | if ((retVal == pcie_RET_OK) && (writeRegs->plconfIatuRegUpperBase != NULL)) { |
1390 | pcie_check_result(retVal, pciev1_write_plconfIatuRegUpperBase_reg (baseCfgPlRegs, writeRegs->plconfIatuRegUpperBase)); | 1405 | retVal = pciev1_write_plconfIatuRegUpperBase_reg (baseCfgPlRegs, writeRegs->plconfIatuRegUpperBase); |
1391 | } | 1406 | } |
1392 | if (writeRegs->plconfIatuRegLimit) { | 1407 | if ((retVal == pcie_RET_OK) && (writeRegs->plconfIatuRegLimit != NULL)) { |
1393 | pcie_check_result(retVal, pciev1_write_plconfIatuRegLimit_reg (baseCfgPlRegs, writeRegs->plconfIatuRegLimit)); | 1408 | retVal = pciev1_write_plconfIatuRegLimit_reg (baseCfgPlRegs, writeRegs->plconfIatuRegLimit); |
1394 | } | 1409 | } |
1395 | if (writeRegs->plconfIatuRegLowerTarget) { | 1410 | if ((retVal == pcie_RET_OK) && (writeRegs->plconfIatuRegLowerTarget != NULL)) { |
1396 | pcie_check_result(retVal, pciev1_write_plconfIatuRegLowerTarget_reg (baseCfgPlRegs, writeRegs->plconfIatuRegLowerTarget)); | 1411 | retVal = pciev1_write_plconfIatuRegLowerTarget_reg (baseCfgPlRegs, writeRegs->plconfIatuRegLowerTarget); |
1397 | } | 1412 | } |
1398 | if (writeRegs->plconfIatuRegUpperTarget) { | 1413 | if ((retVal == pcie_RET_OK) && (writeRegs->plconfIatuRegUpperTarget != NULL)) { |
1399 | pcie_check_result(retVal, pciev1_write_plconfIatuRegUpperTarget_reg (baseCfgPlRegs, writeRegs->plconfIatuRegUpperTarget)); | 1414 | retVal = pciev1_write_plconfIatuRegUpperTarget_reg (baseCfgPlRegs, writeRegs->plconfIatuRegUpperTarget); |
1400 | } | 1415 | } |
1401 | if (writeRegs->plconfIatuRegCtrl3) { | 1416 | if ((retVal == pcie_RET_OK) && (writeRegs->plconfIatuRegCtrl3 != NULL)) { |
1402 | /* Pure RO register */ | 1417 | /* Pure RO register */ |
1403 | pcie_check_result(retVal, pcie_RET_INV_REG); | 1418 | retVal = pcie_RET_INV_REG; |
1404 | } | 1419 | } |
1405 | /* Ctrl1 is done last since it has enable bit */ | 1420 | /* Ctrl1 is done last since it has enable bit */ |
1406 | if (writeRegs->plconfIatuRegCtrl1) { | 1421 | if ((retVal == pcie_RET_OK) && (writeRegs->plconfIatuRegCtrl1 != NULL)) { |
1407 | pcie_check_result(retVal, pciev1_write_plconfIatuRegCtrl1_reg (baseCfgPlRegs, writeRegs->plconfIatuRegCtrl1)); | 1422 | retVal = pciev1_write_plconfIatuRegCtrl1_reg (baseCfgPlRegs, writeRegs->plconfIatuRegCtrl1); |
1408 | } | 1423 | } |
1409 | 1424 | ||
1410 | /* TI CONF registers */ | 1425 | /* TI CONF registers */ |
1411 | if (writeRegs->tiConfRevision) { | 1426 | if ((retVal == pcie_RET_OK) && (writeRegs->tiConfRevision != NULL)) { |
1412 | /* Pure RO register */ | 1427 | /* Pure RO register */ |
1413 | pcie_check_result(retVal, pcie_RET_INV_REG); | 1428 | retVal = pcie_RET_INV_REG; |
1414 | } | 1429 | } |
1415 | if (writeRegs->tiConfSysConfig) { | 1430 | if ((retVal == pcie_RET_OK) && (writeRegs->tiConfSysConfig != NULL)) { |
1416 | pcie_check_result(retVal, pciev1_write_tiConfSysConfig_reg (baseCfgTiConfRegs, writeRegs->tiConfSysConfig)); | 1431 | retVal = pciev1_write_tiConfSysConfig_reg (baseCfgTiConfRegs, writeRegs->tiConfSysConfig); |
1417 | } | 1432 | } |
1418 | if (writeRegs->tiConfIrqEoi) { | 1433 | if ((retVal == pcie_RET_OK) && (writeRegs->tiConfIrqEoi != NULL)) { |
1419 | pcie_check_result(retVal, pciev1_write_tiConfIrqEoi_reg (baseCfgTiConfRegs, writeRegs->tiConfIrqEoi)); | 1434 | retVal = pciev1_write_tiConfIrqEoi_reg (baseCfgTiConfRegs, writeRegs->tiConfIrqEoi); |
1420 | } | 1435 | } |
1421 | if (writeRegs->tiConfIrqStatusRawMain) { | 1436 | if ((retVal == pcie_RET_OK) && (writeRegs->tiConfIrqStatusRawMain != NULL)) { |
1422 | pcie_check_result(retVal, pciev1_write_tiConfIrqStatusRawMain_reg (baseCfgTiConfRegs, writeRegs->tiConfIrqStatusRawMain)); | 1437 | retVal = pciev1_write_tiConfIrqStatusRawMain_reg (baseCfgTiConfRegs, writeRegs->tiConfIrqStatusRawMain); |
1423 | } | 1438 | } |
1424 | if (writeRegs->tiConfIrqStatusMain) { | 1439 | if ((retVal == pcie_RET_OK) && (writeRegs->tiConfIrqStatusMain != NULL)) { |
1425 | pcie_check_result(retVal, pciev1_write_tiConfIrqStatusMain_reg (baseCfgTiConfRegs, writeRegs->tiConfIrqStatusMain)); | 1440 | retVal = pciev1_write_tiConfIrqStatusMain_reg (baseCfgTiConfRegs, writeRegs->tiConfIrqStatusMain); |
1426 | } | 1441 | } |
1427 | if (writeRegs->tiConfIrqEnableSetMain) { | 1442 | if ((retVal == pcie_RET_OK) && (writeRegs->tiConfIrqEnableSetMain != NULL)) { |
1428 | pcie_check_result(retVal, pciev1_write_tiConfIrqEnableSetMain_reg (baseCfgTiConfRegs, writeRegs->tiConfIrqEnableSetMain)); | 1443 | retVal = pciev1_write_tiConfIrqEnableSetMain_reg (baseCfgTiConfRegs, writeRegs->tiConfIrqEnableSetMain); |
1429 | } | 1444 | } |
1430 | if (writeRegs->tiConfIrqEnableClrMain) { | 1445 | if ((retVal == pcie_RET_OK) && (writeRegs->tiConfIrqEnableClrMain != NULL)) { |
1431 | pcie_check_result(retVal, pciev1_write_tiConfIrqEnableClrMain_reg (baseCfgTiConfRegs, writeRegs->tiConfIrqEnableClrMain)); | 1446 | retVal = pciev1_write_tiConfIrqEnableClrMain_reg (baseCfgTiConfRegs, writeRegs->tiConfIrqEnableClrMain); |
1432 | } | 1447 | } |
1433 | if (writeRegs->tiConfIrqStatusRawMsi) { | 1448 | if ((retVal == pcie_RET_OK) && (writeRegs->tiConfIrqStatusRawMsi != NULL)) { |
1434 | pcie_check_result(retVal, pciev1_write_tiConfIrqStatusRawMsi_reg (baseCfgTiConfRegs, writeRegs->tiConfIrqStatusRawMsi)); | 1449 | retVal = pciev1_write_tiConfIrqStatusRawMsi_reg (baseCfgTiConfRegs, writeRegs->tiConfIrqStatusRawMsi); |
1435 | } | 1450 | } |
1436 | if (writeRegs->tiConfIrqStatusMsi) { | 1451 | if ((retVal == pcie_RET_OK) && (writeRegs->tiConfIrqStatusMsi != NULL)) { |
1437 | pcie_check_result(retVal, pciev1_write_tiConfIrqStatusMsi_reg (baseCfgTiConfRegs, writeRegs->tiConfIrqStatusMsi)); | 1452 | retVal = pciev1_write_tiConfIrqStatusMsi_reg (baseCfgTiConfRegs, writeRegs->tiConfIrqStatusMsi); |
1438 | } | 1453 | } |
1439 | if (writeRegs->tiConfIrqEnableSetMsi) { | 1454 | if ((retVal == pcie_RET_OK) && (writeRegs->tiConfIrqEnableSetMsi != NULL)) { |
1440 | pcie_check_result(retVal, pciev1_write_tiConfIrqEnableSetMsi_reg (baseCfgTiConfRegs, writeRegs->tiConfIrqEnableSetMsi)); | 1455 | retVal = pciev1_write_tiConfIrqEnableSetMsi_reg (baseCfgTiConfRegs, writeRegs->tiConfIrqEnableSetMsi); |
1441 | } | 1456 | } |
1442 | if (writeRegs->tiConfIrqEnableClrMsi) { | 1457 | if ((retVal == pcie_RET_OK) && (writeRegs->tiConfIrqEnableClrMsi != NULL)) { |
1443 | pcie_check_result(retVal, pciev1_write_tiConfIrqEnableClrMsi_reg (baseCfgTiConfRegs, writeRegs->tiConfIrqEnableClrMsi)); | 1458 | retVal = pciev1_write_tiConfIrqEnableClrMsi_reg (baseCfgTiConfRegs, writeRegs->tiConfIrqEnableClrMsi); |
1444 | } | 1459 | } |
1445 | if (writeRegs->tiConfDeviceType) { | 1460 | if ((retVal == pcie_RET_OK) && (writeRegs->tiConfDeviceType != NULL)) { |
1446 | pcie_check_result(retVal, pciev1_write_tiConfDeviceType_reg (baseCfgTiConfRegs, writeRegs->tiConfDeviceType)); | 1461 | retVal = pciev1_write_tiConfDeviceType_reg (baseCfgTiConfRegs, writeRegs->tiConfDeviceType); |
1447 | } | 1462 | } |
1448 | if (writeRegs->tiConfDeviceCmd) { | 1463 | if ((retVal == pcie_RET_OK) && (writeRegs->tiConfDeviceCmd != NULL)) { |
1449 | pcie_check_result(retVal, pciev1_write_tiConfDeviceCmd_reg (baseCfgTiConfRegs, writeRegs->tiConfDeviceCmd)); | 1464 | retVal = pciev1_write_tiConfDeviceCmd_reg (baseCfgTiConfRegs, writeRegs->tiConfDeviceCmd); |
1450 | } | 1465 | } |
1451 | if (writeRegs->tiConfPmCtrl) { | 1466 | if ((retVal == pcie_RET_OK) && (writeRegs->tiConfPmCtrl != NULL)) { |
1452 | pcie_check_result(retVal, pciev1_write_tiConfPmCtrl_reg (baseCfgTiConfRegs, writeRegs->tiConfPmCtrl)); | 1467 | retVal = pciev1_write_tiConfPmCtrl_reg (baseCfgTiConfRegs, writeRegs->tiConfPmCtrl); |
1453 | } | 1468 | } |
1454 | if (writeRegs->tiConfPhyCs) { | 1469 | if ((retVal == pcie_RET_OK) && (writeRegs->tiConfPhyCs != NULL)) { |
1455 | pcie_check_result(retVal, pciev1_write_tiConfPhyCs_reg (baseCfgTiConfRegs, writeRegs->tiConfPhyCs)); | 1470 | retVal = pciev1_write_tiConfPhyCs_reg (baseCfgTiConfRegs, writeRegs->tiConfPhyCs); |
1456 | } | 1471 | } |
1457 | if (writeRegs->tiConfIntxAssert) { | 1472 | if ((retVal == pcie_RET_OK) && (writeRegs->tiConfIntxAssert != NULL)) { |
1458 | pcie_check_result(retVal, pciev1_write_tiConfIntxAssert_reg (baseCfgTiConfRegs, writeRegs->tiConfIntxAssert)); | 1473 | retVal = pciev1_write_tiConfIntxAssert_reg (baseCfgTiConfRegs, writeRegs->tiConfIntxAssert); |
1459 | } | 1474 | } |
1460 | if (writeRegs->tiConfIntxDeassert) { | 1475 | if ((retVal == pcie_RET_OK) && (writeRegs->tiConfIntxDeassert != NULL)) { |
1461 | pcie_check_result(retVal, pciev1_write_tiConfIntxDeassert_reg (baseCfgTiConfRegs, writeRegs->tiConfIntxDeassert)); | 1476 | retVal = pciev1_write_tiConfIntxDeassert_reg (baseCfgTiConfRegs, writeRegs->tiConfIntxDeassert); |
1462 | } | 1477 | } |
1463 | if (writeRegs->tiConfMsiXmt) { | 1478 | if ((retVal == pcie_RET_OK) && (writeRegs->tiConfMsiXmt != NULL)) { |
1464 | pcie_check_result(retVal, pciev1_write_tiConfMsiXmt_reg (baseCfgTiConfRegs, writeRegs->tiConfMsiXmt)); | 1479 | retVal = pciev1_write_tiConfMsiXmt_reg (baseCfgTiConfRegs, writeRegs->tiConfMsiXmt); |
1465 | } | 1480 | } |
1466 | if (writeRegs->tiConfDebugCfg) { | 1481 | if ((retVal == pcie_RET_OK) && (writeRegs->tiConfDebugCfg != NULL)) { |
1467 | pcie_check_result(retVal, pciev1_write_tiConfDebugCfg_reg (baseCfgTiConfRegs, writeRegs->tiConfDebugCfg)); | 1482 | retVal = pciev1_write_tiConfDebugCfg_reg (baseCfgTiConfRegs, writeRegs->tiConfDebugCfg); |
1468 | } | 1483 | } |
1469 | if (writeRegs->tiConfDebugData) { | 1484 | if ((retVal == pcie_RET_OK) && (writeRegs->tiConfDebugData != NULL)) { |
1470 | /* Pure RO register */ | 1485 | /* Pure RO register */ |
1471 | pcie_check_result(retVal, pcie_RET_INV_REG); | 1486 | retVal = pcie_RET_INV_REG; |
1472 | } | 1487 | } |
1473 | if (writeRegs->tiConfDiagCtrl) { | 1488 | if ((retVal == pcie_RET_OK) && (writeRegs->tiConfDiagCtrl != NULL)) { |
1474 | pcie_check_result(retVal, pciev1_write_tiConfDiagCtrl_reg (baseCfgTiConfRegs, writeRegs->tiConfDiagCtrl)); | 1489 | retVal = pciev1_write_tiConfDiagCtrl_reg (baseCfgTiConfRegs, writeRegs->tiConfDiagCtrl); |
1475 | } | 1490 | } |
1476 | 1491 | ||
1477 | return retVal; | 1492 | return retVal; |
@@ -1494,42 +1509,45 @@ pcieRet_e Pciev1_cfgBar | |||
1494 | uint32_t barAddrField = 0; | 1509 | uint32_t barAddrField = 0; |
1495 | 1510 | ||
1496 | if (pcieLObjIsValid == 0) { | 1511 | if (pcieLObjIsValid == 0) { |
1497 | return pcie_RET_NO_INIT; | 1512 | retVal = pcie_RET_NO_INIT; |
1498 | } | 1513 | } |
1514 | else { | ||
1515 | if (pcie_check_handle_fcn(handle) == 0) { | ||
1516 | retVal = pcie_RET_INV_HANDLE; | ||
1517 | } | ||
1518 | else { | ||
1519 | memset (&setRegs, 0, sizeof(setRegs)); | ||
1520 | memset (&type0BarIdx, 0, sizeof(type0BarIdx)); | ||
1521 | memset (&type1BarIdx, 0, sizeof(type1BarIdx)); | ||
1499 | 1522 | ||
1500 | pcie_check_handle(handle); | 1523 | if(barCfg->mode == pcie_RC_MODE) |
1501 | 1524 | { | |
1502 | memset (&setRegs, 0, sizeof(setRegs)); | 1525 | pcie_getbits(barCfg->base, PCIE_RC_BAR_BASE_FULL, barAddrField); |
1503 | memset (&type0BarIdx, 0, sizeof(type0BarIdx)); | ||
1504 | memset (&type1BarIdx, 0, sizeof(type1BarIdx)); | ||
1505 | 1526 | ||
1506 | if(barCfg->mode == pcie_RC_MODE) | 1527 | type1BarIdx.reg.base = barAddrField; |
1507 | { | 1528 | type1BarIdx.reg.prefetch = barCfg->prefetch; |
1508 | pcie_getbits(barCfg->base, PCIE_RC_BAR_BASE_FULL, barAddrField); | 1529 | type1BarIdx.reg.type = barCfg->type; |
1530 | type1BarIdx.reg.memSpace = barCfg->memSpace; | ||
1531 | type1BarIdx.idx = barCfg->idx; | ||
1509 | 1532 | ||
1510 | type1BarIdx.reg.base = barAddrField; | 1533 | setRegs.type1BarIdx = &type1BarIdx; |
1511 | type1BarIdx.reg.prefetch = barCfg->prefetch; | 1534 | } |
1512 | type1BarIdx.reg.type = barCfg->type; | 1535 | else |
1513 | type1BarIdx.reg.memSpace = barCfg->memSpace; | 1536 | { |
1514 | type1BarIdx.idx = barCfg->idx; | 1537 | pcie_getbits(barCfg->base, PCIE_EP_BAR_BASE_FULL, barAddrField); |
1515 | 1538 | ||
1516 | setRegs.type1BarIdx = &type1BarIdx; | 1539 | type0BarIdx.reg.base = barAddrField; |
1517 | } | 1540 | type0BarIdx.reg.prefetch = barCfg->prefetch; |
1518 | else | 1541 | type0BarIdx.reg.type = barCfg->type; |
1519 | { | 1542 | type0BarIdx.reg.memSpace = barCfg->memSpace; |
1520 | pcie_getbits(barCfg->base, PCIE_EP_BAR_BASE_FULL, barAddrField); | 1543 | type0BarIdx.idx = barCfg->idx; |
1521 | 1544 | ||
1522 | type0BarIdx.reg.base = barAddrField; | 1545 | setRegs.type0BarIdx = &type0BarIdx; |
1523 | type0BarIdx.reg.prefetch = barCfg->prefetch; | 1546 | } |
1524 | type0BarIdx.reg.type = barCfg->type; | ||
1525 | type0BarIdx.reg.memSpace = barCfg->memSpace; | ||
1526 | type0BarIdx.idx = barCfg->idx; | ||
1527 | 1547 | ||
1528 | setRegs.type0BarIdx = &type0BarIdx; | 1548 | retVal = Pciev1_writeRegs (handle, barCfg->location, &setRegs); |
1549 | } | ||
1529 | } | 1550 | } |
1530 | |||
1531 | retVal = Pciev1_writeRegs (handle, barCfg->location, &setRegs); | ||
1532 | |||
1533 | return retVal; | 1551 | return retVal; |
1534 | } /* Pciev1_cfgBar */ | 1552 | } /* Pciev1_cfgBar */ |
1535 | 1553 | ||