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authorJohn Dowdal2015-04-09 11:02:49 -0500
committerJohn Dowdal2015-04-09 11:02:49 -0500
commite60afa6baf80d4b59250fa12dece24c1a8eb8207 (patch)
tree56286d4cd3d194fd732b1d387d2a5917153b214d /src
parent75a2d15f7d1269707477803e026710f18421f812 (diff)
downloadpcie-lld-e60afa6baf80d4b59250fa12dece24c1a8eb8207.tar.gz
pcie-lld-e60afa6baf80d4b59250fa12dece24c1a8eb8207.tar.xz
pcie-lld-e60afa6baf80d4b59250fa12dece24c1a8eb8207.zip
refactor for v0/v1 and run on k2h
Diffstat (limited to 'src')
-rw-r--r--[-rwxr-xr-x]src/Module.xs5
-rw-r--r--[-rwxr-xr-x]src/pcie.c1014
-rw-r--r--[-rwxr-xr-x]src/pcieinit.c16
-rw-r--r--[-rwxr-xr-x]src/pcieloc.h1136
-rw-r--r--src/v0/pcie.h129
-rw-r--r--src/v0/pcieloc.h1181
-rw-r--r--src/v0/pciev0.c1090
-rw-r--r--[-rwxr-xr-x]src/v0/pciev0_app.c (renamed from src/pcieapp.c)365
-rw-r--r--[-rwxr-xr-x]src/v0/pciev0_cfg.c (renamed from src/pciecfg.c)503
9 files changed, 2934 insertions, 2505 deletions
diff --git a/src/Module.xs b/src/Module.xs
index abedd60..9e36c93 100755..100644
--- a/src/Module.xs
+++ b/src/Module.xs
@@ -16,8 +16,9 @@ var libUtility = xdc.loadCapsule ("../build/buildlib.xs");
16var pcielldFile = [ 16var pcielldFile = [
17 "src/pcie.c", 17 "src/pcie.c",
18 "src/pcieinit.c", 18 "src/pcieinit.c",
19 "src/pcieapp.c", 19 "src/v0/pciev0.c",
20 "src/pciecfg.c", 20 "src/v0/pciev0_app.c",
21 "src/v0/pciev0_cfg.c"
21]; 22];
22 23
23/************************************************************************** 24/**************************************************************************
diff --git a/src/pcie.c b/src/pcie.c
index 9db26ba..51f0478 100755..100644
--- a/src/pcie.c
+++ b/src/pcie.c
@@ -1,6 +1,6 @@
1/* 1/*
2 * 2 *
3 * Copyright (C) 2010-2013 Texas Instruments Incorporated - http://www.ti.com/ 3 * Copyright (C) 2010-2015 Texas Instruments Incorporated - http://www.ti.com/
4 * 4 *
5 * 5 *
6 * Redistribution and use in source and binary forms, with or without 6 * Redistribution and use in source and binary forms, with or without
@@ -40,11 +40,8 @@
40 * 40 *
41 */ 41 */
42 42
43#include "pcie.h" 43#include <ti/drv/pcie/pcie.h>
44#include "pcieloc.h" 44#include <ti/drv/pcie/src/pcieloc.h>
45#include <ti/csl/cslr_pcie_cfg_space_endpoint.h>
46#include <ti/csl/cslr_pcie_cfg_space_rootcomplex.h>
47#include <ti/csl/cslr_pciess_app.h>
48 45
49#include <string.h> 46#include <string.h>
50 47
@@ -60,7 +57,7 @@ int pcie_check_handle_fcn (Pcie_Handle handle)
60 57
61 if (handle) { 58 if (handle) {
62 for (i = 0; i < pcie_MAX_PERIPHS; i++) { 59 for (i = 0; i < pcie_MAX_PERIPHS; i++) {
63 if (handle == pcieLObj.cfg.dev.bases[i].cfgBase) { 60 if (handle == &pcieLObj.insts[i]) {
64 return 1; 61 return 1;
65 } 62 }
66 } 63 }
@@ -73,38 +70,13 @@ int pcie_check_handle_fcn (Pcie_Handle handle)
73 * Convert the handle (which is a configuration base address) into 70 * Convert the handle (which is a configuration base address) into
74 * associated Pcie_DeviceCfgBaseAddr 71 * associated Pcie_DeviceCfgBaseAddr
75 ****************************************************************************/ 72 ****************************************************************************/
76static Pcie_DeviceCfgBaseAddr *pcie_handle_to_cfg (Pcie_Handle handle) 73Pcie_DeviceCfgBaseAddr *pcie_handle_to_cfg (Pcie_Handle handle)
77{ 74{
78 Pcie_DeviceCfgBaseAddr *ret = NULL; 75 Pcie_IntHandle h = (Pcie_IntHandle)handle;
79 int i;
80 76
81 for (i = 0; i < pcie_MAX_PERIPHS; i++) { 77 return &h->bases;
82 if (handle == pcieLObj.cfg.dev.bases[i].cfgBase) {
83 ret = &pcieLObj.cfg.dev.bases[i];
84 break;
85 }
86 }
87
88 return ret;
89} /* pcie_handle_to_cfg */ 78} /* pcie_handle_to_cfg */
90 79
91/*****************************************************************************
92 * Set the mode of one interface without depending directly on device
93 * dependant registers (via device.c)
94 ****************************************************************************/
95static void pcie_set_mode (Pcie_DeviceCfgBaseAddr *iface, pcieMode_e mode)
96{
97 uint32_t modeReg;
98 uint32_t newMode = (uint32_t)mode;
99
100 /* Set the mode, without depending on device specific csl files */
101 modeReg = *iface->pcieSSModeAddr;
102 modeReg &= ~iface->pcieSSModeMask;
103 newMode <<= iface->pcieSSModeShift;
104 newMode &= iface->pcieSSModeMask;
105 modeReg |= newMode;
106 *iface->pcieSSModeAddr = modeReg;
107} /* pcie_set_mode */
108 80
109/***************************************************************************** 81/*****************************************************************************
110 ********** External APIs ********************** 82 ********** External APIs **********************
@@ -120,34 +92,20 @@ pcieRet_e Pcie_setInterfaceMode
120 pcieMode_e mode /**< [in] PCIE Mode */ 92 pcieMode_e mode /**< [in] PCIE Mode */
121) 93)
122{ 94{
123 Pcie_DeviceCfgBaseAddr *bases = pcie_handle_to_cfg (handle); 95 Pcie_IntHandle h = (Pcie_IntHandle)handle;
124 96
125 if (bases) { 97 if (! h)
126 pcie_set_mode (bases, mode); 98 {
127 return pcie_RET_OK; 99 return pcie_RET_INV_HANDLE;
128 } 100 }
129 101
130 return pcie_RET_INV_HANDLE; 102 if (! h->fxnTable.setInterfaceMode)
131} /* Pcie_setMode */ 103 {
132 104 return pcie_RET_INV_FXNPTR;
133/*********************************************************************
134 * FUNCTION PURPOSE: Sets PCIe mode to RC or EP for all interfaces
135 *********************************************************************/
136pcieRet_e Pcie_setMode
137(
138 pcieMode_e mode /**< [in] PCIE Mode */
139)
140{
141 int i;
142
143 for (i = 0; i < pcie_MAX_PERIPHS; i++) {
144 if (pcieLObj.cfg.dev.bases[i].cfgBase &&
145 pcieLObj.cfg.dev.bases[i].pcieSSModeAddr) {
146 pcie_set_mode (&pcieLObj.cfg.dev.bases[i], mode);
147 }
148 } 105 }
149 return pcie_RET_OK; 106
150} 107 return h->fxnTable.setInterfaceMode (handle, mode);
108} /* Pcie_setInterfaceMode */
151 109
152/********************************************************************* 110/*********************************************************************
153 * FUNCTION PURPOSE: Returns the PCIe Internal Address Range for the 111 * FUNCTION PURPOSE: Returns the PCIe Internal Address Range for the
@@ -160,26 +118,19 @@ pcieRet_e Pcie_getMemSpaceRange
160 uint32_t *size /**< [out] Memory Space total size */ 118 uint32_t *size /**< [out] Memory Space total size */
161) 119)
162{ 120{
163 pcieRet_e retVal = pcie_RET_OK; 121 Pcie_IntHandle h = (Pcie_IntHandle)handle;
164 122
165 if (! pcieLObjIsValid) { 123 if (! h)
166 return pcie_RET_NO_INIT; 124 {
125 return pcie_RET_INV_HANDLE;
167 } 126 }
168 127
169 pcie_check_handle(handle); 128 if (! h->fxnTable.getMemSpaceRange)
170 129 {
171 if (base) { 130 return pcie_RET_INV_FXNPTR;
172 Pcie_DeviceCfgBaseAddr *bases = pcie_handle_to_cfg (handle);
173 if (bases) {
174 *base = bases->dataBase;
175 } else {
176 retVal = pcie_RET_INV_HANDLE;
177 }
178 } 131 }
179 132
180 if (size) *size = 0x10000000; /* 256 MB */ 133 return h->fxnTable.getMemSpaceRange (handle, base, size);
181
182 return retVal;
183} /* Pcie_getMemSpaceRange */ 134} /* Pcie_getMemSpaceRange */
184 135
185/********************************************************************* 136/*********************************************************************
@@ -192,411 +143,19 @@ pcieRet_e Pcie_readRegs
192 pcieRegisters_t *readRegs /**< [in/out] List of registers to read */ 143 pcieRegisters_t *readRegs /**< [in/out] List of registers to read */
193) 144)
194{ 145{
195 /* Base Address for the Application Registers */ 146 Pcie_IntHandle h = (Pcie_IntHandle)handle;
196 CSL_Pciess_appRegs *baseAppRegs = (CSL_Pciess_appRegs *)handle;
197
198 /* Base Address for the Config Space
199 These registers can be Local/Remote and Type0(EP)/Type1(RC) */
200 CSL_Pcie_cfg_space_rootcomplexRegs *baseCfgRcRegs = NULL;
201 CSL_Pcie_cfg_space_endpointRegs *baseCfgEpRegs = NULL;
202
203 pcieRet_e retVal = pcie_RET_OK;
204 int i;
205
206 if (! pcieLObjIsValid) {
207 return pcie_RET_NO_INIT;
208 }
209 147
210 pcie_check_handle(handle); 148 if (! h)
211
212 /* Get base address for Local or Remote config space */
213 if (location == pcie_LOCATION_LOCAL)
214 {
215 pcie_get_loc_cfg_base(handle, baseCfgEpRegs, baseCfgRcRegs)
216 }
217 else
218 { 149 {
219 pcie_get_rem_cfg_base(handle, baseCfgEpRegs, baseCfgRcRegs) 150 return pcie_RET_INV_HANDLE;
220 }
221
222 /*****************************************************************************************
223 *Application Registers
224 *****************************************************************************************/
225 if (readRegs->pid) {
226 pcie_check_result(retVal, pcie_read_pid_reg (baseAppRegs, readRegs->pid));
227 }
228 if (readRegs->cmdStatus) {
229 pcie_check_result(retVal, pcie_read_cmdStatus_reg (baseAppRegs, readRegs->cmdStatus));
230 }
231 if (readRegs->cfgTrans) {
232 pcie_check_result(retVal, pcie_read_cfgTrans_reg (baseAppRegs, readRegs->cfgTrans));
233 }
234 if (readRegs->ioBase) {
235 pcie_check_result(retVal, pcie_read_ioBase_reg (baseAppRegs, readRegs->ioBase));
236 }
237 if (readRegs->tlpCfg) {
238 pcie_check_result(retVal, pcie_read_tlpCfg_reg (baseAppRegs, readRegs->tlpCfg));
239 }
240 if (readRegs->rstCmd) {
241 pcie_check_result(retVal, pcie_read_rstCmd_reg (baseAppRegs, readRegs->rstCmd));
242 }
243 if (readRegs->pmCmd) {
244 pcie_check_result(retVal, pcie_read_pmCmd_reg (baseAppRegs, readRegs->pmCmd));
245 }
246 if (readRegs->pmCfg) {
247 pcie_check_result(retVal, pcie_read_pmCfg_reg (baseAppRegs, readRegs->pmCfg));
248 }
249 if (readRegs->actStatus) {
250 pcie_check_result(retVal, pcie_read_actStatus_reg (baseAppRegs, readRegs->actStatus));
251 }
252 if (readRegs->obSize) {
253 pcie_check_result(retVal, pcie_read_obSize_reg (baseAppRegs, readRegs->obSize));
254 }
255 if (readRegs->diagCtrl) {
256 pcie_check_result(retVal, pcie_read_diagCtrl_reg (baseAppRegs, readRegs->diagCtrl));
257 }
258 if (readRegs->endian) {
259 pcie_check_result(retVal, pcie_read_endian_reg (baseAppRegs, readRegs->endian));
260 }
261 if (readRegs->priority) {
262 pcie_check_result(retVal, pcie_read_priority_reg (baseAppRegs, readRegs->priority));
263 }
264 if (readRegs->irqEOI) {
265 pcie_check_result(retVal, pcie_read_irqEOI_reg (baseAppRegs, readRegs->irqEOI));
266 }
267 if (readRegs->msiIrq) {
268 pcie_check_result(retVal, pcie_read_msiIrq_reg (baseAppRegs, readRegs->msiIrq));
269 }
270 if (readRegs->epIrqSet) {
271 pcie_check_result(retVal, pcie_read_epIrqSet_reg (baseAppRegs, readRegs->epIrqSet));
272 }
273 if (readRegs->epIrqClr) {
274 pcie_check_result(retVal, pcie_read_epIrqClr_reg (baseAppRegs, readRegs->epIrqClr));
275 }
276 if (readRegs->epIrqStatus) {
277 pcie_check_result(retVal, pcie_read_epIrqStatus_reg (baseAppRegs, readRegs->epIrqStatus));
278 }
279 for (i = 0; i < 4; i++) {
280 if (readRegs->genPurpose[i]) {
281 pcie_check_result(retVal, pcie_read_genPurpose_reg (baseAppRegs, readRegs->genPurpose[i], i));
282 }
283 }
284 for (i = 0; i < 8; i++) {
285 if (readRegs->msiIrqStatusRaw[i]) {
286 pcie_check_result(retVal, pcie_read_msiIrqStatusRaw_reg (baseAppRegs, readRegs->msiIrqStatusRaw[i], i));
287 }
288 if (readRegs->msiIrqStatus[i]) {
289 pcie_check_result(retVal, pcie_read_msiIrqStatus_reg (baseAppRegs, readRegs->msiIrqStatus[i], i));
290 }
291 if (readRegs->msiIrqEnableSet[i]) {
292 pcie_check_result(retVal, pcie_read_msiIrqEnableSet_reg (baseAppRegs, readRegs->msiIrqEnableSet[i], i));
293 }
294 if (readRegs->msiIrqEnableClr[i]) {
295 pcie_check_result(retVal, pcie_read_msiIrqEnableClr_reg (baseAppRegs, readRegs->msiIrqEnableClr[i], i));
296 }
297 }
298 for (i = 0; i < 4; i++) {
299 if (readRegs->legacyIrqStatusRaw[i]) {
300 pcie_check_result(retVal, pcie_read_legacyIrqStatusRaw_reg (baseAppRegs, readRegs->legacyIrqStatusRaw[i], i));
301 }
302 if (readRegs->legacyIrqStatus[i]) {
303 pcie_check_result(retVal, pcie_read_legacyIrqStatus_reg (baseAppRegs, readRegs->legacyIrqStatus[i], i));
304 }
305 if (readRegs->legacyIrqEnableSet[i]) {
306 pcie_check_result(retVal, pcie_read_legacyIrqEnableSet_reg (baseAppRegs, readRegs->legacyIrqEnableSet[i], i));
307 }
308 if (readRegs->legacyIrqEnableClr[i]) {
309 pcie_check_result(retVal, pcie_read_legacyIrqEnableClr_reg (baseAppRegs, readRegs->legacyIrqEnableClr[i], i));
310 }
311 }
312 if (readRegs->errIrqStatusRaw) {
313 pcie_check_result(retVal, pcie_read_errIrqStatusRaw_reg (baseAppRegs, readRegs->errIrqStatusRaw));
314 }
315 if (readRegs->errIrqStatus) {
316 pcie_check_result(retVal, pcie_read_errIrqStatus_reg (baseAppRegs, readRegs->errIrqStatus));
317 }
318 if (readRegs->errIrqEnableSet) {
319 pcie_check_result(retVal, pcie_read_errIrqEnableSet_reg (baseAppRegs, readRegs->errIrqEnableSet));
320 }
321 if (readRegs->errIrqEnableClr) {
322 pcie_check_result(retVal, pcie_read_errIrqEnableClr_reg (baseAppRegs, readRegs->errIrqEnableClr));
323 }
324
325 if (readRegs->pmRstIrqStatusRaw) {
326 pcie_check_result(retVal, pcie_read_pmRstIrqStatusRaw_reg (baseAppRegs, readRegs->pmRstIrqStatusRaw));
327 }
328 if (readRegs->pmRstIrqStatus) {
329 pcie_check_result(retVal, pcie_read_pmRstIrqStatus_reg (baseAppRegs, readRegs->pmRstIrqStatus));
330 }
331 if (readRegs->pmRstIrqEnableSet) {
332 pcie_check_result(retVal, pcie_read_pmRstIrqEnableSet_reg (baseAppRegs, readRegs->pmRstIrqEnableSet));
333 }
334 if (readRegs->pmRstIrqEnableClr) {
335 pcie_check_result(retVal, pcie_read_pmRstIrqEnableClr_reg (baseAppRegs, readRegs->pmRstIrqEnableClr));
336 }
337
338 for (i = 0; i < 8; i ++) {
339 if (readRegs->obOffsetLo[i]) {
340 pcie_check_result(retVal, pcie_read_obOffsetLo_reg (baseAppRegs, readRegs->obOffsetLo[i], i));
341 }
342 if (readRegs->obOffsetHi[i]) {
343 pcie_check_result(retVal, pcie_read_obOffsetHi_reg (baseAppRegs, readRegs->obOffsetHi[i], i));
344 }
345 }
346
347 for (i = 0; i < 4; i ++) {
348 if (readRegs->ibBar[i]) {
349 pcie_check_result(retVal, pcie_read_ibBar_reg (baseAppRegs, readRegs->ibBar[i], i));
350 }
351 if (readRegs->ibStartLo[i]) {
352 pcie_check_result(retVal, pcie_read_ibStartLo_reg (baseAppRegs, readRegs->ibStartLo[i], i));
353 }
354 if (readRegs->ibStartHi[i]) {
355 pcie_check_result(retVal, pcie_read_ibStartHi_reg (baseAppRegs, readRegs->ibStartHi[i], i));
356 }
357 if (readRegs->ibOffset[i]) {
358 pcie_check_result(retVal, pcie_read_ibOffset_reg (baseAppRegs, readRegs->ibOffset[i], i));
359 }
360 }
361
362 if (readRegs->pcsCfg0) {
363 pcie_check_result(retVal, pcie_read_pcsCfg0_reg (baseAppRegs, readRegs->pcsCfg0));
364 }
365 if (readRegs->pcsCfg1) {
366 pcie_check_result(retVal, pcie_read_pcsCfg1_reg (baseAppRegs, readRegs->pcsCfg1));
367 }
368 if (readRegs->pcsStatus) {
369 pcie_check_result(retVal, pcie_read_pcsStatus_reg (baseAppRegs, readRegs->pcsStatus));
370 }
371
372 if (readRegs->serdesCfg0) {
373 pcie_check_result(retVal, pcie_read_serdesCfg0_reg (baseAppRegs, readRegs->serdesCfg0));
374 }
375 if (readRegs->serdesCfg1) {
376 pcie_check_result(retVal, pcie_read_serdesCfg1_reg (baseAppRegs, readRegs->serdesCfg1));
377 }
378
379 /*****************************************************************************************
380 *Configuration Registers
381 *****************************************************************************************/
382
383 /*Type 0, Type1 Common Registers*/
384
385 if (readRegs->vndDevId) {
386 pcie_check_result(retVal, pcie_read_vndDevId_reg (baseCfgEpRegs, readRegs->vndDevId));
387 }
388 if (readRegs->statusCmd) {
389 pcie_check_result(retVal, pcie_read_statusCmd_reg (baseCfgEpRegs, readRegs->statusCmd));
390 }
391 if (readRegs->revId) {
392 pcie_check_result(retVal, pcie_read_revId_reg (baseCfgEpRegs, readRegs->revId));
393 }
394
395 /*Type 0 Registers*/
396 if (readRegs->bist) {
397 pcie_check_result(retVal, pcie_read_bist_reg (baseCfgEpRegs, readRegs->bist));
398 }
399 if (readRegs->type0BarIdx) {
400 pcie_check_result(retVal, pcie_read_type0Bar_reg (baseCfgEpRegs, &(readRegs->type0BarIdx->reg),
401 readRegs->type0BarIdx->idx));
402 }
403 if (readRegs->type0Bar32bitIdx) {
404 pcie_check_result(retVal, pcie_read_type0Bar32bit_reg (baseCfgEpRegs, &(readRegs->type0Bar32bitIdx->reg),
405 readRegs->type0Bar32bitIdx->idx));
406 }
407 if (readRegs->subId) {
408 pcie_check_result(retVal, pcie_read_subId_reg (baseCfgEpRegs, readRegs->subId));
409 }
410 if (readRegs->expRom) {
411 pcie_check_result(retVal, pcie_read_expRom_reg (baseCfgEpRegs, readRegs->expRom));
412 }
413 if (readRegs->capPtr) {
414 pcie_check_result(retVal, pcie_read_capPtr_reg (baseCfgEpRegs, readRegs->capPtr));
415 }
416 if (readRegs->intPin) {
417 pcie_check_result(retVal, pcie_read_intPin_reg (baseCfgEpRegs, readRegs->intPin));
418 }
419
420 /*Type 1 Registers*/
421 if (readRegs->type1BistHeader) {
422 pcie_check_result(retVal, pcie_read_type1BistHeader_reg (baseCfgRcRegs, readRegs->type1BistHeader));
423 }
424 if (readRegs->type1BarIdx) {
425 pcie_check_result(retVal, pcie_read_type1Bar_reg (baseCfgRcRegs, &(readRegs->type1BarIdx->reg),
426 readRegs->type1BarIdx->idx));
427 }
428 if (readRegs->type1Bar32bitIdx) {
429 pcie_check_result(retVal, pcie_read_type1Bar32bit_reg (baseCfgRcRegs, &(readRegs->type1Bar32bitIdx->reg),
430 readRegs->type1Bar32bitIdx->idx));
431 }
432 if (readRegs->type1BusNum) {
433 pcie_check_result(retVal, pcie_read_type1BusNum_reg (baseCfgRcRegs, readRegs->type1BusNum));
434 }
435 if (readRegs->type1SecStat) {
436 pcie_check_result(retVal, pcie_read_type1SecStat_reg (baseCfgRcRegs, readRegs->type1SecStat));
437 }
438 if (readRegs->type1Memspace) {
439 pcie_check_result(retVal, pcie_read_type1Memspace_reg (baseCfgRcRegs, readRegs->type1Memspace));
440 }
441 if (readRegs->prefMem) {
442 pcie_check_result(retVal, pcie_read_prefMem_reg (baseCfgRcRegs, readRegs->prefMem));
443 }
444 if (readRegs->prefBaseUpper) {
445 pcie_check_result(retVal, pcie_read_prefBaseUpper_reg (baseCfgRcRegs, readRegs->prefBaseUpper));
446 }
447 if (readRegs->prefLimitUpper) {
448 pcie_check_result(retVal, pcie_read_prefLimitUpper_reg (baseCfgRcRegs, readRegs->prefLimitUpper));
449 }
450 if (readRegs->type1IOSpace) {
451 pcie_check_result(retVal, pcie_read_type1IOSpace_reg (baseCfgRcRegs, readRegs->type1IOSpace));
452 }
453 if (readRegs->type1CapPtr) {
454 pcie_check_result(retVal, pcie_read_type1CapPtr_reg (baseCfgRcRegs, readRegs->type1CapPtr));
455 }
456 if (readRegs->type1ExpnsnRom) {
457 pcie_check_result(retVal, pcie_read_type1ExpnsnRom_reg (baseCfgRcRegs, readRegs->type1ExpnsnRom));
458 }
459 if (readRegs->type1BridgeInt) {
460 pcie_check_result(retVal, pcie_read_type1BridgeInt_reg (baseCfgRcRegs, readRegs->type1BridgeInt));
461 }
462
463 /* Power Management Capabilities Registers */
464 if (readRegs->pmCap) {
465 pcie_check_result(retVal, pcie_read_pmCap_reg (baseCfgEpRegs, readRegs->pmCap));
466 } 151 }
467 if (readRegs->pmCapCtlStat) {
468 pcie_check_result(retVal, pcie_read_pmCapCtlStat_reg (baseCfgEpRegs, readRegs->pmCapCtlStat));
469 }
470
471 /*MSI Registers*/
472 if (readRegs->msiCap) {
473 pcie_check_result(retVal, pcie_read_msiCap_reg (baseCfgEpRegs, readRegs->msiCap));
474 }
475 if (readRegs->msiLo32) {
476 pcie_check_result(retVal, pcie_read_msiLo32_reg (baseCfgEpRegs, readRegs->msiLo32));
477 }
478 if (readRegs->msiUp32) {
479 pcie_check_result(retVal, pcie_read_msiUp32_reg (baseCfgEpRegs, readRegs->msiUp32));
480 }
481 if (readRegs->msiData) {
482 pcie_check_result(retVal, pcie_read_msiData_reg (baseCfgEpRegs, readRegs->msiData));
483 }
484
485 /*Capabilities Registers*/
486 if (readRegs->pciesCap) {
487 pcie_check_result(retVal, pcie_read_pciesCap_reg (baseCfgEpRegs, readRegs->pciesCap));
488 }
489 if (readRegs->deviceCap) {
490 pcie_check_result(retVal, pcie_read_deviceCap_reg (baseCfgEpRegs, readRegs->deviceCap));
491 }
492 if (readRegs->devStatCtrl) {
493 pcie_check_result(retVal, pcie_read_devStatCtrl_reg (baseCfgEpRegs, readRegs->devStatCtrl));
494 }
495 if (readRegs->linkCap) {
496 pcie_check_result(retVal, pcie_read_linkCap_reg (baseCfgEpRegs, readRegs->linkCap));
497 }
498 if (readRegs->linkStatCtrl) {
499 pcie_check_result(retVal, pcie_read_linkStatCtrl_reg (baseCfgEpRegs, readRegs->linkStatCtrl));
500 }
501 if (readRegs->slotCap) {
502 pcie_check_result(retVal, pcie_read_slotCap_reg (baseCfgRcRegs, readRegs->slotCap));
503 }
504 if (readRegs->slotStatCtrl) {
505 pcie_check_result(retVal, pcie_read_slotStatCtrl_reg (baseCfgRcRegs, readRegs->slotStatCtrl));
506 }
507 if (readRegs->rootCtrlCap) {
508 pcie_check_result(retVal, pcie_read_rootCtrlCap_reg (baseCfgRcRegs, readRegs->rootCtrlCap));
509 }
510 if (readRegs->rootStatus) {
511 pcie_check_result(retVal, pcie_read_rootStatus_reg (baseCfgRcRegs, readRegs->rootStatus));
512 }
513 if (readRegs->devCap2) {
514 pcie_check_result(retVal, pcie_read_devCap2_reg (baseCfgEpRegs, readRegs->devCap2));
515 }
516 if (readRegs->devStatCtrl2) {
517 pcie_check_result(retVal, pcie_read_devStatCtrl2_reg (baseCfgEpRegs, readRegs->devStatCtrl2));
518 }
519 if (readRegs->linkCtrl2) {
520 pcie_check_result(retVal, pcie_read_linkCtrl2_reg (baseCfgEpRegs, readRegs->linkCtrl2));
521 }
522
523 152
524 /*Capabilities Extended Registers*/ 153 if (! h->fxnTable.readRegs)
525 if (readRegs->extCap) { 154 {
526 pcie_check_result(retVal, pcie_read_extCap_reg (baseCfgEpRegs, readRegs->extCap)); 155 return pcie_RET_INV_FXNPTR;
527 }
528 if (readRegs->uncErr) {
529 pcie_check_result(retVal, pcie_read_uncErr_reg (baseCfgEpRegs, readRegs->uncErr));
530 }
531 if (readRegs->uncErrMask) {
532 pcie_check_result(retVal, pcie_read_uncErrMask_reg (baseCfgEpRegs, readRegs->uncErrMask));
533 }
534 if (readRegs->uncErrSvrty) {
535 pcie_check_result(retVal, pcie_read_uncErrSvrty_reg (baseCfgEpRegs, readRegs->uncErrSvrty));
536 }
537 if (readRegs->corErr) {
538 pcie_check_result(retVal, pcie_read_corErr_reg (baseCfgEpRegs, readRegs->corErr));
539 }
540 if (readRegs->corErrMask) {
541 pcie_check_result(retVal, pcie_read_corErrMask_reg (baseCfgEpRegs, readRegs->corErrMask));
542 }
543 if (readRegs->accr) {
544 pcie_check_result(retVal, pcie_read_accr_reg (baseCfgEpRegs, readRegs->accr));
545 }
546 for (i = 0; i < 4; i ++) {
547 if (readRegs->hdrLog[i]) {
548 pcie_check_result(retVal, pcie_read_hdrLog_reg (baseCfgEpRegs, readRegs->hdrLog[i], i));
549 }
550 }
551 if (readRegs->rootErrCmd) {
552 pcie_check_result(retVal, pcie_read_rootErrCmd_reg (baseCfgEpRegs, readRegs->rootErrCmd));
553 }
554 if (readRegs->rootErrSt) {
555 pcie_check_result(retVal, pcie_read_rootErrSt_reg (baseCfgEpRegs, readRegs->rootErrSt));
556 }
557 if (readRegs->errSrcID) {
558 pcie_check_result(retVal, pcie_read_errSrcID_reg (baseCfgEpRegs, readRegs->errSrcID));
559 }
560
561 /*Port Logic Registers*/
562 if (readRegs->plAckTimer) {
563 pcie_check_result(retVal, pcie_read_plAckTimer_reg (baseCfgEpRegs, readRegs->plAckTimer));
564 }
565 if (readRegs->plOMsg) {
566 pcie_check_result(retVal, pcie_read_plOMsg_reg (baseCfgEpRegs, readRegs->plOMsg));
567 }
568 if (readRegs->plForceLink) {
569 pcie_check_result(retVal, pcie_read_plForceLink_reg (baseCfgEpRegs, readRegs->plForceLink));
570 }
571 if (readRegs->ackFreq) {
572 pcie_check_result(retVal, pcie_read_ackFreq_reg (baseCfgEpRegs, readRegs->ackFreq));
573 }
574 if (readRegs->lnkCtrl) {
575 pcie_check_result(retVal, pcie_read_lnkCtrl_reg (baseCfgEpRegs, readRegs->lnkCtrl));
576 }
577 if (readRegs->laneSkew) {
578 pcie_check_result(retVal, pcie_read_laneSkew_reg (baseCfgEpRegs, readRegs->laneSkew));
579 }
580 if (readRegs->symNum) {
581 pcie_check_result(retVal, pcie_read_symNum_reg (baseCfgEpRegs, readRegs->symNum));
582 }
583 if (readRegs->symTimerFltMask) {
584 pcie_check_result(retVal, pcie_read_symTimerFltMask_reg (baseCfgEpRegs, readRegs->symTimerFltMask));
585 }
586 if (readRegs->fltMask2) {
587 pcie_check_result(retVal, pcie_read_fltMask2_reg (baseCfgEpRegs, readRegs->fltMask2));
588 }
589 if (readRegs->debug0) {
590 pcie_check_result(retVal, pcie_read_debug0_reg (baseCfgEpRegs, readRegs->debug0));
591 }
592 if (readRegs->debug1) {
593 pcie_check_result(retVal, pcie_read_debug1_reg (baseCfgEpRegs, readRegs->debug1));
594 }
595 if (readRegs->gen2) {
596 pcie_check_result(retVal, pcie_read_gen2_reg (baseCfgEpRegs, readRegs->gen2));
597 } 156 }
598 157
599 return retVal; 158 return h->fxnTable.readRegs (handle, location, readRegs);
600} /* Pcie_readRegs */ 159} /* Pcie_readRegs */
601 160
602 161
@@ -610,385 +169,19 @@ pcieRet_e Pcie_writeRegs
610 pcieRegisters_t *writeRegs /**< [in] List of registers to write */ 169 pcieRegisters_t *writeRegs /**< [in] List of registers to write */
611) 170)
612{ 171{
613 /* Base Address for the Application Registers */ 172 Pcie_IntHandle h = (Pcie_IntHandle)handle;
614 CSL_Pciess_appRegs *baseAppRegs = (CSL_Pciess_appRegs *)handle;
615
616 /* Base Address for the Config Space
617 These registers can be Local/Remote and Type0(EP)/Type1(RC) */
618 CSL_Pcie_cfg_space_rootcomplexRegs *baseCfgRcRegs = NULL;
619 CSL_Pcie_cfg_space_endpointRegs *baseCfgEpRegs = NULL;
620
621 pcieRet_e retVal = pcie_RET_OK;
622 int i;
623
624 if (! pcieLObjIsValid) {
625 return pcie_RET_NO_INIT;
626 }
627
628 pcie_check_handle(handle);
629 173
630 /* Get base address for Local/Remote config space */ 174 if (! h)
631 if (location == pcie_LOCATION_LOCAL)
632 { 175 {
633 pcie_get_loc_cfg_base(handle, baseCfgEpRegs, baseCfgRcRegs) 176 return pcie_RET_INV_HANDLE;
634 }
635 else
636 {
637 pcie_get_rem_cfg_base(handle, baseCfgEpRegs, baseCfgRcRegs)
638 }
639
640 /*****************************************************************************************
641 *Application Registers
642 *****************************************************************************************/
643 if (writeRegs->cmdStatus) {
644 pcie_check_result(retVal, pcie_write_cmdStatus_reg (baseAppRegs, writeRegs->cmdStatus));
645 }
646 if (writeRegs->cfgTrans) {
647 pcie_check_result(retVal, pcie_write_cfgTrans_reg (baseAppRegs, writeRegs->cfgTrans));
648 }
649 if (writeRegs->ioBase) {
650 pcie_check_result(retVal, pcie_write_ioBase_reg (baseAppRegs, writeRegs->ioBase));
651 }
652 if (writeRegs->tlpCfg) {
653 pcie_check_result(retVal, pcie_write_tlpCfg_reg (baseAppRegs, writeRegs->tlpCfg));
654 }
655 if (writeRegs->rstCmd) {
656 pcie_check_result(retVal, pcie_write_rstCmd_reg (baseAppRegs, writeRegs->rstCmd));
657 }
658 if (writeRegs->pmCmd) {
659 pcie_check_result(retVal, pcie_write_pmCmd_reg (baseAppRegs, writeRegs->pmCmd));
660 }
661 if (writeRegs->pmCfg) {
662 pcie_check_result(retVal, pcie_write_pmCfg_reg (baseAppRegs, writeRegs->pmCfg));
663 }
664 if (writeRegs->obSize) {
665 pcie_check_result(retVal, pcie_write_obSize_reg (baseAppRegs, writeRegs->obSize));
666 }
667 if (writeRegs->diagCtrl) {
668 pcie_check_result(retVal, pcie_write_diagCtrl_reg (baseAppRegs, writeRegs->diagCtrl));
669 }
670 if (writeRegs->endian) {
671 pcie_check_result(retVal, pcie_write_endian_reg (baseAppRegs, writeRegs->endian));
672 }
673 if (writeRegs->priority) {
674 pcie_check_result(retVal, pcie_write_priority_reg (baseAppRegs, writeRegs->priority));
675 }
676 if (writeRegs->irqEOI) {
677 pcie_check_result(retVal, pcie_write_irqEOI_reg (baseAppRegs, writeRegs->irqEOI));
678 }
679 if (writeRegs->msiIrq) {
680 pcie_check_result(retVal, pcie_write_msiIrq_reg (baseAppRegs, writeRegs->msiIrq));
681 }
682 if (writeRegs->epIrqSet) {
683 pcie_check_result(retVal, pcie_write_epIrqSet_reg (baseAppRegs, writeRegs->epIrqSet));
684 }
685 if (writeRegs->epIrqClr) {
686 pcie_check_result(retVal, pcie_write_epIrqClr_reg (baseAppRegs, writeRegs->epIrqClr));
687 }
688 if (writeRegs->epIrqStatus) {
689 pcie_check_result(retVal, pcie_write_epIrqStatus_reg (baseAppRegs, writeRegs->epIrqStatus));
690 }
691 for (i = 0; i < 4; i++) {
692 if (writeRegs->genPurpose[i]) {
693 pcie_check_result(retVal, pcie_write_genPurpose_reg (baseAppRegs, writeRegs->genPurpose[i], i));
694 }
695 }
696 for (i = 0; i < 8; i++) {
697 if (writeRegs->msiIrqStatusRaw[i]) {
698 pcie_check_result(retVal, pcie_write_msiIrqStatusRaw_reg (baseAppRegs, writeRegs->msiIrqStatusRaw[i], i));
699 }
700 if (writeRegs->msiIrqStatus[i]) {
701 pcie_check_result(retVal, pcie_write_msiIrqStatus_reg (baseAppRegs, writeRegs->msiIrqStatus[i], i));
702 }
703 if (writeRegs->msiIrqEnableSet[i]) {
704 pcie_check_result(retVal, pcie_write_msiIrqEnableSet_reg (baseAppRegs, writeRegs->msiIrqEnableSet[i], i));
705 }
706 if (writeRegs->msiIrqEnableClr[i]) {
707 pcie_check_result(retVal, pcie_write_msiIrqEnableClr_reg (baseAppRegs, writeRegs->msiIrqEnableClr[i], i));
708 }
709 }
710 for (i = 0; i < 4; i++) {
711 if (writeRegs->legacyIrqStatusRaw[i]) {
712 pcie_check_result(retVal, pcie_write_legacyIrqStatusRaw_reg (baseAppRegs, writeRegs->legacyIrqStatusRaw[i], i));
713 }
714 if (writeRegs->legacyIrqStatus[i]) {
715 pcie_check_result(retVal, pcie_write_legacyIrqStatus_reg (baseAppRegs, writeRegs->legacyIrqStatus[i], i));
716 }
717 if (writeRegs->legacyIrqEnableSet[i]) {
718 pcie_check_result(retVal, pcie_write_legacyIrqEnableSet_reg (baseAppRegs, writeRegs->legacyIrqEnableSet[i], i));
719 }
720 if (writeRegs->legacyIrqEnableClr[i]) {
721 pcie_check_result(retVal, pcie_write_legacyIrqEnableClr_reg (baseAppRegs, writeRegs->legacyIrqEnableClr[i], i));
722 }
723 }
724 if (writeRegs->errIrqStatusRaw) {
725 pcie_check_result(retVal, pcie_write_errIrqStatusRaw_reg (baseAppRegs, writeRegs->errIrqStatusRaw));
726 }
727 if (writeRegs->errIrqStatus) {
728 pcie_check_result(retVal, pcie_write_errIrqStatus_reg (baseAppRegs, writeRegs->errIrqStatus));
729 }
730 if (writeRegs->errIrqEnableSet) {
731 pcie_check_result(retVal, pcie_write_errIrqEnableSet_reg (baseAppRegs, writeRegs->errIrqEnableSet));
732 }
733 if (writeRegs->errIrqEnableClr) {
734 pcie_check_result(retVal, pcie_write_errIrqEnableClr_reg (baseAppRegs, writeRegs->errIrqEnableClr));
735 }
736
737 if (writeRegs->pmRstIrqStatusRaw) {
738 pcie_check_result(retVal, pcie_write_pmRstIrqStatusRaw_reg (baseAppRegs, writeRegs->pmRstIrqStatusRaw));
739 }
740 if (writeRegs->pmRstIrqStatus) {
741 pcie_check_result(retVal, pcie_write_pmRstIrqStatus_reg (baseAppRegs, writeRegs->pmRstIrqStatus));
742 }
743 if (writeRegs->pmRstIrqEnableSet) {
744 pcie_check_result(retVal, pcie_write_pmRstIrqEnableSet_reg (baseAppRegs, writeRegs->pmRstIrqEnableSet));
745 }
746 if (writeRegs->pmRstIrqEnableClr) {
747 pcie_check_result(retVal, pcie_write_pmRstIrqEnableClr_reg (baseAppRegs, writeRegs->pmRstIrqEnableClr));
748 }
749
750 for (i = 0; i < 8; i ++) {
751 if (writeRegs->obOffsetLo[i]) {
752 pcie_check_result(retVal, pcie_write_obOffsetLo_reg (baseAppRegs, writeRegs->obOffsetLo[i], i));
753 }
754 if (writeRegs->obOffsetHi[i]) {
755 pcie_check_result(retVal, pcie_write_obOffsetHi_reg (baseAppRegs, writeRegs->obOffsetHi[i], i));
756 }
757 }
758
759 for (i = 0; i < 4; i ++) {
760 if (writeRegs->ibBar[i]) {
761 pcie_check_result(retVal, pcie_write_ibBar_reg (baseAppRegs, writeRegs->ibBar[i], i));
762 }
763 if (writeRegs->ibStartLo[i]) {
764 pcie_check_result(retVal, pcie_write_ibStartLo_reg (baseAppRegs, writeRegs->ibStartLo[i], i));
765 }
766 if (writeRegs->ibStartHi[i]) {
767 pcie_check_result(retVal, pcie_write_ibStartHi_reg (baseAppRegs, writeRegs->ibStartHi[i], i));
768 }
769 if (writeRegs->ibOffset[i]) {
770 pcie_check_result(retVal, pcie_write_ibOffset_reg (baseAppRegs, writeRegs->ibOffset[i], i));
771 }
772 }
773
774 if (writeRegs->pcsCfg0) {
775 pcie_check_result(retVal, pcie_write_pcsCfg0_reg (baseAppRegs, writeRegs->pcsCfg0));
776 }
777 if (writeRegs->pcsCfg1) {
778 pcie_check_result(retVal, pcie_write_pcsCfg1_reg (baseAppRegs, writeRegs->pcsCfg1));
779 }
780
781 if (writeRegs->serdesCfg0) {
782 pcie_check_result(retVal, pcie_write_serdesCfg0_reg (baseAppRegs, writeRegs->serdesCfg0));
783 }
784 if (writeRegs->serdesCfg1) {
785 pcie_check_result(retVal, pcie_write_serdesCfg1_reg (baseAppRegs, writeRegs->serdesCfg1));
786 }
787
788 /*****************************************************************************************
789 *Configuration Registers
790 *****************************************************************************************/
791
792 /*Type 0, Type1 Common Registers*/
793
794 if (writeRegs->vndDevId) {
795 pcie_check_result(retVal, pcie_write_vndDevId_reg (baseCfgEpRegs, writeRegs->vndDevId));
796 }
797 if (writeRegs->statusCmd) {
798 pcie_check_result(retVal, pcie_write_statusCmd_reg (baseCfgEpRegs, writeRegs->statusCmd));
799 }
800 if (writeRegs->revId) {
801 pcie_check_result(retVal, pcie_write_revId_reg (baseCfgEpRegs, writeRegs->revId));
802 }
803
804 /*Type 0 Registers*/
805 if (writeRegs->bist) {
806 pcie_check_result(retVal, pcie_write_bist_reg (baseCfgEpRegs, writeRegs->bist));
807 }
808 if (writeRegs->type0BarIdx) {
809 pcie_check_result(retVal, pcie_write_type0Bar_reg (baseCfgEpRegs, &(writeRegs->type0BarIdx->reg),
810 writeRegs->type0BarIdx->idx));
811 }
812 if (writeRegs->type0Bar32bitIdx) {
813 pcie_check_result(retVal, pcie_write_type0Bar32bit_reg (baseCfgEpRegs, &(writeRegs->type0Bar32bitIdx->reg),
814 writeRegs->type0Bar32bitIdx->idx));
815 }
816 if (writeRegs->subId) {
817 pcie_check_result(retVal, pcie_write_subId_reg (baseCfgEpRegs, writeRegs->subId));
818 }
819 if (writeRegs->expRom) {
820 pcie_check_result(retVal, pcie_write_expRom_reg (baseCfgEpRegs, writeRegs->expRom));
821 }
822 if (writeRegs->capPtr) {
823 pcie_check_result(retVal, pcie_write_capPtr_reg (baseCfgEpRegs, writeRegs->capPtr));
824 }
825 if (writeRegs->intPin) {
826 pcie_check_result(retVal, pcie_write_intPin_reg (baseCfgEpRegs, writeRegs->intPin));
827 } 177 }
828 178
829 /*Type 1 Registers*/ 179 if (! h->fxnTable.writeRegs)
830 if (writeRegs->type1BistHeader) { 180 {
831 pcie_check_result(retVal, pcie_write_type1BistHeader_reg (baseCfgRcRegs, writeRegs->type1BistHeader)); 181 return pcie_RET_INV_FXNPTR;
832 }
833 if (writeRegs->type1BarIdx) {
834 pcie_check_result(retVal, pcie_write_type1Bar_reg (baseCfgRcRegs, &(writeRegs->type1BarIdx->reg),
835 writeRegs->type1BarIdx->idx));
836 }
837 if (writeRegs->type1Bar32bitIdx) {
838 pcie_check_result(retVal, pcie_write_type1Bar32bit_reg (baseCfgRcRegs, &(writeRegs->type1Bar32bitIdx->reg),
839 writeRegs->type1Bar32bitIdx->idx));
840 }
841 if (writeRegs->type1BusNum) {
842 pcie_check_result(retVal, pcie_write_type1BusNum_reg (baseCfgRcRegs, writeRegs->type1BusNum));
843 }
844 if (writeRegs->type1SecStat) {
845 pcie_check_result(retVal, pcie_write_type1SecStat_reg (baseCfgRcRegs, writeRegs->type1SecStat));
846 }
847 if (writeRegs->type1Memspace) {
848 pcie_check_result(retVal, pcie_write_type1Memspace_reg (baseCfgRcRegs, writeRegs->type1Memspace));
849 }
850 if (writeRegs->prefMem) {
851 pcie_check_result(retVal, pcie_write_prefMem_reg (baseCfgRcRegs, writeRegs->prefMem));
852 }
853 if (writeRegs->prefBaseUpper) {
854 pcie_check_result(retVal, pcie_write_prefBaseUpper_reg (baseCfgRcRegs, writeRegs->prefBaseUpper));
855 }
856 if (writeRegs->prefLimitUpper) {
857 pcie_check_result(retVal, pcie_write_prefLimitUpper_reg (baseCfgRcRegs, writeRegs->prefLimitUpper));
858 }
859 if (writeRegs->type1IOSpace) {
860 pcie_check_result(retVal, pcie_write_type1IOSpace_reg (baseCfgRcRegs, writeRegs->type1IOSpace));
861 }
862 if (writeRegs->type1CapPtr) {
863 pcie_check_result(retVal, pcie_write_type1CapPtr_reg (baseCfgRcRegs, writeRegs->type1CapPtr));
864 }
865 if (writeRegs->type1ExpnsnRom) {
866 pcie_check_result(retVal, pcie_write_type1ExpnsnRom_reg (baseCfgRcRegs, writeRegs->type1ExpnsnRom));
867 }
868 if (writeRegs->type1BridgeInt) {
869 pcie_check_result(retVal, pcie_write_type1BridgeInt_reg (baseCfgRcRegs, writeRegs->type1BridgeInt));
870 }
871
872 /* Power Management Capabilities Registers */
873 if (writeRegs->pmCap) {
874 pcie_check_result(retVal, pcie_write_pmCap_reg (baseCfgEpRegs, writeRegs->pmCap));
875 }
876 if (writeRegs->pmCapCtlStat) {
877 pcie_check_result(retVal, pcie_write_pmCapCtlStat_reg (baseCfgEpRegs, writeRegs->pmCapCtlStat));
878 }
879
880 /*MSI Registers*/
881 if (writeRegs->msiCap) {
882 pcie_check_result(retVal, pcie_write_msiCap_reg (baseCfgEpRegs, writeRegs->msiCap));
883 }
884 if (writeRegs->msiLo32) {
885 pcie_check_result(retVal, pcie_write_msiLo32_reg (baseCfgEpRegs, writeRegs->msiLo32));
886 }
887 if (writeRegs->msiUp32) {
888 pcie_check_result(retVal, pcie_write_msiUp32_reg (baseCfgEpRegs, writeRegs->msiUp32));
889 }
890 if (writeRegs->msiData) {
891 pcie_check_result(retVal, pcie_write_msiData_reg (baseCfgEpRegs, writeRegs->msiData));
892 }
893
894 /*Capabilities Registers*/
895 if (writeRegs->pciesCap) {
896 pcie_check_result(retVal, pcie_write_pciesCap_reg (baseCfgEpRegs, writeRegs->pciesCap));
897 }
898 if (writeRegs->deviceCap) {
899 pcie_check_result(retVal, pcie_write_deviceCap_reg (baseCfgEpRegs, writeRegs->deviceCap));
900 }
901
902 if (writeRegs->devStatCtrl) {
903 pcie_check_result(retVal, pcie_write_devStatCtrl_reg (baseCfgEpRegs, writeRegs->devStatCtrl));
904 }
905 if (writeRegs->linkCap) {
906 pcie_check_result(retVal, pcie_write_linkCap_reg (baseCfgEpRegs, writeRegs->linkCap));
907 }
908 if (writeRegs->linkStatCtrl) {
909 pcie_check_result(retVal, pcie_write_linkStatCtrl_reg (baseCfgEpRegs, writeRegs->linkStatCtrl));
910 }
911 if (writeRegs->slotCap) {
912 pcie_check_result(retVal, pcie_write_slotCap_reg (baseCfgRcRegs, writeRegs->slotCap));
913 }
914 if (writeRegs->slotStatCtrl) {
915 pcie_check_result(retVal, pcie_write_slotStatCtrl_reg (baseCfgRcRegs, writeRegs->slotStatCtrl));
916 }
917 if (writeRegs->rootCtrlCap) {
918 pcie_check_result(retVal, pcie_write_rootCtrlCap_reg (baseCfgRcRegs, writeRegs->rootCtrlCap));
919 }
920 if (writeRegs->rootStatus) {
921 pcie_check_result(retVal, pcie_write_rootStatus_reg (baseCfgRcRegs, writeRegs->rootStatus));
922 }
923 if (writeRegs->devCap2) {
924 pcie_check_result(retVal, pcie_write_devCap2_reg (baseCfgEpRegs, writeRegs->devCap2));
925 }
926 if (writeRegs->devStatCtrl2) {
927 pcie_check_result(retVal, pcie_write_devStatCtrl2_reg (baseCfgEpRegs, writeRegs->devStatCtrl2));
928 }
929 if (writeRegs->linkCtrl2) {
930 pcie_check_result(retVal, pcie_write_linkCtrl2_reg (baseCfgEpRegs, writeRegs->linkCtrl2));
931 }
932
933 /*Capabilities Extended Registers*/
934 if (writeRegs->uncErr) {
935 pcie_check_result(retVal, pcie_write_uncErr_reg (baseCfgEpRegs, writeRegs->uncErr));
936 }
937 if (writeRegs->uncErrMask) {
938 pcie_check_result(retVal, pcie_write_uncErrMask_reg (baseCfgEpRegs, writeRegs->uncErrMask));
939 }
940 if (writeRegs->uncErrSvrty) {
941 pcie_check_result(retVal, pcie_write_uncErrSvrty_reg (baseCfgEpRegs, writeRegs->uncErrSvrty));
942 }
943 if (writeRegs->corErr) {
944 pcie_check_result(retVal, pcie_write_corErr_reg (baseCfgEpRegs, writeRegs->corErr));
945 }
946 if (writeRegs->corErrMask) {
947 pcie_check_result(retVal, pcie_write_corErrMask_reg (baseCfgEpRegs, writeRegs->corErrMask));
948 }
949 if (writeRegs->accr) {
950 pcie_check_result(retVal, pcie_write_accr_reg (baseCfgEpRegs, writeRegs->accr));
951 }
952 if (writeRegs->rootErrCmd) {
953 pcie_check_result(retVal, pcie_write_rootErrCmd_reg (baseCfgEpRegs, writeRegs->rootErrCmd));
954 }
955 if (writeRegs->rootErrSt) {
956 pcie_check_result(retVal, pcie_write_rootErrSt_reg (baseCfgEpRegs, writeRegs->rootErrSt));
957 }
958
959 /*Port Logic Registers*/
960 if (writeRegs->plAckTimer) {
961 pcie_check_result(retVal, pcie_write_plAckTimer_reg (baseCfgEpRegs, writeRegs->plAckTimer));
962 }
963 if (writeRegs->plOMsg) {
964 pcie_check_result(retVal, pcie_write_plOMsg_reg (baseCfgEpRegs, writeRegs->plOMsg));
965 }
966 if (writeRegs->plForceLink) {
967 pcie_check_result(retVal, pcie_write_plForceLink_reg (baseCfgEpRegs, writeRegs->plForceLink));
968 }
969 if (writeRegs->ackFreq) {
970 pcie_check_result(retVal, pcie_write_ackFreq_reg (baseCfgEpRegs, writeRegs->ackFreq));
971 }
972 if (writeRegs->lnkCtrl) {
973 pcie_check_result(retVal, pcie_write_lnkCtrl_reg (baseCfgEpRegs, writeRegs->lnkCtrl));
974 }
975 if (writeRegs->laneSkew) {
976 pcie_check_result(retVal, pcie_write_laneSkew_reg (baseCfgEpRegs, writeRegs->laneSkew));
977 }
978 if (writeRegs->symNum) {
979 pcie_check_result(retVal, pcie_write_symNum_reg (baseCfgEpRegs, writeRegs->symNum));
980 }
981 if (writeRegs->symTimerFltMask) {
982 pcie_check_result(retVal, pcie_write_symTimerFltMask_reg (baseCfgEpRegs, writeRegs->symTimerFltMask));
983 }
984 if (writeRegs->fltMask2) {
985 pcie_check_result(retVal, pcie_write_fltMask2_reg (baseCfgEpRegs, writeRegs->fltMask2));
986 }
987 if (writeRegs->gen2) {
988 pcie_check_result(retVal, pcie_write_gen2_reg (baseCfgEpRegs, writeRegs->gen2));
989 } 182 }
990 183
991 return retVal; 184 return h->fxnTable.writeRegs (handle, location, writeRegs);
992} /* Pcie_writeRegs */ 185} /* Pcie_writeRegs */
993 186
994 187
@@ -1004,34 +197,20 @@ pcieRet_e Pcie_cfgObOffset
1004 uint8_t region /**< [in] Identifies the Outbound region (0-31) */ 197 uint8_t region /**< [in] Identifies the Outbound region (0-31) */
1005) 198)
1006{ 199{
200 Pcie_IntHandle h = (Pcie_IntHandle)handle;
1007 201
1008 CSL_Pciess_appRegs *baseAppRegs = (CSL_Pciess_appRegs *)handle; 202 if (! h)
1009 pcieRet_e retVal = pcie_RET_OK; 203 {
1010 pcieObOffsetLoReg_t obOffsetLo; 204 return pcie_RET_INV_HANDLE;
1011 pcieObOffsetHiReg_t obOffsetHi;
1012 uint16_t obAddrLoField;
1013
1014 if (! pcieLObjIsValid) {
1015 return pcie_RET_NO_INIT;
1016 } 205 }
1017 206
1018 pcie_check_handle(handle); 207 if (! h->fxnTable.cfgObOffset)
1019 208 {
1020 memset (&obOffsetLo, 0, sizeof(obOffsetLo)); 209 return pcie_RET_INV_FXNPTR;
1021 memset (&obOffsetHi, 0, sizeof(obOffsetHi)); 210 }
1022
1023 pcie_getbits(obAddrLo, CSL_PCIESS_APP_OB_OFFSET_INDEX_OB_OFFSET_LO, obAddrLoField);
1024
1025 obOffsetLo.enable = 1;
1026 obOffsetLo.offsetLo = obAddrLoField;
1027
1028 obOffsetHi.offsetHi = obAddrHi;
1029
1030 pcie_check_result(retVal, pcie_write_obOffsetLo_reg(baseAppRegs, &obOffsetLo, region));
1031 pcie_check_result(retVal, pcie_write_obOffsetHi_reg(baseAppRegs, &obOffsetHi, region));
1032 211
1033 return retVal; 212 return h->fxnTable.cfgObOffset (handle, obAddrLo, obAddrHi, region);
1034} 213} /* Pcie_cfgObOffset */
1035 214
1036 215
1037/********************************************************************* 216/*********************************************************************
@@ -1043,47 +222,20 @@ pcieRet_e Pcie_cfgIbTrans
1043 pcieIbTransCfg_t *ibCfg /**< [in] Inbound Translation Configuration parameters */ 222 pcieIbTransCfg_t *ibCfg /**< [in] Inbound Translation Configuration parameters */
1044) 223)
1045{ 224{
225 Pcie_IntHandle h = (Pcie_IntHandle)handle;
1046 226
1047 CSL_Pciess_appRegs *baseAppRegs = (CSL_Pciess_appRegs *)handle; 227 if (! h)
1048 pcieRet_e retVal = pcie_RET_OK; 228 {
1049 229 return pcie_RET_INV_HANDLE;
1050 pcieIbBarReg_t ibBar;
1051 pcieIbStartLoReg_t ibStartLo;
1052 pcieIbStartHiReg_t ibStartHi;
1053 pcieIbOffsetReg_t ibOffset;
1054
1055 uint32_t ibStartLoField;
1056 uint32_t ibOffsetField;
1057
1058 if (! pcieLObjIsValid) {
1059 return pcie_RET_NO_INIT;
1060 } 230 }
1061 231
1062 pcie_check_handle(handle); 232 if (! h->fxnTable.cfgIbTrans)
1063 233 {
1064 memset (&ibBar, 0, sizeof(ibBar)); 234 return pcie_RET_INV_FXNPTR;
1065 memset (&ibStartLo, 0, sizeof(ibStartLo)); 235 }
1066 memset (&ibStartHi, 0, sizeof(ibStartHi));
1067 memset (&ibOffset, 0, sizeof(ibOffset));
1068
1069 ibBar.ibBar = ibCfg->ibBar;
1070
1071 pcie_getbits(ibCfg->ibStartAddrLo, CSL_PCIESS_APP_IB_START_LO_IB_START_LO, ibStartLoField);
1072 ibStartLo.ibStartLo = ibStartLoField;
1073
1074 ibStartHi.ibStartHi = ibCfg->ibStartAddrHi;
1075
1076 pcie_getbits(ibCfg->ibOffsetAddr, CSL_PCIESS_APP_IB_OFFSET_IB_OFFSET, ibOffsetField);
1077 ibOffset.ibOffset = ibOffsetField;
1078
1079
1080 pcie_check_result(retVal, pcie_write_ibBar_reg (baseAppRegs, &ibBar, ibCfg->region));
1081 pcie_check_result(retVal, pcie_write_ibStartLo_reg(baseAppRegs, &ibStartLo, ibCfg->region));
1082 pcie_check_result(retVal, pcie_write_ibStartHi_reg(baseAppRegs, &ibStartHi, ibCfg->region));
1083 pcie_check_result(retVal, pcie_write_ibOffset_reg (baseAppRegs, &ibOffset, ibCfg->region));
1084 236
1085 return retVal; 237 return h->fxnTable.cfgIbTrans (handle, ibCfg);
1086} 238} /* Pcie_cfgIbTrans */
1087 239
1088 240
1089/********************************************************************* 241/*********************************************************************
@@ -1095,54 +247,20 @@ pcieRet_e Pcie_cfgBar
1095 pcieBarCfg_t *barCfg /**< [in] BAR configuration parameters */ 247 pcieBarCfg_t *barCfg /**< [in] BAR configuration parameters */
1096) 248)
1097{ 249{
1098 pcieType0BarIdx_t type0BarIdx; 250 Pcie_IntHandle h = (Pcie_IntHandle)handle;
1099 pcieType1BarIdx_t type1BarIdx;
1100 pcieRegisters_t setRegs;
1101 uint32_t barAddrField = 0;
1102 pcieRet_e retVal = pcie_RET_OK;
1103
1104 if (! pcieLObjIsValid) {
1105 return pcie_RET_NO_INIT;
1106 }
1107
1108 pcie_check_handle(handle);
1109
1110 memset (&setRegs, 0, sizeof(setRegs));
1111 memset (&type0BarIdx, 0, sizeof(type0BarIdx));
1112 memset (&type1BarIdx, 0, sizeof(type1BarIdx));
1113
1114 if(barCfg->mode == pcie_RC_MODE)
1115 {
1116 pcie_getbits(barCfg->base, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BAR_BASE_ADDRESS, barAddrField);
1117
1118 type1BarIdx.reg.base = barAddrField;
1119 type1BarIdx.reg.prefetch = barCfg->prefetch;
1120 type1BarIdx.reg.type = barCfg->type;
1121 type1BarIdx.reg.memSpace = barCfg->memSpace;
1122 type1BarIdx.idx = barCfg->idx;
1123 251
1124 setRegs.type1BarIdx = &type1BarIdx; 252 if (! h)
1125 }
1126 else
1127 { 253 {
1128 pcie_getbits(barCfg->base, CSL_PCIE_CFG_SPACE_ENDPOINT_BAR_BASE_ADDRESS, barAddrField); 254 return pcie_RET_INV_HANDLE;
1129
1130 type0BarIdx.reg.base = barAddrField;
1131 type0BarIdx.reg.prefetch = barCfg->prefetch;
1132 type0BarIdx.reg.type = barCfg->type;
1133 type0BarIdx.reg.memSpace = barCfg->memSpace;
1134 type0BarIdx.idx = barCfg->idx;
1135
1136 setRegs.type0BarIdx = &type0BarIdx;
1137 } 255 }
1138 256
1139 if ((retVal = Pcie_writeRegs (handle, barCfg->location, &setRegs)) != pcie_RET_OK) 257 if (! h->fxnTable.cfgBar)
1140 { 258 {
1141 return retVal; 259 return pcie_RET_INV_FXNPTR;
1142 } 260 }
1143 261
1144 return retVal; 262 return h->fxnTable.cfgBar (handle, barCfg);
1145} 263} /* Pcie_cfgBar */
1146 264
1147 265
1148/********************************************************************* 266/*********************************************************************
diff --git a/src/pcieinit.c b/src/pcieinit.c
index f680ea6..98942d1 100755..100644
--- a/src/pcieinit.c
+++ b/src/pcieinit.c
@@ -1,6 +1,6 @@
1/* 1/*
2 * 2 *
3 * Copyright (C) 2010-2013 Texas Instruments Incorporated - http://www.ti.com/ 3 * Copyright (C) 2010-2015 Texas Instruments Incorporated - http://www.ti.com/
4 * 4 *
5 * 5 *
6 * Redistribution and use in source and binary forms, with or without 6 * Redistribution and use in source and binary forms, with or without
@@ -62,7 +62,13 @@ pcieRet_e Pcie_init
62 const Pcie_InitCfg *cfg /**< [in] configuration */ 62 const Pcie_InitCfg *cfg /**< [in] configuration */
63) 63)
64{ 64{
65 pcieLObj.cfg = *cfg; 65 int i;
66
67 for (i = 0; i < pcie_MAX_PERIPHS; i++)
68 {
69 pcieLObj.insts[i].fxnTable = *cfg->dev.fxnTablePtr[i];
70 pcieLObj.insts[i].bases = *cfg->dev.basesPtr[i];
71 }
66 pcieLObjIsValid = 1; 72 pcieLObjIsValid = 1;
67 73
68 return pcie_RET_OK; 74 return pcie_RET_OK;
@@ -91,9 +97,9 @@ pcieRet_e Pcie_open
91 } else if (!pHandle) { 97 } else if (!pHandle) {
92 retVal = pcie_RET_INV_HANDLE; 98 retVal = pcie_RET_INV_HANDLE;
93 } else { 99 } else {
94 if (pcieLObj.cfg.dev.bases[deviceNum].cfgBase && 100 if (pcieLObj.insts[deviceNum].bases.cfgBase &&
95 pcieLObj.cfg.dev.bases[deviceNum].dataBase) { 101 pcieLObj.insts[deviceNum].bases.dataBase) {
96 *pHandle = pcieLObj.cfg.dev.bases[deviceNum].cfgBase; 102 *pHandle = &pcieLObj.insts[deviceNum];
97 } else { 103 } else {
98 retVal = pcie_RET_INV_DEVICENUM; 104 retVal = pcie_RET_INV_DEVICENUM;
99 } 105 }
diff --git a/src/pcieloc.h b/src/pcieloc.h
index 1584284..05e8936 100755..100644
--- a/src/pcieloc.h
+++ b/src/pcieloc.h
@@ -1,6 +1,6 @@
1/* 1/*
2 * 2 *
3 * Copyright (C) 2010-2013 Texas Instruments Incorporated - http://www.ti.com/ 3 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
4 * 4 *
5 * 5 *
6 * Redistribution and use in source and binary forms, with or without 6 * Redistribution and use in source and binary forms, with or without
@@ -55,22 +55,10 @@ extern "C" {
55 55
56/* Common utility macros */ 56/* Common utility macros */
57 57
58/* Get base address for Local Configuration Space */
59#define pcie_get_loc_cfg_base(handle, ep_loc_base, rc_loc_base) \
60 { \
61 ep_loc_base = (CSL_Pcie_cfg_space_endpointRegs *) ((unsigned int)handle + 0x1000); \
62 rc_loc_base = (CSL_Pcie_cfg_space_rootcomplexRegs *) ((unsigned int)handle + 0x1000); \
63 }
64
65/* Get base address for Remote Configuration Space */
66#define pcie_get_rem_cfg_base(handle, ep_rem_base, rc_rem_base) \
67 { \
68 ep_rem_base = (CSL_Pcie_cfg_space_endpointRegs *) ((unsigned int)handle + 0x2000); \
69 rc_rem_base = (CSL_Pcie_cfg_space_rootcomplexRegs *) ((unsigned int)handle + 0x2000); \
70 }
71
72/* Handle must point to one of the valid peripheral base addresses */ 58/* Handle must point to one of the valid peripheral base addresses */
73int pcie_check_handle_fcn (Pcie_Handle handle); 59int pcie_check_handle_fcn (Pcie_Handle handle);
60Pcie_DeviceCfgBaseAddr *pcie_handle_to_cfg (Pcie_Handle handle);
61
74#define pcie_check_handle(x) \ 62#define pcie_check_handle(x) \
75 if (pcie_check_handle_fcn(x) == 0) { \ 63 if (pcie_check_handle_fcn(x) == 0) { \
76 return pcie_RET_INV_HANDLE; \ 64 return pcie_RET_INV_HANDLE; \
@@ -136,1106 +124,18 @@ int pcie_check_handle_fcn (Pcie_Handle handle);
136#define pcie_getbits(val,field,final_result) \ 124#define pcie_getbits(val,field,final_result) \
137 final_result = (val & field##_MASK) >> field##_SHIFT; 125 final_result = (val & field##_MASK) >> field##_SHIFT;
138 126
139 127/*****************************************************************************
140 128 * pcie handle - internal definition
141/****************************************************************************** 129 *
142 * Prototypes 130 * handle/instance pointer, complete type (external is void *)
143 ******************************************************************************/ 131 *****************************************************************************/
144 132typedef struct Pcie_IntHandle_s
145/***************************************************************************************** 133{
146*Application Registers 134 /*! table of soc specific PCIE functions */
147*****************************************************************************************/ 135 Pcie_FxnTable fxnTable;
148 136 /*! sructure containing base addresses for this PCIE */
149pcieRet_e pcie_read_pid_reg( 137 Pcie_DeviceCfgBaseAddr bases;
150 CSL_Pciess_appRegs *baseAddr, 138} *Pcie_IntHandle;
151 pciePidReg_t *reg);
152pcieRet_e pcie_read_cmdStatus_reg
153(
154 CSL_Pciess_appRegs *baseAddr,
155 pcieCmdStatusReg_t *reg);
156pcieRet_e pcie_write_cmdStatus_reg
157(
158 CSL_Pciess_appRegs *baseAddr,
159 pcieCmdStatusReg_t *reg);
160pcieRet_e pcie_read_cfgTrans_reg
161(
162 CSL_Pciess_appRegs *baseAddr,
163 pcieCfgTransReg_t *reg);
164pcieRet_e pcie_write_cfgTrans_reg
165(
166 CSL_Pciess_appRegs *baseAddr,
167 pcieCfgTransReg_t *reg);
168pcieRet_e pcie_read_ioBase_reg
169(
170 CSL_Pciess_appRegs *baseAddr,
171 pcieIoBaseReg_t *reg);
172pcieRet_e pcie_write_ioBase_reg
173(
174 CSL_Pciess_appRegs *baseAddr,
175 pcieIoBaseReg_t *reg);
176pcieRet_e pcie_read_tlpCfg_reg
177(
178 CSL_Pciess_appRegs *baseAddr,
179 pcieTlpCfgReg_t *reg);
180pcieRet_e pcie_write_tlpCfg_reg
181(
182 CSL_Pciess_appRegs *baseAddr,
183 pcieTlpCfgReg_t *reg);
184pcieRet_e pcie_read_rstCmd_reg
185(
186 CSL_Pciess_appRegs *baseAddr,
187 pcieRstCmdReg_t *reg);
188pcieRet_e pcie_write_rstCmd_reg
189(
190 CSL_Pciess_appRegs *baseAddr,
191 pcieRstCmdReg_t *reg);
192pcieRet_e pcie_read_pmCmd_reg
193(
194 CSL_Pciess_appRegs *baseAddr,
195 pciePmCmdReg_t *reg);
196pcieRet_e pcie_write_pmCmd_reg
197(
198 CSL_Pciess_appRegs *baseAddr,
199 pciePmCmdReg_t *reg);
200pcieRet_e pcie_read_pmCfg_reg
201(
202 CSL_Pciess_appRegs *baseAddr,
203 pciePmCfgReg_t *reg);
204pcieRet_e pcie_write_pmCfg_reg
205(
206 CSL_Pciess_appRegs *baseAddr,
207 pciePmCfgReg_t *reg);
208pcieRet_e pcie_read_actStatus_reg
209(
210 CSL_Pciess_appRegs *baseAddr,
211 pcieActStatusReg_t *reg);
212pcieRet_e pcie_read_obSize_reg
213(
214 CSL_Pciess_appRegs *baseAddr,
215 pcieObSizeReg_t *reg);
216pcieRet_e pcie_write_obSize_reg
217(
218 CSL_Pciess_appRegs *baseAddr,
219 pcieObSizeReg_t *reg);
220pcieRet_e pcie_read_diagCtrl_reg
221(
222 CSL_Pciess_appRegs *baseAddr,
223 pcieDiagCtrlReg_t *reg
224);
225pcieRet_e pcie_write_diagCtrl_reg
226(
227 CSL_Pciess_appRegs *baseAddr,
228 pcieDiagCtrlReg_t *reg
229);
230pcieRet_e pcie_read_endian_reg
231(
232 CSL_Pciess_appRegs *baseAddr,
233 pcieEndianReg_t *reg
234);
235pcieRet_e pcie_write_endian_reg
236(
237 CSL_Pciess_appRegs *baseAddr,
238 pcieEndianReg_t *reg
239);
240pcieRet_e pcie_read_priority_reg
241(
242 CSL_Pciess_appRegs *baseAddr,
243 pciePriorityReg_t *reg
244);
245pcieRet_e pcie_write_priority_reg
246(
247 CSL_Pciess_appRegs *baseAddr,
248 pciePriorityReg_t *reg
249);
250pcieRet_e pcie_read_irqEOI_reg
251(
252 CSL_Pciess_appRegs *baseAddr,
253 pcieIrqEOIReg_t *reg
254);
255pcieRet_e pcie_write_irqEOI_reg
256(
257 CSL_Pciess_appRegs *baseAddr,
258 pcieIrqEOIReg_t *reg
259);
260pcieRet_e pcie_read_msiIrq_reg
261(
262 CSL_Pciess_appRegs *baseAddr,
263 pcieMsiIrqReg_t *reg
264);
265pcieRet_e pcie_write_msiIrq_reg
266(
267 CSL_Pciess_appRegs *baseAddr,
268 pcieMsiIrqReg_t *reg
269);
270pcieRet_e pcie_read_epIrqSet_reg
271(
272 CSL_Pciess_appRegs *baseAddr,
273 pcieEpIrqSetReg_t *reg
274);
275pcieRet_e pcie_write_epIrqSet_reg
276(
277 CSL_Pciess_appRegs *baseAddr,
278 pcieEpIrqSetReg_t *reg
279);
280pcieRet_e pcie_read_epIrqClr_reg
281(
282 CSL_Pciess_appRegs *baseAddr,
283 pcieEpIrqClrReg_t *reg
284);
285pcieRet_e pcie_write_epIrqClr_reg
286(
287 CSL_Pciess_appRegs *baseAddr,
288 pcieEpIrqClrReg_t *reg
289);
290pcieRet_e pcie_read_epIrqStatus_reg
291(
292 CSL_Pciess_appRegs *baseAddr,
293 pcieEpIrqStatusReg_t *reg
294);
295pcieRet_e pcie_write_epIrqStatus_reg
296(
297 CSL_Pciess_appRegs *baseAddr,
298 pcieEpIrqStatusReg_t *reg
299);
300pcieRet_e pcie_read_genPurpose_reg
301(
302 CSL_Pciess_appRegs *baseAddr,
303 pcieGenPurposeReg_t *reg,
304 int regNum
305);
306pcieRet_e pcie_write_genPurpose_reg
307(
308 CSL_Pciess_appRegs *baseAddr,
309 pcieGenPurposeReg_t *reg,
310 int regNum
311);
312pcieRet_e pcie_read_msiIrqStatusRaw_reg
313(
314 CSL_Pciess_appRegs *baseAddr,
315 pcieMsiIrqStatusRawReg_t *reg,
316 int regNum
317);
318pcieRet_e pcie_write_msiIrqStatusRaw_reg
319(
320 CSL_Pciess_appRegs *baseAddr,
321 pcieMsiIrqStatusRawReg_t *reg,
322 int regNum
323);
324pcieRet_e pcie_read_msiIrqStatus_reg
325(
326 CSL_Pciess_appRegs *baseAddr,
327 pcieMsiIrqStatusReg_t *reg,
328 int regNum
329);
330pcieRet_e pcie_write_msiIrqStatus_reg
331(
332 CSL_Pciess_appRegs *baseAddr,
333 pcieMsiIrqStatusReg_t *reg,
334 int regNum
335);
336pcieRet_e pcie_read_msiIrqEnableSet_reg
337(
338 CSL_Pciess_appRegs *baseAddr,
339 pcieMsiIrqEnableSetReg_t *reg,
340 int regNum
341);
342pcieRet_e pcie_write_msiIrqEnableSet_reg
343(
344 CSL_Pciess_appRegs *baseAddr,
345 pcieMsiIrqEnableSetReg_t *reg,
346 int regNum
347);
348pcieRet_e pcie_read_msiIrqEnableClr_reg
349(
350 CSL_Pciess_appRegs *baseAddr,
351 pcieMsiIrqEnableClrReg_t *reg,
352 int regNum
353);
354pcieRet_e pcie_write_msiIrqEnableClr_reg
355(
356 CSL_Pciess_appRegs *baseAddr,
357 pcieMsiIrqEnableClrReg_t *reg,
358 int regNum
359);
360pcieRet_e pcie_read_legacyIrqStatusRaw_reg
361(
362 CSL_Pciess_appRegs *baseAddr,
363 pcieLegacyIrqStatusRawReg_t *reg,
364 int regNum
365);
366pcieRet_e pcie_write_legacyIrqStatusRaw_reg
367(
368 CSL_Pciess_appRegs *baseAddr,
369 pcieLegacyIrqStatusRawReg_t *reg,
370 int regNum
371);
372pcieRet_e pcie_read_legacyIrqStatus_reg
373(
374 CSL_Pciess_appRegs *baseAddr,
375 pcieLegacyIrqStatusReg_t *reg,
376 int regNum
377);
378pcieRet_e pcie_write_legacyIrqStatus_reg
379(
380 CSL_Pciess_appRegs *baseAddr,
381 pcieLegacyIrqStatusReg_t *reg,
382 int regNum
383);
384pcieRet_e pcie_read_legacyIrqEnableSet_reg
385(
386 CSL_Pciess_appRegs *baseAddr,
387 pcieLegacyIrqEnableSetReg_t *reg,
388 int regNum
389);
390pcieRet_e pcie_write_legacyIrqEnableSet_reg
391(
392 CSL_Pciess_appRegs *baseAddr,
393 pcieLegacyIrqEnableSetReg_t *reg,
394 int regNum
395);
396pcieRet_e pcie_read_legacyIrqEnableClr_reg
397(
398 CSL_Pciess_appRegs *baseAddr,
399 pcieLegacyIrqEnableClrReg_t *reg,
400 int regNum
401);
402pcieRet_e pcie_write_legacyIrqEnableClr_reg
403(
404 CSL_Pciess_appRegs *baseAddr,
405 pcieLegacyIrqEnableClrReg_t *reg,
406 int regNum
407);
408pcieRet_e pcie_read_errIrqStatusRaw_reg
409(
410 CSL_Pciess_appRegs *baseAddr,
411 pcieErrIrqStatusRawReg_t *reg
412);
413pcieRet_e pcie_write_errIrqStatusRaw_reg
414(
415 CSL_Pciess_appRegs *baseAddr,
416 pcieErrIrqStatusRawReg_t *reg
417);
418pcieRet_e pcie_read_errIrqStatus_reg
419(
420 CSL_Pciess_appRegs *baseAddr,
421 pcieErrIrqStatusReg_t *reg
422);
423pcieRet_e pcie_write_errIrqStatus_reg
424(
425 CSL_Pciess_appRegs *baseAddr,
426 pcieErrIrqStatusReg_t *reg
427);
428pcieRet_e pcie_read_errIrqEnableSet_reg
429(
430 CSL_Pciess_appRegs *baseAddr,
431 pcieErrIrqEnableSetReg_t *reg
432);
433pcieRet_e pcie_write_errIrqEnableSet_reg
434(
435 CSL_Pciess_appRegs *baseAddr,
436 pcieErrIrqEnableSetReg_t *reg
437);
438pcieRet_e pcie_read_errIrqEnableClr_reg
439(
440 CSL_Pciess_appRegs *baseAddr,
441 pcieErrIrqEnableClrReg_t *reg
442);
443pcieRet_e pcie_write_errIrqEnableClr_reg
444(
445 CSL_Pciess_appRegs *baseAddr,
446 pcieErrIrqEnableClrReg_t *reg
447);
448pcieRet_e pcie_read_pmRstIrqStatusRaw_reg
449(
450 CSL_Pciess_appRegs *baseAddr,
451 pciePmRstIrqStatusRawReg_t *reg
452);
453pcieRet_e pcie_write_pmRstIrqStatusRaw_reg
454(
455 CSL_Pciess_appRegs *baseAddr,
456 pciePmRstIrqStatusRawReg_t *reg
457);
458pcieRet_e pcie_read_pmRstIrqStatus_reg
459(
460 CSL_Pciess_appRegs *baseAddr,
461 pciePmRstIrqStatusReg_t *reg
462);
463pcieRet_e pcie_write_pmRstIrqStatus_reg
464(
465 CSL_Pciess_appRegs *baseAddr,
466 pciePmRstIrqStatusReg_t *reg
467);
468pcieRet_e pcie_read_pmRstIrqEnableSet_reg
469(
470 CSL_Pciess_appRegs *baseAddr,
471 pciePmRstIrqEnableSetReg_t *reg
472);
473pcieRet_e pcie_write_pmRstIrqEnableSet_reg
474(
475 CSL_Pciess_appRegs *baseAddr,
476 pciePmRstIrqEnableSetReg_t *reg
477);
478pcieRet_e pcie_read_pmRstIrqEnableClr_reg
479(
480 CSL_Pciess_appRegs *baseAddr,
481 pciePmRstIrqEnableClrReg_t *reg
482);
483pcieRet_e pcie_write_pmRstIrqEnableClr_reg
484(
485 CSL_Pciess_appRegs *baseAddr,
486 pciePmRstIrqEnableClrReg_t *reg
487);
488pcieRet_e pcie_read_obOffsetLo_reg
489(
490 CSL_Pciess_appRegs *baseAddr,
491 pcieObOffsetLoReg_t *reg,
492 int regNum);
493pcieRet_e pcie_write_obOffsetLo_reg
494(
495 CSL_Pciess_appRegs *baseAddr,
496 pcieObOffsetLoReg_t *reg,
497 int regNum);
498pcieRet_e pcie_read_obOffsetHi_reg
499(
500 CSL_Pciess_appRegs *baseAddr,
501 pcieObOffsetHiReg_t *reg,
502 int regNum);
503pcieRet_e pcie_write_obOffsetHi_reg
504(
505 CSL_Pciess_appRegs *baseAddr,
506 pcieObOffsetHiReg_t *reg,
507 int regNum);
508pcieRet_e pcie_read_ibBar_reg
509(
510 CSL_Pciess_appRegs *baseAddr,
511 pcieIbBarReg_t *reg,
512 int regNum);
513pcieRet_e pcie_write_ibBar_reg
514(
515 CSL_Pciess_appRegs *baseAddr,
516 pcieIbBarReg_t *reg,
517 int regNum);
518pcieRet_e pcie_read_ibStartLo_reg
519(
520 CSL_Pciess_appRegs *baseAddr,
521 pcieIbStartLoReg_t *reg,
522 int regNum);
523pcieRet_e pcie_write_ibStartLo_reg
524(
525 CSL_Pciess_appRegs *baseAddr,
526 pcieIbStartLoReg_t *reg,
527 int regNum);
528pcieRet_e pcie_read_ibStartHi_reg
529(
530 CSL_Pciess_appRegs *baseAddr,
531 pcieIbStartHiReg_t *reg,
532 int regNum);
533pcieRet_e pcie_write_ibStartHi_reg
534(
535 CSL_Pciess_appRegs *baseAddr,
536 pcieIbStartHiReg_t *reg,
537 int regNum);
538pcieRet_e pcie_read_ibOffset_reg
539(
540 CSL_Pciess_appRegs *baseAddr,
541 pcieIbOffsetReg_t *reg,
542 int regNum);
543pcieRet_e pcie_write_ibOffset_reg
544(
545 CSL_Pciess_appRegs *baseAddr,
546 pcieIbOffsetReg_t *reg,
547 int regNum);
548pcieRet_e pcie_read_pcsCfg0_reg
549(
550 CSL_Pciess_appRegs *baseAddr,
551 pciePcsCfg0Reg_t *reg
552);
553pcieRet_e pcie_write_pcsCfg0_reg
554(
555 CSL_Pciess_appRegs *baseAddr,
556 pciePcsCfg0Reg_t *reg
557);
558pcieRet_e pcie_read_pcsCfg1_reg
559(
560 CSL_Pciess_appRegs *baseAddr,
561 pciePcsCfg1Reg_t *reg
562);
563pcieRet_e pcie_write_pcsCfg1_reg
564(
565 CSL_Pciess_appRegs *baseAddr,
566 pciePcsCfg1Reg_t *reg
567);
568pcieRet_e pcie_read_pcsStatus_reg
569(
570 CSL_Pciess_appRegs *baseAddr,
571 pciePcsStatusReg_t *reg
572);
573
574pcieRet_e pcie_read_serdesCfg0_reg
575(
576 CSL_Pciess_appRegs *baseAddr,
577 pcieSerdesCfg0Reg_t *reg
578);
579pcieRet_e pcie_write_serdesCfg0_reg
580(
581 CSL_Pciess_appRegs *baseAddr,
582 pcieSerdesCfg0Reg_t *reg
583);
584pcieRet_e pcie_read_serdesCfg1_reg
585(
586 CSL_Pciess_appRegs *baseAddr,
587 pcieSerdesCfg1Reg_t *reg
588);
589pcieRet_e pcie_write_serdesCfg1_reg
590(
591 CSL_Pciess_appRegs *baseAddr,
592 pcieSerdesCfg1Reg_t *reg
593);
594
595
596/*****************************************************************************************
597*Configuration Registers
598*****************************************************************************************/
599
600/*Type 0, Type1 Common Registers*/
601pcieRet_e pcie_read_vndDevId_reg
602(
603 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
604 pcieVndDevIdReg_t *reg
605);
606pcieRet_e pcie_write_vndDevId_reg
607(
608 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
609 pcieVndDevIdReg_t *reg
610);
611pcieRet_e pcie_read_statusCmd_reg
612(
613 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
614 pcieStatusCmdReg_t *reg
615);
616pcieRet_e pcie_write_statusCmd_reg
617(
618 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
619 pcieStatusCmdReg_t *reg
620);
621pcieRet_e pcie_read_revId_reg
622(
623 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
624 pcieRevIdReg_t *reg
625);
626pcieRet_e pcie_write_revId_reg
627(
628 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
629 pcieRevIdReg_t *reg
630);
631
632/*Type 0 Registers*/
633pcieRet_e pcie_read_bist_reg
634(
635 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
636 pcieBistReg_t *reg
637);
638pcieRet_e pcie_write_bist_reg
639(
640 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
641 pcieBistReg_t *reg
642);
643pcieRet_e pcie_read_type0Bar_reg
644(
645 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
646 pcieBarReg_t *reg,
647 int barNum
648);
649pcieRet_e pcie_write_type0Bar_reg
650(
651 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
652 pcieBarReg_t *reg,
653 int barNum
654);
655pcieRet_e pcie_read_type0Bar32bit_reg
656(
657 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
658 pcieBar32bitReg_t *reg,
659 int barNum
660);
661pcieRet_e pcie_write_type0Bar32bit_reg
662(
663 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
664 pcieBar32bitReg_t *reg,
665 int barNum
666);
667pcieRet_e pcie_read_subId_reg
668(
669 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
670 pcieSubIdReg_t *reg
671);
672pcieRet_e pcie_write_subId_reg
673(
674 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
675 pcieSubIdReg_t *reg
676);
677pcieRet_e pcie_read_expRom_reg
678(
679 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
680 pcieExpRomReg_t *reg
681);
682pcieRet_e pcie_write_expRom_reg
683(
684 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
685 pcieExpRomReg_t *reg
686);
687pcieRet_e pcie_read_capPtr_reg
688(
689 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
690 pcieCapPtrReg_t *reg
691);
692pcieRet_e pcie_write_capPtr_reg
693(
694 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
695 pcieCapPtrReg_t *reg
696);
697pcieRet_e pcie_read_intPin_reg
698(
699 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
700 pcieIntPinReg_t *reg
701);
702pcieRet_e pcie_write_intPin_reg
703(
704 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
705 pcieIntPinReg_t *reg
706);
707
708/*Type 1 Registers*/
709pcieRet_e pcie_read_type1BistHeader_reg
710(
711 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
712 pcieType1BistHeaderReg_t *reg
713);
714pcieRet_e pcie_write_type1BistHeader_reg
715(
716 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
717 pcieType1BistHeaderReg_t *reg
718);
719pcieRet_e pcie_read_type1Bar_reg
720(
721 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
722 pcieBarReg_t *reg,
723 int barNum
724);
725pcieRet_e pcie_write_type1Bar_reg
726(
727 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
728 pcieBarReg_t *reg,
729 int barNum
730);
731pcieRet_e pcie_read_type1Bar32bit_reg
732(
733 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
734 pcieBar32bitReg_t *reg,
735 int barNum
736);
737pcieRet_e pcie_write_type1Bar32bit_reg
738(
739 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
740 pcieBar32bitReg_t *reg,
741 int barNum
742);
743pcieRet_e pcie_read_type1BusNum_reg
744(
745 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
746 pcieType1BusNumReg_t *reg
747);
748pcieRet_e pcie_write_type1BusNum_reg
749(
750 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
751 pcieType1BusNumReg_t *reg
752);
753pcieRet_e pcie_read_type1SecStat_reg
754(
755 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
756 pcieType1SecStatReg_t *reg
757);
758pcieRet_e pcie_write_type1SecStat_reg
759(
760 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
761 pcieType1SecStatReg_t *reg
762);
763pcieRet_e pcie_read_type1Memspace_reg
764(
765 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
766 pcieType1MemspaceReg_t *reg
767);
768pcieRet_e pcie_write_type1Memspace_reg
769(
770 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
771 pcieType1MemspaceReg_t *reg
772);
773pcieRet_e pcie_read_prefMem_reg
774(
775 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
776 pciePrefMemReg_t *reg
777);
778pcieRet_e pcie_write_prefMem_reg
779(
780 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
781 pciePrefMemReg_t *reg
782);
783pcieRet_e pcie_read_prefBaseUpper_reg
784(
785 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
786 pciePrefBaseUpperReg_t *reg
787);
788pcieRet_e pcie_write_prefBaseUpper_reg
789(
790 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
791 pciePrefBaseUpperReg_t *reg
792);
793pcieRet_e pcie_read_prefLimitUpper_reg
794(
795 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
796 pciePrefLimitUpperReg_t *reg
797);
798pcieRet_e pcie_write_prefLimitUpper_reg
799(
800 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
801 pciePrefLimitUpperReg_t *reg
802);
803pcieRet_e pcie_read_type1IOSpace_reg
804(
805 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
806 pcieType1IOSpaceReg_t *reg
807);
808pcieRet_e pcie_write_type1IOSpace_reg
809(
810 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
811 pcieType1IOSpaceReg_t *reg
812);
813pcieRet_e pcie_read_type1CapPtr_reg
814(
815 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
816 pcieType1CapPtrReg_t *reg
817);
818pcieRet_e pcie_write_type1CapPtr_reg
819(
820 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
821 pcieType1CapPtrReg_t *reg
822);
823pcieRet_e pcie_read_type1ExpnsnRom_reg
824(
825 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
826 pcieType1ExpnsnRomReg_t *reg
827);
828pcieRet_e pcie_write_type1ExpnsnRom_reg
829(
830 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
831 pcieType1ExpnsnRomReg_t *reg
832);
833pcieRet_e pcie_read_type1BridgeInt_reg
834(
835 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
836 pcieType1BridgeIntReg_t *reg
837);
838pcieRet_e pcie_write_type1BridgeInt_reg
839(
840 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
841 pcieType1BridgeIntReg_t *reg
842);
843
844/* power management capabilities*/
845pcieRet_e pcie_read_pmCap_reg
846(
847 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
848 pciePMCapReg_t *reg
849);
850pcieRet_e pcie_write_pmCap_reg
851(
852 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
853 pciePMCapReg_t *reg
854);
855pcieRet_e pcie_read_pmCapCtlStat_reg
856(
857 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
858 pciePMCapCtlStatReg_t *reg
859);
860pcieRet_e pcie_write_pmCapCtlStat_reg
861(
862 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
863 pciePMCapCtlStatReg_t *reg
864);
865/* MSI capabilities*/
866pcieRet_e pcie_read_msiCap_reg
867(
868 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
869 pcieMsiCapReg_t *reg
870);
871pcieRet_e pcie_write_msiCap_reg
872(
873 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
874 pcieMsiCapReg_t *reg
875);
876pcieRet_e pcie_read_msiLo32_reg
877(
878 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
879 pcieMsiLo32Reg_t *reg
880);
881pcieRet_e pcie_write_msiLo32_reg
882(
883 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
884 pcieMsiLo32Reg_t *reg
885);
886pcieRet_e pcie_read_msiUp32_reg
887(
888 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
889 pcieMsiUp32Reg_t *reg
890);
891pcieRet_e pcie_write_msiUp32_reg
892(
893 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
894 pcieMsiUp32Reg_t *reg
895);
896pcieRet_e pcie_read_msiData_reg
897(
898 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
899 pcieMsiDataReg_t *reg
900);
901pcieRet_e pcie_write_msiData_reg
902(
903 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
904 pcieMsiDataReg_t *reg
905);
906
907/*Capabilities Registers*/
908pcieRet_e pcie_read_pciesCap_reg
909(
910 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
911 pciePciesCapReg_t *reg
912);
913pcieRet_e pcie_write_pciesCap_reg
914(
915 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
916 pciePciesCapReg_t *reg
917);
918pcieRet_e pcie_read_deviceCap_reg
919(
920 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
921 pcieDeviceCapReg_t *reg
922);
923pcieRet_e pcie_write_deviceCap_reg
924(
925 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
926 pcieDeviceCapReg_t *reg
927);
928pcieRet_e pcie_read_devStatCtrl_reg
929(
930 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
931 pcieDevStatCtrlReg_t *reg
932);
933pcieRet_e pcie_write_devStatCtrl_reg
934(
935 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
936 pcieDevStatCtrlReg_t *reg
937);
938pcieRet_e pcie_read_linkCap_reg
939(
940 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
941 pcieLinkCapReg_t *reg
942);
943
944pcieRet_e pcie_write_linkCap_reg
945(
946 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
947 pcieLinkCapReg_t *reg
948);
949pcieRet_e pcie_read_linkStatCtrl_reg
950(
951 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
952 pcieLinkStatCtrlReg_t *reg
953);
954pcieRet_e pcie_write_linkStatCtrl_reg
955(
956 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
957 pcieLinkStatCtrlReg_t *reg
958);
959pcieRet_e pcie_read_slotCap_reg
960(
961 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
962 pcieSlotCapReg_t *reg
963);
964pcieRet_e pcie_write_slotCap_reg
965(
966 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
967 pcieSlotCapReg_t *reg
968);
969pcieRet_e pcie_read_slotStatCtrl_reg
970(
971 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
972 pcieSlotStatCtrlReg_t *reg
973);
974pcieRet_e pcie_write_slotStatCtrl_reg
975(
976 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
977 pcieSlotStatCtrlReg_t *reg
978);
979pcieRet_e pcie_read_rootCtrlCap_reg
980(
981 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
982 pcieRootCtrlCapReg_t *reg
983);
984pcieRet_e pcie_write_rootCtrlCap_reg
985(
986 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
987 pcieRootCtrlCapReg_t *reg
988);
989pcieRet_e pcie_read_rootStatus_reg
990(
991 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
992 pcieRootStatusReg_t *reg
993);
994pcieRet_e pcie_write_rootStatus_reg
995(
996 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
997 pcieRootStatusReg_t *reg
998);
999pcieRet_e pcie_read_devCap2_reg
1000(
1001 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1002 pcieDevCap2Reg_t *reg
1003);
1004pcieRet_e pcie_write_devCap2_reg
1005(
1006 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1007 pcieDevCap2Reg_t *reg
1008);
1009pcieRet_e pcie_read_devStatCtrl2_reg
1010(
1011 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1012 pcieDevStatCtrl2Reg_t *reg
1013);
1014pcieRet_e pcie_write_devStatCtrl2_reg
1015(
1016 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1017 pcieDevStatCtrl2Reg_t *reg
1018);
1019pcieRet_e pcie_read_linkCtrl2_reg
1020(
1021 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1022 pcieLinkCtrl2Reg_t *reg
1023);
1024pcieRet_e pcie_write_linkCtrl2_reg
1025(
1026 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1027 pcieLinkCtrl2Reg_t *reg
1028);
1029
1030/*Capabilities Extended Registers*/
1031pcieRet_e pcie_read_extCap_reg
1032(
1033 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1034 pcieExtCapReg_t *reg
1035);
1036pcieRet_e pcie_read_uncErr_reg
1037(
1038 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1039 pcieUncErrReg_t *reg
1040);
1041pcieRet_e pcie_write_uncErr_reg
1042(
1043 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1044 pcieUncErrReg_t *reg
1045);
1046pcieRet_e pcie_read_uncErrMask_reg
1047(
1048 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1049 pcieUncErrMaskReg_t *reg
1050);
1051pcieRet_e pcie_write_uncErrMask_reg
1052(
1053 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1054 pcieUncErrMaskReg_t *reg
1055);
1056pcieRet_e pcie_read_uncErrSvrty_reg
1057(
1058 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1059 pcieUncErrSvrtyReg_t *reg
1060);
1061pcieRet_e pcie_write_uncErrSvrty_reg
1062(
1063 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1064 pcieUncErrSvrtyReg_t *reg
1065);
1066pcieRet_e pcie_read_corErr_reg
1067(
1068 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1069 pcieCorErrReg_t *reg
1070);
1071pcieRet_e pcie_write_corErr_reg
1072(
1073 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1074 pcieCorErrReg_t *reg
1075);
1076pcieRet_e pcie_read_corErrMask_reg
1077(
1078 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1079 pcieCorErrMaskReg_t *reg
1080);
1081pcieRet_e pcie_write_corErrMask_reg
1082(
1083 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1084 pcieCorErrMaskReg_t *reg
1085);
1086pcieRet_e pcie_read_accr_reg
1087(
1088 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1089 pcieAccrReg_t *reg
1090);
1091pcieRet_e pcie_write_accr_reg
1092(
1093 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1094 pcieAccrReg_t *reg
1095);
1096pcieRet_e pcie_read_hdrLog_reg
1097(
1098 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1099 pcieHdrLogReg_t *reg,
1100 int regNum
1101);
1102pcieRet_e pcie_read_rootErrCmd_reg
1103(
1104 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1105 pcieRootErrCmdReg_t *reg
1106);
1107pcieRet_e pcie_write_rootErrCmd_reg
1108(
1109 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1110 pcieRootErrCmdReg_t *reg
1111);
1112pcieRet_e pcie_read_rootErrSt_reg
1113(
1114 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1115 pcieRootErrStReg_t *reg
1116);
1117pcieRet_e pcie_write_rootErrSt_reg
1118(
1119 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1120 pcieRootErrStReg_t *reg
1121);
1122pcieRet_e pcie_read_errSrcID_reg
1123(
1124 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1125 pcieErrSrcIDReg_t *reg
1126);
1127
1128/*Port Logic Registers*/
1129pcieRet_e pcie_read_plAckTimer_reg
1130(
1131 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1132 pciePlAckTimerReg_t *reg
1133);
1134pcieRet_e pcie_write_plAckTimer_reg
1135(
1136 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1137 pciePlAckTimerReg_t *reg
1138);
1139pcieRet_e pcie_read_plOMsg_reg
1140(
1141 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1142 pciePlOMsgReg_t *reg
1143);
1144pcieRet_e pcie_write_plOMsg_reg
1145(
1146 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1147 pciePlOMsgReg_t *reg
1148);
1149pcieRet_e pcie_read_plForceLink_reg
1150(
1151 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1152 pciePlForceLinkReg_t *reg
1153);
1154pcieRet_e pcie_write_plForceLink_reg
1155(
1156 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1157 pciePlForceLinkReg_t *reg
1158);
1159pcieRet_e pcie_read_ackFreq_reg
1160(
1161 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1162 pcieAckFreqReg_t *reg
1163);
1164pcieRet_e pcie_write_ackFreq_reg
1165(
1166 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1167 pcieAckFreqReg_t *reg
1168);
1169pcieRet_e pcie_read_lnkCtrl_reg
1170(
1171 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1172 pcieLnkCtrlReg_t *reg
1173);
1174pcieRet_e pcie_write_lnkCtrl_reg
1175(
1176 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1177 pcieLnkCtrlReg_t *reg
1178);
1179pcieRet_e pcie_read_laneSkew_reg
1180(
1181 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1182 pcieLaneSkewReg_t *reg
1183);
1184pcieRet_e pcie_write_laneSkew_reg
1185(
1186 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1187 pcieLaneSkewReg_t *reg
1188);
1189pcieRet_e pcie_read_symNum_reg
1190(
1191 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1192 pcieSymNumReg_t *reg
1193);
1194pcieRet_e pcie_write_symNum_reg
1195(
1196 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1197 pcieSymNumReg_t *reg
1198);
1199pcieRet_e pcie_read_symTimerFltMask_reg
1200(
1201 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1202 pcieSymTimerFltMaskReg_t *reg
1203);
1204pcieRet_e pcie_write_symTimerFltMask_reg
1205(
1206 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1207 pcieSymTimerFltMaskReg_t *reg
1208);
1209pcieRet_e pcie_read_fltMask2_reg
1210(
1211 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1212 pcieFltMask2Reg_t *reg
1213);
1214pcieRet_e pcie_write_fltMask2_reg
1215(
1216 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1217 pcieFltMask2Reg_t *reg
1218);
1219pcieRet_e pcie_read_debug0_reg
1220(
1221 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1222 pcieDebug0Reg_t *reg
1223);
1224pcieRet_e pcie_read_debug1_reg
1225(
1226 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1227 pcieDebug1Reg_t *reg
1228);
1229pcieRet_e pcie_read_gen2_reg
1230(
1231 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1232 pcieGen2Reg_t *reg
1233);
1234pcieRet_e pcie_write_gen2_reg
1235(
1236 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1237 pcieGen2Reg_t *reg
1238);
1239 139
1240/***************************************************************************** 140/*****************************************************************************
1241 * Local Object - per core device configuration 141 * Local Object - per core device configuration
@@ -1243,14 +143,16 @@ pcieRet_e pcie_write_gen2_reg
1243 * This will store any device addresses as accessible from this core. Thus, 143 * This will store any device addresses as accessible from this core. Thus,
1244 * if virt2phys is required, store virtual addresses 144 * if virt2phys is required, store virtual addresses
1245 *****************************************************************************/ 145 *****************************************************************************/
1246typedef struct 146typedef struct
1247{ 147{
1248 Pcie_InitCfg cfg; 148 /*! one instance for each peripheral on device, which is used as handle */
149 struct Pcie_IntHandle_s insts[pcie_MAX_PERIPHS];
1249} Pcie_LocalObj; 150} Pcie_LocalObj;
1250 151
1251extern Pcie_LocalObj pcieLObj; 152extern Pcie_LocalObj pcieLObj;
1252extern uint8_t pcieLObjIsValid; 153extern uint8_t pcieLObjIsValid;
1253 154
155
1254#ifdef __cplusplus 156#ifdef __cplusplus
1255} 157}
1256#endif 158#endif
diff --git a/src/v0/pcie.h b/src/v0/pcie.h
new file mode 100644
index 0000000..b0c9d6f
--- /dev/null
+++ b/src/v0/pcie.h
@@ -0,0 +1,129 @@
1/*
2 *
3 * Copyright (C) 2010-2015 Texas Instruments Incorporated - http://www.ti.com/
4 *
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 *
13 * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the
16 * distribution.
17 *
18 * Neither the name of Texas Instruments Incorporated nor the names of
19 * its contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34*/
35
36#ifndef _PCIEV0_H
37#define _PCIEV0_H
38
39#ifdef __cplusplus
40extern "C" {
41#endif
42
43/* System level header files */
44#include <stdint.h>
45#include <stdlib.h>
46
47/* ============================================================== */
48/**
49 * @file ti/drv/pcie/src/v0/pcie.h
50 *
51 * @brief PCIe hw rev 0 sub-system API and Data Definitions
52 *
53 */
54
55/** v0 version of @ref Pcie_open */
56pcieRet_e Pciev0_open
57(
58 int deviceNum, /**< [in] PCIe device number (0,1,...) */
59 Pcie_Handle *pHandle /**< [out] Resulting instance handle */
60);
61
62/** v0 version of @ref Pcie_close */
63pcieRet_e Pciev0_close
64(
65 Pcie_Handle *pHandle /**< [in] The PCIE LLD instance indentifier */
66);
67
68/** v0 version of @ref Pcie_readRegs */
69pcieRet_e Pciev0_readRegs
70(
71 Pcie_Handle handle, /**< [in] The PCIE LLD instance identifier */
72 pcieLocation_e location, /**< [in] Local or remote peripheral */
73 pcieRegisters_t *readRegs /**< [in/out] List of registers to read */
74);
75
76/** v0 version of @ref Pcie_writeRegs */
77pcieRet_e Pciev0_writeRegs
78(
79 Pcie_Handle handle, /**< [in] The PCIE LLD instance identifier */
80 pcieLocation_e location, /**< [in] Local or remote peripheral */
81 pcieRegisters_t *writeRegs /**< [in] List of registers to write */
82);
83
84/** v0 version of @ref Pcie_setInterfaceMode */
85pcieRet_e Pciev0_setInterfaceMode
86(
87 Pcie_Handle handle, /**< [in] specified interface */
88 pcieMode_e mode /**< [in] PCIE Mode */
89);
90
91/** v0 version of @ref Pcie_getMemSpaceRange */
92pcieRet_e Pciev0_getMemSpaceRange
93(
94 Pcie_Handle handle, /**< [in] The PCIE LLD instance identifier */
95 void **base, /**< [out] The memory space base address */
96 uint32_t *size /**< [out] Total size of the memory space [bytes] */
97);
98
99/** v0 version of @ref Pcie_cfgObOffset */
100pcieRet_e Pciev0_cfgObOffset
101(
102 Pcie_Handle handle, /**< [in] The PCIE LLD instance identifier */
103 uint32_t obAddrLo, /**< [in] Low Outbound address offset (32bits) */
104 uint32_t obAddrHi, /**< [in] High Outbound address offset (32bits) */
105 uint8_t region /**< [in] Identifies the Outbound region (0-7) */
106);
107
108/** v0 version of @ref Pcie_cfgIbTrans */
109pcieRet_e Pciev0_cfgIbTrans
110(
111 Pcie_Handle handle, /**< [in] The PCIE LLD instance identifier */
112 pcieIbTransCfg_t *ibCfg /**< [in] Inbound Address Translation Configuration parameters */
113);
114
115/** v0 version of @ref Pcie_cfgBar */
116pcieRet_e Pciev0_cfgBar
117(
118 Pcie_Handle handle, /**< [in] The PCIE LLD instance identifier */
119 pcieBarCfg_t *barCfg /**< [in] BAR configuration parameters */
120);
121
122#ifdef __cplusplus
123}
124#endif
125
126#endif /* _PCIEV0_H */
127
128/* Nothing past this point */
129
diff --git a/src/v0/pcieloc.h b/src/v0/pcieloc.h
new file mode 100644
index 0000000..4561388
--- /dev/null
+++ b/src/v0/pcieloc.h
@@ -0,0 +1,1181 @@
1/*
2 *
3 * Copyright (C) 2010-2015 Texas Instruments Incorporated - http://www.ti.com/
4 *
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 *
13 * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the
16 * distribution.
17 *
18 * Neither the name of Texas Instruments Incorporated nor the names of
19 * its contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34*/
35
36/* ================================================================= */
37/* file pcieloc.h
38 *
39 * Internal module data structures and definitions
40 *
41 */
42#ifndef _PCIEV0LOC_H
43#define _PCIEV0LOC_H
44
45#ifdef __cplusplus
46extern "C" {
47#endif
48
49
50/* System level header files */
51#include "pcie.h"
52#include <ti/csl/cslr_pcie_cfg_space_endpoint.h>
53#include <ti/csl/cslr_pcie_cfg_space_rootcomplex.h>
54#include <ti/csl/cslr_pciess_app.h>
55
56/* Common utility macros */
57
58
59/* Get base address for Local Configuration Space */
60#define pcie_get_loc_cfg_base(handle, ep_loc_base, rc_loc_base) \
61 { \
62 ep_loc_base = (CSL_Pcie_cfg_space_endpointRegs *) ((unsigned int)handle + 0x1000); \
63 rc_loc_base = (CSL_Pcie_cfg_space_rootcomplexRegs *) ((unsigned int)handle + 0x1000); \
64 }
65
66/* Get base address for Remote Configuration Space */
67#define pcie_get_rem_cfg_base(handle, ep_rem_base, rc_rem_base) \
68 { \
69 ep_rem_base = (CSL_Pcie_cfg_space_endpointRegs *) ((unsigned int)handle + 0x2000); \
70 rc_rem_base = (CSL_Pcie_cfg_space_rootcomplexRegs *) ((unsigned int)handle + 0x2000); \
71 }
72
73
74
75/******************************************************************************
76 * Prototypes
77 ******************************************************************************/
78
79/*****************************************************************************************
80*Application Registers
81*****************************************************************************************/
82
83pcieRet_e pciev0_read_pid_reg(
84 CSL_Pciess_appRegs *baseAddr,
85 pciePidReg_t *reg);
86pcieRet_e pciev0_read_cmdStatus_reg
87(
88 CSL_Pciess_appRegs *baseAddr,
89 pcieCmdStatusReg_t *reg);
90pcieRet_e pciev0_write_cmdStatus_reg
91(
92 CSL_Pciess_appRegs *baseAddr,
93 pcieCmdStatusReg_t *reg);
94pcieRet_e pciev0_read_cfgTrans_reg
95(
96 CSL_Pciess_appRegs *baseAddr,
97 pcieCfgTransReg_t *reg);
98pcieRet_e pciev0_write_cfgTrans_reg
99(
100 CSL_Pciess_appRegs *baseAddr,
101 pcieCfgTransReg_t *reg);
102pcieRet_e pciev0_read_ioBase_reg
103(
104 CSL_Pciess_appRegs *baseAddr,
105 pcieIoBaseReg_t *reg);
106pcieRet_e pciev0_write_ioBase_reg
107(
108 CSL_Pciess_appRegs *baseAddr,
109 pcieIoBaseReg_t *reg);
110pcieRet_e pciev0_read_tlpCfg_reg
111(
112 CSL_Pciess_appRegs *baseAddr,
113 pcieTlpCfgReg_t *reg);
114pcieRet_e pciev0_write_tlpCfg_reg
115(
116 CSL_Pciess_appRegs *baseAddr,
117 pcieTlpCfgReg_t *reg);
118pcieRet_e pciev0_read_rstCmd_reg
119(
120 CSL_Pciess_appRegs *baseAddr,
121 pcieRstCmdReg_t *reg);
122pcieRet_e pciev0_write_rstCmd_reg
123(
124 CSL_Pciess_appRegs *baseAddr,
125 pcieRstCmdReg_t *reg);
126pcieRet_e pciev0_read_pmCmd_reg
127(
128 CSL_Pciess_appRegs *baseAddr,
129 pciePmCmdReg_t *reg);
130pcieRet_e pciev0_write_pmCmd_reg
131(
132 CSL_Pciess_appRegs *baseAddr,
133 pciePmCmdReg_t *reg);
134pcieRet_e pciev0_read_pmCfg_reg
135(
136 CSL_Pciess_appRegs *baseAddr,
137 pciePmCfgReg_t *reg);
138pcieRet_e pciev0_write_pmCfg_reg
139(
140 CSL_Pciess_appRegs *baseAddr,
141 pciePmCfgReg_t *reg);
142pcieRet_e pciev0_read_actStatus_reg
143(
144 CSL_Pciess_appRegs *baseAddr,
145 pcieActStatusReg_t *reg);
146pcieRet_e pciev0_read_obSize_reg
147(
148 CSL_Pciess_appRegs *baseAddr,
149 pcieObSizeReg_t *reg);
150pcieRet_e pciev0_write_obSize_reg
151(
152 CSL_Pciess_appRegs *baseAddr,
153 pcieObSizeReg_t *reg);
154pcieRet_e pciev0_read_diagCtrl_reg
155(
156 CSL_Pciess_appRegs *baseAddr,
157 pcieDiagCtrlReg_t *reg
158);
159pcieRet_e pciev0_write_diagCtrl_reg
160(
161 CSL_Pciess_appRegs *baseAddr,
162 pcieDiagCtrlReg_t *reg
163);
164pcieRet_e pciev0_read_endian_reg
165(
166 CSL_Pciess_appRegs *baseAddr,
167 pcieEndianReg_t *reg
168);
169pcieRet_e pciev0_write_endian_reg
170(
171 CSL_Pciess_appRegs *baseAddr,
172 pcieEndianReg_t *reg
173);
174pcieRet_e pciev0_read_priority_reg
175(
176 CSL_Pciess_appRegs *baseAddr,
177 pciePriorityReg_t *reg
178);
179pcieRet_e pciev0_write_priority_reg
180(
181 CSL_Pciess_appRegs *baseAddr,
182 pciePriorityReg_t *reg
183);
184pcieRet_e pciev0_read_irqEOI_reg
185(
186 CSL_Pciess_appRegs *baseAddr,
187 pcieIrqEOIReg_t *reg
188);
189pcieRet_e pciev0_write_irqEOI_reg
190(
191 CSL_Pciess_appRegs *baseAddr,
192 pcieIrqEOIReg_t *reg
193);
194pcieRet_e pciev0_read_msiIrq_reg
195(
196 CSL_Pciess_appRegs *baseAddr,
197 pcieMsiIrqReg_t *reg
198);
199pcieRet_e pciev0_write_msiIrq_reg
200(
201 CSL_Pciess_appRegs *baseAddr,
202 pcieMsiIrqReg_t *reg
203);
204pcieRet_e pciev0_read_epIrqSet_reg
205(
206 CSL_Pciess_appRegs *baseAddr,
207 pcieEpIrqSetReg_t *reg
208);
209pcieRet_e pciev0_write_epIrqSet_reg
210(
211 CSL_Pciess_appRegs *baseAddr,
212 pcieEpIrqSetReg_t *reg
213);
214pcieRet_e pciev0_read_epIrqClr_reg
215(
216 CSL_Pciess_appRegs *baseAddr,
217 pcieEpIrqClrReg_t *reg
218);
219pcieRet_e pciev0_write_epIrqClr_reg
220(
221 CSL_Pciess_appRegs *baseAddr,
222 pcieEpIrqClrReg_t *reg
223);
224pcieRet_e pciev0_read_epIrqStatus_reg
225(
226 CSL_Pciess_appRegs *baseAddr,
227 pcieEpIrqStatusReg_t *reg
228);
229pcieRet_e pciev0_write_epIrqStatus_reg
230(
231 CSL_Pciess_appRegs *baseAddr,
232 pcieEpIrqStatusReg_t *reg
233);
234pcieRet_e pciev0_read_genPurpose_reg
235(
236 CSL_Pciess_appRegs *baseAddr,
237 pcieGenPurposeReg_t *reg,
238 int regNum
239);
240pcieRet_e pciev0_write_genPurpose_reg
241(
242 CSL_Pciess_appRegs *baseAddr,
243 pcieGenPurposeReg_t *reg,
244 int regNum
245);
246pcieRet_e pciev0_read_msiIrqStatusRaw_reg
247(
248 CSL_Pciess_appRegs *baseAddr,
249 pcieMsiIrqStatusRawReg_t *reg,
250 int regNum
251);
252pcieRet_e pciev0_write_msiIrqStatusRaw_reg
253(
254 CSL_Pciess_appRegs *baseAddr,
255 pcieMsiIrqStatusRawReg_t *reg,
256 int regNum
257);
258pcieRet_e pciev0_read_msiIrqStatus_reg
259(
260 CSL_Pciess_appRegs *baseAddr,
261 pcieMsiIrqStatusReg_t *reg,
262 int regNum
263);
264pcieRet_e pciev0_write_msiIrqStatus_reg
265(
266 CSL_Pciess_appRegs *baseAddr,
267 pcieMsiIrqStatusReg_t *reg,
268 int regNum
269);
270pcieRet_e pciev0_read_msiIrqEnableSet_reg
271(
272 CSL_Pciess_appRegs *baseAddr,
273 pcieMsiIrqEnableSetReg_t *reg,
274 int regNum
275);
276pcieRet_e pciev0_write_msiIrqEnableSet_reg
277(
278 CSL_Pciess_appRegs *baseAddr,
279 pcieMsiIrqEnableSetReg_t *reg,
280 int regNum
281);
282pcieRet_e pciev0_read_msiIrqEnableClr_reg
283(
284 CSL_Pciess_appRegs *baseAddr,
285 pcieMsiIrqEnableClrReg_t *reg,
286 int regNum
287);
288pcieRet_e pciev0_write_msiIrqEnableClr_reg
289(
290 CSL_Pciess_appRegs *baseAddr,
291 pcieMsiIrqEnableClrReg_t *reg,
292 int regNum
293);
294pcieRet_e pciev0_read_legacyIrqStatusRaw_reg
295(
296 CSL_Pciess_appRegs *baseAddr,
297 pcieLegacyIrqStatusRawReg_t *reg,
298 int regNum
299);
300pcieRet_e pciev0_write_legacyIrqStatusRaw_reg
301(
302 CSL_Pciess_appRegs *baseAddr,
303 pcieLegacyIrqStatusRawReg_t *reg,
304 int regNum
305);
306pcieRet_e pciev0_read_legacyIrqStatus_reg
307(
308 CSL_Pciess_appRegs *baseAddr,
309 pcieLegacyIrqStatusReg_t *reg,
310 int regNum
311);
312pcieRet_e pciev0_write_legacyIrqStatus_reg
313(
314 CSL_Pciess_appRegs *baseAddr,
315 pcieLegacyIrqStatusReg_t *reg,
316 int regNum
317);
318pcieRet_e pciev0_read_legacyIrqEnableSet_reg
319(
320 CSL_Pciess_appRegs *baseAddr,
321 pcieLegacyIrqEnableSetReg_t *reg,
322 int regNum
323);
324pcieRet_e pciev0_write_legacyIrqEnableSet_reg
325(
326 CSL_Pciess_appRegs *baseAddr,
327 pcieLegacyIrqEnableSetReg_t *reg,
328 int regNum
329);
330pcieRet_e pciev0_read_legacyIrqEnableClr_reg
331(
332 CSL_Pciess_appRegs *baseAddr,
333 pcieLegacyIrqEnableClrReg_t *reg,
334 int regNum
335);
336pcieRet_e pciev0_write_legacyIrqEnableClr_reg
337(
338 CSL_Pciess_appRegs *baseAddr,
339 pcieLegacyIrqEnableClrReg_t *reg,
340 int regNum
341);
342pcieRet_e pciev0_read_errIrqStatusRaw_reg
343(
344 CSL_Pciess_appRegs *baseAddr,
345 pcieErrIrqStatusRawReg_t *reg
346);
347pcieRet_e pciev0_write_errIrqStatusRaw_reg
348(
349 CSL_Pciess_appRegs *baseAddr,
350 pcieErrIrqStatusRawReg_t *reg
351);
352pcieRet_e pciev0_read_errIrqStatus_reg
353(
354 CSL_Pciess_appRegs *baseAddr,
355 pcieErrIrqStatusReg_t *reg
356);
357pcieRet_e pciev0_write_errIrqStatus_reg
358(
359 CSL_Pciess_appRegs *baseAddr,
360 pcieErrIrqStatusReg_t *reg
361);
362pcieRet_e pciev0_read_errIrqEnableSet_reg
363(
364 CSL_Pciess_appRegs *baseAddr,
365 pcieErrIrqEnableSetReg_t *reg
366);
367pcieRet_e pciev0_write_errIrqEnableSet_reg
368(
369 CSL_Pciess_appRegs *baseAddr,
370 pcieErrIrqEnableSetReg_t *reg
371);
372pcieRet_e pciev0_read_errIrqEnableClr_reg
373(
374 CSL_Pciess_appRegs *baseAddr,
375 pcieErrIrqEnableClrReg_t *reg
376);
377pcieRet_e pciev0_write_errIrqEnableClr_reg
378(
379 CSL_Pciess_appRegs *baseAddr,
380 pcieErrIrqEnableClrReg_t *reg
381);
382pcieRet_e pciev0_read_pmRstIrqStatusRaw_reg
383(
384 CSL_Pciess_appRegs *baseAddr,
385 pciePmRstIrqStatusRawReg_t *reg
386);
387pcieRet_e pciev0_write_pmRstIrqStatusRaw_reg
388(
389 CSL_Pciess_appRegs *baseAddr,
390 pciePmRstIrqStatusRawReg_t *reg
391);
392pcieRet_e pciev0_read_pmRstIrqStatus_reg
393(
394 CSL_Pciess_appRegs *baseAddr,
395 pciePmRstIrqStatusReg_t *reg
396);
397pcieRet_e pciev0_write_pmRstIrqStatus_reg
398(
399 CSL_Pciess_appRegs *baseAddr,
400 pciePmRstIrqStatusReg_t *reg
401);
402pcieRet_e pciev0_read_pmRstIrqEnableSet_reg
403(
404 CSL_Pciess_appRegs *baseAddr,
405 pciePmRstIrqEnableSetReg_t *reg
406);
407pcieRet_e pciev0_write_pmRstIrqEnableSet_reg
408(
409 CSL_Pciess_appRegs *baseAddr,
410 pciePmRstIrqEnableSetReg_t *reg
411);
412pcieRet_e pciev0_read_pmRstIrqEnableClr_reg
413(
414 CSL_Pciess_appRegs *baseAddr,
415 pciePmRstIrqEnableClrReg_t *reg
416);
417pcieRet_e pciev0_write_pmRstIrqEnableClr_reg
418(
419 CSL_Pciess_appRegs *baseAddr,
420 pciePmRstIrqEnableClrReg_t *reg
421);
422pcieRet_e pciev0_read_obOffsetLo_reg
423(
424 CSL_Pciess_appRegs *baseAddr,
425 pcieObOffsetLoReg_t *reg,
426 int regNum);
427pcieRet_e pciev0_write_obOffsetLo_reg
428(
429 CSL_Pciess_appRegs *baseAddr,
430 pcieObOffsetLoReg_t *reg,
431 int regNum);
432pcieRet_e pciev0_read_obOffsetHi_reg
433(
434 CSL_Pciess_appRegs *baseAddr,
435 pcieObOffsetHiReg_t *reg,
436 int regNum);
437pcieRet_e pciev0_write_obOffsetHi_reg
438(
439 CSL_Pciess_appRegs *baseAddr,
440 pcieObOffsetHiReg_t *reg,
441 int regNum);
442pcieRet_e pciev0_read_ibBar_reg
443(
444 CSL_Pciess_appRegs *baseAddr,
445 pcieIbBarReg_t *reg,
446 int regNum);
447pcieRet_e pciev0_write_ibBar_reg
448(
449 CSL_Pciess_appRegs *baseAddr,
450 pcieIbBarReg_t *reg,
451 int regNum);
452pcieRet_e pciev0_read_ibStartLo_reg
453(
454 CSL_Pciess_appRegs *baseAddr,
455 pcieIbStartLoReg_t *reg,
456 int regNum);
457pcieRet_e pciev0_write_ibStartLo_reg
458(
459 CSL_Pciess_appRegs *baseAddr,
460 pcieIbStartLoReg_t *reg,
461 int regNum);
462pcieRet_e pciev0_read_ibStartHi_reg
463(
464 CSL_Pciess_appRegs *baseAddr,
465 pcieIbStartHiReg_t *reg,
466 int regNum);
467pcieRet_e pciev0_write_ibStartHi_reg
468(
469 CSL_Pciess_appRegs *baseAddr,
470 pcieIbStartHiReg_t *reg,
471 int regNum);
472pcieRet_e pciev0_read_ibOffset_reg
473(
474 CSL_Pciess_appRegs *baseAddr,
475 pcieIbOffsetReg_t *reg,
476 int regNum);
477pcieRet_e pciev0_write_ibOffset_reg
478(
479 CSL_Pciess_appRegs *baseAddr,
480 pcieIbOffsetReg_t *reg,
481 int regNum);
482pcieRet_e pciev0_read_pcsCfg0_reg
483(
484 CSL_Pciess_appRegs *baseAddr,
485 pciePcsCfg0Reg_t *reg
486);
487pcieRet_e pciev0_write_pcsCfg0_reg
488(
489 CSL_Pciess_appRegs *baseAddr,
490 pciePcsCfg0Reg_t *reg
491);
492pcieRet_e pciev0_read_pcsCfg1_reg
493(
494 CSL_Pciess_appRegs *baseAddr,
495 pciePcsCfg1Reg_t *reg
496);
497pcieRet_e pciev0_write_pcsCfg1_reg
498(
499 CSL_Pciess_appRegs *baseAddr,
500 pciePcsCfg1Reg_t *reg
501);
502pcieRet_e pciev0_read_pcsStatus_reg
503(
504 CSL_Pciess_appRegs *baseAddr,
505 pciePcsStatusReg_t *reg
506);
507
508pcieRet_e pciev0_read_serdesCfg0_reg
509(
510 CSL_Pciess_appRegs *baseAddr,
511 pcieSerdesCfg0Reg_t *reg
512);
513pcieRet_e pciev0_write_serdesCfg0_reg
514(
515 CSL_Pciess_appRegs *baseAddr,
516 pcieSerdesCfg0Reg_t *reg
517);
518pcieRet_e pciev0_read_serdesCfg1_reg
519(
520 CSL_Pciess_appRegs *baseAddr,
521 pcieSerdesCfg1Reg_t *reg
522);
523pcieRet_e pciev0_write_serdesCfg1_reg
524(
525 CSL_Pciess_appRegs *baseAddr,
526 pcieSerdesCfg1Reg_t *reg
527);
528
529
530/*****************************************************************************************
531*Configuration Registers
532*****************************************************************************************/
533
534/*Type 0, Type1 Common Registers*/
535pcieRet_e pciev0_read_vndDevId_reg
536(
537 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
538 pcieVndDevIdReg_t *reg
539);
540pcieRet_e pciev0_write_vndDevId_reg
541(
542 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
543 pcieVndDevIdReg_t *reg
544);
545pcieRet_e pciev0_read_statusCmd_reg
546(
547 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
548 pcieStatusCmdReg_t *reg
549);
550pcieRet_e pciev0_write_statusCmd_reg
551(
552 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
553 pcieStatusCmdReg_t *reg
554);
555pcieRet_e pciev0_read_revId_reg
556(
557 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
558 pcieRevIdReg_t *reg
559);
560pcieRet_e pciev0_write_revId_reg
561(
562 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
563 pcieRevIdReg_t *reg
564);
565
566/*Type 0 Registers*/
567pcieRet_e pciev0_read_bist_reg
568(
569 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
570 pcieBistReg_t *reg
571);
572pcieRet_e pciev0_write_bist_reg
573(
574 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
575 pcieBistReg_t *reg
576);
577pcieRet_e pciev0_read_type0Bar_reg
578(
579 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
580 pcieBarReg_t *reg,
581 int barNum
582);
583pcieRet_e pciev0_write_type0Bar_reg
584(
585 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
586 pcieBarReg_t *reg,
587 int barNum
588);
589pcieRet_e pciev0_read_type0Bar32bit_reg
590(
591 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
592 pcieBar32bitReg_t *reg,
593 int barNum
594);
595pcieRet_e pciev0_write_type0Bar32bit_reg
596(
597 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
598 pcieBar32bitReg_t *reg,
599 int barNum
600);
601pcieRet_e pciev0_read_subId_reg
602(
603 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
604 pcieSubIdReg_t *reg
605);
606pcieRet_e pciev0_write_subId_reg
607(
608 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
609 pcieSubIdReg_t *reg
610);
611pcieRet_e pciev0_read_expRom_reg
612(
613 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
614 pcieExpRomReg_t *reg
615);
616pcieRet_e pciev0_write_expRom_reg
617(
618 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
619 pcieExpRomReg_t *reg
620);
621pcieRet_e pciev0_read_capPtr_reg
622(
623 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
624 pcieCapPtrReg_t *reg
625);
626pcieRet_e pciev0_write_capPtr_reg
627(
628 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
629 pcieCapPtrReg_t *reg
630);
631pcieRet_e pciev0_read_intPin_reg
632(
633 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
634 pcieIntPinReg_t *reg
635);
636pcieRet_e pciev0_write_intPin_reg
637(
638 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
639 pcieIntPinReg_t *reg
640);
641
642/*Type 1 Registers*/
643pcieRet_e pciev0_read_type1BistHeader_reg
644(
645 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
646 pcieType1BistHeaderReg_t *reg
647);
648pcieRet_e pciev0_write_type1BistHeader_reg
649(
650 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
651 pcieType1BistHeaderReg_t *reg
652);
653pcieRet_e pciev0_read_type1Bar_reg
654(
655 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
656 pcieBarReg_t *reg,
657 int barNum
658);
659pcieRet_e pciev0_write_type1Bar_reg
660(
661 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
662 pcieBarReg_t *reg,
663 int barNum
664);
665pcieRet_e pciev0_read_type1Bar32bit_reg
666(
667 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
668 pcieBar32bitReg_t *reg,
669 int barNum
670);
671pcieRet_e pciev0_write_type1Bar32bit_reg
672(
673 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
674 pcieBar32bitReg_t *reg,
675 int barNum
676);
677pcieRet_e pciev0_read_type1BusNum_reg
678(
679 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
680 pcieType1BusNumReg_t *reg
681);
682pcieRet_e pciev0_write_type1BusNum_reg
683(
684 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
685 pcieType1BusNumReg_t *reg
686);
687pcieRet_e pciev0_read_type1SecStat_reg
688(
689 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
690 pcieType1SecStatReg_t *reg
691);
692pcieRet_e pciev0_write_type1SecStat_reg
693(
694 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
695 pcieType1SecStatReg_t *reg
696);
697pcieRet_e pciev0_read_type1Memspace_reg
698(
699 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
700 pcieType1MemspaceReg_t *reg
701);
702pcieRet_e pciev0_write_type1Memspace_reg
703(
704 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
705 pcieType1MemspaceReg_t *reg
706);
707pcieRet_e pciev0_read_prefMem_reg
708(
709 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
710 pciePrefMemReg_t *reg
711);
712pcieRet_e pciev0_write_prefMem_reg
713(
714 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
715 pciePrefMemReg_t *reg
716);
717pcieRet_e pciev0_read_prefBaseUpper_reg
718(
719 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
720 pciePrefBaseUpperReg_t *reg
721);
722pcieRet_e pciev0_write_prefBaseUpper_reg
723(
724 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
725 pciePrefBaseUpperReg_t *reg
726);
727pcieRet_e pciev0_read_prefLimitUpper_reg
728(
729 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
730 pciePrefLimitUpperReg_t *reg
731);
732pcieRet_e pciev0_write_prefLimitUpper_reg
733(
734 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
735 pciePrefLimitUpperReg_t *reg
736);
737pcieRet_e pciev0_read_type1IOSpace_reg
738(
739 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
740 pcieType1IOSpaceReg_t *reg
741);
742pcieRet_e pciev0_write_type1IOSpace_reg
743(
744 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
745 pcieType1IOSpaceReg_t *reg
746);
747pcieRet_e pciev0_read_type1CapPtr_reg
748(
749 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
750 pcieType1CapPtrReg_t *reg
751);
752pcieRet_e pciev0_write_type1CapPtr_reg
753(
754 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
755 pcieType1CapPtrReg_t *reg
756);
757pcieRet_e pciev0_read_type1ExpnsnRom_reg
758(
759 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
760 pcieType1ExpnsnRomReg_t *reg
761);
762pcieRet_e pciev0_write_type1ExpnsnRom_reg
763(
764 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
765 pcieType1ExpnsnRomReg_t *reg
766);
767pcieRet_e pciev0_read_type1BridgeInt_reg
768(
769 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
770 pcieType1BridgeIntReg_t *reg
771);
772pcieRet_e pciev0_write_type1BridgeInt_reg
773(
774 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
775 pcieType1BridgeIntReg_t *reg
776);
777
778/* power management capabilities*/
779pcieRet_e pciev0_read_pmCap_reg
780(
781 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
782 pciePMCapReg_t *reg
783);
784pcieRet_e pciev0_write_pmCap_reg
785(
786 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
787 pciePMCapReg_t *reg
788);
789pcieRet_e pciev0_read_pmCapCtlStat_reg
790(
791 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
792 pciePMCapCtlStatReg_t *reg
793);
794pcieRet_e pciev0_write_pmCapCtlStat_reg
795(
796 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
797 pciePMCapCtlStatReg_t *reg
798);
799/* MSI capabilities*/
800pcieRet_e pciev0_read_msiCap_reg
801(
802 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
803 pcieMsiCapReg_t *reg
804);
805pcieRet_e pciev0_write_msiCap_reg
806(
807 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
808 pcieMsiCapReg_t *reg
809);
810pcieRet_e pciev0_read_msiLo32_reg
811(
812 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
813 pcieMsiLo32Reg_t *reg
814);
815pcieRet_e pciev0_write_msiLo32_reg
816(
817 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
818 pcieMsiLo32Reg_t *reg
819);
820pcieRet_e pciev0_read_msiUp32_reg
821(
822 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
823 pcieMsiUp32Reg_t *reg
824);
825pcieRet_e pciev0_write_msiUp32_reg
826(
827 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
828 pcieMsiUp32Reg_t *reg
829);
830pcieRet_e pciev0_read_msiData_reg
831(
832 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
833 pcieMsiDataReg_t *reg
834);
835pcieRet_e pciev0_write_msiData_reg
836(
837 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
838 pcieMsiDataReg_t *reg
839);
840
841/*Capabilities Registers*/
842pcieRet_e pciev0_read_pciesCap_reg
843(
844 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
845 pciePciesCapReg_t *reg
846);
847pcieRet_e pciev0_write_pciesCap_reg
848(
849 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
850 pciePciesCapReg_t *reg
851);
852pcieRet_e pciev0_read_deviceCap_reg
853(
854 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
855 pcieDeviceCapReg_t *reg
856);
857pcieRet_e pciev0_write_deviceCap_reg
858(
859 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
860 pcieDeviceCapReg_t *reg
861);
862pcieRet_e pciev0_read_devStatCtrl_reg
863(
864 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
865 pcieDevStatCtrlReg_t *reg
866);
867pcieRet_e pciev0_write_devStatCtrl_reg
868(
869 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
870 pcieDevStatCtrlReg_t *reg
871);
872pcieRet_e pciev0_read_linkCap_reg
873(
874 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
875 pcieLinkCapReg_t *reg
876);
877
878pcieRet_e pciev0_write_linkCap_reg
879(
880 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
881 pcieLinkCapReg_t *reg
882);
883pcieRet_e pciev0_read_linkStatCtrl_reg
884(
885 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
886 pcieLinkStatCtrlReg_t *reg
887);
888pcieRet_e pciev0_write_linkStatCtrl_reg
889(
890 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
891 pcieLinkStatCtrlReg_t *reg
892);
893pcieRet_e pciev0_read_slotCap_reg
894(
895 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
896 pcieSlotCapReg_t *reg
897);
898pcieRet_e pciev0_write_slotCap_reg
899(
900 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
901 pcieSlotCapReg_t *reg
902);
903pcieRet_e pciev0_read_slotStatCtrl_reg
904(
905 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
906 pcieSlotStatCtrlReg_t *reg
907);
908pcieRet_e pciev0_write_slotStatCtrl_reg
909(
910 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
911 pcieSlotStatCtrlReg_t *reg
912);
913pcieRet_e pciev0_read_rootCtrlCap_reg
914(
915 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
916 pcieRootCtrlCapReg_t *reg
917);
918pcieRet_e pciev0_write_rootCtrlCap_reg
919(
920 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
921 pcieRootCtrlCapReg_t *reg
922);
923pcieRet_e pciev0_read_rootStatus_reg
924(
925 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
926 pcieRootStatusReg_t *reg
927);
928pcieRet_e pciev0_write_rootStatus_reg
929(
930 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
931 pcieRootStatusReg_t *reg
932);
933pcieRet_e pciev0_read_devCap2_reg
934(
935 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
936 pcieDevCap2Reg_t *reg
937);
938pcieRet_e pciev0_write_devCap2_reg
939(
940 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
941 pcieDevCap2Reg_t *reg
942);
943pcieRet_e pciev0_read_devStatCtrl2_reg
944(
945 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
946 pcieDevStatCtrl2Reg_t *reg
947);
948pcieRet_e pciev0_write_devStatCtrl2_reg
949(
950 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
951 pcieDevStatCtrl2Reg_t *reg
952);
953pcieRet_e pciev0_read_linkCtrl2_reg
954(
955 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
956 pcieLinkCtrl2Reg_t *reg
957);
958pcieRet_e pciev0_write_linkCtrl2_reg
959(
960 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
961 pcieLinkCtrl2Reg_t *reg
962);
963
964/*Capabilities Extended Registers*/
965pcieRet_e pciev0_read_extCap_reg
966(
967 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
968 pcieExtCapReg_t *reg
969);
970pcieRet_e pciev0_read_uncErr_reg
971(
972 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
973 pcieUncErrReg_t *reg
974);
975pcieRet_e pciev0_write_uncErr_reg
976(
977 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
978 pcieUncErrReg_t *reg
979);
980pcieRet_e pciev0_read_uncErrMask_reg
981(
982 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
983 pcieUncErrMaskReg_t *reg
984);
985pcieRet_e pciev0_write_uncErrMask_reg
986(
987 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
988 pcieUncErrMaskReg_t *reg
989);
990pcieRet_e pciev0_read_uncErrSvrty_reg
991(
992 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
993 pcieUncErrSvrtyReg_t *reg
994);
995pcieRet_e pciev0_write_uncErrSvrty_reg
996(
997 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
998 pcieUncErrSvrtyReg_t *reg
999);
1000pcieRet_e pciev0_read_corErr_reg
1001(
1002 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1003 pcieCorErrReg_t *reg
1004);
1005pcieRet_e pciev0_write_corErr_reg
1006(
1007 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1008 pcieCorErrReg_t *reg
1009);
1010pcieRet_e pciev0_read_corErrMask_reg
1011(
1012 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1013 pcieCorErrMaskReg_t *reg
1014);
1015pcieRet_e pciev0_write_corErrMask_reg
1016(
1017 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1018 pcieCorErrMaskReg_t *reg
1019);
1020pcieRet_e pciev0_read_accr_reg
1021(
1022 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1023 pcieAccrReg_t *reg
1024);
1025pcieRet_e pciev0_write_accr_reg
1026(
1027 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1028 pcieAccrReg_t *reg
1029);
1030pcieRet_e pciev0_read_hdrLog_reg
1031(
1032 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1033 pcieHdrLogReg_t *reg,
1034 int regNum
1035);
1036pcieRet_e pciev0_read_rootErrCmd_reg
1037(
1038 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1039 pcieRootErrCmdReg_t *reg
1040);
1041pcieRet_e pciev0_write_rootErrCmd_reg
1042(
1043 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1044 pcieRootErrCmdReg_t *reg
1045);
1046pcieRet_e pciev0_read_rootErrSt_reg
1047(
1048 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1049 pcieRootErrStReg_t *reg
1050);
1051pcieRet_e pciev0_write_rootErrSt_reg
1052(
1053 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1054 pcieRootErrStReg_t *reg
1055);
1056pcieRet_e pciev0_read_errSrcID_reg
1057(
1058 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1059 pcieErrSrcIDReg_t *reg
1060);
1061
1062/*Port Logic Registers*/
1063pcieRet_e pciev0_read_plAckTimer_reg
1064(
1065 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1066 pciePlAckTimerReg_t *reg
1067);
1068pcieRet_e pciev0_write_plAckTimer_reg
1069(
1070 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1071 pciePlAckTimerReg_t *reg
1072);
1073pcieRet_e pciev0_read_plOMsg_reg
1074(
1075 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1076 pciePlOMsgReg_t *reg
1077);
1078pcieRet_e pciev0_write_plOMsg_reg
1079(
1080 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1081 pciePlOMsgReg_t *reg
1082);
1083pcieRet_e pciev0_read_plForceLink_reg
1084(
1085 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1086 pciePlForceLinkReg_t *reg
1087);
1088pcieRet_e pciev0_write_plForceLink_reg
1089(
1090 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1091 pciePlForceLinkReg_t *reg
1092);
1093pcieRet_e pciev0_read_ackFreq_reg
1094(
1095 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1096 pcieAckFreqReg_t *reg
1097);
1098pcieRet_e pciev0_write_ackFreq_reg
1099(
1100 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1101 pcieAckFreqReg_t *reg
1102);
1103pcieRet_e pciev0_read_lnkCtrl_reg
1104(
1105 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1106 pcieLnkCtrlReg_t *reg
1107);
1108pcieRet_e pciev0_write_lnkCtrl_reg
1109(
1110 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1111 pcieLnkCtrlReg_t *reg
1112);
1113pcieRet_e pciev0_read_laneSkew_reg
1114(
1115 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1116 pcieLaneSkewReg_t *reg
1117);
1118pcieRet_e pciev0_write_laneSkew_reg
1119(
1120 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1121 pcieLaneSkewReg_t *reg
1122);
1123pcieRet_e pciev0_read_symNum_reg
1124(
1125 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1126 pcieSymNumReg_t *reg
1127);
1128pcieRet_e pciev0_write_symNum_reg
1129(
1130 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1131 pcieSymNumReg_t *reg
1132);
1133pcieRet_e pciev0_read_symTimerFltMask_reg
1134(
1135 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1136 pcieSymTimerFltMaskReg_t *reg
1137);
1138pcieRet_e pciev0_write_symTimerFltMask_reg
1139(
1140 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1141 pcieSymTimerFltMaskReg_t *reg
1142);
1143pcieRet_e pciev0_read_fltMask2_reg
1144(
1145 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1146 pcieFltMask2Reg_t *reg
1147);
1148pcieRet_e pciev0_write_fltMask2_reg
1149(
1150 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1151 pcieFltMask2Reg_t *reg
1152);
1153pcieRet_e pciev0_read_debug0_reg
1154(
1155 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1156 pcieDebug0Reg_t *reg
1157);
1158pcieRet_e pciev0_read_debug1_reg
1159(
1160 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1161 pcieDebug1Reg_t *reg
1162);
1163pcieRet_e pciev0_read_gen2_reg
1164(
1165 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1166 pcieGen2Reg_t *reg
1167);
1168pcieRet_e pciev0_write_gen2_reg
1169(
1170 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1171 pcieGen2Reg_t *reg
1172);
1173
1174#ifdef __cplusplus
1175}
1176#endif
1177
1178#endif /* _PCIEV0LOC_H */
1179
1180/* Nothing past this point */
1181
diff --git a/src/v0/pciev0.c b/src/v0/pciev0.c
new file mode 100644
index 0000000..c499457
--- /dev/null
+++ b/src/v0/pciev0.c
@@ -0,0 +1,1090 @@
1/*
2 *
3 * Copyright (C) 2010-2015 Texas Instruments Incorporated - http://www.ti.com/
4 *
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 *
13 * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the
16 * distribution.
17 *
18 * Neither the name of Texas Instruments Incorporated nor the names of
19 * its contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 */
35
36/*
37 * File Name: pcie.c
38 *
39 * Processing/configuration functions for the PCIe driver.
40 *
41 */
42
43#include <ti/drv/pcie/pcie.h>
44#include <ti/drv/pcie/src/pcieloc.h>
45#include <ti/drv/pcie/src/v0/pcieloc.h>
46#include <ti/csl/cslr_pcie_cfg_space_endpoint.h>
47#include <ti/csl/cslr_pcie_cfg_space_rootcomplex.h>
48#include <ti/csl/cslr_pciess_app.h>
49
50#include <string.h>
51
52/*****************************************************************************
53 * Set the mode of one interface without depending directly on device
54 * dependant registers (via device.c)
55 ****************************************************************************/
56static void pcie_set_mode (Pcie_DeviceCfgBaseAddr *iface, pcieMode_e mode)
57{
58 uint32_t modeReg;
59 uint32_t newMode = (uint32_t)mode;
60
61 /* Set the mode, without depending on device specific csl files */
62 modeReg = *iface->pcieSSModeAddr;
63 modeReg &= ~iface->pcieSSModeMask;
64 newMode <<= iface->pcieSSModeShift;
65 newMode &= iface->pcieSSModeMask;
66 modeReg |= newMode;
67 *iface->pcieSSModeAddr = modeReg;
68} /* pcie_set_mode */
69
70/*****************************************************************************
71 ********** External APIs **********************
72 ****************************************************************************/
73
74/*********************************************************************
75 * FUNCTION PURPOSE: Sets PCIe mode to RC or EP for interface
76 * specified by handle
77 *********************************************************************/
78pcieRet_e Pciev0_setInterfaceMode
79(
80 Pcie_Handle handle, /**< [in] The PCIE LLD instance identifier */
81 pcieMode_e mode /**< [in] PCIE Mode */
82)
83{
84 Pcie_DeviceCfgBaseAddr *bases = pcie_handle_to_cfg (handle);
85
86 if (bases) {
87 pcie_set_mode (bases, mode);
88 return pcie_RET_OK;
89 }
90
91 return pcie_RET_INV_HANDLE;
92} /* Pciev0_setInterfaceMode */
93
94/*********************************************************************
95 * FUNCTION PURPOSE: Returns the PCIe Internal Address Range for the
96 * Memory Space. This range is used for accessing memory.
97 *********************************************************************/
98pcieRet_e Pciev0_getMemSpaceRange
99(
100 Pcie_Handle handle, /**< [in] The PCIE LLD instance identifier */
101 void **base, /**< [out] Memory Space base address */
102 uint32_t *size /**< [out] Memory Space total size */
103)
104{
105 pcieRet_e retVal = pcie_RET_OK;
106
107 if (! pcieLObjIsValid) {
108 return pcie_RET_NO_INIT;
109 }
110
111 pcie_check_handle(handle);
112
113 if (base) {
114 Pcie_DeviceCfgBaseAddr *bases = pcie_handle_to_cfg (handle);
115 if (bases) {
116 *base = bases->dataBase;
117 } else {
118 retVal = pcie_RET_INV_HANDLE;
119 }
120 }
121
122 if (size) *size = 0x10000000; /* 256 MB */
123
124 return retVal;
125} /* Pciev0_getMemSpaceRange */
126
127/*********************************************************************
128 * FUNCTION PURPOSE: Reads any register
129 ********************************************************************/
130pcieRet_e Pciev0_readRegs
131(
132 Pcie_Handle handle, /**< [in] The PCIE LLD instance identifier */
133 pcieLocation_e location, /**< [in] Local or remote peripheral */
134 pcieRegisters_t *readRegs /**< [in/out] List of registers to read */
135)
136{
137 /* Base Address for the Application Registers */
138 CSL_Pciess_appRegs *baseAppRegs = (CSL_Pciess_appRegs *)handle;
139
140 /* Base Address for the Config Space
141 These registers can be Local/Remote and Type0(EP)/Type1(RC) */
142 CSL_Pcie_cfg_space_rootcomplexRegs *baseCfgRcRegs = NULL;
143 CSL_Pcie_cfg_space_endpointRegs *baseCfgEpRegs = NULL;
144
145 pcieRet_e retVal = pcie_RET_OK;
146 int i;
147
148 if (! pcieLObjIsValid) {
149 return pcie_RET_NO_INIT;
150 }
151
152 pcie_check_handle(handle);
153
154 /* Get base address for Local or Remote config space */
155 if (location == pcie_LOCATION_LOCAL)
156 {
157 pcie_get_loc_cfg_base(handle, baseCfgEpRegs, baseCfgRcRegs)
158 }
159 else
160 {
161 pcie_get_rem_cfg_base(handle, baseCfgEpRegs, baseCfgRcRegs)
162 }
163
164 /*****************************************************************************************
165 *Application Registers
166 *****************************************************************************************/
167 if (readRegs->pid) {
168 pcie_check_result(retVal, pciev0_read_pid_reg (baseAppRegs, readRegs->pid));
169 }
170 if (readRegs->cmdStatus) {
171 pcie_check_result(retVal, pciev0_read_cmdStatus_reg (baseAppRegs, readRegs->cmdStatus));
172 }
173 if (readRegs->cfgTrans) {
174 pcie_check_result(retVal, pciev0_read_cfgTrans_reg (baseAppRegs, readRegs->cfgTrans));
175 }
176 if (readRegs->ioBase) {
177 pcie_check_result(retVal, pciev0_read_ioBase_reg (baseAppRegs, readRegs->ioBase));
178 }
179 if (readRegs->tlpCfg) {
180 pcie_check_result(retVal, pciev0_read_tlpCfg_reg (baseAppRegs, readRegs->tlpCfg));
181 }
182 if (readRegs->rstCmd) {
183 pcie_check_result(retVal, pciev0_read_rstCmd_reg (baseAppRegs, readRegs->rstCmd));
184 }
185 if (readRegs->pmCmd) {
186 pcie_check_result(retVal, pciev0_read_pmCmd_reg (baseAppRegs, readRegs->pmCmd));
187 }
188 if (readRegs->pmCfg) {
189 pcie_check_result(retVal, pciev0_read_pmCfg_reg (baseAppRegs, readRegs->pmCfg));
190 }
191 if (readRegs->actStatus) {
192 pcie_check_result(retVal, pciev0_read_actStatus_reg (baseAppRegs, readRegs->actStatus));
193 }
194 if (readRegs->obSize) {
195 pcie_check_result(retVal, pciev0_read_obSize_reg (baseAppRegs, readRegs->obSize));
196 }
197 if (readRegs->diagCtrl) {
198 pcie_check_result(retVal, pciev0_read_diagCtrl_reg (baseAppRegs, readRegs->diagCtrl));
199 }
200 if (readRegs->endian) {
201 pcie_check_result(retVal, pciev0_read_endian_reg (baseAppRegs, readRegs->endian));
202 }
203 if (readRegs->priority) {
204 pcie_check_result(retVal, pciev0_read_priority_reg (baseAppRegs, readRegs->priority));
205 }
206 if (readRegs->irqEOI) {
207 pcie_check_result(retVal, pciev0_read_irqEOI_reg (baseAppRegs, readRegs->irqEOI));
208 }
209 if (readRegs->msiIrq) {
210 pcie_check_result(retVal, pciev0_read_msiIrq_reg (baseAppRegs, readRegs->msiIrq));
211 }
212 if (readRegs->epIrqSet) {
213 pcie_check_result(retVal, pciev0_read_epIrqSet_reg (baseAppRegs, readRegs->epIrqSet));
214 }
215 if (readRegs->epIrqClr) {
216 pcie_check_result(retVal, pciev0_read_epIrqClr_reg (baseAppRegs, readRegs->epIrqClr));
217 }
218 if (readRegs->epIrqStatus) {
219 pcie_check_result(retVal, pciev0_read_epIrqStatus_reg (baseAppRegs, readRegs->epIrqStatus));
220 }
221 for (i = 0; i < 4; i++) {
222 if (readRegs->genPurpose[i]) {
223 pcie_check_result(retVal, pciev0_read_genPurpose_reg (baseAppRegs, readRegs->genPurpose[i], i));
224 }
225 }
226 for (i = 0; i < 8; i++) {
227 if (readRegs->msiIrqStatusRaw[i]) {
228 pcie_check_result(retVal, pciev0_read_msiIrqStatusRaw_reg (baseAppRegs, readRegs->msiIrqStatusRaw[i], i));
229 }
230 if (readRegs->msiIrqStatus[i]) {
231 pcie_check_result(retVal, pciev0_read_msiIrqStatus_reg (baseAppRegs, readRegs->msiIrqStatus[i], i));
232 }
233 if (readRegs->msiIrqEnableSet[i]) {
234 pcie_check_result(retVal, pciev0_read_msiIrqEnableSet_reg (baseAppRegs, readRegs->msiIrqEnableSet[i], i));
235 }
236 if (readRegs->msiIrqEnableClr[i]) {
237 pcie_check_result(retVal, pciev0_read_msiIrqEnableClr_reg (baseAppRegs, readRegs->msiIrqEnableClr[i], i));
238 }
239 }
240 for (i = 0; i < 4; i++) {
241 if (readRegs->legacyIrqStatusRaw[i]) {
242 pcie_check_result(retVal, pciev0_read_legacyIrqStatusRaw_reg (baseAppRegs, readRegs->legacyIrqStatusRaw[i], i));
243 }
244 if (readRegs->legacyIrqStatus[i]) {
245 pcie_check_result(retVal, pciev0_read_legacyIrqStatus_reg (baseAppRegs, readRegs->legacyIrqStatus[i], i));
246 }
247 if (readRegs->legacyIrqEnableSet[i]) {
248 pcie_check_result(retVal, pciev0_read_legacyIrqEnableSet_reg (baseAppRegs, readRegs->legacyIrqEnableSet[i], i));
249 }
250 if (readRegs->legacyIrqEnableClr[i]) {
251 pcie_check_result(retVal, pciev0_read_legacyIrqEnableClr_reg (baseAppRegs, readRegs->legacyIrqEnableClr[i], i));
252 }
253 }
254 if (readRegs->errIrqStatusRaw) {
255 pcie_check_result(retVal, pciev0_read_errIrqStatusRaw_reg (baseAppRegs, readRegs->errIrqStatusRaw));
256 }
257 if (readRegs->errIrqStatus) {
258 pcie_check_result(retVal, pciev0_read_errIrqStatus_reg (baseAppRegs, readRegs->errIrqStatus));
259 }
260 if (readRegs->errIrqEnableSet) {
261 pcie_check_result(retVal, pciev0_read_errIrqEnableSet_reg (baseAppRegs, readRegs->errIrqEnableSet));
262 }
263 if (readRegs->errIrqEnableClr) {
264 pcie_check_result(retVal, pciev0_read_errIrqEnableClr_reg (baseAppRegs, readRegs->errIrqEnableClr));
265 }
266
267 if (readRegs->pmRstIrqStatusRaw) {
268 pcie_check_result(retVal, pciev0_read_pmRstIrqStatusRaw_reg (baseAppRegs, readRegs->pmRstIrqStatusRaw));
269 }
270 if (readRegs->pmRstIrqStatus) {
271 pcie_check_result(retVal, pciev0_read_pmRstIrqStatus_reg (baseAppRegs, readRegs->pmRstIrqStatus));
272 }
273 if (readRegs->pmRstIrqEnableSet) {
274 pcie_check_result(retVal, pciev0_read_pmRstIrqEnableSet_reg (baseAppRegs, readRegs->pmRstIrqEnableSet));
275 }
276 if (readRegs->pmRstIrqEnableClr) {
277 pcie_check_result(retVal, pciev0_read_pmRstIrqEnableClr_reg (baseAppRegs, readRegs->pmRstIrqEnableClr));
278 }
279
280 for (i = 0; i < 8; i ++) {
281 if (readRegs->obOffsetLo[i]) {
282 pcie_check_result(retVal, pciev0_read_obOffsetLo_reg (baseAppRegs, readRegs->obOffsetLo[i], i));
283 }
284 if (readRegs->obOffsetHi[i]) {
285 pcie_check_result(retVal, pciev0_read_obOffsetHi_reg (baseAppRegs, readRegs->obOffsetHi[i], i));
286 }
287 }
288
289 for (i = 0; i < 4; i ++) {
290 if (readRegs->ibBar[i]) {
291 pcie_check_result(retVal, pciev0_read_ibBar_reg (baseAppRegs, readRegs->ibBar[i], i));
292 }
293 if (readRegs->ibStartLo[i]) {
294 pcie_check_result(retVal, pciev0_read_ibStartLo_reg (baseAppRegs, readRegs->ibStartLo[i], i));
295 }
296 if (readRegs->ibStartHi[i]) {
297 pcie_check_result(retVal, pciev0_read_ibStartHi_reg (baseAppRegs, readRegs->ibStartHi[i], i));
298 }
299 if (readRegs->ibOffset[i]) {
300 pcie_check_result(retVal, pciev0_read_ibOffset_reg (baseAppRegs, readRegs->ibOffset[i], i));
301 }
302 }
303
304 if (readRegs->pcsCfg0) {
305 pcie_check_result(retVal, pciev0_read_pcsCfg0_reg (baseAppRegs, readRegs->pcsCfg0));
306 }
307 if (readRegs->pcsCfg1) {
308 pcie_check_result(retVal, pciev0_read_pcsCfg1_reg (baseAppRegs, readRegs->pcsCfg1));
309 }
310 if (readRegs->pcsStatus) {
311 pcie_check_result(retVal, pciev0_read_pcsStatus_reg (baseAppRegs, readRegs->pcsStatus));
312 }
313
314 if (readRegs->serdesCfg0) {
315 pcie_check_result(retVal, pciev0_read_serdesCfg0_reg (baseAppRegs, readRegs->serdesCfg0));
316 }
317 if (readRegs->serdesCfg1) {
318 pcie_check_result(retVal, pciev0_read_serdesCfg1_reg (baseAppRegs, readRegs->serdesCfg1));
319 }
320
321 /*****************************************************************************************
322 *Configuration Registers
323 *****************************************************************************************/
324
325 /*Type 0, Type1 Common Registers*/
326
327 if (readRegs->vndDevId) {
328 pcie_check_result(retVal, pciev0_read_vndDevId_reg (baseCfgEpRegs, readRegs->vndDevId));
329 }
330 if (readRegs->statusCmd) {
331 pcie_check_result(retVal, pciev0_read_statusCmd_reg (baseCfgEpRegs, readRegs->statusCmd));
332 }
333 if (readRegs->revId) {
334 pcie_check_result(retVal, pciev0_read_revId_reg (baseCfgEpRegs, readRegs->revId));
335 }
336
337 /*Type 0 Registers*/
338 if (readRegs->bist) {
339 pcie_check_result(retVal, pciev0_read_bist_reg (baseCfgEpRegs, readRegs->bist));
340 }
341 if (readRegs->type0BarIdx) {
342 pcie_check_result(retVal, pciev0_read_type0Bar_reg (baseCfgEpRegs, &(readRegs->type0BarIdx->reg),
343 readRegs->type0BarIdx->idx));
344 }
345 if (readRegs->type0Bar32bitIdx) {
346 pcie_check_result(retVal, pciev0_read_type0Bar32bit_reg (baseCfgEpRegs, &(readRegs->type0Bar32bitIdx->reg),
347 readRegs->type0Bar32bitIdx->idx));
348 }
349 if (readRegs->subId) {
350 pcie_check_result(retVal, pciev0_read_subId_reg (baseCfgEpRegs, readRegs->subId));
351 }
352 if (readRegs->expRom) {
353 pcie_check_result(retVal, pciev0_read_expRom_reg (baseCfgEpRegs, readRegs->expRom));
354 }
355 if (readRegs->capPtr) {
356 pcie_check_result(retVal, pciev0_read_capPtr_reg (baseCfgEpRegs, readRegs->capPtr));
357 }
358 if (readRegs->intPin) {
359 pcie_check_result(retVal, pciev0_read_intPin_reg (baseCfgEpRegs, readRegs->intPin));
360 }
361
362 /*Type 1 Registers*/
363 if (readRegs->type1BistHeader) {
364 pcie_check_result(retVal, pciev0_read_type1BistHeader_reg (baseCfgRcRegs, readRegs->type1BistHeader));
365 }
366 if (readRegs->type1BarIdx) {
367 pcie_check_result(retVal, pciev0_read_type1Bar_reg (baseCfgRcRegs, &(readRegs->type1BarIdx->reg),
368 readRegs->type1BarIdx->idx));
369 }
370 if (readRegs->type1Bar32bitIdx) {
371 pcie_check_result(retVal, pciev0_read_type1Bar32bit_reg (baseCfgRcRegs, &(readRegs->type1Bar32bitIdx->reg),
372 readRegs->type1Bar32bitIdx->idx));
373 }
374 if (readRegs->type1BusNum) {
375 pcie_check_result(retVal, pciev0_read_type1BusNum_reg (baseCfgRcRegs, readRegs->type1BusNum));
376 }
377 if (readRegs->type1SecStat) {
378 pcie_check_result(retVal, pciev0_read_type1SecStat_reg (baseCfgRcRegs, readRegs->type1SecStat));
379 }
380 if (readRegs->type1Memspace) {
381 pcie_check_result(retVal, pciev0_read_type1Memspace_reg (baseCfgRcRegs, readRegs->type1Memspace));
382 }
383 if (readRegs->prefMem) {
384 pcie_check_result(retVal, pciev0_read_prefMem_reg (baseCfgRcRegs, readRegs->prefMem));
385 }
386 if (readRegs->prefBaseUpper) {
387 pcie_check_result(retVal, pciev0_read_prefBaseUpper_reg (baseCfgRcRegs, readRegs->prefBaseUpper));
388 }
389 if (readRegs->prefLimitUpper) {
390 pcie_check_result(retVal, pciev0_read_prefLimitUpper_reg (baseCfgRcRegs, readRegs->prefLimitUpper));
391 }
392 if (readRegs->type1IOSpace) {
393 pcie_check_result(retVal, pciev0_read_type1IOSpace_reg (baseCfgRcRegs, readRegs->type1IOSpace));
394 }
395 if (readRegs->type1CapPtr) {
396 pcie_check_result(retVal, pciev0_read_type1CapPtr_reg (baseCfgRcRegs, readRegs->type1CapPtr));
397 }
398 if (readRegs->type1ExpnsnRom) {
399 pcie_check_result(retVal, pciev0_read_type1ExpnsnRom_reg (baseCfgRcRegs, readRegs->type1ExpnsnRom));
400 }
401 if (readRegs->type1BridgeInt) {
402 pcie_check_result(retVal, pciev0_read_type1BridgeInt_reg (baseCfgRcRegs, readRegs->type1BridgeInt));
403 }
404
405 /* Power Management Capabilities Registers */
406 if (readRegs->pmCap) {
407 pcie_check_result(retVal, pciev0_read_pmCap_reg (baseCfgEpRegs, readRegs->pmCap));
408 }
409 if (readRegs->pmCapCtlStat) {
410 pcie_check_result(retVal, pciev0_read_pmCapCtlStat_reg (baseCfgEpRegs, readRegs->pmCapCtlStat));
411 }
412
413 /*MSI Registers*/
414 if (readRegs->msiCap) {
415 pcie_check_result(retVal, pciev0_read_msiCap_reg (baseCfgEpRegs, readRegs->msiCap));
416 }
417 if (readRegs->msiLo32) {
418 pcie_check_result(retVal, pciev0_read_msiLo32_reg (baseCfgEpRegs, readRegs->msiLo32));
419 }
420 if (readRegs->msiUp32) {
421 pcie_check_result(retVal, pciev0_read_msiUp32_reg (baseCfgEpRegs, readRegs->msiUp32));
422 }
423 if (readRegs->msiData) {
424 pcie_check_result(retVal, pciev0_read_msiData_reg (baseCfgEpRegs, readRegs->msiData));
425 }
426
427 /*Capabilities Registers*/
428 if (readRegs->pciesCap) {
429 pcie_check_result(retVal, pciev0_read_pciesCap_reg (baseCfgEpRegs, readRegs->pciesCap));
430 }
431 if (readRegs->deviceCap) {
432 pcie_check_result(retVal, pciev0_read_deviceCap_reg (baseCfgEpRegs, readRegs->deviceCap));
433 }
434 if (readRegs->devStatCtrl) {
435 pcie_check_result(retVal, pciev0_read_devStatCtrl_reg (baseCfgEpRegs, readRegs->devStatCtrl));
436 }
437 if (readRegs->linkCap) {
438 pcie_check_result(retVal, pciev0_read_linkCap_reg (baseCfgEpRegs, readRegs->linkCap));
439 }
440 if (readRegs->linkStatCtrl) {
441 pcie_check_result(retVal, pciev0_read_linkStatCtrl_reg (baseCfgEpRegs, readRegs->linkStatCtrl));
442 }
443 if (readRegs->slotCap) {
444 pcie_check_result(retVal, pciev0_read_slotCap_reg (baseCfgRcRegs, readRegs->slotCap));
445 }
446 if (readRegs->slotStatCtrl) {
447 pcie_check_result(retVal, pciev0_read_slotStatCtrl_reg (baseCfgRcRegs, readRegs->slotStatCtrl));
448 }
449 if (readRegs->rootCtrlCap) {
450 pcie_check_result(retVal, pciev0_read_rootCtrlCap_reg (baseCfgRcRegs, readRegs->rootCtrlCap));
451 }
452 if (readRegs->rootStatus) {
453 pcie_check_result(retVal, pciev0_read_rootStatus_reg (baseCfgRcRegs, readRegs->rootStatus));
454 }
455 if (readRegs->devCap2) {
456 pcie_check_result(retVal, pciev0_read_devCap2_reg (baseCfgEpRegs, readRegs->devCap2));
457 }
458 if (readRegs->devStatCtrl2) {
459 pcie_check_result(retVal, pciev0_read_devStatCtrl2_reg (baseCfgEpRegs, readRegs->devStatCtrl2));
460 }
461 if (readRegs->linkCtrl2) {
462 pcie_check_result(retVal, pciev0_read_linkCtrl2_reg (baseCfgEpRegs, readRegs->linkCtrl2));
463 }
464
465
466 /*Capabilities Extended Registers*/
467 if (readRegs->extCap) {
468 pcie_check_result(retVal, pciev0_read_extCap_reg (baseCfgEpRegs, readRegs->extCap));
469 }
470 if (readRegs->uncErr) {
471 pcie_check_result(retVal, pciev0_read_uncErr_reg (baseCfgEpRegs, readRegs->uncErr));
472 }
473 if (readRegs->uncErrMask) {
474 pcie_check_result(retVal, pciev0_read_uncErrMask_reg (baseCfgEpRegs, readRegs->uncErrMask));
475 }
476 if (readRegs->uncErrSvrty) {
477 pcie_check_result(retVal, pciev0_read_uncErrSvrty_reg (baseCfgEpRegs, readRegs->uncErrSvrty));
478 }
479 if (readRegs->corErr) {
480 pcie_check_result(retVal, pciev0_read_corErr_reg (baseCfgEpRegs, readRegs->corErr));
481 }
482 if (readRegs->corErrMask) {
483 pcie_check_result(retVal, pciev0_read_corErrMask_reg (baseCfgEpRegs, readRegs->corErrMask));
484 }
485 if (readRegs->accr) {
486 pcie_check_result(retVal, pciev0_read_accr_reg (baseCfgEpRegs, readRegs->accr));
487 }
488 for (i = 0; i < 4; i ++) {
489 if (readRegs->hdrLog[i]) {
490 pcie_check_result(retVal, pciev0_read_hdrLog_reg (baseCfgEpRegs, readRegs->hdrLog[i], i));
491 }
492 }
493 if (readRegs->rootErrCmd) {
494 pcie_check_result(retVal, pciev0_read_rootErrCmd_reg (baseCfgEpRegs, readRegs->rootErrCmd));
495 }
496 if (readRegs->rootErrSt) {
497 pcie_check_result(retVal, pciev0_read_rootErrSt_reg (baseCfgEpRegs, readRegs->rootErrSt));
498 }
499 if (readRegs->errSrcID) {
500 pcie_check_result(retVal, pciev0_read_errSrcID_reg (baseCfgEpRegs, readRegs->errSrcID));
501 }
502
503 /*Port Logic Registers*/
504 if (readRegs->plAckTimer) {
505 pcie_check_result(retVal, pciev0_read_plAckTimer_reg (baseCfgEpRegs, readRegs->plAckTimer));
506 }
507 if (readRegs->plOMsg) {
508 pcie_check_result(retVal, pciev0_read_plOMsg_reg (baseCfgEpRegs, readRegs->plOMsg));
509 }
510 if (readRegs->plForceLink) {
511 pcie_check_result(retVal, pciev0_read_plForceLink_reg (baseCfgEpRegs, readRegs->plForceLink));
512 }
513 if (readRegs->ackFreq) {
514 pcie_check_result(retVal, pciev0_read_ackFreq_reg (baseCfgEpRegs, readRegs->ackFreq));
515 }
516 if (readRegs->lnkCtrl) {
517 pcie_check_result(retVal, pciev0_read_lnkCtrl_reg (baseCfgEpRegs, readRegs->lnkCtrl));
518 }
519 if (readRegs->laneSkew) {
520 pcie_check_result(retVal, pciev0_read_laneSkew_reg (baseCfgEpRegs, readRegs->laneSkew));
521 }
522 if (readRegs->symNum) {
523 pcie_check_result(retVal, pciev0_read_symNum_reg (baseCfgEpRegs, readRegs->symNum));
524 }
525 if (readRegs->symTimerFltMask) {
526 pcie_check_result(retVal, pciev0_read_symTimerFltMask_reg (baseCfgEpRegs, readRegs->symTimerFltMask));
527 }
528 if (readRegs->fltMask2) {
529 pcie_check_result(retVal, pciev0_read_fltMask2_reg (baseCfgEpRegs, readRegs->fltMask2));
530 }
531 if (readRegs->debug0) {
532 pcie_check_result(retVal, pciev0_read_debug0_reg (baseCfgEpRegs, readRegs->debug0));
533 }
534 if (readRegs->debug1) {
535 pcie_check_result(retVal, pciev0_read_debug1_reg (baseCfgEpRegs, readRegs->debug1));
536 }
537 if (readRegs->gen2) {
538 pcie_check_result(retVal, pciev0_read_gen2_reg (baseCfgEpRegs, readRegs->gen2));
539 }
540
541 return retVal;
542} /* Pciev0_readRegs */
543
544
545/*********************************************************************
546 * FUNCTION PURPOSE: Writes any register
547 ********************************************************************/
548pcieRet_e Pciev0_writeRegs
549(
550 Pcie_Handle handle, /**< [in] The PCIE LLD instance identifier */
551 pcieLocation_e location, /**< [in] Local or remote peripheral */
552 pcieRegisters_t *writeRegs /**< [in] List of registers to write */
553)
554{
555 /* Base Address for the Application Registers */
556 CSL_Pciess_appRegs *baseAppRegs = (CSL_Pciess_appRegs *)handle;
557
558 /* Base Address for the Config Space
559 These registers can be Local/Remote and Type0(EP)/Type1(RC) */
560 CSL_Pcie_cfg_space_rootcomplexRegs *baseCfgRcRegs = NULL;
561 CSL_Pcie_cfg_space_endpointRegs *baseCfgEpRegs = NULL;
562
563 pcieRet_e retVal = pcie_RET_OK;
564 int i;
565
566 if (! pcieLObjIsValid) {
567 return pcie_RET_NO_INIT;
568 }
569
570 pcie_check_handle(handle);
571
572 /* Get base address for Local/Remote config space */
573 if (location == pcie_LOCATION_LOCAL)
574 {
575 pcie_get_loc_cfg_base(handle, baseCfgEpRegs, baseCfgRcRegs)
576 }
577 else
578 {
579 pcie_get_rem_cfg_base(handle, baseCfgEpRegs, baseCfgRcRegs)
580 }
581
582 /*****************************************************************************************
583 *Application Registers
584 *****************************************************************************************/
585 if (writeRegs->cmdStatus) {
586 pcie_check_result(retVal, pciev0_write_cmdStatus_reg (baseAppRegs, writeRegs->cmdStatus));
587 }
588 if (writeRegs->cfgTrans) {
589 pcie_check_result(retVal, pciev0_write_cfgTrans_reg (baseAppRegs, writeRegs->cfgTrans));
590 }
591 if (writeRegs->ioBase) {
592 pcie_check_result(retVal, pciev0_write_ioBase_reg (baseAppRegs, writeRegs->ioBase));
593 }
594 if (writeRegs->tlpCfg) {
595 pcie_check_result(retVal, pciev0_write_tlpCfg_reg (baseAppRegs, writeRegs->tlpCfg));
596 }
597 if (writeRegs->rstCmd) {
598 pcie_check_result(retVal, pciev0_write_rstCmd_reg (baseAppRegs, writeRegs->rstCmd));
599 }
600 if (writeRegs->pmCmd) {
601 pcie_check_result(retVal, pciev0_write_pmCmd_reg (baseAppRegs, writeRegs->pmCmd));
602 }
603 if (writeRegs->pmCfg) {
604 pcie_check_result(retVal, pciev0_write_pmCfg_reg (baseAppRegs, writeRegs->pmCfg));
605 }
606 if (writeRegs->obSize) {
607 pcie_check_result(retVal, pciev0_write_obSize_reg (baseAppRegs, writeRegs->obSize));
608 }
609 if (writeRegs->diagCtrl) {
610 pcie_check_result(retVal, pciev0_write_diagCtrl_reg (baseAppRegs, writeRegs->diagCtrl));
611 }
612 if (writeRegs->endian) {
613 pcie_check_result(retVal, pciev0_write_endian_reg (baseAppRegs, writeRegs->endian));
614 }
615 if (writeRegs->priority) {
616 pcie_check_result(retVal, pciev0_write_priority_reg (baseAppRegs, writeRegs->priority));
617 }
618 if (writeRegs->irqEOI) {
619 pcie_check_result(retVal, pciev0_write_irqEOI_reg (baseAppRegs, writeRegs->irqEOI));
620 }
621 if (writeRegs->msiIrq) {
622 pcie_check_result(retVal, pciev0_write_msiIrq_reg (baseAppRegs, writeRegs->msiIrq));
623 }
624 if (writeRegs->epIrqSet) {
625 pcie_check_result(retVal, pciev0_write_epIrqSet_reg (baseAppRegs, writeRegs->epIrqSet));
626 }
627 if (writeRegs->epIrqClr) {
628 pcie_check_result(retVal, pciev0_write_epIrqClr_reg (baseAppRegs, writeRegs->epIrqClr));
629 }
630 if (writeRegs->epIrqStatus) {
631 pcie_check_result(retVal, pciev0_write_epIrqStatus_reg (baseAppRegs, writeRegs->epIrqStatus));
632 }
633 for (i = 0; i < 4; i++) {
634 if (writeRegs->genPurpose[i]) {
635 pcie_check_result(retVal, pciev0_write_genPurpose_reg (baseAppRegs, writeRegs->genPurpose[i], i));
636 }
637 }
638 for (i = 0; i < 8; i++) {
639 if (writeRegs->msiIrqStatusRaw[i]) {
640 pcie_check_result(retVal, pciev0_write_msiIrqStatusRaw_reg (baseAppRegs, writeRegs->msiIrqStatusRaw[i], i));
641 }
642 if (writeRegs->msiIrqStatus[i]) {
643 pcie_check_result(retVal, pciev0_write_msiIrqStatus_reg (baseAppRegs, writeRegs->msiIrqStatus[i], i));
644 }
645 if (writeRegs->msiIrqEnableSet[i]) {
646 pcie_check_result(retVal, pciev0_write_msiIrqEnableSet_reg (baseAppRegs, writeRegs->msiIrqEnableSet[i], i));
647 }
648 if (writeRegs->msiIrqEnableClr[i]) {
649 pcie_check_result(retVal, pciev0_write_msiIrqEnableClr_reg (baseAppRegs, writeRegs->msiIrqEnableClr[i], i));
650 }
651 }
652 for (i = 0; i < 4; i++) {
653 if (writeRegs->legacyIrqStatusRaw[i]) {
654 pcie_check_result(retVal, pciev0_write_legacyIrqStatusRaw_reg (baseAppRegs, writeRegs->legacyIrqStatusRaw[i], i));
655 }
656 if (writeRegs->legacyIrqStatus[i]) {
657 pcie_check_result(retVal, pciev0_write_legacyIrqStatus_reg (baseAppRegs, writeRegs->legacyIrqStatus[i], i));
658 }
659 if (writeRegs->legacyIrqEnableSet[i]) {
660 pcie_check_result(retVal, pciev0_write_legacyIrqEnableSet_reg (baseAppRegs, writeRegs->legacyIrqEnableSet[i], i));
661 }
662 if (writeRegs->legacyIrqEnableClr[i]) {
663 pcie_check_result(retVal, pciev0_write_legacyIrqEnableClr_reg (baseAppRegs, writeRegs->legacyIrqEnableClr[i], i));
664 }
665 }
666 if (writeRegs->errIrqStatusRaw) {
667 pcie_check_result(retVal, pciev0_write_errIrqStatusRaw_reg (baseAppRegs, writeRegs->errIrqStatusRaw));
668 }
669 if (writeRegs->errIrqStatus) {
670 pcie_check_result(retVal, pciev0_write_errIrqStatus_reg (baseAppRegs, writeRegs->errIrqStatus));
671 }
672 if (writeRegs->errIrqEnableSet) {
673 pcie_check_result(retVal, pciev0_write_errIrqEnableSet_reg (baseAppRegs, writeRegs->errIrqEnableSet));
674 }
675 if (writeRegs->errIrqEnableClr) {
676 pcie_check_result(retVal, pciev0_write_errIrqEnableClr_reg (baseAppRegs, writeRegs->errIrqEnableClr));
677 }
678
679 if (writeRegs->pmRstIrqStatusRaw) {
680 pcie_check_result(retVal, pciev0_write_pmRstIrqStatusRaw_reg (baseAppRegs, writeRegs->pmRstIrqStatusRaw));
681 }
682 if (writeRegs->pmRstIrqStatus) {
683 pcie_check_result(retVal, pciev0_write_pmRstIrqStatus_reg (baseAppRegs, writeRegs->pmRstIrqStatus));
684 }
685 if (writeRegs->pmRstIrqEnableSet) {
686 pcie_check_result(retVal, pciev0_write_pmRstIrqEnableSet_reg (baseAppRegs, writeRegs->pmRstIrqEnableSet));
687 }
688 if (writeRegs->pmRstIrqEnableClr) {
689 pcie_check_result(retVal, pciev0_write_pmRstIrqEnableClr_reg (baseAppRegs, writeRegs->pmRstIrqEnableClr));
690 }
691
692 for (i = 0; i < 8; i ++) {
693 if (writeRegs->obOffsetLo[i]) {
694 pcie_check_result(retVal, pciev0_write_obOffsetLo_reg (baseAppRegs, writeRegs->obOffsetLo[i], i));
695 }
696 if (writeRegs->obOffsetHi[i]) {
697 pcie_check_result(retVal, pciev0_write_obOffsetHi_reg (baseAppRegs, writeRegs->obOffsetHi[i], i));
698 }
699 }
700
701 for (i = 0; i < 4; i ++) {
702 if (writeRegs->ibBar[i]) {
703 pcie_check_result(retVal, pciev0_write_ibBar_reg (baseAppRegs, writeRegs->ibBar[i], i));
704 }
705 if (writeRegs->ibStartLo[i]) {
706 pcie_check_result(retVal, pciev0_write_ibStartLo_reg (baseAppRegs, writeRegs->ibStartLo[i], i));
707 }
708 if (writeRegs->ibStartHi[i]) {
709 pcie_check_result(retVal, pciev0_write_ibStartHi_reg (baseAppRegs, writeRegs->ibStartHi[i], i));
710 }
711 if (writeRegs->ibOffset[i]) {
712 pcie_check_result(retVal, pciev0_write_ibOffset_reg (baseAppRegs, writeRegs->ibOffset[i], i));
713 }
714 }
715
716 if (writeRegs->pcsCfg0) {
717 pcie_check_result(retVal, pciev0_write_pcsCfg0_reg (baseAppRegs, writeRegs->pcsCfg0));
718 }
719 if (writeRegs->pcsCfg1) {
720 pcie_check_result(retVal, pciev0_write_pcsCfg1_reg (baseAppRegs, writeRegs->pcsCfg1));
721 }
722
723 if (writeRegs->serdesCfg0) {
724 pcie_check_result(retVal, pciev0_write_serdesCfg0_reg (baseAppRegs, writeRegs->serdesCfg0));
725 }
726 if (writeRegs->serdesCfg1) {
727 pcie_check_result(retVal, pciev0_write_serdesCfg1_reg (baseAppRegs, writeRegs->serdesCfg1));
728 }
729
730 /*****************************************************************************************
731 *Configuration Registers
732 *****************************************************************************************/
733
734 /*Type 0, Type1 Common Registers*/
735
736 if (writeRegs->vndDevId) {
737 pcie_check_result(retVal, pciev0_write_vndDevId_reg (baseCfgEpRegs, writeRegs->vndDevId));
738 }
739 if (writeRegs->statusCmd) {
740 pcie_check_result(retVal, pciev0_write_statusCmd_reg (baseCfgEpRegs, writeRegs->statusCmd));
741 }
742 if (writeRegs->revId) {
743 pcie_check_result(retVal, pciev0_write_revId_reg (baseCfgEpRegs, writeRegs->revId));
744 }
745
746 /*Type 0 Registers*/
747 if (writeRegs->bist) {
748 pcie_check_result(retVal, pciev0_write_bist_reg (baseCfgEpRegs, writeRegs->bist));
749 }
750 if (writeRegs->type0BarIdx) {
751 pcie_check_result(retVal, pciev0_write_type0Bar_reg (baseCfgEpRegs, &(writeRegs->type0BarIdx->reg),
752 writeRegs->type0BarIdx->idx));
753 }
754 if (writeRegs->type0Bar32bitIdx) {
755 pcie_check_result(retVal, pciev0_write_type0Bar32bit_reg (baseCfgEpRegs, &(writeRegs->type0Bar32bitIdx->reg),
756 writeRegs->type0Bar32bitIdx->idx));
757 }
758 if (writeRegs->subId) {
759 pcie_check_result(retVal, pciev0_write_subId_reg (baseCfgEpRegs, writeRegs->subId));
760 }
761 if (writeRegs->expRom) {
762 pcie_check_result(retVal, pciev0_write_expRom_reg (baseCfgEpRegs, writeRegs->expRom));
763 }
764 if (writeRegs->capPtr) {
765 pcie_check_result(retVal, pciev0_write_capPtr_reg (baseCfgEpRegs, writeRegs->capPtr));
766 }
767 if (writeRegs->intPin) {
768 pcie_check_result(retVal, pciev0_write_intPin_reg (baseCfgEpRegs, writeRegs->intPin));
769 }
770
771 /*Type 1 Registers*/
772 if (writeRegs->type1BistHeader) {
773 pcie_check_result(retVal, pciev0_write_type1BistHeader_reg (baseCfgRcRegs, writeRegs->type1BistHeader));
774 }
775 if (writeRegs->type1BarIdx) {
776 pcie_check_result(retVal, pciev0_write_type1Bar_reg (baseCfgRcRegs, &(writeRegs->type1BarIdx->reg),
777 writeRegs->type1BarIdx->idx));
778 }
779 if (writeRegs->type1Bar32bitIdx) {
780 pcie_check_result(retVal, pciev0_write_type1Bar32bit_reg (baseCfgRcRegs, &(writeRegs->type1Bar32bitIdx->reg),
781 writeRegs->type1Bar32bitIdx->idx));
782 }
783 if (writeRegs->type1BusNum) {
784 pcie_check_result(retVal, pciev0_write_type1BusNum_reg (baseCfgRcRegs, writeRegs->type1BusNum));
785 }
786 if (writeRegs->type1SecStat) {
787 pcie_check_result(retVal, pciev0_write_type1SecStat_reg (baseCfgRcRegs, writeRegs->type1SecStat));
788 }
789 if (writeRegs->type1Memspace) {
790 pcie_check_result(retVal, pciev0_write_type1Memspace_reg (baseCfgRcRegs, writeRegs->type1Memspace));
791 }
792 if (writeRegs->prefMem) {
793 pcie_check_result(retVal, pciev0_write_prefMem_reg (baseCfgRcRegs, writeRegs->prefMem));
794 }
795 if (writeRegs->prefBaseUpper) {
796 pcie_check_result(retVal, pciev0_write_prefBaseUpper_reg (baseCfgRcRegs, writeRegs->prefBaseUpper));
797 }
798 if (writeRegs->prefLimitUpper) {
799 pcie_check_result(retVal, pciev0_write_prefLimitUpper_reg (baseCfgRcRegs, writeRegs->prefLimitUpper));
800 }
801 if (writeRegs->type1IOSpace) {
802 pcie_check_result(retVal, pciev0_write_type1IOSpace_reg (baseCfgRcRegs, writeRegs->type1IOSpace));
803 }
804 if (writeRegs->type1CapPtr) {
805 pcie_check_result(retVal, pciev0_write_type1CapPtr_reg (baseCfgRcRegs, writeRegs->type1CapPtr));
806 }
807 if (writeRegs->type1ExpnsnRom) {
808 pcie_check_result(retVal, pciev0_write_type1ExpnsnRom_reg (baseCfgRcRegs, writeRegs->type1ExpnsnRom));
809 }
810 if (writeRegs->type1BridgeInt) {
811 pcie_check_result(retVal, pciev0_write_type1BridgeInt_reg (baseCfgRcRegs, writeRegs->type1BridgeInt));
812 }
813
814 /* Power Management Capabilities Registers */
815 if (writeRegs->pmCap) {
816 pcie_check_result(retVal, pciev0_write_pmCap_reg (baseCfgEpRegs, writeRegs->pmCap));
817 }
818 if (writeRegs->pmCapCtlStat) {
819 pcie_check_result(retVal, pciev0_write_pmCapCtlStat_reg (baseCfgEpRegs, writeRegs->pmCapCtlStat));
820 }
821
822 /*MSI Registers*/
823 if (writeRegs->msiCap) {
824 pcie_check_result(retVal, pciev0_write_msiCap_reg (baseCfgEpRegs, writeRegs->msiCap));
825 }
826 if (writeRegs->msiLo32) {
827 pcie_check_result(retVal, pciev0_write_msiLo32_reg (baseCfgEpRegs, writeRegs->msiLo32));
828 }
829 if (writeRegs->msiUp32) {
830 pcie_check_result(retVal, pciev0_write_msiUp32_reg (baseCfgEpRegs, writeRegs->msiUp32));
831 }
832 if (writeRegs->msiData) {
833 pcie_check_result(retVal, pciev0_write_msiData_reg (baseCfgEpRegs, writeRegs->msiData));
834 }
835
836 /*Capabilities Registers*/
837 if (writeRegs->pciesCap) {
838 pcie_check_result(retVal, pciev0_write_pciesCap_reg (baseCfgEpRegs, writeRegs->pciesCap));
839 }
840 if (writeRegs->deviceCap) {
841 pcie_check_result(retVal, pciev0_write_deviceCap_reg (baseCfgEpRegs, writeRegs->deviceCap));
842 }
843
844 if (writeRegs->devStatCtrl) {
845 pcie_check_result(retVal, pciev0_write_devStatCtrl_reg (baseCfgEpRegs, writeRegs->devStatCtrl));
846 }
847 if (writeRegs->linkCap) {
848 pcie_check_result(retVal, pciev0_write_linkCap_reg (baseCfgEpRegs, writeRegs->linkCap));
849 }
850 if (writeRegs->linkStatCtrl) {
851 pcie_check_result(retVal, pciev0_write_linkStatCtrl_reg (baseCfgEpRegs, writeRegs->linkStatCtrl));
852 }
853 if (writeRegs->slotCap) {
854 pcie_check_result(retVal, pciev0_write_slotCap_reg (baseCfgRcRegs, writeRegs->slotCap));
855 }
856 if (writeRegs->slotStatCtrl) {
857 pcie_check_result(retVal, pciev0_write_slotStatCtrl_reg (baseCfgRcRegs, writeRegs->slotStatCtrl));
858 }
859 if (writeRegs->rootCtrlCap) {
860 pcie_check_result(retVal, pciev0_write_rootCtrlCap_reg (baseCfgRcRegs, writeRegs->rootCtrlCap));
861 }
862 if (writeRegs->rootStatus) {
863 pcie_check_result(retVal, pciev0_write_rootStatus_reg (baseCfgRcRegs, writeRegs->rootStatus));
864 }
865 if (writeRegs->devCap2) {
866 pcie_check_result(retVal, pciev0_write_devCap2_reg (baseCfgEpRegs, writeRegs->devCap2));
867 }
868 if (writeRegs->devStatCtrl2) {
869 pcie_check_result(retVal, pciev0_write_devStatCtrl2_reg (baseCfgEpRegs, writeRegs->devStatCtrl2));
870 }
871 if (writeRegs->linkCtrl2) {
872 pcie_check_result(retVal, pciev0_write_linkCtrl2_reg (baseCfgEpRegs, writeRegs->linkCtrl2));
873 }
874
875 /*Capabilities Extended Registers*/
876 if (writeRegs->uncErr) {
877 pcie_check_result(retVal, pciev0_write_uncErr_reg (baseCfgEpRegs, writeRegs->uncErr));
878 }
879 if (writeRegs->uncErrMask) {
880 pcie_check_result(retVal, pciev0_write_uncErrMask_reg (baseCfgEpRegs, writeRegs->uncErrMask));
881 }
882 if (writeRegs->uncErrSvrty) {
883 pcie_check_result(retVal, pciev0_write_uncErrSvrty_reg (baseCfgEpRegs, writeRegs->uncErrSvrty));
884 }
885 if (writeRegs->corErr) {
886 pcie_check_result(retVal, pciev0_write_corErr_reg (baseCfgEpRegs, writeRegs->corErr));
887 }
888 if (writeRegs->corErrMask) {
889 pcie_check_result(retVal, pciev0_write_corErrMask_reg (baseCfgEpRegs, writeRegs->corErrMask));
890 }
891 if (writeRegs->accr) {
892 pcie_check_result(retVal, pciev0_write_accr_reg (baseCfgEpRegs, writeRegs->accr));
893 }
894 if (writeRegs->rootErrCmd) {
895 pcie_check_result(retVal, pciev0_write_rootErrCmd_reg (baseCfgEpRegs, writeRegs->rootErrCmd));
896 }
897 if (writeRegs->rootErrSt) {
898 pcie_check_result(retVal, pciev0_write_rootErrSt_reg (baseCfgEpRegs, writeRegs->rootErrSt));
899 }
900
901 /*Port Logic Registers*/
902 if (writeRegs->plAckTimer) {
903 pcie_check_result(retVal, pciev0_write_plAckTimer_reg (baseCfgEpRegs, writeRegs->plAckTimer));
904 }
905 if (writeRegs->plOMsg) {
906 pcie_check_result(retVal, pciev0_write_plOMsg_reg (baseCfgEpRegs, writeRegs->plOMsg));
907 }
908 if (writeRegs->plForceLink) {
909 pcie_check_result(retVal, pciev0_write_plForceLink_reg (baseCfgEpRegs, writeRegs->plForceLink));
910 }
911 if (writeRegs->ackFreq) {
912 pcie_check_result(retVal, pciev0_write_ackFreq_reg (baseCfgEpRegs, writeRegs->ackFreq));
913 }
914 if (writeRegs->lnkCtrl) {
915 pcie_check_result(retVal, pciev0_write_lnkCtrl_reg (baseCfgEpRegs, writeRegs->lnkCtrl));
916 }
917 if (writeRegs->laneSkew) {
918 pcie_check_result(retVal, pciev0_write_laneSkew_reg (baseCfgEpRegs, writeRegs->laneSkew));
919 }
920 if (writeRegs->symNum) {
921 pcie_check_result(retVal, pciev0_write_symNum_reg (baseCfgEpRegs, writeRegs->symNum));
922 }
923 if (writeRegs->symTimerFltMask) {
924 pcie_check_result(retVal, pciev0_write_symTimerFltMask_reg (baseCfgEpRegs, writeRegs->symTimerFltMask));
925 }
926 if (writeRegs->fltMask2) {
927 pcie_check_result(retVal, pciev0_write_fltMask2_reg (baseCfgEpRegs, writeRegs->fltMask2));
928 }
929 if (writeRegs->gen2) {
930 pcie_check_result(retVal, pciev0_write_gen2_reg (baseCfgEpRegs, writeRegs->gen2));
931 }
932
933 return retVal;
934} /* Pciev0_writeRegs */
935
936
937/*********************************************************************
938 * FUNCTION PURPOSE: Configures the Outbound Offset registers
939 * for outbound address translation
940 ********************************************************************/
941pcieRet_e Pciev0_cfgObOffset
942(
943 Pcie_Handle handle, /**< [in] The PCIE LLD instance identifier */
944 uint32_t obAddrLo, /**< [in] Low Outbound address offset (32bits) */
945 uint32_t obAddrHi, /**< [in] High Outbound address offset (32bits) */
946 uint8_t region /**< [in] Identifies the Outbound region (0-31) */
947)
948{
949
950 CSL_Pciess_appRegs *baseAppRegs = (CSL_Pciess_appRegs *)handle;
951 pcieRet_e retVal = pcie_RET_OK;
952 pcieObOffsetLoReg_t obOffsetLo;
953 pcieObOffsetHiReg_t obOffsetHi;
954 uint16_t obAddrLoField;
955
956 if (! pcieLObjIsValid) {
957 return pcie_RET_NO_INIT;
958 }
959
960 pcie_check_handle(handle);
961
962 memset (&obOffsetLo, 0, sizeof(obOffsetLo));
963 memset (&obOffsetHi, 0, sizeof(obOffsetHi));
964
965 pcie_getbits(obAddrLo, CSL_PCIESS_APP_OB_OFFSET_INDEX_OB_OFFSET_LO, obAddrLoField);
966
967 obOffsetLo.enable = 1;
968 obOffsetLo.offsetLo = obAddrLoField;
969
970 obOffsetHi.offsetHi = obAddrHi;
971
972 pcie_check_result(retVal, pciev0_write_obOffsetLo_reg(baseAppRegs, &obOffsetLo, region));
973 pcie_check_result(retVal, pciev0_write_obOffsetHi_reg(baseAppRegs, &obOffsetHi, region));
974
975 return retVal;
976} /* Pciev0_cfgObOffset */
977
978
979/*********************************************************************
980 * FUNCTION PURPOSE: Configures the Inbound Translation registers
981 ********************************************************************/
982pcieRet_e Pciev0_cfgIbTrans
983(
984 Pcie_Handle handle, /**< [in] The PCIE LLD instance identifier */
985 pcieIbTransCfg_t *ibCfg /**< [in] Inbound Translation Configuration parameters */
986)
987{
988
989 CSL_Pciess_appRegs *baseAppRegs = (CSL_Pciess_appRegs *)handle;
990 pcieRet_e retVal = pcie_RET_OK;
991
992 pcieIbBarReg_t ibBar;
993 pcieIbStartLoReg_t ibStartLo;
994 pcieIbStartHiReg_t ibStartHi;
995 pcieIbOffsetReg_t ibOffset;
996
997 uint32_t ibStartLoField;
998 uint32_t ibOffsetField;
999
1000 if (! pcieLObjIsValid) {
1001 return pcie_RET_NO_INIT;
1002 }
1003
1004 pcie_check_handle(handle);
1005
1006 memset (&ibBar, 0, sizeof(ibBar));
1007 memset (&ibStartLo, 0, sizeof(ibStartLo));
1008 memset (&ibStartHi, 0, sizeof(ibStartHi));
1009 memset (&ibOffset, 0, sizeof(ibOffset));
1010
1011 ibBar.ibBar = ibCfg->ibBar;
1012
1013 pcie_getbits(ibCfg->ibStartAddrLo, CSL_PCIESS_APP_IB_START_LO_IB_START_LO, ibStartLoField);
1014 ibStartLo.ibStartLo = ibStartLoField;
1015
1016 ibStartHi.ibStartHi = ibCfg->ibStartAddrHi;
1017
1018 pcie_getbits(ibCfg->ibOffsetAddr, CSL_PCIESS_APP_IB_OFFSET_IB_OFFSET, ibOffsetField);
1019 ibOffset.ibOffset = ibOffsetField;
1020
1021
1022 pcie_check_result(retVal, pciev0_write_ibBar_reg (baseAppRegs, &ibBar, ibCfg->region));
1023 pcie_check_result(retVal, pciev0_write_ibStartLo_reg(baseAppRegs, &ibStartLo, ibCfg->region));
1024 pcie_check_result(retVal, pciev0_write_ibStartHi_reg(baseAppRegs, &ibStartHi, ibCfg->region));
1025 pcie_check_result(retVal, pciev0_write_ibOffset_reg (baseAppRegs, &ibOffset, ibCfg->region));
1026
1027 return retVal;
1028} /* Pciev0_cfgIbTrans */
1029
1030
1031/*********************************************************************
1032 * FUNCTION PURPOSE: Configures a BAR Register (32bits)
1033 ********************************************************************/
1034pcieRet_e Pciev0_cfgBar
1035(
1036 Pcie_Handle handle, /**< [in] The PCIE LLD instance identifier */
1037 pcieBarCfg_t *barCfg /**< [in] BAR configuration parameters */
1038)
1039{
1040 pcieType0BarIdx_t type0BarIdx;
1041 pcieType1BarIdx_t type1BarIdx;
1042 pcieRegisters_t setRegs;
1043 uint32_t barAddrField = 0;
1044 pcieRet_e retVal = pcie_RET_OK;
1045
1046 if (! pcieLObjIsValid) {
1047 return pcie_RET_NO_INIT;
1048 }
1049
1050 pcie_check_handle(handle);
1051
1052 memset (&setRegs, 0, sizeof(setRegs));
1053 memset (&type0BarIdx, 0, sizeof(type0BarIdx));
1054 memset (&type1BarIdx, 0, sizeof(type1BarIdx));
1055
1056 if(barCfg->mode == pcie_RC_MODE)
1057 {
1058 pcie_getbits(barCfg->base, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BAR_BASE_ADDRESS, barAddrField);
1059
1060 type1BarIdx.reg.base = barAddrField;
1061 type1BarIdx.reg.prefetch = barCfg->prefetch;
1062 type1BarIdx.reg.type = barCfg->type;
1063 type1BarIdx.reg.memSpace = barCfg->memSpace;
1064 type1BarIdx.idx = barCfg->idx;
1065
1066 setRegs.type1BarIdx = &type1BarIdx;
1067 }
1068 else
1069 {
1070 pcie_getbits(barCfg->base, CSL_PCIE_CFG_SPACE_ENDPOINT_BAR_BASE_ADDRESS, barAddrField);
1071
1072 type0BarIdx.reg.base = barAddrField;
1073 type0BarIdx.reg.prefetch = barCfg->prefetch;
1074 type0BarIdx.reg.type = barCfg->type;
1075 type0BarIdx.reg.memSpace = barCfg->memSpace;
1076 type0BarIdx.idx = barCfg->idx;
1077
1078 setRegs.type0BarIdx = &type0BarIdx;
1079 }
1080
1081 if ((retVal = Pcie_writeRegs (handle, barCfg->location, &setRegs)) != pcie_RET_OK)
1082 {
1083 return retVal;
1084 }
1085
1086 return retVal;
1087} /* Pciev0_cfgBar */
1088
1089/* Nothing past this point */
1090
diff --git a/src/pcieapp.c b/src/v0/pciev0_app.c
index fcbb006..3980b68 100755..100644
--- a/src/pcieapp.c
+++ b/src/v0/pciev0_app.c
@@ -1,6 +1,6 @@
1/* 1/*
2 * 2 *
3 * Copyright (C) 2010-2013 Texas Instruments Incorporated - http://www.ti.com/ 3 * Copyright (C) 2010-2015 Texas Instruments Incorporated - http://www.ti.com/
4 * 4 *
5 * 5 *
6 * Redistribution and use in source and binary forms, with or without 6 * Redistribution and use in source and binary forms, with or without
@@ -41,8 +41,9 @@
41 */ 41 */
42 42
43 43
44#include "pcie.h" 44#include <ti/drv/pcie/pcie.h>
45#include "pcieloc.h" 45#include <ti/drv/pcie/src/pcieloc.h>
46#include <ti/drv/pcie/src/v0/pcieloc.h>
46#include <ti/csl/cslr_pcie_cfg_space_endpoint.h> 47#include <ti/csl/cslr_pcie_cfg_space_endpoint.h>
47#include <ti/csl/cslr_pcie_cfg_space_rootcomplex.h> 48#include <ti/csl/cslr_pcie_cfg_space_rootcomplex.h>
48#include <ti/csl/cslr_pciess_app.h> 49#include <ti/csl/cslr_pciess_app.h>
@@ -54,7 +55,7 @@
54/***************************************************************************** 55/*****************************************************************************
55 * Read and split up the Peripheral Version and ID register 56 * Read and split up the Peripheral Version and ID register
56 ****************************************************************************/ 57 ****************************************************************************/
57pcieRet_e pcie_read_pid_reg 58pcieRet_e pciev0_read_pid_reg
58( 59(
59 CSL_Pciess_appRegs *baseAddr, 60 CSL_Pciess_appRegs *baseAddr,
60 pciePidReg_t *reg 61 pciePidReg_t *reg
@@ -70,12 +71,12 @@ pcieRet_e pcie_read_pid_reg
70 pcie_getbits(val, CSL_PCIESS_APP_PID_MINOR, reg->revMin); 71 pcie_getbits(val, CSL_PCIESS_APP_PID_MINOR, reg->revMin);
71 72
72 return pcie_RET_OK; 73 return pcie_RET_OK;
73} /* pcie_read_pid_reg */ 74} /* pciev0_read_pid_reg */
74 75
75/***************************************************************************** 76/*****************************************************************************
76 * Read and split up the Command Status register 77 * Read and split up the Command Status register
77 ****************************************************************************/ 78 ****************************************************************************/
78pcieRet_e pcie_read_cmdStatus_reg 79pcieRet_e pciev0_read_cmdStatus_reg
79( 80(
80 CSL_Pciess_appRegs *baseAddr, 81 CSL_Pciess_appRegs *baseAddr,
81 pcieCmdStatusReg_t *reg 82 pcieCmdStatusReg_t *reg
@@ -91,12 +92,12 @@ pcieRet_e pcie_read_cmdStatus_reg
91 pcie_getbits(val, CSL_PCIESS_APP_CMD_STATUS_LTSSM_EN, reg->ltssmEn); 92 pcie_getbits(val, CSL_PCIESS_APP_CMD_STATUS_LTSSM_EN, reg->ltssmEn);
92 93
93 return pcie_RET_OK; 94 return pcie_RET_OK;
94} /* pcie_read_cmdStatus_reg */ 95} /* pciev0_read_cmdStatus_reg */
95 96
96/***************************************************************************** 97/*****************************************************************************
97 * Combine and write the Command Status register 98 * Combine and write the Command Status register
98 ****************************************************************************/ 99 ****************************************************************************/
99pcieRet_e pcie_write_cmdStatus_reg 100pcieRet_e pciev0_write_cmdStatus_reg
100( 101(
101 CSL_Pciess_appRegs *baseAddr, 102 CSL_Pciess_appRegs *baseAddr,
102 pcieCmdStatusReg_t *reg 103 pcieCmdStatusReg_t *reg
@@ -114,13 +115,13 @@ pcieRet_e pcie_write_cmdStatus_reg
114 115
115 baseAddr->CMD_STATUS = reg->raw = new_val; 116 baseAddr->CMD_STATUS = reg->raw = new_val;
116 return pcie_range_check_return; 117 return pcie_range_check_return;
117} /* pcie_write_cmdStatus_reg */ 118} /* pciev0_write_cmdStatus_reg */
118 119
119 120
120/***************************************************************************** 121/*****************************************************************************
121 * Read and split up the Configuration Transaction Setup register 122 * Read and split up the Configuration Transaction Setup register
122 ****************************************************************************/ 123 ****************************************************************************/
123pcieRet_e pcie_read_cfgTrans_reg 124pcieRet_e pciev0_read_cfgTrans_reg
124( 125(
125 CSL_Pciess_appRegs *baseAddr, 126 CSL_Pciess_appRegs *baseAddr,
126 pcieCfgTransReg_t *reg 127 pcieCfgTransReg_t *reg
@@ -134,12 +135,12 @@ pcieRet_e pcie_read_cfgTrans_reg
134 pcie_getbits(val, CSL_PCIESS_APP_CFG_SETUP_CFG_FUNC, reg->func); 135 pcie_getbits(val, CSL_PCIESS_APP_CFG_SETUP_CFG_FUNC, reg->func);
135 136
136 return pcie_RET_OK; 137 return pcie_RET_OK;
137} /* pcie_read_cfgTrans_reg */ 138} /* pciev0_read_cfgTrans_reg */
138 139
139/***************************************************************************** 140/*****************************************************************************
140 * Combine and write the Configuration Transaction Setup register 141 * Combine and write the Configuration Transaction Setup register
141 ****************************************************************************/ 142 ****************************************************************************/
142pcieRet_e pcie_write_cfgTrans_reg 143pcieRet_e pciev0_write_cfgTrans_reg
143( 144(
144 CSL_Pciess_appRegs *baseAddr, 145 CSL_Pciess_appRegs *baseAddr,
145 pcieCfgTransReg_t *reg 146 pcieCfgTransReg_t *reg
@@ -155,13 +156,13 @@ pcieRet_e pcie_write_cfgTrans_reg
155 156
156 baseAddr->CFG_SETUP = reg->raw = new_val; 157 baseAddr->CFG_SETUP = reg->raw = new_val;
157 return pcie_range_check_return; 158 return pcie_range_check_return;
158} /* pcie_write_cfgTrans_reg */ 159} /* pciev0_write_cfgTrans_reg */
159 160
160 161
161/***************************************************************************** 162/*****************************************************************************
162 * Read and split up the IO TLP Base register 163 * Read and split up the IO TLP Base register
163 ****************************************************************************/ 164 ****************************************************************************/
164pcieRet_e pcie_read_ioBase_reg 165pcieRet_e pciev0_read_ioBase_reg
165( 166(
166 CSL_Pciess_appRegs *baseAddr, 167 CSL_Pciess_appRegs *baseAddr,
167 pcieIoBaseReg_t *reg 168 pcieIoBaseReg_t *reg
@@ -172,12 +173,12 @@ pcieRet_e pcie_read_ioBase_reg
172 pcie_getbits(val, CSL_PCIESS_APP_IOBASE_IOBASE, reg->ioBase); 173 pcie_getbits(val, CSL_PCIESS_APP_IOBASE_IOBASE, reg->ioBase);
173 174
174 return pcie_RET_OK; 175 return pcie_RET_OK;
175} /* pcie_read_ioBase_reg */ 176} /* pciev0_read_ioBase_reg */
176 177
177/***************************************************************************** 178/*****************************************************************************
178 * Combine and write the IO TLP Base register 179 * Combine and write the IO TLP Base register
179 ****************************************************************************/ 180 ****************************************************************************/
180pcieRet_e pcie_write_ioBase_reg 181pcieRet_e pciev0_write_ioBase_reg
181( 182(
182 CSL_Pciess_appRegs *baseAddr, 183 CSL_Pciess_appRegs *baseAddr,
183 pcieIoBaseReg_t *reg 184 pcieIoBaseReg_t *reg
@@ -190,13 +191,13 @@ pcieRet_e pcie_write_ioBase_reg
190 191
191 baseAddr->IOBASE = reg->raw = new_val; 192 baseAddr->IOBASE = reg->raw = new_val;
192 return pcie_range_check_return; 193 return pcie_range_check_return;
193} /* pcie_write_ioBase_reg */ 194} /* pciev0_write_ioBase_reg */
194 195
195 196
196/***************************************************************************** 197/*****************************************************************************
197 * Read and split up the TLP Attribute Configuration register 198 * Read and split up the TLP Attribute Configuration register
198 ****************************************************************************/ 199 ****************************************************************************/
199pcieRet_e pcie_read_tlpCfg_reg 200pcieRet_e pciev0_read_tlpCfg_reg
200( 201(
201 CSL_Pciess_appRegs *baseAddr, 202 CSL_Pciess_appRegs *baseAddr,
202 pcieTlpCfgReg_t *reg 203 pcieTlpCfgReg_t *reg
@@ -208,12 +209,12 @@ pcieRet_e pcie_read_tlpCfg_reg
208 pcie_getbits(val, CSL_PCIESS_APP_TLPCFG_NO_SNOOP, reg->noSnoop); 209 pcie_getbits(val, CSL_PCIESS_APP_TLPCFG_NO_SNOOP, reg->noSnoop);
209 210
210 return pcie_RET_OK; 211 return pcie_RET_OK;
211} /* pcie_read_tlpCfg_reg */ 212} /* pciev0_read_tlpCfg_reg */
212 213
213/***************************************************************************** 214/*****************************************************************************
214 * Combine and write the TLP Attribute Configuration register 215 * Combine and write the TLP Attribute Configuration register
215 ****************************************************************************/ 216 ****************************************************************************/
216pcieRet_e pcie_write_tlpCfg_reg 217pcieRet_e pciev0_write_tlpCfg_reg
217( 218(
218 CSL_Pciess_appRegs *baseAddr, 219 CSL_Pciess_appRegs *baseAddr,
219 pcieTlpCfgReg_t *reg 220 pcieTlpCfgReg_t *reg
@@ -227,13 +228,13 @@ pcieRet_e pcie_write_tlpCfg_reg
227 228
228 baseAddr->TLPCFG = reg->raw = new_val; 229 baseAddr->TLPCFG = reg->raw = new_val;
229 return pcie_range_check_return; 230 return pcie_range_check_return;
230} /* pcie_write_tlpCfg_reg */ 231} /* pciev0_write_tlpCfg_reg */
231 232
232 233
233/***************************************************************************** 234/*****************************************************************************
234 * Read and split up the Reset Command register 235 * Read and split up the Reset Command register
235 ****************************************************************************/ 236 ****************************************************************************/
236pcieRet_e pcie_read_rstCmd_reg 237pcieRet_e pciev0_read_rstCmd_reg
237( 238(
238 CSL_Pciess_appRegs *baseAddr, 239 CSL_Pciess_appRegs *baseAddr,
239 pcieRstCmdReg_t *reg 240 pcieRstCmdReg_t *reg
@@ -245,12 +246,12 @@ pcieRet_e pcie_read_rstCmd_reg
245 pcie_getbits(val, CSL_PCIESS_APP_RSTCMD_INIT_RST, reg->initRst); 246 pcie_getbits(val, CSL_PCIESS_APP_RSTCMD_INIT_RST, reg->initRst);
246 247
247 return pcie_RET_OK; 248 return pcie_RET_OK;
248} /* pcie_read_rstCmd_reg */ 249} /* pciev0_read_rstCmd_reg */
249 250
250/***************************************************************************** 251/*****************************************************************************
251 * Combine and write the Reset Command register 252 * Combine and write the Reset Command register
252 ****************************************************************************/ 253 ****************************************************************************/
253pcieRet_e pcie_write_rstCmd_reg 254pcieRet_e pciev0_write_rstCmd_reg
254( 255(
255 CSL_Pciess_appRegs *baseAddr, 256 CSL_Pciess_appRegs *baseAddr,
256 pcieRstCmdReg_t *reg 257 pcieRstCmdReg_t *reg
@@ -264,13 +265,13 @@ pcieRet_e pcie_write_rstCmd_reg
264 265
265 baseAddr->RSTCMD = reg->raw = new_val; 266 baseAddr->RSTCMD = reg->raw = new_val;
266 return pcie_range_check_return; 267 return pcie_range_check_return;
267} /* pcie_write_rstCmd_reg */ 268} /* pciev0_write_rstCmd_reg */
268 269
269 270
270/***************************************************************************** 271/*****************************************************************************
271 * Read and split up the Power Management Command register 272 * Read and split up the Power Management Command register
272 ****************************************************************************/ 273 ****************************************************************************/
273pcieRet_e pcie_read_pmCmd_reg 274pcieRet_e pciev0_read_pmCmd_reg
274( 275(
275 CSL_Pciess_appRegs *baseAddr, 276 CSL_Pciess_appRegs *baseAddr,
276 pciePmCmdReg_t *reg 277 pciePmCmdReg_t *reg
@@ -282,12 +283,12 @@ pcieRet_e pcie_read_pmCmd_reg
282 pcie_getbits(val, CSL_PCIESS_APP_PMCMD_PM_XMT_PME, reg->pme); 283 pcie_getbits(val, CSL_PCIESS_APP_PMCMD_PM_XMT_PME, reg->pme);
283 284
284 return pcie_RET_OK; 285 return pcie_RET_OK;
285} /* pcie_read_pmCmd_reg */ 286} /* pciev0_read_pmCmd_reg */
286 287
287/***************************************************************************** 288/*****************************************************************************
288 * Combine and write the Power Management Command register 289 * Combine and write the Power Management Command register
289 ****************************************************************************/ 290 ****************************************************************************/
290pcieRet_e pcie_write_pmCmd_reg 291pcieRet_e pciev0_write_pmCmd_reg
291( 292(
292 CSL_Pciess_appRegs *baseAddr, 293 CSL_Pciess_appRegs *baseAddr,
293 pciePmCmdReg_t *reg 294 pciePmCmdReg_t *reg
@@ -301,12 +302,12 @@ pcieRet_e pcie_write_pmCmd_reg
301 302
302 baseAddr->PMCMD = reg->raw = new_val; 303 baseAddr->PMCMD = reg->raw = new_val;
303 return pcie_range_check_return; 304 return pcie_range_check_return;
304} /* pcie_write_pmCmd_reg */ 305} /* pciev0_write_pmCmd_reg */
305 306
306/***************************************************************************** 307/*****************************************************************************
307 * Read and split up the Power Mangement Configuration register 308 * Read and split up the Power Mangement Configuration register
308 ****************************************************************************/ 309 ****************************************************************************/
309pcieRet_e pcie_read_pmCfg_reg 310pcieRet_e pciev0_read_pmCfg_reg
310( 311(
311 CSL_Pciess_appRegs *baseAddr, 312 CSL_Pciess_appRegs *baseAddr,
312 pciePmCfgReg_t *reg 313 pciePmCfgReg_t *reg
@@ -317,12 +318,12 @@ pcieRet_e pcie_read_pmCfg_reg
317 pcie_getbits(val, CSL_PCIESS_APP_PMCFG_ENTR_L23, reg->entrL23); 318 pcie_getbits(val, CSL_PCIESS_APP_PMCFG_ENTR_L23, reg->entrL23);
318 319
319 return pcie_RET_OK; 320 return pcie_RET_OK;
320} /* pcie_read_pmCfg_reg */ 321} /* pciev0_read_pmCfg_reg */
321 322
322/***************************************************************************** 323/*****************************************************************************
323 * Combine and write the Power Mangement Configuration register 324 * Combine and write the Power Mangement Configuration register
324 ****************************************************************************/ 325 ****************************************************************************/
325pcieRet_e pcie_write_pmCfg_reg 326pcieRet_e pciev0_write_pmCfg_reg
326( 327(
327 CSL_Pciess_appRegs *baseAddr, 328 CSL_Pciess_appRegs *baseAddr,
328 pciePmCfgReg_t *reg 329 pciePmCfgReg_t *reg
@@ -335,12 +336,12 @@ pcieRet_e pcie_write_pmCfg_reg
335 336
336 baseAddr->PMCFG = reg->raw = new_val; 337 baseAddr->PMCFG = reg->raw = new_val;
337 return pcie_range_check_return; 338 return pcie_range_check_return;
338} /* pcie_write_pmCfg_reg */ 339} /* pciev0_write_pmCfg_reg */
339 340
340/***************************************************************************** 341/*****************************************************************************
341 * Read and split up the Activity Status register 342 * Read and split up the Activity Status register
342 ****************************************************************************/ 343 ****************************************************************************/
343pcieRet_e pcie_read_actStatus_reg 344pcieRet_e pciev0_read_actStatus_reg
344( 345(
345 CSL_Pciess_appRegs *baseAddr, 346 CSL_Pciess_appRegs *baseAddr,
346 pcieActStatusReg_t *reg 347 pcieActStatusReg_t *reg
@@ -352,12 +353,12 @@ pcieRet_e pcie_read_actStatus_reg
352 pcie_getbits(val, CSL_PCIESS_APP_ACT_STATUS_IB_NOT_EMPTY, reg->ibNotEmpty); 353 pcie_getbits(val, CSL_PCIESS_APP_ACT_STATUS_IB_NOT_EMPTY, reg->ibNotEmpty);
353 354
354 return pcie_RET_OK; 355 return pcie_RET_OK;
355} /* pcie_read_actStatus_reg */ 356} /* pciev0_read_actStatus_reg */
356 357
357/***************************************************************************** 358/*****************************************************************************
358 * Read and split up the Outbound Size register 359 * Read and split up the Outbound Size register
359 ****************************************************************************/ 360 ****************************************************************************/
360pcieRet_e pcie_read_obSize_reg 361pcieRet_e pciev0_read_obSize_reg
361( 362(
362 CSL_Pciess_appRegs *baseAddr, 363 CSL_Pciess_appRegs *baseAddr,
363 pcieObSizeReg_t *reg 364 pcieObSizeReg_t *reg
@@ -368,13 +369,13 @@ pcieRet_e pcie_read_obSize_reg
368 pcie_getbits(val, CSL_PCIESS_APP_OB_SIZE_OB_SIZE, reg->size); 369 pcie_getbits(val, CSL_PCIESS_APP_OB_SIZE_OB_SIZE, reg->size);
369 370
370 return pcie_RET_OK; 371 return pcie_RET_OK;
371} /* pcie_read_obSize_reg */ 372} /* pciev0_read_obSize_reg */
372 373
373 374
374/***************************************************************************** 375/*****************************************************************************
375 * Combine and write the Outbound Size register 376 * Combine and write the Outbound Size register
376 ****************************************************************************/ 377 ****************************************************************************/
377pcieRet_e pcie_write_obSize_reg 378pcieRet_e pciev0_write_obSize_reg
378( 379(
379 CSL_Pciess_appRegs *baseAddr, 380 CSL_Pciess_appRegs *baseAddr,
380 pcieObSizeReg_t *reg 381 pcieObSizeReg_t *reg
@@ -387,12 +388,12 @@ pcieRet_e pcie_write_obSize_reg
387 388
388 baseAddr->OB_SIZE = reg->raw = new_val; 389 baseAddr->OB_SIZE = reg->raw = new_val;
389 return pcie_range_check_return; 390 return pcie_range_check_return;
390} /* pcie_write_obSize_reg */ 391} /* pciev0_write_obSize_reg */
391 392
392/***************************************************************************** 393/*****************************************************************************
393 * Read and split up the Diagnostic Control register 394 * Read and split up the Diagnostic Control register
394 ****************************************************************************/ 395 ****************************************************************************/
395pcieRet_e pcie_read_diagCtrl_reg 396pcieRet_e pciev0_read_diagCtrl_reg
396( 397(
397 CSL_Pciess_appRegs *baseAddr, 398 CSL_Pciess_appRegs *baseAddr,
398 pcieDiagCtrlReg_t *reg 399 pcieDiagCtrlReg_t *reg
@@ -404,13 +405,13 @@ pcieRet_e pcie_read_diagCtrl_reg
404 pcie_getbits(val, CSL_PCIESS_APP_DIAG_CTRL_INV_LCRC, reg->invLcrc); 405 pcie_getbits(val, CSL_PCIESS_APP_DIAG_CTRL_INV_LCRC, reg->invLcrc);
405 406
406 return pcie_RET_OK; 407 return pcie_RET_OK;
407} /*pcie_read_diagCtrl_reg*/ 408} /* pciev0_read_diagCtrl_reg */
408 409
409 410
410/***************************************************************************** 411/*****************************************************************************
411 * Combine and write the Diagnostic Control register 412 * Combine and write the Diagnostic Control register
412 ****************************************************************************/ 413 ****************************************************************************/
413pcieRet_e pcie_write_diagCtrl_reg 414pcieRet_e pciev0_write_diagCtrl_reg
414( 415(
415 CSL_Pciess_appRegs *baseAddr, 416 CSL_Pciess_appRegs *baseAddr,
416 pcieDiagCtrlReg_t *reg 417 pcieDiagCtrlReg_t *reg
@@ -425,12 +426,12 @@ pcieRet_e pcie_write_diagCtrl_reg
425 baseAddr->DIAG_CTRL = reg->raw = new_val; 426 baseAddr->DIAG_CTRL = reg->raw = new_val;
426 427
427 return pcie_range_check_return; 428 return pcie_range_check_return;
428} /*pcie_write_diagCtrl_reg*/ 429} /* pciev0_write_diagCtrl_reg */
429 430
430/***************************************************************************** 431/*****************************************************************************
431 * Read and split up the Endian Mode register 432 * Read and split up the Endian Mode register
432 ****************************************************************************/ 433 ****************************************************************************/
433pcieRet_e pcie_read_endian_reg 434pcieRet_e pciev0_read_endian_reg
434( 435(
435 CSL_Pciess_appRegs *baseAddr, 436 CSL_Pciess_appRegs *baseAddr,
436 pcieEndianReg_t *reg 437 pcieEndianReg_t *reg
@@ -441,13 +442,13 @@ pcieRet_e pcie_read_endian_reg
441 pcie_getbits(val, CSL_PCIESS_APP_ENDIAN_ENDIAN_MODE, reg->mode); 442 pcie_getbits(val, CSL_PCIESS_APP_ENDIAN_ENDIAN_MODE, reg->mode);
442 443
443 return pcie_RET_OK; 444 return pcie_RET_OK;
444} /*pcie_read_endian_reg*/ 445} /* pciev0_read_endian_reg */
445 446
446 447
447/***************************************************************************** 448/*****************************************************************************
448 * Combine and write the Endian Mode register 449 * Combine and write the Endian Mode register
449 ****************************************************************************/ 450 ****************************************************************************/
450pcieRet_e pcie_write_endian_reg 451pcieRet_e pciev0_write_endian_reg
451( 452(
452 CSL_Pciess_appRegs *baseAddr, 453 CSL_Pciess_appRegs *baseAddr,
453 pcieEndianReg_t *reg 454 pcieEndianReg_t *reg
@@ -461,12 +462,12 @@ pcieRet_e pcie_write_endian_reg
461 baseAddr->ENDIAN = reg->raw = new_val; 462 baseAddr->ENDIAN = reg->raw = new_val;
462 463
463 return pcie_range_check_return; 464 return pcie_range_check_return;
464} /*pcie_write_endian_reg*/ 465} /* pciev0_write_endian_reg */
465 466
466/***************************************************************************** 467/*****************************************************************************
467 * Read and split up the transaction priority register 468 * Read and split up the transaction priority register
468 ****************************************************************************/ 469 ****************************************************************************/
469pcieRet_e pcie_read_priority_reg 470pcieRet_e pciev0_read_priority_reg
470( 471(
471 CSL_Pciess_appRegs *baseAddr, 472 CSL_Pciess_appRegs *baseAddr,
472 pciePriorityReg_t *reg 473 pciePriorityReg_t *reg
@@ -479,12 +480,12 @@ pcieRet_e pcie_read_priority_reg
479 pcie_getbits(val, CSL_PCIESS_APP_PRIORITY_MST_PRIORITY, reg->mstPriority); 480 pcie_getbits(val, CSL_PCIESS_APP_PRIORITY_MST_PRIORITY, reg->mstPriority);
480 481
481 return pcie_RET_OK; 482 return pcie_RET_OK;
482} /*pcie_read_priority_reg*/ 483} /* pciev0_read_priority_reg */
483 484
484/***************************************************************************** 485/*****************************************************************************
485 * Combine and write the transaction priority register 486 * Combine and write the transaction priority register
486 ****************************************************************************/ 487 ****************************************************************************/
487pcieRet_e pcie_write_priority_reg 488pcieRet_e pciev0_write_priority_reg
488( 489(
489 CSL_Pciess_appRegs *baseAddr, 490 CSL_Pciess_appRegs *baseAddr,
490 pciePriorityReg_t *reg 491 pciePriorityReg_t *reg
@@ -500,12 +501,12 @@ pcieRet_e pcie_write_priority_reg
500 baseAddr->PRIORITY = reg->raw = new_val; 501 baseAddr->PRIORITY = reg->raw = new_val;
501 502
502 return pcie_range_check_return; 503 return pcie_range_check_return;
503} /*pcie_write_priority_reg*/ 504} /* pciev0_write_priority_reg */
504 505
505/***************************************************************************** 506/*****************************************************************************
506 * Read and split up the End of Interrupt register 507 * Read and split up the End of Interrupt register
507 ****************************************************************************/ 508 ****************************************************************************/
508pcieRet_e pcie_read_irqEOI_reg 509pcieRet_e pciev0_read_irqEOI_reg
509( 510(
510 CSL_Pciess_appRegs *baseAddr, 511 CSL_Pciess_appRegs *baseAddr,
511 pcieIrqEOIReg_t *reg 512 pcieIrqEOIReg_t *reg
@@ -516,13 +517,13 @@ pcieRet_e pcie_read_irqEOI_reg
516 pcie_getbits(val, CSL_PCIESS_APP_IRQ_EOI_EOI, reg->EOI); 517 pcie_getbits(val, CSL_PCIESS_APP_IRQ_EOI_EOI, reg->EOI);
517 518
518 return pcie_RET_OK; 519 return pcie_RET_OK;
519} /*pcie_read_irqEOI_reg*/ 520} /* pciev0_read_irqEOI_reg */
520 521
521 522
522/***************************************************************************** 523/*****************************************************************************
523 * Combine and write the End of Interrupt register 524 * Combine and write the End of Interrupt register
524 ****************************************************************************/ 525 ****************************************************************************/
525pcieRet_e pcie_write_irqEOI_reg 526pcieRet_e pciev0_write_irqEOI_reg
526( 527(
527 CSL_Pciess_appRegs *baseAddr, 528 CSL_Pciess_appRegs *baseAddr,
528 pcieIrqEOIReg_t *reg 529 pcieIrqEOIReg_t *reg
@@ -536,12 +537,12 @@ pcieRet_e pcie_write_irqEOI_reg
536 baseAddr->IRQ_EOI = reg->raw = new_val; 537 baseAddr->IRQ_EOI = reg->raw = new_val;
537 538
538 return pcie_range_check_return; 539 return pcie_range_check_return;
539} /*pcie_write_irqEOI_reg*/ 540} /* pciev0_write_irqEOI_reg */
540 541
541/***************************************************************************** 542/*****************************************************************************
542 * Read and split up the MSI Interrupt IRQ register 543 * Read and split up the MSI Interrupt IRQ register
543 ****************************************************************************/ 544 ****************************************************************************/
544pcieRet_e pcie_read_msiIrq_reg 545pcieRet_e pciev0_read_msiIrq_reg
545( 546(
546 CSL_Pciess_appRegs *baseAddr, 547 CSL_Pciess_appRegs *baseAddr,
547 pcieMsiIrqReg_t *reg 548 pcieMsiIrqReg_t *reg
@@ -552,13 +553,13 @@ pcieRet_e pcie_read_msiIrq_reg
552 pcie_getbits(val, CSL_PCIESS_APP_MSI_IRQ_MSI_IRQ, reg->msiIrq); 553 pcie_getbits(val, CSL_PCIESS_APP_MSI_IRQ_MSI_IRQ, reg->msiIrq);
553 554
554 return pcie_RET_OK; 555 return pcie_RET_OK;
555} /*pcie_read_msiIrq_reg*/ 556} /* pciev0_read_msiIrq_reg */
556 557
557 558
558/***************************************************************************** 559/*****************************************************************************
559 * Combine and write the MSI Interrupt IRQ register 560 * Combine and write the MSI Interrupt IRQ register
560 ****************************************************************************/ 561 ****************************************************************************/
561pcieRet_e pcie_write_msiIrq_reg 562pcieRet_e pciev0_write_msiIrq_reg
562( 563(
563 CSL_Pciess_appRegs *baseAddr, 564 CSL_Pciess_appRegs *baseAddr,
564 pcieMsiIrqReg_t *reg 565 pcieMsiIrqReg_t *reg
@@ -572,12 +573,12 @@ pcieRet_e pcie_write_msiIrq_reg
572 baseAddr->MSI_IRQ = reg->raw = new_val; 573 baseAddr->MSI_IRQ = reg->raw = new_val;
573 574
574 return pcie_range_check_return; 575 return pcie_range_check_return;
575} /*pcie_write_msiIrq_reg*/ 576} /* pciev0_write_msiIrq_reg */
576 577
577/***************************************************************************** 578/*****************************************************************************
578 * Read and split up the Endpoint Interrupt Request Set register 579 * Read and split up the Endpoint Interrupt Request Set register
579 ****************************************************************************/ 580 ****************************************************************************/
580pcieRet_e pcie_read_epIrqSet_reg 581pcieRet_e pciev0_read_epIrqSet_reg
581( 582(
582 CSL_Pciess_appRegs *baseAddr, 583 CSL_Pciess_appRegs *baseAddr,
583 pcieEpIrqSetReg_t *reg 584 pcieEpIrqSetReg_t *reg
@@ -588,13 +589,13 @@ pcieRet_e pcie_read_epIrqSet_reg
588 pcie_getbits(val, CSL_PCIESS_APP_EP_IRQ_SET_EP_IRQ_SET, reg->epIrqSet); 589 pcie_getbits(val, CSL_PCIESS_APP_EP_IRQ_SET_EP_IRQ_SET, reg->epIrqSet);
589 590
590 return pcie_RET_OK; 591 return pcie_RET_OK;
591} /*pcie_read_epIrqSet_reg*/ 592} /* pciev0_read_epIrqSet_reg */
592 593
593 594
594/***************************************************************************** 595/*****************************************************************************
595 * Combine and write the Endpoint Interrupt Request Set register 596 * Combine and write the Endpoint Interrupt Request Set register
596 ****************************************************************************/ 597 ****************************************************************************/
597pcieRet_e pcie_write_epIrqSet_reg 598pcieRet_e pciev0_write_epIrqSet_reg
598( 599(
599 CSL_Pciess_appRegs *baseAddr, 600 CSL_Pciess_appRegs *baseAddr,
600 pcieEpIrqSetReg_t *reg 601 pcieEpIrqSetReg_t *reg
@@ -608,12 +609,12 @@ pcieRet_e pcie_write_epIrqSet_reg
608 baseAddr->EP_IRQ_SET = reg->raw = new_val; 609 baseAddr->EP_IRQ_SET = reg->raw = new_val;
609 610
610 return pcie_range_check_return; 611 return pcie_range_check_return;
611} /*pcie_write_epIrqSet_reg*/ 612} /* pciev0_write_epIrqSet_reg */
612 613
613/***************************************************************************** 614/*****************************************************************************
614 * Read and split up the Endpoint Interrupt Request Clear register 615 * Read and split up the Endpoint Interrupt Request Clear register
615 ****************************************************************************/ 616 ****************************************************************************/
616pcieRet_e pcie_read_epIrqClr_reg 617pcieRet_e pciev0_read_epIrqClr_reg
617( 618(
618 CSL_Pciess_appRegs *baseAddr, 619 CSL_Pciess_appRegs *baseAddr,
619 pcieEpIrqClrReg_t *reg 620 pcieEpIrqClrReg_t *reg
@@ -624,12 +625,12 @@ pcieRet_e pcie_read_epIrqClr_reg
624 pcie_getbits(val, CSL_PCIESS_APP_EP_IRQ_CLR_EP_IRQ_CLR, reg->epIrqClr); 625 pcie_getbits(val, CSL_PCIESS_APP_EP_IRQ_CLR_EP_IRQ_CLR, reg->epIrqClr);
625 626
626 return pcie_RET_OK; 627 return pcie_RET_OK;
627} /*pcie_read_epIrqClr_reg*/ 628} /* pciev0_read_epIrqClr_reg */
628 629
629/***************************************************************************** 630/*****************************************************************************
630 * Combine and write the Endpoint Interrupt Request Clear register 631 * Combine and write the Endpoint Interrupt Request Clear register
631 ****************************************************************************/ 632 ****************************************************************************/
632pcieRet_e pcie_write_epIrqClr_reg 633pcieRet_e pciev0_write_epIrqClr_reg
633( 634(
634 CSL_Pciess_appRegs *baseAddr, 635 CSL_Pciess_appRegs *baseAddr,
635 pcieEpIrqClrReg_t *reg 636 pcieEpIrqClrReg_t *reg
@@ -643,12 +644,12 @@ pcieRet_e pcie_write_epIrqClr_reg
643 baseAddr->EP_IRQ_CLR = reg->raw = new_val; 644 baseAddr->EP_IRQ_CLR = reg->raw = new_val;
644 645
645 return pcie_range_check_return; 646 return pcie_range_check_return;
646} /*pcie_write_epIrqClr_reg*/ 647} /* pciev0_write_epIrqClr_reg */
647 648
648/***************************************************************************** 649/*****************************************************************************
649 * Read and split up the Endpoint Interrupt Status register 650 * Read and split up the Endpoint Interrupt Status register
650 ****************************************************************************/ 651 ****************************************************************************/
651pcieRet_e pcie_read_epIrqStatus_reg 652pcieRet_e pciev0_read_epIrqStatus_reg
652( 653(
653 CSL_Pciess_appRegs *baseAddr, 654 CSL_Pciess_appRegs *baseAddr,
654 pcieEpIrqStatusReg_t *reg 655 pcieEpIrqStatusReg_t *reg
@@ -659,13 +660,13 @@ pcieRet_e pcie_read_epIrqStatus_reg
659 pcie_getbits(val, CSL_PCIESS_APP_EP_IRQ_STATUS_EP_IRQ_STATUS, reg->epIrqStatus); 660 pcie_getbits(val, CSL_PCIESS_APP_EP_IRQ_STATUS_EP_IRQ_STATUS, reg->epIrqStatus);
660 661
661 return pcie_RET_OK; 662 return pcie_RET_OK;
662} /*pcie_read_epIrqStatus_reg*/ 663} /* pciev0_read_epIrqStatus_reg */
663 664
664 665
665/***************************************************************************** 666/*****************************************************************************
666 * Combine and write the Endpoint Interrupt Status register 667 * Combine and write the Endpoint Interrupt Status register
667 ****************************************************************************/ 668 ****************************************************************************/
668pcieRet_e pcie_write_epIrqStatus_reg 669pcieRet_e pciev0_write_epIrqStatus_reg
669( 670(
670 CSL_Pciess_appRegs *baseAddr, 671 CSL_Pciess_appRegs *baseAddr,
671 pcieEpIrqStatusReg_t *reg 672 pcieEpIrqStatusReg_t *reg
@@ -679,28 +680,28 @@ pcieRet_e pcie_write_epIrqStatus_reg
679 baseAddr->EP_IRQ_STATUS = reg->raw = new_val; 680 baseAddr->EP_IRQ_STATUS = reg->raw = new_val;
680 681
681 return pcie_range_check_return; 682 return pcie_range_check_return;
682} /*pcie_write_epIrqStatus_reg*/ 683} /* pciev0_write_epIrqStatus_reg */
683 684
684/***************************************************************************** 685/*****************************************************************************
685 * Read and split up a General Purpose register [0-3] 686 * Read and split up a General Purpose register [0-3]
686 ****************************************************************************/ 687 ****************************************************************************/
687pcieRet_e pcie_read_genPurpose_reg 688pcieRet_e pciev0_read_genPurpose_reg
688( 689(
689 CSL_Pciess_appRegs *baseAddr, 690 CSL_Pciess_appRegs *baseAddr,
690 pcieGenPurposeReg_t *reg, 691 pcieGenPurposeReg_t *reg,
691 int regNum 692 int regNum
692) 693)
693{ 694{
694 uint32_t val = reg->raw = reg->genPurpose = baseAddr->GPR[regNum]; 695 reg->raw = reg->genPurpose = baseAddr->GPR[regNum];
695 696
696 return pcie_RET_OK; 697 return pcie_RET_OK;
697} /*pcie_read_epIrqStatus_reg*/ 698} /* pciev0_read_epIrqStatus_reg */
698 699
699 700
700/***************************************************************************** 701/*****************************************************************************
701 * Combine and write a General Purpose register [0-3] 702 * Combine and write a General Purpose register [0-3]
702 ****************************************************************************/ 703 ****************************************************************************/
703pcieRet_e pcie_write_genPurpose_reg 704pcieRet_e pciev0_write_genPurpose_reg
704( 705(
705 CSL_Pciess_appRegs *baseAddr, 706 CSL_Pciess_appRegs *baseAddr,
706 pcieGenPurposeReg_t *reg, 707 pcieGenPurposeReg_t *reg,
@@ -710,12 +711,12 @@ pcieRet_e pcie_write_genPurpose_reg
710 baseAddr->GPR[regNum] = reg->raw = reg->genPurpose; 711 baseAddr->GPR[regNum] = reg->raw = reg->genPurpose;
711 712
712 return pcie_RET_OK; 713 return pcie_RET_OK;
713} /*pcie_write_epIrqStatus_reg*/ 714} /* pciev0_write_epIrqStatus_reg */
714 715
715/***************************************************************************** 716/*****************************************************************************
716 * Read and split up a MSI Raw Interrupt Status register 717 * Read and split up a MSI Raw Interrupt Status register
717 ****************************************************************************/ 718 ****************************************************************************/
718pcieRet_e pcie_read_msiIrqStatusRaw_reg 719pcieRet_e pciev0_read_msiIrqStatusRaw_reg
719( 720(
720 CSL_Pciess_appRegs *baseAddr, 721 CSL_Pciess_appRegs *baseAddr,
721 pcieMsiIrqStatusRawReg_t *reg, 722 pcieMsiIrqStatusRawReg_t *reg,
@@ -727,13 +728,13 @@ pcieRet_e pcie_read_msiIrqStatusRaw_reg
727 pcie_getbits(val, CSL_PCIESS_APP_MSI_IRQ_STATUS_RAW_MSI_RAW_STATUS, reg->msiRawStatus); 728 pcie_getbits(val, CSL_PCIESS_APP_MSI_IRQ_STATUS_RAW_MSI_RAW_STATUS, reg->msiRawStatus);
728 729
729 return pcie_RET_OK; 730 return pcie_RET_OK;
730} /*pcie_read_msiIrqStatusRaw_reg*/ 731} /* pciev0_read_msiIrqStatusRaw_reg */
731 732
732 733
733/***************************************************************************** 734/*****************************************************************************
734 * Combine and write a MSI Raw Interrupt Status register 735 * Combine and write a MSI Raw Interrupt Status register
735 ****************************************************************************/ 736 ****************************************************************************/
736pcieRet_e pcie_write_msiIrqStatusRaw_reg 737pcieRet_e pciev0_write_msiIrqStatusRaw_reg
737( 738(
738 CSL_Pciess_appRegs *baseAddr, 739 CSL_Pciess_appRegs *baseAddr,
739 pcieMsiIrqStatusRawReg_t *reg, 740 pcieMsiIrqStatusRawReg_t *reg,
@@ -748,12 +749,12 @@ pcieRet_e pcie_write_msiIrqStatusRaw_reg
748 baseAddr->MSIX_IRQ[regNum].MSI_IRQ_STATUS_RAW = reg->raw = new_val; 749 baseAddr->MSIX_IRQ[regNum].MSI_IRQ_STATUS_RAW = reg->raw = new_val;
749 750
750 return pcie_range_check_return; 751 return pcie_range_check_return;
751} /*pcie_write_msiIrqStatusRaw_reg*/ 752} /* pciev0_write_msiIrqStatusRaw_reg */
752 753
753/***************************************************************************** 754/*****************************************************************************
754 * Read and split up a MSI Interrupt Status register 755 * Read and split up a MSI Interrupt Status register
755 ****************************************************************************/ 756 ****************************************************************************/
756pcieRet_e pcie_read_msiIrqStatus_reg 757pcieRet_e pciev0_read_msiIrqStatus_reg
757( 758(
758 CSL_Pciess_appRegs *baseAddr, 759 CSL_Pciess_appRegs *baseAddr,
759 pcieMsiIrqStatusReg_t *reg, 760 pcieMsiIrqStatusReg_t *reg,
@@ -765,13 +766,13 @@ pcieRet_e pcie_read_msiIrqStatus_reg
765 pcie_getbits(val, CSL_PCIESS_APP_MSI_IRQ_STATUS_MSI_IRQ_STATUS, reg->msiIrqStatus); 766 pcie_getbits(val, CSL_PCIESS_APP_MSI_IRQ_STATUS_MSI_IRQ_STATUS, reg->msiIrqStatus);
766 767
767 return pcie_RET_OK; 768 return pcie_RET_OK;
768} /*pcie_read_msiIrqStatus_reg*/ 769} /* pciev0_read_msiIrqStatus_reg */
769 770
770 771
771/***************************************************************************** 772/*****************************************************************************
772 * Combine and write a MSI Interrupt Status register 773 * Combine and write a MSI Interrupt Status register
773 ****************************************************************************/ 774 ****************************************************************************/
774pcieRet_e pcie_write_msiIrqStatus_reg 775pcieRet_e pciev0_write_msiIrqStatus_reg
775( 776(
776 CSL_Pciess_appRegs *baseAddr, 777 CSL_Pciess_appRegs *baseAddr,
777 pcieMsiIrqStatusReg_t *reg, 778 pcieMsiIrqStatusReg_t *reg,
@@ -786,12 +787,12 @@ pcieRet_e pcie_write_msiIrqStatus_reg
786 baseAddr->MSIX_IRQ[regNum].MSI_IRQ_STATUS = reg->raw = new_val; 787 baseAddr->MSIX_IRQ[regNum].MSI_IRQ_STATUS = reg->raw = new_val;
787 788
788 return pcie_range_check_return; 789 return pcie_range_check_return;
789} /*pcie_write_msiIrqStatus_reg*/ 790} /* pciev0_write_msiIrqStatus_reg */
790 791
791/***************************************************************************** 792/*****************************************************************************
792 * Read and split up a MSI Interrupt Enable Set register 793 * Read and split up a MSI Interrupt Enable Set register
793 ****************************************************************************/ 794 ****************************************************************************/
794pcieRet_e pcie_read_msiIrqEnableSet_reg 795pcieRet_e pciev0_read_msiIrqEnableSet_reg
795( 796(
796 CSL_Pciess_appRegs *baseAddr, 797 CSL_Pciess_appRegs *baseAddr,
797 pcieMsiIrqEnableSetReg_t *reg, 798 pcieMsiIrqEnableSetReg_t *reg,
@@ -803,13 +804,13 @@ pcieRet_e pcie_read_msiIrqEnableSet_reg
803 pcie_getbits(val, CSL_PCIESS_APP_MSI_IRQ_ENABLE_SET_MSI_IRQ_EN_SET, reg->msiIrqEnSet); 804 pcie_getbits(val, CSL_PCIESS_APP_MSI_IRQ_ENABLE_SET_MSI_IRQ_EN_SET, reg->msiIrqEnSet);
804 805
805 return pcie_RET_OK; 806 return pcie_RET_OK;
806} /*pcie_read_msiIrqEnableSet_reg*/ 807} /* pciev0_read_msiIrqEnableSet_reg */
807 808
808 809
809/***************************************************************************** 810/*****************************************************************************
810 * Combine and write a MSI Interrupt Enable Set register 811 * Combine and write a MSI Interrupt Enable Set register
811 ****************************************************************************/ 812 ****************************************************************************/
812pcieRet_e pcie_write_msiIrqEnableSet_reg 813pcieRet_e pciev0_write_msiIrqEnableSet_reg
813( 814(
814 CSL_Pciess_appRegs *baseAddr, 815 CSL_Pciess_appRegs *baseAddr,
815 pcieMsiIrqEnableSetReg_t *reg, 816 pcieMsiIrqEnableSetReg_t *reg,
@@ -824,12 +825,12 @@ pcieRet_e pcie_write_msiIrqEnableSet_reg
824 baseAddr->MSIX_IRQ[regNum].MSI_IRQ_ENABLE_SET = reg->raw = new_val; 825 baseAddr->MSIX_IRQ[regNum].MSI_IRQ_ENABLE_SET = reg->raw = new_val;
825 826
826 return pcie_range_check_return; 827 return pcie_range_check_return;
827} /*pcie_write_msiIrqEnableSet_reg*/ 828} /* pciev0_write_msiIrqEnableSet_reg */
828 829
829/***************************************************************************** 830/*****************************************************************************
830 * Read and split up the MSI Interrupt Enable Clear register 831 * Read and split up the MSI Interrupt Enable Clear register
831 ****************************************************************************/ 832 ****************************************************************************/
832pcieRet_e pcie_read_msiIrqEnableClr_reg 833pcieRet_e pciev0_read_msiIrqEnableClr_reg
833( 834(
834 CSL_Pciess_appRegs *baseAddr, 835 CSL_Pciess_appRegs *baseAddr,
835 pcieMsiIrqEnableClrReg_t *reg, 836 pcieMsiIrqEnableClrReg_t *reg,
@@ -841,13 +842,13 @@ pcieRet_e pcie_read_msiIrqEnableClr_reg
841 pcie_getbits(val, CSL_PCIESS_APP_MSI_IRQ_ENABLE_CLR_MSI_IRQ_EN_CLR, reg->msiIrqEnClr); 842 pcie_getbits(val, CSL_PCIESS_APP_MSI_IRQ_ENABLE_CLR_MSI_IRQ_EN_CLR, reg->msiIrqEnClr);
842 843
843 return pcie_RET_OK; 844 return pcie_RET_OK;
844} /*pcie_read_msiIrqEnableClr_reg*/ 845} /* pciev0_read_msiIrqEnableClr_reg */
845 846
846 847
847/***************************************************************************** 848/*****************************************************************************
848 * Combine and write the MSI Interrupt Enable Clear register 849 * Combine and write the MSI Interrupt Enable Clear register
849 ****************************************************************************/ 850 ****************************************************************************/
850pcieRet_e pcie_write_msiIrqEnableClr_reg 851pcieRet_e pciev0_write_msiIrqEnableClr_reg
851( 852(
852 CSL_Pciess_appRegs *baseAddr, 853 CSL_Pciess_appRegs *baseAddr,
853 pcieMsiIrqEnableClrReg_t *reg, 854 pcieMsiIrqEnableClrReg_t *reg,
@@ -862,12 +863,12 @@ pcieRet_e pcie_write_msiIrqEnableClr_reg
862 baseAddr->MSIX_IRQ[regNum].MSI_IRQ_ENABLE_CLR = reg->raw = new_val; 863 baseAddr->MSIX_IRQ[regNum].MSI_IRQ_ENABLE_CLR = reg->raw = new_val;
863 864
864 return pcie_range_check_return; 865 return pcie_range_check_return;
865} /*pcie_write_msiIrqEnableClr_reg*/ 866} /* pciev0_write_msiIrqEnableClr_reg */
866 867
867/***************************************************************************** 868/*****************************************************************************
868 * Read and split up a Legacy Raw Interrupt Status register 869 * Read and split up a Legacy Raw Interrupt Status register
869 ****************************************************************************/ 870 ****************************************************************************/
870pcieRet_e pcie_read_legacyIrqStatusRaw_reg 871pcieRet_e pciev0_read_legacyIrqStatusRaw_reg
871( 872(
872 CSL_Pciess_appRegs *baseAddr, 873 CSL_Pciess_appRegs *baseAddr,
873 pcieLegacyIrqStatusRawReg_t *reg, 874 pcieLegacyIrqStatusRawReg_t *reg,
@@ -879,13 +880,13 @@ pcieRet_e pcie_read_legacyIrqStatusRaw_reg
879 pcie_getbits(val, CSL_PCIESS_APP_LEGACY_IRQ_STATUS_RAW_LEGACY_RAW_STATUS, reg->legacyRawStatus); 880 pcie_getbits(val, CSL_PCIESS_APP_LEGACY_IRQ_STATUS_RAW_LEGACY_RAW_STATUS, reg->legacyRawStatus);
880 881
881 return pcie_RET_OK; 882 return pcie_RET_OK;
882} /*pcie_read_legacyIrqStatusRaw_reg*/ 883} /* pciev0_read_legacyIrqStatusRaw_reg */
883 884
884 885
885/***************************************************************************** 886/*****************************************************************************
886 * Combine and write a Legacy Raw Interrupt Status register 887 * Combine and write a Legacy Raw Interrupt Status register
887 ****************************************************************************/ 888 ****************************************************************************/
888pcieRet_e pcie_write_legacyIrqStatusRaw_reg 889pcieRet_e pciev0_write_legacyIrqStatusRaw_reg
889( 890(
890 CSL_Pciess_appRegs *baseAddr, 891 CSL_Pciess_appRegs *baseAddr,
891 pcieLegacyIrqStatusRawReg_t *reg, 892 pcieLegacyIrqStatusRawReg_t *reg,
@@ -900,12 +901,12 @@ pcieRet_e pcie_write_legacyIrqStatusRaw_reg
900 baseAddr->LEGACY_X_IRQ[regNum].LEGACY_IRQ_STATUS_RAW = reg->raw = new_val; 901 baseAddr->LEGACY_X_IRQ[regNum].LEGACY_IRQ_STATUS_RAW = reg->raw = new_val;
901 902
902 return pcie_range_check_return; 903 return pcie_range_check_return;
903} /*pcie_write_legacyIrqStatusRaw_reg*/ 904} /* pciev0_write_legacyIrqStatusRaw_reg */
904 905
905/***************************************************************************** 906/*****************************************************************************
906 * Read and split up a Legacy Interrupt Status register 907 * Read and split up a Legacy Interrupt Status register
907 ****************************************************************************/ 908 ****************************************************************************/
908pcieRet_e pcie_read_legacyIrqStatus_reg 909pcieRet_e pciev0_read_legacyIrqStatus_reg
909( 910(
910 CSL_Pciess_appRegs *baseAddr, 911 CSL_Pciess_appRegs *baseAddr,
911 pcieLegacyIrqStatusReg_t *reg, 912 pcieLegacyIrqStatusReg_t *reg,
@@ -917,13 +918,13 @@ pcieRet_e pcie_read_legacyIrqStatus_reg
917 pcie_getbits(val, CSL_PCIESS_APP_LEGACY_IRQ_STATUS_LEGACY_IRQ_STATUS, reg->legacyIrqStatus); 918 pcie_getbits(val, CSL_PCIESS_APP_LEGACY_IRQ_STATUS_LEGACY_IRQ_STATUS, reg->legacyIrqStatus);
918 919
919 return pcie_RET_OK; 920 return pcie_RET_OK;
920} /*pcie_read_legacyIrqStatus_reg*/ 921} /* pciev0_read_legacyIrqStatus_reg */
921 922
922 923
923/***************************************************************************** 924/*****************************************************************************
924 * Combine and write a Legacy Interrupt Status register 925 * Combine and write a Legacy Interrupt Status register
925 ****************************************************************************/ 926 ****************************************************************************/
926pcieRet_e pcie_write_legacyIrqStatus_reg 927pcieRet_e pciev0_write_legacyIrqStatus_reg
927( 928(
928 CSL_Pciess_appRegs *baseAddr, 929 CSL_Pciess_appRegs *baseAddr,
929 pcieLegacyIrqStatusReg_t *reg, 930 pcieLegacyIrqStatusReg_t *reg,
@@ -938,12 +939,12 @@ pcieRet_e pcie_write_legacyIrqStatus_reg
938 baseAddr->LEGACY_X_IRQ[regNum].LEGACY_IRQ_STATUS = reg->raw = new_val; 939 baseAddr->LEGACY_X_IRQ[regNum].LEGACY_IRQ_STATUS = reg->raw = new_val;
939 940
940 return pcie_range_check_return; 941 return pcie_range_check_return;
941} /*pcie_write_legacyIrqStatus_reg*/ 942} /* pciev0_write_legacyIrqStatus_reg */
942 943
943/***************************************************************************** 944/*****************************************************************************
944 * Read and split up a Legacy Interrupt Enable Set register 945 * Read and split up a Legacy Interrupt Enable Set register
945 ****************************************************************************/ 946 ****************************************************************************/
946pcieRet_e pcie_read_legacyIrqEnableSet_reg 947pcieRet_e pciev0_read_legacyIrqEnableSet_reg
947( 948(
948 CSL_Pciess_appRegs *baseAddr, 949 CSL_Pciess_appRegs *baseAddr,
949 pcieLegacyIrqEnableSetReg_t *reg, 950 pcieLegacyIrqEnableSetReg_t *reg,
@@ -955,12 +956,12 @@ pcieRet_e pcie_read_legacyIrqEnableSet_reg
955 pcie_getbits(val, CSL_PCIESS_APP_LEGACY_IRQ_ENABLE_SET_LEGACY_IRQ_EN_SET, reg->legacyIrqEnSet); 956 pcie_getbits(val, CSL_PCIESS_APP_LEGACY_IRQ_ENABLE_SET_LEGACY_IRQ_EN_SET, reg->legacyIrqEnSet);
956 957
957 return pcie_RET_OK; 958 return pcie_RET_OK;
958} /*pcie_read_legacyIrqEnableSet_reg*/ 959} /* pciev0_read_legacyIrqEnableSet_reg */
959 960
960/***************************************************************************** 961/*****************************************************************************
961 * Combine and write a Legacy Interrupt Enable Set register 962 * Combine and write a Legacy Interrupt Enable Set register
962 ****************************************************************************/ 963 ****************************************************************************/
963pcieRet_e pcie_write_legacyIrqEnableSet_reg 964pcieRet_e pciev0_write_legacyIrqEnableSet_reg
964( 965(
965 CSL_Pciess_appRegs *baseAddr, 966 CSL_Pciess_appRegs *baseAddr,
966 pcieLegacyIrqEnableSetReg_t *reg, 967 pcieLegacyIrqEnableSetReg_t *reg,
@@ -975,12 +976,12 @@ pcieRet_e pcie_write_legacyIrqEnableSet_reg
975 baseAddr->LEGACY_X_IRQ[regNum].LEGACY_IRQ_ENABLE_SET = reg->raw = new_val; 976 baseAddr->LEGACY_X_IRQ[regNum].LEGACY_IRQ_ENABLE_SET = reg->raw = new_val;
976 977
977 return pcie_range_check_return; 978 return pcie_range_check_return;
978} /*pcie_write_legacyIrqEnableSet_reg*/ 979} /* pciev0_write_legacyIrqEnableSet_reg */
979 980
980/***************************************************************************** 981/*****************************************************************************
981 * Read and split up the Legacy Interrupt Enable Clear register 982 * Read and split up the Legacy Interrupt Enable Clear register
982 ****************************************************************************/ 983 ****************************************************************************/
983pcieRet_e pcie_read_legacyIrqEnableClr_reg 984pcieRet_e pciev0_read_legacyIrqEnableClr_reg
984( 985(
985 CSL_Pciess_appRegs *baseAddr, 986 CSL_Pciess_appRegs *baseAddr,
986 pcieLegacyIrqEnableClrReg_t *reg, 987 pcieLegacyIrqEnableClrReg_t *reg,
@@ -992,13 +993,13 @@ pcieRet_e pcie_read_legacyIrqEnableClr_reg
992 pcie_getbits(val, CSL_PCIESS_APP_LEGACY_IRQ_ENABLE_CLR_LEGACY_IRQ_EN_CLR, reg->legacyIrqEnClr); 993 pcie_getbits(val, CSL_PCIESS_APP_LEGACY_IRQ_ENABLE_CLR_LEGACY_IRQ_EN_CLR, reg->legacyIrqEnClr);
993 994
994 return pcie_RET_OK; 995 return pcie_RET_OK;
995} /*pcie_read_legacyIrqEnableClr_reg*/ 996} /* pciev0_read_legacyIrqEnableClr_reg */
996 997
997 998
998/***************************************************************************** 999/*****************************************************************************
999 * Combine and write the Legacy Interrupt Enable Clear register 1000 * Combine and write the Legacy Interrupt Enable Clear register
1000 ****************************************************************************/ 1001 ****************************************************************************/
1001pcieRet_e pcie_write_legacyIrqEnableClr_reg 1002pcieRet_e pciev0_write_legacyIrqEnableClr_reg
1002( 1003(
1003 CSL_Pciess_appRegs *baseAddr, 1004 CSL_Pciess_appRegs *baseAddr,
1004 pcieLegacyIrqEnableClrReg_t *reg, 1005 pcieLegacyIrqEnableClrReg_t *reg,
@@ -1013,12 +1014,12 @@ pcieRet_e pcie_write_legacyIrqEnableClr_reg
1013 baseAddr->LEGACY_X_IRQ[regNum].LEGACY_IRQ_ENABLE_CLR = reg->raw = new_val; 1014 baseAddr->LEGACY_X_IRQ[regNum].LEGACY_IRQ_ENABLE_CLR = reg->raw = new_val;
1014 1015
1015 return pcie_range_check_return; 1016 return pcie_range_check_return;
1016} /*pcie_write_legacyIrqEnableClr_reg*/ 1017} /* pciev0_write_legacyIrqEnableClr_reg */
1017 1018
1018/***************************************************************************** 1019/*****************************************************************************
1019 * Read and split up a Raw ERR Interrupt Status register 1020 * Read and split up a Raw ERR Interrupt Status register
1020 ****************************************************************************/ 1021 ****************************************************************************/
1021pcieRet_e pcie_read_errIrqStatusRaw_reg 1022pcieRet_e pciev0_read_errIrqStatusRaw_reg
1022( 1023(
1023 CSL_Pciess_appRegs *baseAddr, 1024 CSL_Pciess_appRegs *baseAddr,
1024 pcieErrIrqStatusRawReg_t *reg 1025 pcieErrIrqStatusRawReg_t *reg
@@ -1034,13 +1035,13 @@ pcieRet_e pcie_read_errIrqStatusRaw_reg
1034 pcie_getbits(val, CSL_PCIESS_APP_ERR_IRQ_STATUS_RAW_ERR_SYS, reg->errSys); 1035 pcie_getbits(val, CSL_PCIESS_APP_ERR_IRQ_STATUS_RAW_ERR_SYS, reg->errSys);
1035 1036
1036 return pcie_RET_OK; 1037 return pcie_RET_OK;
1037} /*pcie_read_errIrqStatusRaw_reg*/ 1038} /* pciev0_read_errIrqStatusRaw_reg */
1038 1039
1039 1040
1040/***************************************************************************** 1041/*****************************************************************************
1041 * Combine and write a Raw ERR Interrupt Status register 1042 * Combine and write a Raw ERR Interrupt Status register
1042 ****************************************************************************/ 1043 ****************************************************************************/
1043pcieRet_e pcie_write_errIrqStatusRaw_reg 1044pcieRet_e pciev0_write_errIrqStatusRaw_reg
1044( 1045(
1045 CSL_Pciess_appRegs *baseAddr, 1046 CSL_Pciess_appRegs *baseAddr,
1046 pcieErrIrqStatusRawReg_t *reg 1047 pcieErrIrqStatusRawReg_t *reg
@@ -1059,12 +1060,12 @@ pcieRet_e pcie_write_errIrqStatusRaw_reg
1059 baseAddr->ERR_IRQ_STATUS_RAW = reg->raw = new_val; 1060 baseAddr->ERR_IRQ_STATUS_RAW = reg->raw = new_val;
1060 1061
1061 return pcie_range_check_return; 1062 return pcie_range_check_return;
1062} /*pcie_write_errIrqStatusRaw_reg*/ 1063} /* pciev0_write_errIrqStatusRaw_reg */
1063 1064
1064/***************************************************************************** 1065/*****************************************************************************
1065 * Read and split up a Err Interrupt Status register 1066 * Read and split up a Err Interrupt Status register
1066 ****************************************************************************/ 1067 ****************************************************************************/
1067pcieRet_e pcie_read_errIrqStatus_reg 1068pcieRet_e pciev0_read_errIrqStatus_reg
1068( 1069(
1069 CSL_Pciess_appRegs *baseAddr, 1070 CSL_Pciess_appRegs *baseAddr,
1070 pcieErrIrqStatusReg_t *reg 1071 pcieErrIrqStatusReg_t *reg
@@ -1080,12 +1081,12 @@ pcieRet_e pcie_read_errIrqStatus_reg
1080 pcie_getbits(val, CSL_PCIESS_APP_ERR_IRQ_STATUS_ERR_SYS, reg->errSys); 1081 pcie_getbits(val, CSL_PCIESS_APP_ERR_IRQ_STATUS_ERR_SYS, reg->errSys);
1081 1082
1082 return pcie_RET_OK; 1083 return pcie_RET_OK;
1083} /*pcie_read_errIrqStatus_reg*/ 1084} /* pciev0_read_errIrqStatus_reg */
1084 1085
1085/***************************************************************************** 1086/*****************************************************************************
1086 * Combine and write a Err Interrupt Status register 1087 * Combine and write a Err Interrupt Status register
1087 ****************************************************************************/ 1088 ****************************************************************************/
1088pcieRet_e pcie_write_errIrqStatus_reg 1089pcieRet_e pciev0_write_errIrqStatus_reg
1089( 1090(
1090 CSL_Pciess_appRegs *baseAddr, 1091 CSL_Pciess_appRegs *baseAddr,
1091 pcieErrIrqStatusReg_t *reg 1092 pcieErrIrqStatusReg_t *reg
@@ -1104,12 +1105,12 @@ pcieRet_e pcie_write_errIrqStatus_reg
1104 baseAddr->ERR_IRQ_STATUS = reg->raw = new_val; 1105 baseAddr->ERR_IRQ_STATUS = reg->raw = new_val;
1105 1106
1106 return pcie_range_check_return; 1107 return pcie_range_check_return;
1107} /*pcie_write_errIrqStatus_reg*/ 1108} /* pciev0_write_errIrqStatus_reg */
1108 1109
1109/***************************************************************************** 1110/*****************************************************************************
1110 * Read and split up a Err Interrupt Enable Set register 1111 * Read and split up a Err Interrupt Enable Set register
1111 ****************************************************************************/ 1112 ****************************************************************************/
1112pcieRet_e pcie_read_errIrqEnableSet_reg 1113pcieRet_e pciev0_read_errIrqEnableSet_reg
1113( 1114(
1114 CSL_Pciess_appRegs *baseAddr, 1115 CSL_Pciess_appRegs *baseAddr,
1115 pcieErrIrqEnableSetReg_t *reg 1116 pcieErrIrqEnableSetReg_t *reg
@@ -1125,12 +1126,12 @@ pcieRet_e pcie_read_errIrqEnableSet_reg
1125 pcie_getbits(val, CSL_PCIESS_APP_ERR_IRQ_ENABLE_SET_ERR_SYS, reg->errSys); 1126 pcie_getbits(val, CSL_PCIESS_APP_ERR_IRQ_ENABLE_SET_ERR_SYS, reg->errSys);
1126 1127
1127 return pcie_RET_OK; 1128 return pcie_RET_OK;
1128} /*pcie_read_errIrqEnableSet_reg*/ 1129} /* pciev0_read_errIrqEnableSet_reg */
1129 1130
1130/***************************************************************************** 1131/*****************************************************************************
1131 * Combine and write a Err Interrupt Enable Set register 1132 * Combine and write a Err Interrupt Enable Set register
1132 ****************************************************************************/ 1133 ****************************************************************************/
1133pcieRet_e pcie_write_errIrqEnableSet_reg 1134pcieRet_e pciev0_write_errIrqEnableSet_reg
1134( 1135(
1135 CSL_Pciess_appRegs *baseAddr, 1136 CSL_Pciess_appRegs *baseAddr,
1136 pcieErrIrqEnableSetReg_t *reg 1137 pcieErrIrqEnableSetReg_t *reg
@@ -1149,12 +1150,12 @@ pcieRet_e pcie_write_errIrqEnableSet_reg
1149 baseAddr->ERR_IRQ_ENABLE_SET = reg->raw = new_val; 1150 baseAddr->ERR_IRQ_ENABLE_SET = reg->raw = new_val;
1150 1151
1151 return pcie_range_check_return; 1152 return pcie_range_check_return;
1152} /*pcie_write_errIrqEnableSet_reg*/ 1153} /* pciev0_write_errIrqEnableSet_reg */
1153 1154
1154/***************************************************************************** 1155/*****************************************************************************
1155 * Read and split up the Err Interrupt Enable Clear register 1156 * Read and split up the Err Interrupt Enable Clear register
1156 ****************************************************************************/ 1157 ****************************************************************************/
1157pcieRet_e pcie_read_errIrqEnableClr_reg 1158pcieRet_e pciev0_read_errIrqEnableClr_reg
1158( 1159(
1159 CSL_Pciess_appRegs *baseAddr, 1160 CSL_Pciess_appRegs *baseAddr,
1160 pcieErrIrqEnableClrReg_t *reg 1161 pcieErrIrqEnableClrReg_t *reg
@@ -1170,13 +1171,13 @@ pcieRet_e pcie_read_errIrqEnableClr_reg
1170 pcie_getbits(val, CSL_PCIESS_APP_ERR_IRQ_ENABLE_CLR_ERR_SYS, reg->errSys); 1171 pcie_getbits(val, CSL_PCIESS_APP_ERR_IRQ_ENABLE_CLR_ERR_SYS, reg->errSys);
1171 1172
1172 return pcie_RET_OK; 1173 return pcie_RET_OK;
1173} /*pcie_read_errIrqEnableClr_reg*/ 1174} /* pciev0_read_errIrqEnableClr_reg */
1174 1175
1175 1176
1176/***************************************************************************** 1177/*****************************************************************************
1177 * Combine and write the Err Interrupt Enable Clear register 1178 * Combine and write the Err Interrupt Enable Clear register
1178 ****************************************************************************/ 1179 ****************************************************************************/
1179pcieRet_e pcie_write_errIrqEnableClr_reg 1180pcieRet_e pciev0_write_errIrqEnableClr_reg
1180( 1181(
1181 CSL_Pciess_appRegs *baseAddr, 1182 CSL_Pciess_appRegs *baseAddr,
1182 pcieErrIrqEnableClrReg_t *reg 1183 pcieErrIrqEnableClrReg_t *reg
@@ -1195,12 +1196,12 @@ pcieRet_e pcie_write_errIrqEnableClr_reg
1195 baseAddr->ERR_IRQ_ENABLE_CLR = reg->raw = new_val; 1196 baseAddr->ERR_IRQ_ENABLE_CLR = reg->raw = new_val;
1196 1197
1197 return pcie_range_check_return; 1198 return pcie_range_check_return;
1198} /*pcie_write_errIrqEnableClr_reg*/ 1199} /* pciev0_write_errIrqEnableClr_reg */
1199 1200
1200/***************************************************************************** 1201/*****************************************************************************
1201 * Read and split up a Raw Power Management and Reset Status register 1202 * Read and split up a Raw Power Management and Reset Status register
1202 ****************************************************************************/ 1203 ****************************************************************************/
1203pcieRet_e pcie_read_pmRstIrqStatusRaw_reg 1204pcieRet_e pciev0_read_pmRstIrqStatusRaw_reg
1204( 1205(
1205 CSL_Pciess_appRegs *baseAddr, 1206 CSL_Pciess_appRegs *baseAddr,
1206 pciePmRstIrqStatusRawReg_t *reg 1207 pciePmRstIrqStatusRawReg_t *reg
@@ -1214,13 +1215,13 @@ pcieRet_e pcie_read_pmRstIrqStatusRaw_reg
1214 pcie_getbits(val, CSL_PCIESS_APP_PMRST_IRQ_STATUS_RAW_PM_TURNOFF, reg->pmTurnoff); 1215 pcie_getbits(val, CSL_PCIESS_APP_PMRST_IRQ_STATUS_RAW_PM_TURNOFF, reg->pmTurnoff);
1215 1216
1216 return pcie_RET_OK; 1217 return pcie_RET_OK;
1217} /*pcie_read_pmRstIrqStatusRaw_reg*/ 1218} /* pciev0_read_pmRstIrqStatusRaw_reg */
1218 1219
1219 1220
1220/***************************************************************************** 1221/*****************************************************************************
1221 * Combine and write a Raw Power Management and Reset Status register 1222 * Combine and write a Raw Power Management and Reset Status register
1222 ****************************************************************************/ 1223 ****************************************************************************/
1223pcieRet_e pcie_write_pmRstIrqStatusRaw_reg 1224pcieRet_e pciev0_write_pmRstIrqStatusRaw_reg
1224( 1225(
1225 CSL_Pciess_appRegs *baseAddr, 1226 CSL_Pciess_appRegs *baseAddr,
1226 pciePmRstIrqStatusRawReg_t *reg 1227 pciePmRstIrqStatusRawReg_t *reg
@@ -1237,12 +1238,12 @@ pcieRet_e pcie_write_pmRstIrqStatusRaw_reg
1237 baseAddr->PMRST_IRQ_STATUS_RAW = reg->raw = new_val; 1238 baseAddr->PMRST_IRQ_STATUS_RAW = reg->raw = new_val;
1238 1239
1239 return pcie_range_check_return; 1240 return pcie_range_check_return;
1240} /*pcie_write_pmRstIrqStatusRaw_reg*/ 1241} /* pciev0_write_pmRstIrqStatusRaw_reg */
1241 1242
1242/***************************************************************************** 1243/*****************************************************************************
1243 * Read and split up a Power Management and Reset Status register 1244 * Read and split up a Power Management and Reset Status register
1244 ****************************************************************************/ 1245 ****************************************************************************/
1245pcieRet_e pcie_read_pmRstIrqStatus_reg 1246pcieRet_e pciev0_read_pmRstIrqStatus_reg
1246( 1247(
1247 CSL_Pciess_appRegs *baseAddr, 1248 CSL_Pciess_appRegs *baseAddr,
1248 pciePmRstIrqStatusReg_t *reg 1249 pciePmRstIrqStatusReg_t *reg
@@ -1256,12 +1257,12 @@ pcieRet_e pcie_read_pmRstIrqStatus_reg
1256 pcie_getbits(val, CSL_PCIESS_APP_PMRST_IRQ_STATUS_PM_TURNOFF, reg->pmTurnoff); 1257 pcie_getbits(val, CSL_PCIESS_APP_PMRST_IRQ_STATUS_PM_TURNOFF, reg->pmTurnoff);
1257 1258
1258 return pcie_RET_OK; 1259 return pcie_RET_OK;
1259} /*pcie_read_pmRstIrqStatus_reg*/ 1260} /* pciev0_read_pmRstIrqStatus_reg */
1260 1261
1261/***************************************************************************** 1262/*****************************************************************************
1262 * Combine and write a Power Management and Reset Status register 1263 * Combine and write a Power Management and Reset Status register
1263 ****************************************************************************/ 1264 ****************************************************************************/
1264pcieRet_e pcie_write_pmRstIrqStatus_reg 1265pcieRet_e pciev0_write_pmRstIrqStatus_reg
1265( 1266(
1266 CSL_Pciess_appRegs *baseAddr, 1267 CSL_Pciess_appRegs *baseAddr,
1267 pciePmRstIrqStatusReg_t *reg 1268 pciePmRstIrqStatusReg_t *reg
@@ -1278,12 +1279,12 @@ pcieRet_e pcie_write_pmRstIrqStatus_reg
1278 baseAddr->PMRST_IRQ_STATUS = reg->raw = new_val; 1279 baseAddr->PMRST_IRQ_STATUS = reg->raw = new_val;
1279 1280
1280 return pcie_range_check_return; 1281 return pcie_range_check_return;
1281} /*pcie_write_pmRstIrqStatus_reg*/ 1282} /* pciev0_write_pmRstIrqStatus_reg */
1282 1283
1283/***************************************************************************** 1284/*****************************************************************************
1284 * Read and split up a Power Management and Reset Enable Set register 1285 * Read and split up a Power Management and Reset Enable Set register
1285 ****************************************************************************/ 1286 ****************************************************************************/
1286pcieRet_e pcie_read_pmRstIrqEnableSet_reg 1287pcieRet_e pciev0_read_pmRstIrqEnableSet_reg
1287( 1288(
1288 CSL_Pciess_appRegs *baseAddr, 1289 CSL_Pciess_appRegs *baseAddr,
1289 pciePmRstIrqEnableSetReg_t *reg 1290 pciePmRstIrqEnableSetReg_t *reg
@@ -1297,12 +1298,12 @@ pcieRet_e pcie_read_pmRstIrqEnableSet_reg
1297 pcie_getbits(val, CSL_PCIESS_APP_PMRST_ENABLE_SET_PM_TURNOFF, reg->pmTurnoff); 1298 pcie_getbits(val, CSL_PCIESS_APP_PMRST_ENABLE_SET_PM_TURNOFF, reg->pmTurnoff);
1298 1299
1299 return pcie_RET_OK; 1300 return pcie_RET_OK;
1300} /*pcie_read_pmRstIrqEnableSet_reg*/ 1301} /* pciev0_read_pmRstIrqEnableSet_reg */
1301 1302
1302/***************************************************************************** 1303/*****************************************************************************
1303 * Combine and write a Power Management and Reset Enable Set register 1304 * Combine and write a Power Management and Reset Enable Set register
1304 ****************************************************************************/ 1305 ****************************************************************************/
1305pcieRet_e pcie_write_pmRstIrqEnableSet_reg 1306pcieRet_e pciev0_write_pmRstIrqEnableSet_reg
1306( 1307(
1307 CSL_Pciess_appRegs *baseAddr, 1308 CSL_Pciess_appRegs *baseAddr,
1308 pciePmRstIrqEnableSetReg_t *reg 1309 pciePmRstIrqEnableSetReg_t *reg
@@ -1319,12 +1320,12 @@ pcieRet_e pcie_write_pmRstIrqEnableSet_reg
1319 baseAddr->PMRST_ENABLE_SET = reg->raw = new_val; 1320 baseAddr->PMRST_ENABLE_SET = reg->raw = new_val;
1320 1321
1321 return pcie_range_check_return; 1322 return pcie_range_check_return;
1322} /*pcie_write_pmRstIrqEnableSet_reg*/ 1323} /* pciev0_write_pmRstIrqEnableSet_reg */
1323 1324
1324/***************************************************************************** 1325/*****************************************************************************
1325 * Read and split up the Power Management and Reset Enable Clear register 1326 * Read and split up the Power Management and Reset Enable Clear register
1326 ****************************************************************************/ 1327 ****************************************************************************/
1327pcieRet_e pcie_read_pmRstIrqEnableClr_reg 1328pcieRet_e pciev0_read_pmRstIrqEnableClr_reg
1328( 1329(
1329 CSL_Pciess_appRegs *baseAddr, 1330 CSL_Pciess_appRegs *baseAddr,
1330 pciePmRstIrqEnableClrReg_t *reg 1331 pciePmRstIrqEnableClrReg_t *reg
@@ -1338,13 +1339,13 @@ pcieRet_e pcie_read_pmRstIrqEnableClr_reg
1338 pcie_getbits(val, CSL_PCIESS_APP_PMRST_ENABLE_CLR_PM_TURNOFF, reg->pmTurnoff); 1339 pcie_getbits(val, CSL_PCIESS_APP_PMRST_ENABLE_CLR_PM_TURNOFF, reg->pmTurnoff);
1339 1340
1340 return pcie_RET_OK; 1341 return pcie_RET_OK;
1341} /*pcie_read_pmRstIrqEnableClr_reg*/ 1342} /* pciev0_read_pmRstIrqEnableClr_reg */
1342 1343
1343 1344
1344/***************************************************************************** 1345/*****************************************************************************
1345 * Combine and write the Power Management and Reset Enable Clear register 1346 * Combine and write the Power Management and Reset Enable Clear register
1346 ****************************************************************************/ 1347 ****************************************************************************/
1347pcieRet_e pcie_write_pmRstIrqEnableClr_reg 1348pcieRet_e pciev0_write_pmRstIrqEnableClr_reg
1348( 1349(
1349 CSL_Pciess_appRegs *baseAddr, 1350 CSL_Pciess_appRegs *baseAddr,
1350 pciePmRstIrqEnableClrReg_t *reg 1351 pciePmRstIrqEnableClrReg_t *reg
@@ -1361,12 +1362,12 @@ pcieRet_e pcie_write_pmRstIrqEnableClr_reg
1361 baseAddr->PMRST_ENABLE_CLR = reg->raw = new_val; 1362 baseAddr->PMRST_ENABLE_CLR = reg->raw = new_val;
1362 1363
1363 return pcie_range_check_return; 1364 return pcie_range_check_return;
1364} /*pcie_write_pmRstIrqEnableClr_reg*/ 1365} /* pciev0_write_pmRstIrqEnableClr_reg */
1365 1366
1366/***************************************************************************** 1367/*****************************************************************************
1367 * Read and split up the Outbound Translation Region Offset Low and Index register 1368 * Read and split up the Outbound Translation Region Offset Low and Index register
1368 ****************************************************************************/ 1369 ****************************************************************************/
1369pcieRet_e pcie_read_obOffsetLo_reg 1370pcieRet_e pciev0_read_obOffsetLo_reg
1370( 1371(
1371 CSL_Pciess_appRegs *baseAddr, 1372 CSL_Pciess_appRegs *baseAddr,
1372 pcieObOffsetLoReg_t *reg, 1373 pcieObOffsetLoReg_t *reg,
@@ -1379,12 +1380,12 @@ pcieRet_e pcie_read_obOffsetLo_reg
1379 pcie_getbits(val, CSL_PCIESS_APP_OB_OFFSET_INDEX_OB_ENABLE, reg->enable); 1380 pcie_getbits(val, CSL_PCIESS_APP_OB_OFFSET_INDEX_OB_ENABLE, reg->enable);
1380 1381
1381 return pcie_RET_OK; 1382 return pcie_RET_OK;
1382} /* pcie_read_obOffsetLo_reg */ 1383} /* pciev0_read_obOffsetLo_reg */
1383 1384
1384/***************************************************************************** 1385/*****************************************************************************
1385 * Combine and write the Outbound Translation Region Offset Low and Index register 1386 * Combine and write the Outbound Translation Region Offset Low and Index register
1386 ****************************************************************************/ 1387 ****************************************************************************/
1387pcieRet_e pcie_write_obOffsetLo_reg 1388pcieRet_e pciev0_write_obOffsetLo_reg
1388( 1389(
1389 CSL_Pciess_appRegs *baseAddr, 1390 CSL_Pciess_appRegs *baseAddr,
1390 pcieObOffsetLoReg_t *reg, 1391 pcieObOffsetLoReg_t *reg,
@@ -1399,13 +1400,13 @@ pcieRet_e pcie_write_obOffsetLo_reg
1399 1400
1400 baseAddr->OUTBOUND_TRANSLATION[regNum].OB_OFFSET_INDEX = reg->raw = new_val; 1401 baseAddr->OUTBOUND_TRANSLATION[regNum].OB_OFFSET_INDEX = reg->raw = new_val;
1401 return pcie_range_check_return; 1402 return pcie_range_check_return;
1402} /* pcie_write_obOffsetLo_reg */ 1403} /* pciev0_write_obOffsetLo_reg */
1403 1404
1404 1405
1405/***************************************************************************** 1406/*****************************************************************************
1406 * Read and split up the Outbound Translation Region Offset High register 1407 * Read and split up the Outbound Translation Region Offset High register
1407 ****************************************************************************/ 1408 ****************************************************************************/
1408pcieRet_e pcie_read_obOffsetHi_reg 1409pcieRet_e pciev0_read_obOffsetHi_reg
1409( 1410(
1410 CSL_Pciess_appRegs *baseAddr, 1411 CSL_Pciess_appRegs *baseAddr,
1411 pcieObOffsetHiReg_t *reg, 1412 pcieObOffsetHiReg_t *reg,
@@ -1417,12 +1418,12 @@ pcieRet_e pcie_read_obOffsetHi_reg
1417 pcie_getbits(val, CSL_PCIESS_APP_OB_OFFSET_HI_OB_OFFSET_HI, reg->offsetHi); 1418 pcie_getbits(val, CSL_PCIESS_APP_OB_OFFSET_HI_OB_OFFSET_HI, reg->offsetHi);
1418 1419
1419 return pcie_RET_OK; 1420 return pcie_RET_OK;
1420} /* pcie_read_obOffsetHi_reg */ 1421} /* pciev0_read_obOffsetHi_reg */
1421 1422
1422/***************************************************************************** 1423/*****************************************************************************
1423 * Combine and write the Outbound Translation Region Offset High register 1424 * Combine and write the Outbound Translation Region Offset High register
1424 ****************************************************************************/ 1425 ****************************************************************************/
1425pcieRet_e pcie_write_obOffsetHi_reg 1426pcieRet_e pciev0_write_obOffsetHi_reg
1426( 1427(
1427 CSL_Pciess_appRegs *baseAddr, 1428 CSL_Pciess_appRegs *baseAddr,
1428 pcieObOffsetHiReg_t *reg, 1429 pcieObOffsetHiReg_t *reg,
@@ -1436,12 +1437,12 @@ pcieRet_e pcie_write_obOffsetHi_reg
1436 1437
1437 baseAddr->OUTBOUND_TRANSLATION[regNum].OB_OFFSET_HI = reg->raw = new_val; 1438 baseAddr->OUTBOUND_TRANSLATION[regNum].OB_OFFSET_HI = reg->raw = new_val;
1438 return pcie_range_check_return; 1439 return pcie_range_check_return;
1439} /* pcie_write_obOffsetHi_reg */ 1440} /* pciev0_write_obOffsetHi_reg */
1440 1441
1441/***************************************************************************** 1442/*****************************************************************************
1442 * Read and split up the Inbound Translation BAR Match register 1443 * Read and split up the Inbound Translation BAR Match register
1443 ****************************************************************************/ 1444 ****************************************************************************/
1444pcieRet_e pcie_read_ibBar_reg 1445pcieRet_e pciev0_read_ibBar_reg
1445( 1446(
1446 CSL_Pciess_appRegs *baseAddr, 1447 CSL_Pciess_appRegs *baseAddr,
1447 pcieIbBarReg_t *reg, 1448 pcieIbBarReg_t *reg,
@@ -1453,12 +1454,12 @@ pcieRet_e pcie_read_ibBar_reg
1453 pcie_getbits(val, CSL_PCIESS_APP_IB_BAR_IB_BAR, reg->ibBar); 1454 pcie_getbits(val, CSL_PCIESS_APP_IB_BAR_IB_BAR, reg->ibBar);
1454 1455
1455 return pcie_RET_OK; 1456 return pcie_RET_OK;
1456} /* pcie_read_ibBar_reg */ 1457} /* pciev0_read_ibBar_reg */
1457 1458
1458/***************************************************************************** 1459/*****************************************************************************
1459 * Combine and write the Inbound Translation BAR Match register 1460 * Combine and write the Inbound Translation BAR Match register
1460 ****************************************************************************/ 1461 ****************************************************************************/
1461pcieRet_e pcie_write_ibBar_reg 1462pcieRet_e pciev0_write_ibBar_reg
1462( 1463(
1463 CSL_Pciess_appRegs *baseAddr, 1464 CSL_Pciess_appRegs *baseAddr,
1464 pcieIbBarReg_t *reg, 1465 pcieIbBarReg_t *reg,
@@ -1472,12 +1473,12 @@ pcieRet_e pcie_write_ibBar_reg
1472 1473
1473 baseAddr->INBOUND_TRANSLATION[regNum].IB_BAR = reg->raw = new_val; 1474 baseAddr->INBOUND_TRANSLATION[regNum].IB_BAR = reg->raw = new_val;
1474 return pcie_range_check_return; 1475 return pcie_range_check_return;
1475} /* pcie_write_ibBar_reg */ 1476} /* pciev0_write_ibBar_reg */
1476 1477
1477/***************************************************************************** 1478/*****************************************************************************
1478 * Read and split up the Inbound Translation Start Address Low register 1479 * Read and split up the Inbound Translation Start Address Low register
1479 ****************************************************************************/ 1480 ****************************************************************************/
1480pcieRet_e pcie_read_ibStartLo_reg 1481pcieRet_e pciev0_read_ibStartLo_reg
1481( 1482(
1482 CSL_Pciess_appRegs *baseAddr, 1483 CSL_Pciess_appRegs *baseAddr,
1483 pcieIbStartLoReg_t *reg, 1484 pcieIbStartLoReg_t *reg,
@@ -1489,12 +1490,12 @@ pcieRet_e pcie_read_ibStartLo_reg
1489 pcie_getbits(val, CSL_PCIESS_APP_IB_START_LO_IB_START_LO, reg->ibStartLo); 1490 pcie_getbits(val, CSL_PCIESS_APP_IB_START_LO_IB_START_LO, reg->ibStartLo);
1490 1491
1491 return pcie_RET_OK; 1492 return pcie_RET_OK;
1492} /* pcie_read_ibStartLo_reg */ 1493} /* pciev0_read_ibStartLo_reg */
1493 1494
1494/***************************************************************************** 1495/*****************************************************************************
1495 * Combine and write the Inbound Translation Start Address Low register 1496 * Combine and write the Inbound Translation Start Address Low register
1496 ****************************************************************************/ 1497 ****************************************************************************/
1497pcieRet_e pcie_write_ibStartLo_reg 1498pcieRet_e pciev0_write_ibStartLo_reg
1498( 1499(
1499 CSL_Pciess_appRegs *baseAddr, 1500 CSL_Pciess_appRegs *baseAddr,
1500 pcieIbStartLoReg_t *reg, 1501 pcieIbStartLoReg_t *reg,
@@ -1508,13 +1509,13 @@ pcieRet_e pcie_write_ibStartLo_reg
1508 1509
1509 baseAddr->INBOUND_TRANSLATION[regNum].IB_START_LO = reg->raw = new_val; 1510 baseAddr->INBOUND_TRANSLATION[regNum].IB_START_LO = reg->raw = new_val;
1510 return pcie_range_check_return; 1511 return pcie_range_check_return;
1511} /* pcie_write_ibStartLo_reg */ 1512} /* pciev0_write_ibStartLo_reg */
1512 1513
1513 1514
1514/***************************************************************************** 1515/*****************************************************************************
1515 * Read and split up the Inbound Translation Start Address High register 1516 * Read and split up the Inbound Translation Start Address High register
1516 ****************************************************************************/ 1517 ****************************************************************************/
1517pcieRet_e pcie_read_ibStartHi_reg 1518pcieRet_e pciev0_read_ibStartHi_reg
1518( 1519(
1519 CSL_Pciess_appRegs *baseAddr, 1520 CSL_Pciess_appRegs *baseAddr,
1520 pcieIbStartHiReg_t *reg, 1521 pcieIbStartHiReg_t *reg,
@@ -1526,12 +1527,12 @@ pcieRet_e pcie_read_ibStartHi_reg
1526 pcie_getbits(val, CSL_PCIESS_APP_IB_START_HI_IB_START_HI, reg->ibStartHi); 1527 pcie_getbits(val, CSL_PCIESS_APP_IB_START_HI_IB_START_HI, reg->ibStartHi);
1527 1528
1528 return pcie_RET_OK; 1529 return pcie_RET_OK;
1529} /* pcie_read_ibStartHi_reg */ 1530} /* pciev0_read_ibStartHi_reg */
1530 1531
1531/***************************************************************************** 1532/*****************************************************************************
1532 * Combine and write the Inbound Translation Start Address High register 1533 * Combine and write the Inbound Translation Start Address High register
1533 ****************************************************************************/ 1534 ****************************************************************************/
1534pcieRet_e pcie_write_ibStartHi_reg 1535pcieRet_e pciev0_write_ibStartHi_reg
1535( 1536(
1536 CSL_Pciess_appRegs *baseAddr, 1537 CSL_Pciess_appRegs *baseAddr,
1537 pcieIbStartHiReg_t *reg, 1538 pcieIbStartHiReg_t *reg,
@@ -1545,12 +1546,12 @@ pcieRet_e pcie_write_ibStartHi_reg
1545 1546
1546 baseAddr->INBOUND_TRANSLATION[regNum].IB_START_HI = reg->raw = new_val; 1547 baseAddr->INBOUND_TRANSLATION[regNum].IB_START_HI = reg->raw = new_val;
1547 return pcie_range_check_return; 1548 return pcie_range_check_return;
1548} /* pcie_write_ibStartHi_reg */ 1549} /* pciev0_write_ibStartHi_reg */
1549 1550
1550/***************************************************************************** 1551/*****************************************************************************
1551 * Read and split up the Inbound Translation Offset register 1552 * Read and split up the Inbound Translation Offset register
1552 ****************************************************************************/ 1553 ****************************************************************************/
1553pcieRet_e pcie_read_ibOffset_reg 1554pcieRet_e pciev0_read_ibOffset_reg
1554( 1555(
1555 CSL_Pciess_appRegs *baseAddr, 1556 CSL_Pciess_appRegs *baseAddr,
1556 pcieIbOffsetReg_t *reg, 1557 pcieIbOffsetReg_t *reg,
@@ -1562,12 +1563,12 @@ pcieRet_e pcie_read_ibOffset_reg
1562 pcie_getbits(val, CSL_PCIESS_APP_IB_OFFSET_IB_OFFSET, reg->ibOffset); 1563 pcie_getbits(val, CSL_PCIESS_APP_IB_OFFSET_IB_OFFSET, reg->ibOffset);
1563 1564
1564 return pcie_RET_OK; 1565 return pcie_RET_OK;
1565} /* pcie_read_ibOffset_reg */ 1566} /* pciev0_read_ibOffset_reg */
1566 1567
1567/***************************************************************************** 1568/*****************************************************************************
1568 * Combine and write the Inbound Translation Offset register 1569 * Combine and write the Inbound Translation Offset register
1569 ****************************************************************************/ 1570 ****************************************************************************/
1570pcieRet_e pcie_write_ibOffset_reg 1571pcieRet_e pciev0_write_ibOffset_reg
1571( 1572(
1572 CSL_Pciess_appRegs *baseAddr, 1573 CSL_Pciess_appRegs *baseAddr,
1573 pcieIbOffsetReg_t *reg, 1574 pcieIbOffsetReg_t *reg,
@@ -1581,12 +1582,12 @@ pcieRet_e pcie_write_ibOffset_reg
1581 1582
1582 baseAddr->INBOUND_TRANSLATION[regNum].IB_OFFSET = reg->raw = new_val; 1583 baseAddr->INBOUND_TRANSLATION[regNum].IB_OFFSET = reg->raw = new_val;
1583 return pcie_range_check_return; 1584 return pcie_range_check_return;
1584} /* pcie_write_ibOffset_reg */ 1585} /* pciev0_write_ibOffset_reg */
1585 1586
1586/***************************************************************************** 1587/*****************************************************************************
1587 * Read and split up the PCS Configuration 0 register 1588 * Read and split up the PCS Configuration 0 register
1588 ****************************************************************************/ 1589 ****************************************************************************/
1589pcieRet_e pcie_read_pcsCfg0_reg 1590pcieRet_e pciev0_read_pcsCfg0_reg
1590( 1591(
1591 CSL_Pciess_appRegs *baseAddr, 1592 CSL_Pciess_appRegs *baseAddr,
1592 pciePcsCfg0Reg_t *reg 1593 pciePcsCfg0Reg_t *reg
@@ -1607,12 +1608,12 @@ pcieRet_e pcie_read_pcsCfg0_reg
1607 pcie_getbits(val, CSL_PCIESS_APP_PCS_CFG0_PCS_RXTX_RST, reg->pcsRxTxRst); 1608 pcie_getbits(val, CSL_PCIESS_APP_PCS_CFG0_PCS_RXTX_RST, reg->pcsRxTxRst);
1608 1609
1609 return pcie_RET_OK; 1610 return pcie_RET_OK;
1610} /*pcie_read_pcsCfg0_reg */ 1611} /* pciev0_read_pcsCfg0_reg */
1611 1612
1612/***************************************************************************** 1613/*****************************************************************************
1613 * Combine and write the PCS Configuration 0 register 1614 * Combine and write the PCS Configuration 0 register
1614 ****************************************************************************/ 1615 ****************************************************************************/
1615pcieRet_e pcie_write_pcsCfg0_reg 1616pcieRet_e pciev0_write_pcsCfg0_reg
1616( 1617(
1617 CSL_Pciess_appRegs *baseAddr, 1618 CSL_Pciess_appRegs *baseAddr,
1618 pciePcsCfg0Reg_t *reg 1619 pciePcsCfg0Reg_t *reg
@@ -1636,12 +1637,12 @@ pcieRet_e pcie_write_pcsCfg0_reg
1636 baseAddr->PCS_CFG0 = reg->raw = new_val; 1637 baseAddr->PCS_CFG0 = reg->raw = new_val;
1637 1638
1638 return pcie_range_check_return; 1639 return pcie_range_check_return;
1639} /*pcie_write_pcsCfg0_reg */ 1640} /* pciev0_write_pcsCfg0_reg */
1640 1641
1641/***************************************************************************** 1642/*****************************************************************************
1642 * Read and split up the PCS Configuration 1 register 1643 * Read and split up the PCS Configuration 1 register
1643 ****************************************************************************/ 1644 ****************************************************************************/
1644pcieRet_e pcie_read_pcsCfg1_reg 1645pcieRet_e pciev0_read_pcsCfg1_reg
1645( 1646(
1646 CSL_Pciess_appRegs *baseAddr, 1647 CSL_Pciess_appRegs *baseAddr,
1647 pciePcsCfg1Reg_t *reg 1648 pciePcsCfg1Reg_t *reg
@@ -1654,12 +1655,12 @@ pcieRet_e pcie_read_pcsCfg1_reg
1654 pcie_getbits(val, CSL_PCIESS_APP_PCS_CFG1_PCS_ERR_MODE, reg->pcsErrMode); 1655 pcie_getbits(val, CSL_PCIESS_APP_PCS_CFG1_PCS_ERR_MODE, reg->pcsErrMode);
1655 1656
1656 return pcie_RET_OK; 1657 return pcie_RET_OK;
1657} /*pcie_read_pcsCfg1_reg */ 1658} /* pciev0_read_pcsCfg1_reg */
1658 1659
1659/***************************************************************************** 1660/*****************************************************************************
1660 * Combine and write the PCS Configuration 1 register 1661 * Combine and write the PCS Configuration 1 register
1661 ****************************************************************************/ 1662 ****************************************************************************/
1662pcieRet_e pcie_write_pcsCfg1_reg 1663pcieRet_e pciev0_write_pcsCfg1_reg
1663( 1664(
1664 CSL_Pciess_appRegs *baseAddr, 1665 CSL_Pciess_appRegs *baseAddr,
1665 pciePcsCfg1Reg_t *reg 1666 pciePcsCfg1Reg_t *reg
@@ -1675,12 +1676,12 @@ pcieRet_e pcie_write_pcsCfg1_reg
1675 baseAddr->PCS_CFG1 = reg->raw = new_val; 1676 baseAddr->PCS_CFG1 = reg->raw = new_val;
1676 1677
1677 return pcie_range_check_return; 1678 return pcie_range_check_return;
1678} /*pcie_write_pcsCfg1_reg */ 1679} /* pciev0_write_pcsCfg1_reg */
1679 1680
1680/***************************************************************************** 1681/*****************************************************************************
1681 * Read and split up the PCS Status register 1682 * Read and split up the PCS Status register
1682 ****************************************************************************/ 1683 ****************************************************************************/
1683pcieRet_e pcie_read_pcsStatus_reg 1684pcieRet_e pciev0_read_pcsStatus_reg
1684( 1685(
1685 CSL_Pciess_appRegs *baseAddr, 1686 CSL_Pciess_appRegs *baseAddr,
1686 pciePcsStatusReg_t *reg 1687 pciePcsStatusReg_t *reg
@@ -1694,12 +1695,12 @@ pcieRet_e pcie_read_pcsStatus_reg
1694 pcie_getbits(val, CSL_PCIESS_APP_PCS_STATUS_PCS_RX_EN, reg->pcsRxEn); 1695 pcie_getbits(val, CSL_PCIESS_APP_PCS_STATUS_PCS_RX_EN, reg->pcsRxEn);
1695 1696
1696 return pcie_RET_OK; 1697 return pcie_RET_OK;
1697} /*pcie_read_pcsStatus_reg */ 1698} /* pciev0_read_pcsStatus_reg */
1698 1699
1699/***************************************************************************** 1700/*****************************************************************************
1700 * Read and split up the SERDES Configuration Lane 0 register 1701 * Read and split up the SERDES Configuration Lane 0 register
1701 ****************************************************************************/ 1702 ****************************************************************************/
1702pcieRet_e pcie_read_serdesCfg0_reg 1703pcieRet_e pciev0_read_serdesCfg0_reg
1703( 1704(
1704 CSL_Pciess_appRegs *baseAddr, 1705 CSL_Pciess_appRegs *baseAddr,
1705 pcieSerdesCfg0Reg_t *reg 1706 pcieSerdesCfg0Reg_t *reg
@@ -1720,13 +1721,13 @@ pcieRet_e pcie_read_serdesCfg0_reg
1720 pcie_getbits(val, CSL_PCIESS_APP_SERDES_CFG0_RX_INVPAIR, reg->rxInvpair); 1721 pcie_getbits(val, CSL_PCIESS_APP_SERDES_CFG0_RX_INVPAIR, reg->rxInvpair);
1721 1722
1722 return pcie_RET_OK; 1723 return pcie_RET_OK;
1723} /*pcie_read_serdesCfg0_reg*/ 1724} /* pciev0_read_serdesCfg0_reg */
1724 1725
1725 1726
1726/***************************************************************************** 1727/*****************************************************************************
1727 * Combine and write the SERDES Configuration Lane 0 register 1728 * Combine and write the SERDES Configuration Lane 0 register
1728 ****************************************************************************/ 1729 ****************************************************************************/
1729pcieRet_e pcie_write_serdesCfg0_reg 1730pcieRet_e pciev0_write_serdesCfg0_reg
1730( 1731(
1731 CSL_Pciess_appRegs *baseAddr, 1732 CSL_Pciess_appRegs *baseAddr,
1732 pcieSerdesCfg0Reg_t *reg 1733 pcieSerdesCfg0Reg_t *reg
@@ -1750,12 +1751,12 @@ pcieRet_e pcie_write_serdesCfg0_reg
1750 baseAddr->SERDES_CFG0 = reg->raw = new_val; 1751 baseAddr->SERDES_CFG0 = reg->raw = new_val;
1751 1752
1752 return pcie_range_check_return; 1753 return pcie_range_check_return;
1753} /*pcie_write_serdesCfg0_reg*/ 1754} /* pciev0_write_serdesCfg0_reg */
1754 1755
1755/***************************************************************************** 1756/*****************************************************************************
1756 * Read and split up the SERDES Configuration Lane 1 register 1757 * Read and split up the SERDES Configuration Lane 1 register
1757 ****************************************************************************/ 1758 ****************************************************************************/
1758pcieRet_e pcie_read_serdesCfg1_reg 1759pcieRet_e pciev0_read_serdesCfg1_reg
1759( 1760(
1760 CSL_Pciess_appRegs *baseAddr, 1761 CSL_Pciess_appRegs *baseAddr,
1761 pcieSerdesCfg1Reg_t *reg 1762 pcieSerdesCfg1Reg_t *reg
@@ -1776,13 +1777,13 @@ pcieRet_e pcie_read_serdesCfg1_reg
1776 pcie_getbits(val, CSL_PCIESS_APP_SERDES_CFG1_RX_INVPAIR, reg->rxInvpair); 1777 pcie_getbits(val, CSL_PCIESS_APP_SERDES_CFG1_RX_INVPAIR, reg->rxInvpair);
1777 1778
1778 return pcie_RET_OK; 1779 return pcie_RET_OK;
1779} /*pcie_read_serdesCfg1_reg*/ 1780} /* pciev0_read_serdesCfg1_reg */
1780 1781
1781 1782
1782/***************************************************************************** 1783/*****************************************************************************
1783 * Combine and write the SERDES Configuration Lane 1 register 1784 * Combine and write the SERDES Configuration Lane 1 register
1784 ****************************************************************************/ 1785 ****************************************************************************/
1785pcieRet_e pcie_write_serdesCfg1_reg 1786pcieRet_e pciev0_write_serdesCfg1_reg
1786( 1787(
1787 CSL_Pciess_appRegs *baseAddr, 1788 CSL_Pciess_appRegs *baseAddr,
1788 pcieSerdesCfg1Reg_t *reg 1789 pcieSerdesCfg1Reg_t *reg
@@ -1806,7 +1807,7 @@ pcieRet_e pcie_write_serdesCfg1_reg
1806 baseAddr->SERDES_CFG1 = reg->raw = new_val; 1807 baseAddr->SERDES_CFG1 = reg->raw = new_val;
1807 1808
1808 return pcie_range_check_return; 1809 return pcie_range_check_return;
1809} /*pcie_write_serdesCfg1_reg*/ 1810} /* pciev0_write_serdesCfg1_reg */
1810 1811
1811/* Nothing past this point */ 1812/* Nothing past this point */
1812 1813
diff --git a/src/pciecfg.c b/src/v0/pciev0_cfg.c
index 310fca2..41662f0 100755..100644
--- a/src/pciecfg.c
+++ b/src/v0/pciev0_cfg.c
@@ -1,6 +1,6 @@
1/* 1/*
2 * 2 *
3 * Copyright (C) 2010-2013 Texas Instruments Incorporated - http://www.ti.com/ 3 * Copyright (C) 2010-2015 Texas Instruments Incorporated - http://www.ti.com/
4 * 4 *
5 * 5 *
6 * Redistribution and use in source and binary forms, with or without 6 * Redistribution and use in source and binary forms, with or without
@@ -40,8 +40,9 @@
40 * 40 *
41 */ 41 */
42 42
43#include "pcie.h" 43#include <ti/drv/pcie/pcie.h>
44#include "pcieloc.h" 44#include <ti/drv/pcie/src/pcieloc.h>
45#include <ti/drv/pcie/src/v0/pcieloc.h>
45#include <ti/csl/cslr_pcie_cfg_space_endpoint.h> 46#include <ti/csl/cslr_pcie_cfg_space_endpoint.h>
46#include <ti/csl/cslr_pcie_cfg_space_rootcomplex.h> 47#include <ti/csl/cslr_pcie_cfg_space_rootcomplex.h>
47#include <ti/csl/cslr_pciess_app.h> 48#include <ti/csl/cslr_pciess_app.h>
@@ -60,7 +61,7 @@
60/***************************************************************************** 61/*****************************************************************************
61 * Read and split up the Vendor and Device Identification register 62 * Read and split up the Vendor and Device Identification register
62 ****************************************************************************/ 63 ****************************************************************************/
63pcieRet_e pcie_read_vndDevId_reg 64pcieRet_e pciev0_read_vndDevId_reg
64( 65(
65 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 66 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
66 pcieVndDevIdReg_t *reg 67 pcieVndDevIdReg_t *reg
@@ -72,12 +73,12 @@ pcieRet_e pcie_read_vndDevId_reg
72 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_VENDOR_DEVICE_ID_DEVICE_ID, reg->devId); 73 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_VENDOR_DEVICE_ID_DEVICE_ID, reg->devId);
73 74
74 return pcie_RET_OK; 75 return pcie_RET_OK;
75} /* pcie_read_vndDevId_reg */ 76} /* pciev0_read_vndDevId_reg */
76 77
77/***************************************************************************** 78/*****************************************************************************
78 * Combine and write the Vendor and Device Identification register 79 * Combine and write the Vendor and Device Identification register
79 ****************************************************************************/ 80 ****************************************************************************/
80pcieRet_e pcie_write_vndDevId_reg 81pcieRet_e pciev0_write_vndDevId_reg
81( 82(
82 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 83 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
83 pcieVndDevIdReg_t *reg 84 pcieVndDevIdReg_t *reg
@@ -92,14 +93,14 @@ pcieRet_e pcie_write_vndDevId_reg
92 baseAddr->VENDOR_DEVICE_ID = reg->raw = new_val;; 93 baseAddr->VENDOR_DEVICE_ID = reg->raw = new_val;;
93 94
94 return pcie_range_check_return; 95 return pcie_range_check_return;
95} /* pcie_write_vndDevId_reg */ 96} /* pciev0_write_vndDevId_reg */
96 97
97 98
98 99
99/***************************************************************************** 100/*****************************************************************************
100 * Read and split up the Status and Command register 101 * Read and split up the Status and Command register
101 ****************************************************************************/ 102 ****************************************************************************/
102pcieRet_e pcie_read_statusCmd_reg 103pcieRet_e pciev0_read_statusCmd_reg
103( 104(
104 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 105 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
105 pcieStatusCmdReg_t *reg 106 pcieStatusCmdReg_t *reg
@@ -123,12 +124,12 @@ pcieRet_e pcie_read_statusCmd_reg
123 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_STATUS_COMMAND_IO_SPACE, reg->ioSp); 124 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_STATUS_COMMAND_IO_SPACE, reg->ioSp);
124 125
125 return pcie_RET_OK; 126 return pcie_RET_OK;
126} /* pcie_read_statusCmd_reg */ 127} /* pciev0_read_statusCmd_reg */
127 128
128/***************************************************************************** 129/*****************************************************************************
129 * Combine and write the Status and Command register 130 * Combine and write the Status and Command register
130 ****************************************************************************/ 131 ****************************************************************************/
131pcieRet_e pcie_write_statusCmd_reg 132pcieRet_e pciev0_write_statusCmd_reg
132( 133(
133 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 134 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
134 pcieStatusCmdReg_t *reg 135 pcieStatusCmdReg_t *reg
@@ -155,12 +156,12 @@ pcieRet_e pcie_write_statusCmd_reg
155 baseAddr->STATUS_COMMAND = reg->raw = new_val;; 156 baseAddr->STATUS_COMMAND = reg->raw = new_val;;
156 157
157 return pcie_range_check_return; 158 return pcie_range_check_return;
158} /* pcie_write_statusCmd_reg */ 159} /* pciev0_write_statusCmd_reg */
159 160
160/***************************************************************************** 161/*****************************************************************************
161 * Read and split up the Class Code and Revision ID register 162 * Read and split up the Class Code and Revision ID register
162 ****************************************************************************/ 163 ****************************************************************************/
163pcieRet_e pcie_read_revId_reg 164pcieRet_e pciev0_read_revId_reg
164( 165(
165 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 166 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
166 pcieRevIdReg_t *reg 167 pcieRevIdReg_t *reg
@@ -172,12 +173,12 @@ pcieRet_e pcie_read_revId_reg
172 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_CLASSCODE_REVID_REVISION_ID, reg->revId); 173 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_CLASSCODE_REVID_REVISION_ID, reg->revId);
173 174
174 return pcie_RET_OK; 175 return pcie_RET_OK;
175} /* pcie_read_revId_reg */ 176} /* pciev0_read_revId_reg */
176 177
177/***************************************************************************** 178/*****************************************************************************
178 * Combine and write the Class Code and Revision ID register 179 * Combine and write the Class Code and Revision ID register
179 ****************************************************************************/ 180 ****************************************************************************/
180pcieRet_e pcie_write_revId_reg 181pcieRet_e pciev0_write_revId_reg
181( 182(
182 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 183 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
183 pcieRevIdReg_t *reg 184 pcieRevIdReg_t *reg
@@ -192,7 +193,7 @@ pcieRet_e pcie_write_revId_reg
192 baseAddr->CLASSCODE_REVID = reg->raw = new_val;; 193 baseAddr->CLASSCODE_REVID = reg->raw = new_val;;
193 194
194 return pcie_range_check_return; 195 return pcie_range_check_return;
195} /* pcie_write_revId_reg */ 196} /* pciev0_write_revId_reg */
196 197
197 198
198/***************************************************************************** 199/*****************************************************************************
@@ -202,7 +203,7 @@ pcieRet_e pcie_write_revId_reg
202/***************************************************************************** 203/*****************************************************************************
203 * Read and split up the BIST and Header register 204 * Read and split up the BIST and Header register
204 ****************************************************************************/ 205 ****************************************************************************/
205pcieRet_e pcie_read_bist_reg 206pcieRet_e pciev0_read_bist_reg
206( 207(
207 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 208 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
208 pcieBistReg_t *reg 209 pcieBistReg_t *reg
@@ -219,12 +220,12 @@ pcieRet_e pcie_read_bist_reg
219 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_BIST_HEADER_CACHE_LINE_SIZE, reg->cacheLnSize); 220 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_BIST_HEADER_CACHE_LINE_SIZE, reg->cacheLnSize);
220 221
221 return pcie_RET_OK; 222 return pcie_RET_OK;
222} /* pcie_read_bist_reg */ 223} /* pciev0_read_bist_reg */
223 224
224/***************************************************************************** 225/*****************************************************************************
225 * Combine and write the BIST and Header register 226 * Combine and write the BIST and Header register
226 ****************************************************************************/ 227 ****************************************************************************/
227pcieRet_e pcie_write_bist_reg 228pcieRet_e pciev0_write_bist_reg
228( 229(
229 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 230 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
230 pcieBistReg_t *reg 231 pcieBistReg_t *reg
@@ -244,12 +245,12 @@ pcieRet_e pcie_write_bist_reg
244 baseAddr->BIST_HEADER = reg->raw = new_val;; 245 baseAddr->BIST_HEADER = reg->raw = new_val;;
245 246
246 return pcie_range_check_return; 247 return pcie_range_check_return;
247} /* pcie_write_bist_reg */ 248} /* pciev0_write_bist_reg */
248 249
249/***************************************************************************** 250/*****************************************************************************
250 * Read and split up the BAR register 251 * Read and split up the BAR register
251 ****************************************************************************/ 252 ****************************************************************************/
252pcieRet_e pcie_read_type0Bar_reg 253pcieRet_e pciev0_read_type0Bar_reg
253( 254(
254 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 255 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
255 pcieBarReg_t *reg, 256 pcieBarReg_t *reg,
@@ -264,12 +265,12 @@ pcieRet_e pcie_read_type0Bar_reg
264 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_BAR_MEMORY_SPACE, reg->memSpace); 265 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_BAR_MEMORY_SPACE, reg->memSpace);
265 266
266 return pcie_RET_OK; 267 return pcie_RET_OK;
267} /* pcie_read_type0Bar_reg */ 268} /* pciev0_read_type0Bar_reg */
268 269
269/***************************************************************************** 270/*****************************************************************************
270 * Combine and write the BAR register 271 * Combine and write the BAR register
271 ****************************************************************************/ 272 ****************************************************************************/
272pcieRet_e pcie_write_type0Bar_reg 273pcieRet_e pciev0_write_type0Bar_reg
273( 274(
274 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 275 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
275 pcieBarReg_t *reg, 276 pcieBarReg_t *reg,
@@ -286,13 +287,13 @@ pcieRet_e pcie_write_type0Bar_reg
286 287
287 baseAddr->BAR[barNum] = reg->raw = new_val; 288 baseAddr->BAR[barNum] = reg->raw = new_val;
288 return pcie_range_check_return; 289 return pcie_range_check_return;
289} /* pcie_write_type0Bar_reg */ 290} /* pciev0_write_type0Bar_reg */
290 291
291 292
292/***************************************************************************** 293/*****************************************************************************
293 * Read and split up the BAR 32bits register 294 * Read and split up the BAR 32bits register
294 ****************************************************************************/ 295 ****************************************************************************/
295pcieRet_e pcie_read_type0Bar32bit_reg 296pcieRet_e pciev0_read_type0Bar32bit_reg
296( 297(
297 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 298 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
298 pcieBar32bitReg_t *reg, 299 pcieBar32bitReg_t *reg,
@@ -301,12 +302,12 @@ pcieRet_e pcie_read_type0Bar32bit_reg
301{ 302{
302 reg->reg32 = reg->raw = baseAddr->BAR[barNum]; 303 reg->reg32 = reg->raw = baseAddr->BAR[barNum];
303 return pcie_RET_OK; 304 return pcie_RET_OK;
304} /* pcie_read_type0Bar32bit_reg */ 305} /* pciev0_read_type0Bar32bit_reg */
305 306
306/***************************************************************************** 307/*****************************************************************************
307 * Combine and write the BAR 32bits register 308 * Combine and write the BAR 32bits register
308 ****************************************************************************/ 309 ****************************************************************************/
309pcieRet_e pcie_write_type0Bar32bit_reg 310pcieRet_e pciev0_write_type0Bar32bit_reg
310( 311(
311 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 312 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
312 pcieBar32bitReg_t *reg, 313 pcieBar32bitReg_t *reg,
@@ -315,13 +316,13 @@ pcieRet_e pcie_write_type0Bar32bit_reg
315{ 316{
316 baseAddr->BAR[barNum] = reg->raw = reg->reg32; 317 baseAddr->BAR[barNum] = reg->raw = reg->reg32;
317 return pcie_RET_OK; 318 return pcie_RET_OK;
318} /* pcie_write_type0Bar32bit_reg */ 319} /* pciev0_write_type0Bar32bit_reg */
319 320
320 321
321/***************************************************************************** 322/*****************************************************************************
322 * Read and split up the Subsystem and Subsystem Vendor ID register 323 * Read and split up the Subsystem and Subsystem Vendor ID register
323 ****************************************************************************/ 324 ****************************************************************************/
324pcieRet_e pcie_read_subId_reg 325pcieRet_e pciev0_read_subId_reg
325( 326(
326 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 327 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
327 pcieSubIdReg_t *reg 328 pcieSubIdReg_t *reg
@@ -333,12 +334,12 @@ pcieRet_e pcie_read_subId_reg
333 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_SUBSYS_VNDR_ID_SUBSYSTEM_VENDOR_ID, reg->subVndId); 334 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_SUBSYS_VNDR_ID_SUBSYSTEM_VENDOR_ID, reg->subVndId);
334 335
335 return pcie_RET_OK; 336 return pcie_RET_OK;
336} /* pcie_read_subId_reg */ 337} /* pciev0_read_subId_reg */
337 338
338/***************************************************************************** 339/*****************************************************************************
339 * Combine and write the Subsystem and Subsystem Vendor ID register 340 * Combine and write the Subsystem and Subsystem Vendor ID register
340 ****************************************************************************/ 341 ****************************************************************************/
341pcieRet_e pcie_write_subId_reg 342pcieRet_e pciev0_write_subId_reg
342( 343(
343 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 344 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
344 pcieSubIdReg_t *reg 345 pcieSubIdReg_t *reg
@@ -353,13 +354,13 @@ pcieRet_e pcie_write_subId_reg
353 baseAddr->SUBSYS_VNDR_ID = reg->raw = new_val; 354 baseAddr->SUBSYS_VNDR_ID = reg->raw = new_val;
354 355
355 return pcie_range_check_return; 356 return pcie_range_check_return;
356} /* pcie_write_subId_reg */ 357} /* pciev0_write_subId_reg */
357 358
358 359
359/***************************************************************************** 360/*****************************************************************************
360 * Read and split up the Expansion ROM Base Address register 361 * Read and split up the Expansion ROM Base Address register
361 ****************************************************************************/ 362 ****************************************************************************/
362pcieRet_e pcie_read_expRom_reg 363pcieRet_e pciev0_read_expRom_reg
363( 364(
364 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 365 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
365 pcieExpRomReg_t *reg 366 pcieExpRomReg_t *reg
@@ -371,12 +372,12 @@ pcieRet_e pcie_read_expRom_reg
371 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_EXPNSN_ROM_EXPANSION_ROM_ENABLE, reg->enable); 372 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_EXPNSN_ROM_EXPANSION_ROM_ENABLE, reg->enable);
372 373
373 return pcie_RET_OK; 374 return pcie_RET_OK;
374} /* pcie_read_expRom_reg */ 375} /* pciev0_read_expRom_reg */
375 376
376/***************************************************************************** 377/*****************************************************************************
377 * Combine and write the Expansion ROM Base Address register 378 * Combine and write the Expansion ROM Base Address register
378 ****************************************************************************/ 379 ****************************************************************************/
379pcieRet_e pcie_write_expRom_reg 380pcieRet_e pciev0_write_expRom_reg
380( 381(
381 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 382 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
382 pcieExpRomReg_t *reg 383 pcieExpRomReg_t *reg
@@ -391,13 +392,13 @@ pcieRet_e pcie_write_expRom_reg
391 baseAddr->EXPNSN_ROM = reg->raw = new_val; 392 baseAddr->EXPNSN_ROM = reg->raw = new_val;
392 393
393 return pcie_range_check_return; 394 return pcie_range_check_return;
394} /* pcie_write_expRom_reg */ 395} /* pciev0_write_expRom_reg */
395 396
396 397
397/***************************************************************************** 398/*****************************************************************************
398 * Read and split up the Capabilities Pointer register 399 * Read and split up the Capabilities Pointer register
399 ****************************************************************************/ 400 ****************************************************************************/
400pcieRet_e pcie_read_capPtr_reg 401pcieRet_e pciev0_read_capPtr_reg
401( 402(
402 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 403 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
403 pcieCapPtrReg_t *reg 404 pcieCapPtrReg_t *reg
@@ -408,12 +409,12 @@ pcieRet_e pcie_read_capPtr_reg
408 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_CAP_PTR_CAP_PTR, reg->ptr); 409 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_CAP_PTR_CAP_PTR, reg->ptr);
409 410
410 return pcie_RET_OK; 411 return pcie_RET_OK;
411} /* pcie_read_capPtr_reg */ 412} /* pciev0_read_capPtr_reg */
412 413
413/***************************************************************************** 414/*****************************************************************************
414 * Combine and write the Capabilities Pointer register 415 * Combine and write the Capabilities Pointer register
415 ****************************************************************************/ 416 ****************************************************************************/
416pcieRet_e pcie_write_capPtr_reg 417pcieRet_e pciev0_write_capPtr_reg
417( 418(
418 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 419 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
419 pcieCapPtrReg_t *reg 420 pcieCapPtrReg_t *reg
@@ -427,13 +428,13 @@ pcieRet_e pcie_write_capPtr_reg
427 baseAddr->CAP_PTR = reg->raw = new_val; 428 baseAddr->CAP_PTR = reg->raw = new_val;
428 429
429 return pcie_range_check_return; 430 return pcie_range_check_return;
430} /* pcie_write_capPtr_reg */ 431} /* pciev0_write_capPtr_reg */
431 432
432 433
433/***************************************************************************** 434/*****************************************************************************
434 * Read and split up the Interrupt Pin register 435 * Read and split up the Interrupt Pin register
435 ****************************************************************************/ 436 ****************************************************************************/
436pcieRet_e pcie_read_intPin_reg 437pcieRet_e pciev0_read_intPin_reg
437( 438(
438 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 439 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
439 pcieIntPinReg_t *reg 440 pcieIntPinReg_t *reg
@@ -445,12 +446,12 @@ pcieRet_e pcie_read_intPin_reg
445 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_INT_PIN_INT_LINE, reg->intLine); 446 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_INT_PIN_INT_LINE, reg->intLine);
446 447
447 return pcie_RET_OK; 448 return pcie_RET_OK;
448} /* pcie_read_intPin_reg */ 449} /* pciev0_read_intPin_reg */
449 450
450/***************************************************************************** 451/*****************************************************************************
451 * Combine and write the Interrupt Pin register 452 * Combine and write the Interrupt Pin register
452 ****************************************************************************/ 453 ****************************************************************************/
453pcieRet_e pcie_write_intPin_reg 454pcieRet_e pciev0_write_intPin_reg
454( 455(
455 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 456 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
456 pcieIntPinReg_t *reg 457 pcieIntPinReg_t *reg
@@ -465,7 +466,7 @@ pcieRet_e pcie_write_intPin_reg
465 baseAddr->INT_PIN = reg->raw = new_val; 466 baseAddr->INT_PIN = reg->raw = new_val;
466 467
467 return pcie_range_check_return; 468 return pcie_range_check_return;
468} /* pcie_write_intPin_reg */ 469} /* pciev0_write_intPin_reg */
469 470
470 471
471 472
@@ -475,7 +476,7 @@ pcieRet_e pcie_write_intPin_reg
475/***************************************************************************** 476/*****************************************************************************
476 * Read and split up the BIST, Header Type, Latency Time, and Cache Line Size register 477 * Read and split up the BIST, Header Type, Latency Time, and Cache Line Size register
477 ****************************************************************************/ 478 ****************************************************************************/
478pcieRet_e pcie_read_type1BistHeader_reg 479pcieRet_e pciev0_read_type1BistHeader_reg
479( 480(
480 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr, 481 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
481 pcieType1BistHeaderReg_t *reg 482 pcieType1BistHeaderReg_t *reg
@@ -492,12 +493,12 @@ pcieRet_e pcie_read_type1BistHeader_reg
492 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BIST_HEADER_CACHE_LINE_SIZE, reg->cacheLnSize); 493 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BIST_HEADER_CACHE_LINE_SIZE, reg->cacheLnSize);
493 494
494 return pcie_RET_OK; 495 return pcie_RET_OK;
495} /* pcie_read_type1BistHeader_reg */ 496} /* pciev0_read_type1BistHeader_reg */
496 497
497/***************************************************************************** 498/*****************************************************************************
498 * Combine and write the BIST, Header Type, Latency Time, and Cache Line Size register 499 * Combine and write the BIST, Header Type, Latency Time, and Cache Line Size register
499 ****************************************************************************/ 500 ****************************************************************************/
500pcieRet_e pcie_write_type1BistHeader_reg 501pcieRet_e pciev0_write_type1BistHeader_reg
501( 502(
502 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr, 503 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
503 pcieType1BistHeaderReg_t *reg 504 pcieType1BistHeaderReg_t *reg
@@ -517,12 +518,12 @@ pcieRet_e pcie_write_type1BistHeader_reg
517 baseAddr->BIST_HEADER = reg->raw = new_val; 518 baseAddr->BIST_HEADER = reg->raw = new_val;
518 519
519 return pcie_range_check_return; 520 return pcie_range_check_return;
520} /* pcie_write_type1BistHeader_reg */ 521} /* pciev0_write_type1BistHeader_reg */
521 522
522/***************************************************************************** 523/*****************************************************************************
523 * Read and split up the BAR register 524 * Read and split up the BAR register
524 ****************************************************************************/ 525 ****************************************************************************/
525pcieRet_e pcie_read_type1Bar_reg 526pcieRet_e pciev0_read_type1Bar_reg
526( 527(
527 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr, 528 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
528 pcieBarReg_t *reg, 529 pcieBarReg_t *reg,
@@ -537,12 +538,12 @@ pcieRet_e pcie_read_type1Bar_reg
537 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BAR_MEMORY_SPACE, reg->memSpace); 538 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BAR_MEMORY_SPACE, reg->memSpace);
538 539
539 return pcie_RET_OK; 540 return pcie_RET_OK;
540} /* pcie_read_type1Bar_reg */ 541} /* pciev0_read_type1Bar_reg */
541 542
542/***************************************************************************** 543/*****************************************************************************
543 * Combine and write the BAR register 544 * Combine and write the BAR register
544 ****************************************************************************/ 545 ****************************************************************************/
545pcieRet_e pcie_write_type1Bar_reg 546pcieRet_e pciev0_write_type1Bar_reg
546( 547(
547 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr, 548 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
548 pcieBarReg_t *reg, 549 pcieBarReg_t *reg,
@@ -559,12 +560,12 @@ pcieRet_e pcie_write_type1Bar_reg
559 560
560 baseAddr->BAR[barNum] = reg->raw = new_val; 561 baseAddr->BAR[barNum] = reg->raw = new_val;
561 return pcie_range_check_return; 562 return pcie_range_check_return;
562} /* pcie_write_type1Bar_reg */ 563} /* pciev0_write_type1Bar_reg */
563 564
564/***************************************************************************** 565/*****************************************************************************
565 * Read and split up the BAR 32bits register 566 * Read and split up the BAR 32bits register
566 ****************************************************************************/ 567 ****************************************************************************/
567pcieRet_e pcie_read_type1Bar32bit_reg 568pcieRet_e pciev0_read_type1Bar32bit_reg
568( 569(
569 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr, 570 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
570 pcieBar32bitReg_t *reg, 571 pcieBar32bitReg_t *reg,
@@ -573,12 +574,12 @@ pcieRet_e pcie_read_type1Bar32bit_reg
573{ 574{
574 reg->reg32 = reg->raw = baseAddr->BAR[barNum]; 575 reg->reg32 = reg->raw = baseAddr->BAR[barNum];
575 return pcie_RET_OK; 576 return pcie_RET_OK;
576} /* pcie_read_type1Bar32bit_reg */ 577} /* pciev0_read_type1Bar32bit_reg */
577 578
578/***************************************************************************** 579/*****************************************************************************
579 * Combine and write the BAR 32bits register 580 * Combine and write the BAR 32bits register
580 ****************************************************************************/ 581 ****************************************************************************/
581pcieRet_e pcie_write_type1Bar32bit_reg 582pcieRet_e pciev0_write_type1Bar32bit_reg
582( 583(
583 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr, 584 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
584 pcieBar32bitReg_t *reg, 585 pcieBar32bitReg_t *reg,
@@ -588,12 +589,12 @@ pcieRet_e pcie_write_type1Bar32bit_reg
588 baseAddr->BAR[barNum] = reg->raw = reg->reg32; 589 baseAddr->BAR[barNum] = reg->raw = reg->reg32;
589 590
590 return pcie_RET_OK; 591 return pcie_RET_OK;
591} /* pcie_write_type1Bar32bit_reg */ 592} /* pciev0_write_type1Bar32bit_reg */
592 593
593/***************************************************************************** 594/*****************************************************************************
594 * Read and split up the Latency Timer and Bus Number register 595 * Read and split up the Latency Timer and Bus Number register
595 ****************************************************************************/ 596 ****************************************************************************/
596pcieRet_e pcie_read_type1BusNum_reg 597pcieRet_e pciev0_read_type1BusNum_reg
597( 598(
598 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr, 599 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
599 pcieType1BusNumReg_t *reg 600 pcieType1BusNumReg_t *reg
@@ -607,12 +608,12 @@ pcieRet_e pcie_read_type1BusNum_reg
607 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BUSNUM_PRIMARY_BUS_NUMBER, reg->priBusNum); 608 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BUSNUM_PRIMARY_BUS_NUMBER, reg->priBusNum);
608 609
609 return pcie_RET_OK; 610 return pcie_RET_OK;
610} /* pcie_read_type1BusNum_reg */ 611} /* pciev0_read_type1BusNum_reg */
611 612
612/***************************************************************************** 613/*****************************************************************************
613 * Combine and write the Latency Timer and Bus Number register 614 * Combine and write the Latency Timer and Bus Number register
614 ****************************************************************************/ 615 ****************************************************************************/
615pcieRet_e pcie_write_type1BusNum_reg 616pcieRet_e pciev0_write_type1BusNum_reg
616( 617(
617 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr, 618 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
618 pcieType1BusNumReg_t *reg 619 pcieType1BusNumReg_t *reg
@@ -628,12 +629,12 @@ pcieRet_e pcie_write_type1BusNum_reg
628 629
629 baseAddr->BUSNUM = reg->raw = new_val; 630 baseAddr->BUSNUM = reg->raw = new_val;
630 return pcie_range_check_return; 631 return pcie_range_check_return;
631} /* pcie_write_type1BusNum_reg */ 632} /* pciev0_write_type1BusNum_reg */
632 633
633/***************************************************************************** 634/*****************************************************************************
634 * Read and split up the Secondary Status and IO Base/Limit Register 635 * Read and split up the Secondary Status and IO Base/Limit Register
635 ****************************************************************************/ 636 ****************************************************************************/
636pcieRet_e pcie_read_type1SecStat_reg 637pcieRet_e pciev0_read_type1SecStat_reg
637( 638(
638 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr, 639 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
639 pcieType1SecStatReg_t *reg 640 pcieType1SecStatReg_t *reg
@@ -653,12 +654,12 @@ pcieRet_e pcie_read_type1SecStat_reg
653 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SECSTAT_IO_ADDRESSING2, reg->IOBaseAddr); 654 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SECSTAT_IO_ADDRESSING2, reg->IOBaseAddr);
654 655
655 return pcie_RET_OK; 656 return pcie_RET_OK;
656} /* pcie_read_type1SecStat_reg */ 657} /* pciev0_read_type1SecStat_reg */
657 658
658/***************************************************************************** 659/*****************************************************************************
659 * Combine and write the Secondary Status and IO Base/Limit Register 660 * Combine and write the Secondary Status and IO Base/Limit Register
660 ****************************************************************************/ 661 ****************************************************************************/
661pcieRet_e pcie_write_type1SecStat_reg 662pcieRet_e pciev0_write_type1SecStat_reg
662( 663(
663 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr, 664 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
664 pcieType1SecStatReg_t *reg 665 pcieType1SecStatReg_t *reg
@@ -680,12 +681,12 @@ pcieRet_e pcie_write_type1SecStat_reg
680 681
681 baseAddr->SECSTAT = reg->raw = new_val; 682 baseAddr->SECSTAT = reg->raw = new_val;
682 return pcie_range_check_return; 683 return pcie_range_check_return;
683} /* pcie_write_type1SecStat_reg */ 684} /* pciev0_write_type1SecStat_reg */
684 685
685/***************************************************************************** 686/*****************************************************************************
686 * Read and split up the Memory Limit and Base register 687 * Read and split up the Memory Limit and Base register
687 ****************************************************************************/ 688 ****************************************************************************/
688pcieRet_e pcie_read_type1Memspace_reg 689pcieRet_e pciev0_read_type1Memspace_reg
689( 690(
690 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr, 691 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
691 pcieType1MemspaceReg_t *reg 692 pcieType1MemspaceReg_t *reg
@@ -697,12 +698,12 @@ pcieRet_e pcie_read_type1Memspace_reg
697 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_MEMSPACE_MEMORY_BASE, reg->base); 698 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_MEMSPACE_MEMORY_BASE, reg->base);
698 699
699 return pcie_RET_OK; 700 return pcie_RET_OK;
700} /* pcie_read_type1Memspace_reg */ 701} /* pciev0_read_type1Memspace_reg */
701 702
702/***************************************************************************** 703/*****************************************************************************
703 * Combine and write the Memory Limit and Base register 704 * Combine and write the Memory Limit and Base register
704 ****************************************************************************/ 705 ****************************************************************************/
705pcieRet_e pcie_write_type1Memspace_reg 706pcieRet_e pciev0_write_type1Memspace_reg
706( 707(
707 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr, 708 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
708 pcieType1MemspaceReg_t *reg 709 pcieType1MemspaceReg_t *reg
@@ -716,12 +717,12 @@ pcieRet_e pcie_write_type1Memspace_reg
716 717
717 baseAddr->MEMSPACE = reg->raw = new_val; 718 baseAddr->MEMSPACE = reg->raw = new_val;
718 return pcie_range_check_return; 719 return pcie_range_check_return;
719} /* pcie_write_type1Memspace_reg */ 720} /* pciev0_write_type1Memspace_reg */
720 721
721/***************************************************************************** 722/*****************************************************************************
722 * Read and split up the Prefetchable Memory Limit and Base register 723 * Read and split up the Prefetchable Memory Limit and Base register
723 ****************************************************************************/ 724 ****************************************************************************/
724pcieRet_e pcie_read_prefMem_reg 725pcieRet_e pciev0_read_prefMem_reg
725( 726(
726 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr, 727 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
727 pciePrefMemReg_t *reg 728 pciePrefMemReg_t *reg
@@ -735,12 +736,12 @@ pcieRet_e pcie_read_prefMem_reg
735 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_PREFETCH_MEM_MEMORY_ADDRESSING2, reg->baseAddr); 736 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_PREFETCH_MEM_MEMORY_ADDRESSING2, reg->baseAddr);
736 737
737 return pcie_RET_OK; 738 return pcie_RET_OK;
738} /* pcie_read_prefMem_reg */ 739} /* pciev0_read_prefMem_reg */
739 740
740/***************************************************************************** 741/*****************************************************************************
741 * Combine and write the Prefetchable Memory Limit and Base register 742 * Combine and write the Prefetchable Memory Limit and Base register
742 ****************************************************************************/ 743 ****************************************************************************/
743pcieRet_e pcie_write_prefMem_reg 744pcieRet_e pciev0_write_prefMem_reg
744( 745(
745 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr, 746 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
746 pciePrefMemReg_t *reg 747 pciePrefMemReg_t *reg
@@ -756,12 +757,12 @@ pcieRet_e pcie_write_prefMem_reg
756 757
757 baseAddr->PREFETCH_MEM = reg->raw = new_val; 758 baseAddr->PREFETCH_MEM = reg->raw = new_val;
758 return pcie_range_check_return; 759 return pcie_range_check_return;
759} /* pcie_write_prefMem_reg */ 760} /* pciev0_write_prefMem_reg */
760 761
761/***************************************************************************** 762/*****************************************************************************
762 * Read and split up the Prefetchable Memory Base Upper register 763 * Read and split up the Prefetchable Memory Base Upper register
763 ****************************************************************************/ 764 ****************************************************************************/
764pcieRet_e pcie_read_prefBaseUpper_reg 765pcieRet_e pciev0_read_prefBaseUpper_reg
765( 766(
766 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr, 767 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
767 pciePrefBaseUpperReg_t *reg 768 pciePrefBaseUpperReg_t *reg
@@ -772,12 +773,12 @@ pcieRet_e pcie_read_prefBaseUpper_reg
772 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_PREFETCH_BASE_BASE_ADDRESS, reg->base); 773 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_PREFETCH_BASE_BASE_ADDRESS, reg->base);
773 774
774 return pcie_RET_OK; 775 return pcie_RET_OK;
775} /* pcie_read_prefBaseUp_reg */ 776} /* pciev0_read_prefBaseUp_reg */
776 777
777/***************************************************************************** 778/*****************************************************************************
778 * Combine and write the Prefetchable Memory Base Upper register 779 * Combine and write the Prefetchable Memory Base Upper register
779 ****************************************************************************/ 780 ****************************************************************************/
780pcieRet_e pcie_write_prefBaseUpper_reg 781pcieRet_e pciev0_write_prefBaseUpper_reg
781( 782(
782 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr, 783 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
783 pciePrefBaseUpperReg_t *reg 784 pciePrefBaseUpperReg_t *reg
@@ -790,13 +791,13 @@ pcieRet_e pcie_write_prefBaseUpper_reg
790 791
791 baseAddr->PREFETCH_BASE = reg->raw = new_val; 792 baseAddr->PREFETCH_BASE = reg->raw = new_val;
792 return pcie_range_check_return; 793 return pcie_range_check_return;
793} /* pcie_write_prefBaseUp_reg */ 794} /* pciev0_write_prefBaseUp_reg */
794 795
795 796
796/***************************************************************************** 797/*****************************************************************************
797 * Read and split up the Prefetchable Memory Limit Upper register 798 * Read and split up the Prefetchable Memory Limit Upper register
798 ****************************************************************************/ 799 ****************************************************************************/
799pcieRet_e pcie_read_prefLimitUpper_reg 800pcieRet_e pciev0_read_prefLimitUpper_reg
800( 801(
801 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr, 802 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
802 pciePrefLimitUpperReg_t *reg 803 pciePrefLimitUpperReg_t *reg
@@ -807,12 +808,12 @@ pcieRet_e pcie_read_prefLimitUpper_reg
807 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_PREFETCH_LIMIT_LIMIT_ADDRESS, reg->limit); 808 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_PREFETCH_LIMIT_LIMIT_ADDRESS, reg->limit);
808 809
809 return pcie_RET_OK; 810 return pcie_RET_OK;
810} /* pcie_read_prefLimitUp_reg */ 811} /* pciev0_read_prefLimitUp_reg */
811 812
812/***************************************************************************** 813/*****************************************************************************
813 * Combine and write the Prefetchable Memory Limit Upper register 814 * Combine and write the Prefetchable Memory Limit Upper register
814 ****************************************************************************/ 815 ****************************************************************************/
815pcieRet_e pcie_write_prefLimitUpper_reg 816pcieRet_e pciev0_write_prefLimitUpper_reg
816( 817(
817 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr, 818 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
818 pciePrefLimitUpperReg_t *reg 819 pciePrefLimitUpperReg_t *reg
@@ -825,12 +826,12 @@ pcieRet_e pcie_write_prefLimitUpper_reg
825 826
826 baseAddr->PREFETCH_LIMIT = reg->raw = new_val; 827 baseAddr->PREFETCH_LIMIT = reg->raw = new_val;
827 return pcie_range_check_return; 828 return pcie_range_check_return;
828} /* pcie_write_prefLimitUp_reg */ 829} /* pciev0_write_prefLimitUp_reg */
829 830
830/***************************************************************************** 831/*****************************************************************************
831 * Read and split up the IO Base and Limit Upper 16 bits register 832 * Read and split up the IO Base and Limit Upper 16 bits register
832 ****************************************************************************/ 833 ****************************************************************************/
833pcieRet_e pcie_read_type1IOSpace_reg 834pcieRet_e pciev0_read_type1IOSpace_reg
834( 835(
835 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr, 836 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
836 pcieType1IOSpaceReg_t *reg 837 pcieType1IOSpaceReg_t *reg
@@ -842,12 +843,12 @@ pcieRet_e pcie_read_type1IOSpace_reg
842 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_IOSPACE_IOLIMIT, reg->IOLimit); 843 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_IOSPACE_IOLIMIT, reg->IOLimit);
843 844
844 return pcie_RET_OK; 845 return pcie_RET_OK;
845} /* pcie_read_type1IOSpace_reg */ 846} /* pciev0_read_type1IOSpace_reg */
846 847
847/***************************************************************************** 848/*****************************************************************************
848 * Combine and write the IO Base and Limit Upper 16 bits register 849 * Combine and write the IO Base and Limit Upper 16 bits register
849 ****************************************************************************/ 850 ****************************************************************************/
850pcieRet_e pcie_write_type1IOSpace_reg 851pcieRet_e pciev0_write_type1IOSpace_reg
851( 852(
852 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr, 853 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
853 pcieType1IOSpaceReg_t *reg 854 pcieType1IOSpaceReg_t *reg
@@ -861,12 +862,12 @@ pcieRet_e pcie_write_type1IOSpace_reg
861 862
862 baseAddr->IOSPACE = reg->raw = new_val; 863 baseAddr->IOSPACE = reg->raw = new_val;
863 return pcie_range_check_return; 864 return pcie_range_check_return;
864} /* pcie_write_type1IOSpace_reg */ 865} /* pciev0_write_type1IOSpace_reg */
865 866
866/***************************************************************************** 867/*****************************************************************************
867 * Read and split up the Capabilities Pointer register 868 * Read and split up the Capabilities Pointer register
868 ****************************************************************************/ 869 ****************************************************************************/
869pcieRet_e pcie_read_type1CapPtr_reg 870pcieRet_e pciev0_read_type1CapPtr_reg
870( 871(
871 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr, 872 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
872 pcieType1CapPtrReg_t *reg 873 pcieType1CapPtrReg_t *reg
@@ -877,12 +878,12 @@ pcieRet_e pcie_read_type1CapPtr_reg
877 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_CAP_PTR_CAP_PTR, reg->capPtr); 878 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_CAP_PTR_CAP_PTR, reg->capPtr);
878 879
879 return pcie_RET_OK; 880 return pcie_RET_OK;
880} /* pcie_read_type1CapPtr_reg */ 881} /* pciev0_read_type1CapPtr_reg */
881 882
882/***************************************************************************** 883/*****************************************************************************
883 * Combine and write the Capabilities Pointer register 884 * Combine and write the Capabilities Pointer register
884 ****************************************************************************/ 885 ****************************************************************************/
885pcieRet_e pcie_write_type1CapPtr_reg 886pcieRet_e pciev0_write_type1CapPtr_reg
886( 887(
887 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr, 888 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
888 pcieType1CapPtrReg_t *reg 889 pcieType1CapPtrReg_t *reg
@@ -895,12 +896,12 @@ pcieRet_e pcie_write_type1CapPtr_reg
895 896
896 baseAddr->CAP_PTR = reg->raw = new_val; 897 baseAddr->CAP_PTR = reg->raw = new_val;
897 return pcie_range_check_return; 898 return pcie_range_check_return;
898} /* pcie_write_type1CapPtr_reg */ 899} /* pciev0_write_type1CapPtr_reg */
899 900
900/***************************************************************************** 901/*****************************************************************************
901 * Read and split up the Expansion ROM Base Address register 902 * Read and split up the Expansion ROM Base Address register
902 ****************************************************************************/ 903 ****************************************************************************/
903pcieRet_e pcie_read_type1ExpnsnRom_reg 904pcieRet_e pciev0_read_type1ExpnsnRom_reg
904( 905(
905 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr, 906 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
906 pcieType1ExpnsnRomReg_t *reg 907 pcieType1ExpnsnRomReg_t *reg
@@ -912,12 +913,12 @@ pcieRet_e pcie_read_type1ExpnsnRom_reg
912 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_EXPNSN_ROM_EXPANSION_ROM_ENABLE, reg->expRomEn); 913 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_EXPNSN_ROM_EXPANSION_ROM_ENABLE, reg->expRomEn);
913 914
914 return pcie_RET_OK; 915 return pcie_RET_OK;
915} /* pcie_read_type1ExpnsnRom_reg */ 916} /* pciev0_read_type1ExpnsnRom_reg */
916 917
917/***************************************************************************** 918/*****************************************************************************
918 * Combine and write the Expansion ROM Base Address register 919 * Combine and write the Expansion ROM Base Address register
919 ****************************************************************************/ 920 ****************************************************************************/
920pcieRet_e pcie_write_type1ExpnsnRom_reg 921pcieRet_e pciev0_write_type1ExpnsnRom_reg
921( 922(
922 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr, 923 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
923 pcieType1ExpnsnRomReg_t *reg 924 pcieType1ExpnsnRomReg_t *reg
@@ -931,12 +932,12 @@ pcieRet_e pcie_write_type1ExpnsnRom_reg
931 932
932 baseAddr->EXPNSN_ROM = reg->raw = new_val; 933 baseAddr->EXPNSN_ROM = reg->raw = new_val;
933 return pcie_range_check_return; 934 return pcie_range_check_return;
934} /* pcie_write_type1ExpnsnRom_reg */ 935} /* pciev0_write_type1ExpnsnRom_reg */
935 936
936/***************************************************************************** 937/*****************************************************************************
937 * Read and split up the Bridge Control and Interrupt register 938 * Read and split up the Bridge Control and Interrupt register
938 ****************************************************************************/ 939 ****************************************************************************/
939pcieRet_e pcie_read_type1BridgeInt_reg 940pcieRet_e pciev0_read_type1BridgeInt_reg
940( 941(
941 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr, 942 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
942 pcieType1BridgeIntReg_t *reg 943 pcieType1BridgeIntReg_t *reg
@@ -960,12 +961,12 @@ pcieRet_e pcie_read_type1BridgeInt_reg
960 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BRIDGE_INT_INT_LINE, reg->intLine); 961 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BRIDGE_INT_INT_LINE, reg->intLine);
961 962
962 return pcie_RET_OK; 963 return pcie_RET_OK;
963} /* pcie_read_type1BridgeInt_reg */ 964} /* pciev0_read_type1BridgeInt_reg */
964 965
965/***************************************************************************** 966/*****************************************************************************
966 * Combine and write the Bridge Control and Interrupt register 967 * Combine and write the Bridge Control and Interrupt register
967 ****************************************************************************/ 968 ****************************************************************************/
968pcieRet_e pcie_write_type1BridgeInt_reg 969pcieRet_e pciev0_write_type1BridgeInt_reg
969( 970(
970 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr, 971 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
971 pcieType1BridgeIntReg_t *reg 972 pcieType1BridgeIntReg_t *reg
@@ -991,7 +992,7 @@ pcieRet_e pcie_write_type1BridgeInt_reg
991 992
992 baseAddr->BRIDGE_INT = reg->raw = new_val; 993 baseAddr->BRIDGE_INT = reg->raw = new_val;
993 return pcie_range_check_return; 994 return pcie_range_check_return;
994} /* pcie_write_type1BridgeInt_reg */ 995} /* pciev0_write_type1BridgeInt_reg */
995 996
996/***************************************************************************** 997/*****************************************************************************
997 ********** Power Management Capability Registers *************************** 998 ********** Power Management Capability Registers ***************************
@@ -1006,7 +1007,7 @@ pcieRet_e pcie_write_type1BridgeInt_reg
1006/***************************************************************************** 1007/*****************************************************************************
1007 * Read and split up the Power Management Capability register 1008 * Read and split up the Power Management Capability register
1008 ****************************************************************************/ 1009 ****************************************************************************/
1009pcieRet_e pcie_read_pmCap_reg 1010pcieRet_e pciev0_read_pmCap_reg
1010( 1011(
1011 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 1012 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1012 pciePMCapReg_t *reg 1013 pciePMCapReg_t *reg
@@ -1025,12 +1026,12 @@ pcieRet_e pcie_read_pmCap_reg
1025 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PMCAP_PM_CAP_ID, reg->pmCapID); 1026 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PMCAP_PM_CAP_ID, reg->pmCapID);
1026 1027
1027 return pcie_RET_OK; 1028 return pcie_RET_OK;
1028} /* pcie_read_pmCap_reg */ 1029} /* pciev0_read_pmCap_reg */
1029 1030
1030/***************************************************************************** 1031/*****************************************************************************
1031 * Combine and write the Power Management Capability register 1032 * Combine and write the Power Management Capability register
1032 ****************************************************************************/ 1033 ****************************************************************************/
1033pcieRet_e pcie_write_pmCap_reg 1034pcieRet_e pciev0_write_pmCap_reg
1034( 1035(
1035 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 1036 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1036 pciePMCapReg_t *reg 1037 pciePMCapReg_t *reg
@@ -1051,12 +1052,12 @@ pcieRet_e pcie_write_pmCap_reg
1051 1052
1052 baseAddr->PMCAP = reg->raw = new_val; 1053 baseAddr->PMCAP = reg->raw = new_val;
1053 return pcie_range_check_return; 1054 return pcie_range_check_return;
1054} /* pcie_write_pmCap_reg */ 1055} /* pciev0_write_pmCap_reg */
1055 1056
1056/***************************************************************************** 1057/*****************************************************************************
1057 * Read and split up the Power Management Capabilties Control and Status register 1058 * Read and split up the Power Management Capabilties Control and Status register
1058 ****************************************************************************/ 1059 ****************************************************************************/
1059pcieRet_e pcie_read_pmCapCtlStat_reg 1060pcieRet_e pciev0_read_pmCapCtlStat_reg
1060( 1061(
1061 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 1062 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1062 pciePMCapCtlStatReg_t *reg 1063 pciePMCapCtlStatReg_t *reg
@@ -1075,12 +1076,12 @@ pcieRet_e pcie_read_pmCapCtlStat_reg
1075 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PM_CTL_STAT_PWR_STATE, reg->pwrState); 1076 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PM_CTL_STAT_PWR_STATE, reg->pwrState);
1076 1077
1077 return pcie_RET_OK; 1078 return pcie_RET_OK;
1078} /* pcie_read_pmCapCtlStat_reg */ 1079} /* pciev0_read_pmCapCtlStat_reg */
1079 1080
1080/***************************************************************************** 1081/*****************************************************************************
1081 * Combine and write the Power Management Capabilties Control and Status register 1082 * Combine and write the Power Management Capabilties Control and Status register
1082 ****************************************************************************/ 1083 ****************************************************************************/
1083pcieRet_e pcie_write_pmCapCtlStat_reg 1084pcieRet_e pciev0_write_pmCapCtlStat_reg
1084( 1085(
1085 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 1086 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1086 pciePMCapCtlStatReg_t *reg 1087 pciePMCapCtlStatReg_t *reg
@@ -1101,7 +1102,7 @@ pcieRet_e pcie_write_pmCapCtlStat_reg
1101 1102
1102 baseAddr->PM_CTL_STAT = reg->raw = new_val; 1103 baseAddr->PM_CTL_STAT = reg->raw = new_val;
1103 return pcie_range_check_return; 1104 return pcie_range_check_return;
1104} /* pcie_write_pmCapCtlStat_reg */ 1105} /* pciev0_write_pmCapCtlStat_reg */
1105 1106
1106/***************************************************************************** 1107/*****************************************************************************
1107 ********** Message Signaling Interrupt REGISTERS ************************* 1108 ********** Message Signaling Interrupt REGISTERS *************************
@@ -1117,7 +1118,7 @@ pcieRet_e pcie_write_pmCapCtlStat_reg
1117/***************************************************************************** 1118/*****************************************************************************
1118 * Read and split up the MSI Capabilities register 1119 * Read and split up the MSI Capabilities register
1119 ****************************************************************************/ 1120 ****************************************************************************/
1120pcieRet_e pcie_read_msiCap_reg 1121pcieRet_e pciev0_read_msiCap_reg
1121( 1122(
1122 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 1123 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1123 pcieMsiCapReg_t *reg 1124 pcieMsiCapReg_t *reg
@@ -1133,12 +1134,12 @@ pcieRet_e pcie_read_msiCap_reg
1133 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_MSI_CAP_CAP_ID, reg->capId); 1134 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_MSI_CAP_CAP_ID, reg->capId);
1134 1135
1135 return pcie_RET_OK; 1136 return pcie_RET_OK;
1136} /* pcie_read_msiCap_reg */ 1137} /* pciev0_read_msiCap_reg */
1137 1138
1138/***************************************************************************** 1139/*****************************************************************************
1139 * Combine and write the MSI Capabilities register 1140 * Combine and write the MSI Capabilities register
1140 ****************************************************************************/ 1141 ****************************************************************************/
1141pcieRet_e pcie_write_msiCap_reg 1142pcieRet_e pciev0_write_msiCap_reg
1142( 1143(
1143 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 1144 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1144 pcieMsiCapReg_t *reg 1145 pcieMsiCapReg_t *reg
@@ -1156,13 +1157,13 @@ pcieRet_e pcie_write_msiCap_reg
1156 1157
1157 baseAddr->MSI_CAP = reg->raw = new_val; 1158 baseAddr->MSI_CAP = reg->raw = new_val;
1158 return pcie_range_check_return; 1159 return pcie_range_check_return;
1159} /* pcie_write_msiCap_reg */ 1160} /* pciev0_write_msiCap_reg */
1160 1161
1161 1162
1162/***************************************************************************** 1163/*****************************************************************************
1163 * Read and split up the MSI Lower 32 Bits register 1164 * Read and split up the MSI Lower 32 Bits register
1164 ****************************************************************************/ 1165 ****************************************************************************/
1165pcieRet_e pcie_read_msiLo32_reg 1166pcieRet_e pciev0_read_msiLo32_reg
1166( 1167(
1167 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 1168 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1168 pcieMsiLo32Reg_t *reg 1169 pcieMsiLo32Reg_t *reg
@@ -1173,12 +1174,12 @@ pcieRet_e pcie_read_msiLo32_reg
1173 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_MSI_LOW32_LOW32_ADDR, reg->addr); 1174 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_MSI_LOW32_LOW32_ADDR, reg->addr);
1174 1175
1175 return pcie_RET_OK; 1176 return pcie_RET_OK;
1176} /* pcie_read_msiLo32_reg */ 1177} /* pciev0_read_msiLo32_reg */
1177 1178
1178/***************************************************************************** 1179/*****************************************************************************
1179 * Combine and write the MSI Lower 32 Bits register 1180 * Combine and write the MSI Lower 32 Bits register
1180 ****************************************************************************/ 1181 ****************************************************************************/
1181pcieRet_e pcie_write_msiLo32_reg 1182pcieRet_e pciev0_write_msiLo32_reg
1182( 1183(
1183 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 1184 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1184 pcieMsiLo32Reg_t *reg 1185 pcieMsiLo32Reg_t *reg
@@ -1191,13 +1192,13 @@ pcieRet_e pcie_write_msiLo32_reg
1191 1192
1192 baseAddr->MSI_LOW32 = reg->raw = new_val; 1193 baseAddr->MSI_LOW32 = reg->raw = new_val;
1193 return pcie_range_check_return; 1194 return pcie_range_check_return;
1194} /* pcie_write_msiLo32_reg */ 1195} /* pciev0_write_msiLo32_reg */
1195 1196
1196 1197
1197/***************************************************************************** 1198/*****************************************************************************
1198 * Read and split up the MSI Upper 32 Bits register 1199 * Read and split up the MSI Upper 32 Bits register
1199 ****************************************************************************/ 1200 ****************************************************************************/
1200pcieRet_e pcie_read_msiUp32_reg 1201pcieRet_e pciev0_read_msiUp32_reg
1201( 1202(
1202 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 1203 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1203 pcieMsiUp32Reg_t *reg 1204 pcieMsiUp32Reg_t *reg
@@ -1208,12 +1209,12 @@ pcieRet_e pcie_read_msiUp32_reg
1208 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_MSI_UP32_UP32_ADDR, reg->addr); 1209 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_MSI_UP32_UP32_ADDR, reg->addr);
1209 1210
1210 return pcie_RET_OK; 1211 return pcie_RET_OK;
1211} /* pcie_read_msiUp32_reg */ 1212} /* pciev0_read_msiUp32_reg */
1212 1213
1213/***************************************************************************** 1214/*****************************************************************************
1214 * Combine and write the MSI Upper 32 Bits register 1215 * Combine and write the MSI Upper 32 Bits register
1215 ****************************************************************************/ 1216 ****************************************************************************/
1216pcieRet_e pcie_write_msiUp32_reg 1217pcieRet_e pciev0_write_msiUp32_reg
1217( 1218(
1218 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 1219 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1219 pcieMsiUp32Reg_t *reg 1220 pcieMsiUp32Reg_t *reg
@@ -1226,13 +1227,13 @@ pcieRet_e pcie_write_msiUp32_reg
1226 1227
1227 baseAddr->MSI_UP32 = reg->raw = new_val; 1228 baseAddr->MSI_UP32 = reg->raw = new_val;
1228 return pcie_range_check_return; 1229 return pcie_range_check_return;
1229} /* pcie_write_msiUp32_reg */ 1230} /* pciev0_write_msiUp32_reg */
1230 1231
1231 1232
1232/***************************************************************************** 1233/*****************************************************************************
1233 * Read and split up the MSI Data register 1234 * Read and split up the MSI Data register
1234 ****************************************************************************/ 1235 ****************************************************************************/
1235pcieRet_e pcie_read_msiData_reg 1236pcieRet_e pciev0_read_msiData_reg
1236( 1237(
1237 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 1238 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1238 pcieMsiDataReg_t *reg 1239 pcieMsiDataReg_t *reg
@@ -1243,12 +1244,12 @@ pcieRet_e pcie_read_msiData_reg
1243 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_MSI_DATA_MSI_DATA, reg->data); 1244 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_MSI_DATA_MSI_DATA, reg->data);
1244 1245
1245 return pcie_RET_OK; 1246 return pcie_RET_OK;
1246} /* pcie_read_msiData_reg */ 1247} /* pciev0_read_msiData_reg */
1247 1248
1248/***************************************************************************** 1249/*****************************************************************************
1249 * Combine and write the MSI Data register 1250 * Combine and write the MSI Data register
1250 ****************************************************************************/ 1251 ****************************************************************************/
1251pcieRet_e pcie_write_msiData_reg 1252pcieRet_e pciev0_write_msiData_reg
1252( 1253(
1253 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 1254 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1254 pcieMsiDataReg_t *reg 1255 pcieMsiDataReg_t *reg
@@ -1261,7 +1262,7 @@ pcieRet_e pcie_write_msiData_reg
1261 1262
1262 baseAddr->MSI_DATA = reg->raw = new_val; 1263 baseAddr->MSI_DATA = reg->raw = new_val;
1263 return pcie_range_check_return; 1264 return pcie_range_check_return;
1264} /* pcie_write_msiData_reg */ 1265} /* pciev0_write_msiData_reg */
1265 1266
1266 1267
1267/***************************************************************************** 1268/*****************************************************************************
@@ -1278,7 +1279,7 @@ pcieRet_e pcie_write_msiData_reg
1278/***************************************************************************** 1279/*****************************************************************************
1279 * Read and split up the PCIE Capabilities register 1280 * Read and split up the PCIE Capabilities register
1280 ****************************************************************************/ 1281 ****************************************************************************/
1281pcieRet_e pcie_read_pciesCap_reg 1282pcieRet_e pciev0_read_pciesCap_reg
1282( 1283(
1283 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 1284 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1284 pciePciesCapReg_t *reg 1285 pciePciesCapReg_t *reg
@@ -1294,13 +1295,13 @@ pcieRet_e pcie_read_pciesCap_reg
1294 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIES_CAP_CAP_ID, reg->capId); 1295 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIES_CAP_CAP_ID, reg->capId);
1295 1296
1296 return pcie_RET_OK; 1297 return pcie_RET_OK;
1297} /*pcie_read_pciesCap_reg*/ 1298} /* pciev0_read_pciesCap_reg */
1298 1299
1299 1300
1300/***************************************************************************** 1301/*****************************************************************************
1301 * Combine and write the PCIE Capabilities register 1302 * Combine and write the PCIE Capabilities register
1302 ****************************************************************************/ 1303 ****************************************************************************/
1303pcieRet_e pcie_write_pciesCap_reg 1304pcieRet_e pciev0_write_pciesCap_reg
1304( 1305(
1305 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 1306 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1306 pciePciesCapReg_t *reg 1307 pciePciesCapReg_t *reg
@@ -1319,12 +1320,12 @@ pcieRet_e pcie_write_pciesCap_reg
1319 baseAddr->PCIES_CAP = reg->raw = new_val; 1320 baseAddr->PCIES_CAP = reg->raw = new_val;
1320 1321
1321 return pcie_range_check_return; 1322 return pcie_range_check_return;
1322} /*pcie_write_pciesCap_reg*/ 1323} /* pciev0_write_pciesCap_reg */
1323 1324
1324/***************************************************************************** 1325/*****************************************************************************
1325 * Read and split up the Device Capabilities register 1326 * Read and split up the Device Capabilities register
1326 ****************************************************************************/ 1327 ****************************************************************************/
1327pcieRet_e pcie_read_deviceCap_reg 1328pcieRet_e pciev0_read_deviceCap_reg
1328( 1329(
1329 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 1330 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1330 pcieDeviceCapReg_t *reg 1331 pcieDeviceCapReg_t *reg
@@ -1342,13 +1343,13 @@ pcieRet_e pcie_read_deviceCap_reg
1342 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEVICE_CAP_MAX_PAYLD_SZ, reg->maxPayldSz); 1343 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEVICE_CAP_MAX_PAYLD_SZ, reg->maxPayldSz);
1343 1344
1344 return pcie_RET_OK; 1345 return pcie_RET_OK;
1345} /*pcie_read_deviceCap_reg*/ 1346} /* pciev0_read_deviceCap_reg */
1346 1347
1347 1348
1348/***************************************************************************** 1349/*****************************************************************************
1349 * Combine and write the Device Capabilities register 1350 * Combine and write the Device Capabilities register
1350 ****************************************************************************/ 1351 ****************************************************************************/
1351pcieRet_e pcie_write_deviceCap_reg 1352pcieRet_e pciev0_write_deviceCap_reg
1352( 1353(
1353 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 1354 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1354 pcieDeviceCapReg_t *reg 1355 pcieDeviceCapReg_t *reg
@@ -1369,12 +1370,12 @@ pcieRet_e pcie_write_deviceCap_reg
1369 baseAddr->DEVICE_CAP = reg->raw = new_val; 1370 baseAddr->DEVICE_CAP = reg->raw = new_val;
1370 1371
1371 return pcie_range_check_return; 1372 return pcie_range_check_return;
1372} /*pcie_write_deviceCap_reg*/ 1373} /* pciev0_write_deviceCap_reg */
1373 1374
1374/***************************************************************************** 1375/*****************************************************************************
1375 * Read and split up the Device Status and Control register 1376 * Read and split up the Device Status and Control register
1376 ****************************************************************************/ 1377 ****************************************************************************/
1377pcieRet_e pcie_read_devStatCtrl_reg 1378pcieRet_e pciev0_read_devStatCtrl_reg
1378( 1379(
1379 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 1380 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1380 pcieDevStatCtrlReg_t *reg 1381 pcieDevStatCtrlReg_t *reg
@@ -1401,13 +1402,13 @@ pcieRet_e pcie_read_devStatCtrl_reg
1401 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEV_STAT_CTRL_CORR_ERR_REP, reg->corErRp); 1402 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEV_STAT_CTRL_CORR_ERR_REP, reg->corErRp);
1402 1403
1403 return pcie_RET_OK; 1404 return pcie_RET_OK;
1404} /* pcie_read_devStatCtrl_reg */ 1405} /* pciev0_read_devStatCtrl_reg */
1405 1406
1406 1407
1407/***************************************************************************** 1408/*****************************************************************************
1408 * Combine and write the Device Status and Control register 1409 * Combine and write the Device Status and Control register
1409 ****************************************************************************/ 1410 ****************************************************************************/
1410pcieRet_e pcie_write_devStatCtrl_reg 1411pcieRet_e pciev0_write_devStatCtrl_reg
1411( 1412(
1412 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 1413 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1413 pcieDevStatCtrlReg_t *reg 1414 pcieDevStatCtrlReg_t *reg
@@ -1436,12 +1437,12 @@ pcieRet_e pcie_write_devStatCtrl_reg
1436 1437
1437 baseAddr->DEV_STAT_CTRL = reg->raw = new_val; 1438 baseAddr->DEV_STAT_CTRL = reg->raw = new_val;
1438 return pcie_range_check_return; 1439 return pcie_range_check_return;
1439} /* pcie_write_devStatCtrl_reg */ 1440} /* pciev0_write_devStatCtrl_reg */
1440 1441
1441/***************************************************************************** 1442/*****************************************************************************
1442 * Read and split up the Link Capabilities register 1443 * Read and split up the Link Capabilities register
1443 ****************************************************************************/ 1444 ****************************************************************************/
1444pcieRet_e pcie_read_linkCap_reg 1445pcieRet_e pciev0_read_linkCap_reg
1445( 1446(
1446 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 1447 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1447 pcieLinkCapReg_t *reg 1448 pcieLinkCapReg_t *reg
@@ -1461,13 +1462,13 @@ pcieRet_e pcie_read_linkCap_reg
1461 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_CAP_MAX_LINK_SPEED, reg->maxLinkSpeed); 1462 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_CAP_MAX_LINK_SPEED, reg->maxLinkSpeed);
1462 1463
1463 return pcie_RET_OK; 1464 return pcie_RET_OK;
1464} /*pcie_read_linkCap_reg*/ 1465} /* pciev0_read_linkCap_reg */
1465 1466
1466 1467
1467/***************************************************************************** 1468/*****************************************************************************
1468 * Combine and write the Link Capabilities register 1469 * Combine and write the Link Capabilities register
1469 ****************************************************************************/ 1470 ****************************************************************************/
1470pcieRet_e pcie_write_linkCap_reg 1471pcieRet_e pciev0_write_linkCap_reg
1471( 1472(
1472 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 1473 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1473 pcieLinkCapReg_t *reg 1474 pcieLinkCapReg_t *reg
@@ -1490,13 +1491,13 @@ pcieRet_e pcie_write_linkCap_reg
1490 baseAddr->LINK_CAP = reg->raw = new_val; 1491 baseAddr->LINK_CAP = reg->raw = new_val;
1491 1492
1492 return pcie_range_check_return; 1493 return pcie_range_check_return;
1493} /*pcie_write_linkCap_reg*/ 1494} /* pciev0_write_linkCap_reg */
1494 1495
1495 1496
1496/***************************************************************************** 1497/*****************************************************************************
1497 * Read and split up the Link Status and Control register 1498 * Read and split up the Link Status and Control register
1498 ****************************************************************************/ 1499 ****************************************************************************/
1499pcieRet_e pcie_read_linkStatCtrl_reg 1500pcieRet_e pciev0_read_linkStatCtrl_reg
1500( 1501(
1501 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 1502 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1502 pcieLinkStatCtrlReg_t *reg 1503 pcieLinkStatCtrlReg_t *reg
@@ -1524,13 +1525,13 @@ pcieRet_e pcie_read_linkStatCtrl_reg
1524 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_STAT_CTRL_ACTIVE_LINK_PM, reg->activeLinkPm); 1525 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_STAT_CTRL_ACTIVE_LINK_PM, reg->activeLinkPm);
1525 1526
1526 return pcie_RET_OK; 1527 return pcie_RET_OK;
1527} /*pcie_read_linkStatCtrl_reg*/ 1528} /* pciev0_read_linkStatCtrl_reg */
1528 1529
1529 1530
1530/***************************************************************************** 1531/*****************************************************************************
1531 * Combine and write the Link Status and Control register 1532 * Combine and write the Link Status and Control register
1532 ****************************************************************************/ 1533 ****************************************************************************/
1533pcieRet_e pcie_write_linkStatCtrl_reg 1534pcieRet_e pciev0_write_linkStatCtrl_reg
1534( 1535(
1535 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 1536 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1536 pcieLinkStatCtrlReg_t *reg 1537 pcieLinkStatCtrlReg_t *reg
@@ -1561,13 +1562,13 @@ pcieRet_e pcie_write_linkStatCtrl_reg
1561 baseAddr->LINK_STAT_CTRL = reg->raw = new_val; 1562 baseAddr->LINK_STAT_CTRL = reg->raw = new_val;
1562 1563
1563 return pcie_range_check_return; 1564 return pcie_range_check_return;
1564} /*pcie_write_linkStatCtrl_reg*/ 1565} /* pciev0_write_linkStatCtrl_reg */
1565 1566
1566 1567
1567/***************************************************************************** 1568/*****************************************************************************
1568 * Read and split up the Slot Capabilities register 1569 * Read and split up the Slot Capabilities register
1569 ****************************************************************************/ 1570 ****************************************************************************/
1570pcieRet_e pcie_read_slotCap_reg 1571pcieRet_e pciev0_read_slotCap_reg
1571( 1572(
1572 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr, 1573 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
1573 pcieSlotCapReg_t *reg 1574 pcieSlotCapReg_t *reg
@@ -1589,12 +1590,12 @@ pcieRet_e pcie_read_slotCap_reg
1589 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SLOT_CAP_ATTN_BUTTON, reg->attnButton); 1590 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SLOT_CAP_ATTN_BUTTON, reg->attnButton);
1590 1591
1591 return pcie_RET_OK; 1592 return pcie_RET_OK;
1592} /*pcie_read_slotCap_reg*/ 1593} /* pciev0_read_slotCap_reg */
1593 1594
1594/***************************************************************************** 1595/*****************************************************************************
1595 * Combine and write the Slot Capabilities register 1596 * Combine and write the Slot Capabilities register
1596 ****************************************************************************/ 1597 ****************************************************************************/
1597pcieRet_e pcie_write_slotCap_reg 1598pcieRet_e pciev0_write_slotCap_reg
1598( 1599(
1599 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr, 1600 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
1600 pcieSlotCapReg_t *reg 1601 pcieSlotCapReg_t *reg
@@ -1619,13 +1620,13 @@ pcieRet_e pcie_write_slotCap_reg
1619 baseAddr->SLOT_CAP = reg->raw = new_val; 1620 baseAddr->SLOT_CAP = reg->raw = new_val;
1620 1621
1621 return pcie_range_check_return; 1622 return pcie_range_check_return;
1622} /*pcie_write_slotCap_reg*/ 1623} /* pciev0_write_slotCap_reg */
1623 1624
1624 1625
1625/***************************************************************************** 1626/*****************************************************************************
1626 * Read and split up the Slot Status and Control register 1627 * Read and split up the Slot Status and Control register
1627 ****************************************************************************/ 1628 ****************************************************************************/
1628pcieRet_e pcie_read_slotStatCtrl_reg 1629pcieRet_e pciev0_read_slotStatCtrl_reg
1629( 1630(
1630 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr, 1631 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
1631 pcieSlotStatCtrlReg_t *reg 1632 pcieSlotStatCtrlReg_t *reg
@@ -1655,12 +1656,12 @@ pcieRet_e pcie_read_slotStatCtrl_reg
1655 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SLOT_STAT_CTRL_ATTN_BUTT_EN, reg->attnButtEn); 1656 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SLOT_STAT_CTRL_ATTN_BUTT_EN, reg->attnButtEn);
1656 1657
1657 return pcie_RET_OK; 1658 return pcie_RET_OK;
1658} /*pcie_read_slotStatCtrl_reg*/ 1659} /* pciev0_read_slotStatCtrl_reg */
1659 1660
1660/***************************************************************************** 1661/*****************************************************************************
1661 * Combine and write the Slot Status and Control register 1662 * Combine and write the Slot Status and Control register
1662 ****************************************************************************/ 1663 ****************************************************************************/
1663pcieRet_e pcie_write_slotStatCtrl_reg 1664pcieRet_e pciev0_write_slotStatCtrl_reg
1664( 1665(
1665 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr, 1666 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
1666 pcieSlotStatCtrlReg_t *reg 1667 pcieSlotStatCtrlReg_t *reg
@@ -1693,13 +1694,13 @@ pcieRet_e pcie_write_slotStatCtrl_reg
1693 baseAddr->SLOT_STAT_CTRL = reg->raw = new_val; 1694 baseAddr->SLOT_STAT_CTRL = reg->raw = new_val;
1694 1695
1695 return pcie_range_check_return; 1696 return pcie_range_check_return;
1696} /*pcie_write_slotStatCtrl_reg*/ 1697} /* pciev0_write_slotStatCtrl_reg */
1697 1698
1698 1699
1699/***************************************************************************** 1700/*****************************************************************************
1700 * Read and split up the Root Control and Capabilities register 1701 * Read and split up the Root Control and Capabilities register
1701 ****************************************************************************/ 1702 ****************************************************************************/
1702pcieRet_e pcie_read_rootCtrlCap_reg 1703pcieRet_e pciev0_read_rootCtrlCap_reg
1703( 1704(
1704 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr, 1705 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
1705 pcieRootCtrlCapReg_t *reg 1706 pcieRootCtrlCapReg_t *reg
@@ -1715,13 +1716,13 @@ pcieRet_e pcie_read_rootCtrlCap_reg
1715 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_ROOT_CTRL_CAP_SERR_EN, reg->serrEn); 1716 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_ROOT_CTRL_CAP_SERR_EN, reg->serrEn);
1716 1717
1717 return pcie_RET_OK; 1718 return pcie_RET_OK;
1718} /*pcie_read_rootCtrlCap_reg*/ 1719} /* pciev0_read_rootCtrlCap_reg */
1719 1720
1720 1721
1721/***************************************************************************** 1722/*****************************************************************************
1722 * Combine and write the Root Control and Capabilities register 1723 * Combine and write the Root Control and Capabilities register
1723 ****************************************************************************/ 1724 ****************************************************************************/
1724pcieRet_e pcie_write_rootCtrlCap_reg 1725pcieRet_e pciev0_write_rootCtrlCap_reg
1725( 1726(
1726 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr, 1727 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
1727 pcieRootCtrlCapReg_t *reg 1728 pcieRootCtrlCapReg_t *reg
@@ -1740,13 +1741,13 @@ pcieRet_e pcie_write_rootCtrlCap_reg
1740 baseAddr->ROOT_CTRL_CAP = reg->raw = new_val; 1741 baseAddr->ROOT_CTRL_CAP = reg->raw = new_val;
1741 1742
1742 return pcie_range_check_return; 1743 return pcie_range_check_return;
1743} /*pcie_write_rootCtrlCap_reg*/ 1744} /* pciev0_write_rootCtrlCap_reg */
1744 1745
1745 1746
1746/***************************************************************************** 1747/*****************************************************************************
1747 * Read and split up the Root Status and Control register 1748 * Read and split up the Root Status and Control register
1748 ****************************************************************************/ 1749 ****************************************************************************/
1749pcieRet_e pcie_read_rootStatus_reg 1750pcieRet_e pciev0_read_rootStatus_reg
1750( 1751(
1751 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr, 1752 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
1752 pcieRootStatusReg_t *reg 1753 pcieRootStatusReg_t *reg
@@ -1759,12 +1760,12 @@ pcieRet_e pcie_read_rootStatus_reg
1759 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_ROOT_STATUS_PME_REQ_ID, reg->pmeReqID); 1760 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_ROOT_STATUS_PME_REQ_ID, reg->pmeReqID);
1760 1761
1761 return pcie_RET_OK; 1762 return pcie_RET_OK;
1762} /*pcie_read_rootStatus_reg*/ 1763} /* pciev0_read_rootStatus_reg */
1763 1764
1764/***************************************************************************** 1765/*****************************************************************************
1765 * Combine and write the Root Status and Control register 1766 * Combine and write the Root Status and Control register
1766 ****************************************************************************/ 1767 ****************************************************************************/
1767pcieRet_e pcie_write_rootStatus_reg 1768pcieRet_e pciev0_write_rootStatus_reg
1768( 1769(
1769 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr, 1770 CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr,
1770 pcieRootStatusReg_t *reg 1771 pcieRootStatusReg_t *reg
@@ -1780,12 +1781,12 @@ pcieRet_e pcie_write_rootStatus_reg
1780 baseAddr->ROOT_STATUS = reg->raw = new_val; 1781 baseAddr->ROOT_STATUS = reg->raw = new_val;
1781 1782
1782 return pcie_range_check_return; 1783 return pcie_range_check_return;
1783} /*pcie_write_rootStatus_reg*/ 1784} /* pciev0_write_rootStatus_reg */
1784 1785
1785/***************************************************************************** 1786/*****************************************************************************
1786 * Read and split up the Device Capabilities 2 register 1787 * Read and split up the Device Capabilities 2 register
1787 ****************************************************************************/ 1788 ****************************************************************************/
1788pcieRet_e pcie_read_devCap2_reg 1789pcieRet_e pciev0_read_devCap2_reg
1789( 1790(
1790 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 1791 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1791 pcieDevCap2Reg_t *reg 1792 pcieDevCap2Reg_t *reg
@@ -1797,13 +1798,13 @@ pcieRet_e pcie_read_devCap2_reg
1797 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEV_CAP2_CMPL_TO_EN, reg->cmplToEn); 1798 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEV_CAP2_CMPL_TO_EN, reg->cmplToEn);
1798 1799
1799 return pcie_RET_OK; 1800 return pcie_RET_OK;
1800} /*pcie_read_devCap2_reg*/ 1801} /* pciev0_read_devCap2_reg */
1801 1802
1802 1803
1803/***************************************************************************** 1804/*****************************************************************************
1804 * Combine and write the Device Capabilities 2 register 1805 * Combine and write the Device Capabilities 2 register
1805 ****************************************************************************/ 1806 ****************************************************************************/
1806pcieRet_e pcie_write_devCap2_reg 1807pcieRet_e pciev0_write_devCap2_reg
1807( 1808(
1808 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 1809 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1809 pcieDevCap2Reg_t *reg 1810 pcieDevCap2Reg_t *reg
@@ -1818,13 +1819,13 @@ pcieRet_e pcie_write_devCap2_reg
1818 baseAddr->DEV_CAP2 = reg->raw = new_val; 1819 baseAddr->DEV_CAP2 = reg->raw = new_val;
1819 1820
1820 return pcie_range_check_return; 1821 return pcie_range_check_return;
1821} /*pcie_write_devCap2_reg*/ 1822} /* pciev0_write_devCap2_reg */
1822 1823
1823 1824
1824/***************************************************************************** 1825/*****************************************************************************
1825 * Read and split up the Device Status and Control Register 2 register 1826 * Read and split up the Device Status and Control Register 2 register
1826 ****************************************************************************/ 1827 ****************************************************************************/
1827pcieRet_e pcie_read_devStatCtrl2_reg 1828pcieRet_e pciev0_read_devStatCtrl2_reg
1828( 1829(
1829 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 1830 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1830 pcieDevStatCtrl2Reg_t *reg 1831 pcieDevStatCtrl2Reg_t *reg
@@ -1836,13 +1837,13 @@ pcieRet_e pcie_read_devStatCtrl2_reg
1836 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEV_STAT_CTRL2_CMPL_TO, reg->cmplTo); 1837 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEV_STAT_CTRL2_CMPL_TO, reg->cmplTo);
1837 1838
1838 return pcie_RET_OK; 1839 return pcie_RET_OK;
1839} /*pcie_read_devStatCtrl2_reg*/ 1840} /* pciev0_read_devStatCtrl2_reg */
1840 1841
1841 1842
1842/***************************************************************************** 1843/*****************************************************************************
1843 * Combine and write the Device Status and Control Register 2 register 1844 * Combine and write the Device Status and Control Register 2 register
1844 ****************************************************************************/ 1845 ****************************************************************************/
1845pcieRet_e pcie_write_devStatCtrl2_reg 1846pcieRet_e pciev0_write_devStatCtrl2_reg
1846( 1847(
1847 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 1848 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1848 pcieDevStatCtrl2Reg_t *reg 1849 pcieDevStatCtrl2Reg_t *reg
@@ -1857,12 +1858,12 @@ pcieRet_e pcie_write_devStatCtrl2_reg
1857 baseAddr->DEV_STAT_CTRL2 = reg->raw = new_val; 1858 baseAddr->DEV_STAT_CTRL2 = reg->raw = new_val;
1858 1859
1859 return pcie_range_check_return; 1860 return pcie_range_check_return;
1860} /*pcie_write_devStatCtrl2_reg*/ 1861} /* pciev0_write_devStatCtrl2_reg */
1861 1862
1862/***************************************************************************** 1863/*****************************************************************************
1863 * Read and split up the Link Control 2 register 1864 * Read and split up the Link Control 2 register
1864 ****************************************************************************/ 1865 ****************************************************************************/
1865pcieRet_e pcie_read_linkCtrl2_reg 1866pcieRet_e pciev0_read_linkCtrl2_reg
1866( 1867(
1867 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 1868 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1868 pcieLinkCtrl2Reg_t *reg 1869 pcieLinkCtrl2Reg_t *reg
@@ -1881,13 +1882,13 @@ pcieRet_e pcie_read_linkCtrl2_reg
1881 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_CTRL2_TGT_SPEED, reg->tgtSpeed); 1882 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_CTRL2_TGT_SPEED, reg->tgtSpeed);
1882 1883
1883 return pcie_RET_OK; 1884 return pcie_RET_OK;
1884} /*pcie_read_linkCtrl2_reg*/ 1885} /* pciev0_read_linkCtrl2_reg */
1885 1886
1886 1887
1887/***************************************************************************** 1888/*****************************************************************************
1888 * Combine and write the Link Control 2 register 1889 * Combine and write the Link Control 2 register
1889 ****************************************************************************/ 1890 ****************************************************************************/
1890pcieRet_e pcie_write_linkCtrl2_reg 1891pcieRet_e pciev0_write_linkCtrl2_reg
1891( 1892(
1892 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 1893 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1893 pcieLinkCtrl2Reg_t *reg 1894 pcieLinkCtrl2Reg_t *reg
@@ -1909,7 +1910,7 @@ pcieRet_e pcie_write_linkCtrl2_reg
1909 baseAddr->LINK_CTRL2 = reg->raw = new_val; 1910 baseAddr->LINK_CTRL2 = reg->raw = new_val;
1910 1911
1911 return pcie_range_check_return; 1912 return pcie_range_check_return;
1912} /*pcie_write_linkCtrl2_reg*/ 1913} /* pciev0_write_linkCtrl2_reg */
1913 1914
1914 1915
1915/***************************************************************************** 1916/*****************************************************************************
@@ -1925,7 +1926,7 @@ pcieRet_e pcie_write_linkCtrl2_reg
1925/***************************************************************************** 1926/*****************************************************************************
1926 * Read and split up the PCIE Extended Capabilities Header register 1927 * Read and split up the PCIE Extended Capabilities Header register
1927 ****************************************************************************/ 1928 ****************************************************************************/
1928pcieRet_e pcie_read_extCap_reg 1929pcieRet_e pciev0_read_extCap_reg
1929( 1930(
1930 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 1931 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1931 pcieExtCapReg_t *reg 1932 pcieExtCapReg_t *reg
@@ -1938,13 +1939,13 @@ pcieRet_e pcie_read_extCap_reg
1938 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_EXTCAP_EXT_CAP_ID, reg->extCapID); 1939 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_EXTCAP_EXT_CAP_ID, reg->extCapID);
1939 1940
1940 return pcie_RET_OK; 1941 return pcie_RET_OK;
1941} /*pcie_read_extCap_reg*/ 1942} /* pciev0_read_extCap_reg */
1942 1943
1943 1944
1944/***************************************************************************** 1945/*****************************************************************************
1945 * Read and split up the Uncorrectable Error Status register 1946 * Read and split up the Uncorrectable Error Status register
1946 ****************************************************************************/ 1947 ****************************************************************************/
1947pcieRet_e pcie_read_uncErr_reg 1948pcieRet_e pciev0_read_uncErr_reg
1948( 1949(
1949 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 1950 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1950 pcieUncErrReg_t *reg 1951 pcieUncErrReg_t *reg
@@ -1965,12 +1966,12 @@ pcieRet_e pcie_read_uncErr_reg
1965 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_DLP_ERR_ST, reg->dlpErrSt); 1966 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_DLP_ERR_ST, reg->dlpErrSt);
1966 1967
1967 return pcie_RET_OK; 1968 return pcie_RET_OK;
1968} /*pcie_read_uncErr_reg*/ 1969} /* pciev0_read_uncErr_reg */
1969 1970
1970/***************************************************************************** 1971/*****************************************************************************
1971 * Combine and write the Uncorrectable Error Status register 1972 * Combine and write the Uncorrectable Error Status register
1972 ****************************************************************************/ 1973 ****************************************************************************/
1973pcieRet_e pcie_write_uncErr_reg 1974pcieRet_e pciev0_write_uncErr_reg
1974( 1975(
1975 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 1976 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
1976 pcieUncErrReg_t *reg 1977 pcieUncErrReg_t *reg
@@ -1994,14 +1995,14 @@ pcieRet_e pcie_write_uncErr_reg
1994 baseAddr->PCIE_UNCERR = reg->raw = new_val; 1995 baseAddr->PCIE_UNCERR = reg->raw = new_val;
1995 1996
1996 return pcie_range_check_return; 1997 return pcie_range_check_return;
1997} /*pcie_write_uncErr_reg*/ 1998} /* pciev0_write_uncErr_reg */
1998 1999
1999 2000
2000 2001
2001/***************************************************************************** 2002/*****************************************************************************
2002 * Read and split up the Uncorrectable Error Mask register 2003 * Read and split up the Uncorrectable Error Mask register
2003 ****************************************************************************/ 2004 ****************************************************************************/
2004pcieRet_e pcie_read_uncErrMask_reg 2005pcieRet_e pciev0_read_uncErrMask_reg
2005( 2006(
2006 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 2007 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
2007 pcieUncErrMaskReg_t *reg 2008 pcieUncErrMaskReg_t *reg
@@ -2022,12 +2023,12 @@ pcieRet_e pcie_read_uncErrMask_reg
2022 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_MASK_DLP_ERR_MSK, reg->dlpErrMsk); 2023 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_MASK_DLP_ERR_MSK, reg->dlpErrMsk);
2023 2024
2024 return pcie_RET_OK; 2025 return pcie_RET_OK;
2025} /*pcie_read_uncErrMask_reg*/ 2026} /* pciev0_read_uncErrMask_reg */
2026 2027
2027/***************************************************************************** 2028/*****************************************************************************
2028 * Combine and write the Uncorrectable Error Mask register 2029 * Combine and write the Uncorrectable Error Mask register
2029 ****************************************************************************/ 2030 ****************************************************************************/
2030pcieRet_e pcie_write_uncErrMask_reg 2031pcieRet_e pciev0_write_uncErrMask_reg
2031( 2032(
2032 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 2033 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
2033 pcieUncErrMaskReg_t *reg 2034 pcieUncErrMaskReg_t *reg
@@ -2051,13 +2052,13 @@ pcieRet_e pcie_write_uncErrMask_reg
2051 baseAddr->PCIE_UNCERR_MASK = reg->raw = new_val; 2052 baseAddr->PCIE_UNCERR_MASK = reg->raw = new_val;
2052 2053
2053 return pcie_range_check_return; 2054 return pcie_range_check_return;
2054} /*pcie_write_uncErrMask_reg*/ 2055} /* pciev0_write_uncErrMask_reg */
2055 2056
2056 2057
2057/***************************************************************************** 2058/*****************************************************************************
2058 * Read and split up the Uncorrectable Error Severity register 2059 * Read and split up the Uncorrectable Error Severity register
2059 ****************************************************************************/ 2060 ****************************************************************************/
2060pcieRet_e pcie_read_uncErrSvrty_reg 2061pcieRet_e pciev0_read_uncErrSvrty_reg
2061( 2062(
2062 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 2063 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
2063 pcieUncErrSvrtyReg_t *reg 2064 pcieUncErrSvrtyReg_t *reg
@@ -2078,12 +2079,12 @@ pcieRet_e pcie_read_uncErrSvrty_reg
2078 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_SVRTY_DLP_ERR_SVRTY, reg->dlpErrSvrty); 2079 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_SVRTY_DLP_ERR_SVRTY, reg->dlpErrSvrty);
2079 2080
2080 return pcie_RET_OK; 2081 return pcie_RET_OK;
2081} /*pcie_read_uncErrSvrty_reg*/ 2082} /* pciev0_read_uncErrSvrty_reg */
2082 2083
2083/***************************************************************************** 2084/*****************************************************************************
2084 * Combine and write the Uncorrectable Error Severity register 2085 * Combine and write the Uncorrectable Error Severity register
2085 ****************************************************************************/ 2086 ****************************************************************************/
2086pcieRet_e pcie_write_uncErrSvrty_reg 2087pcieRet_e pciev0_write_uncErrSvrty_reg
2087( 2088(
2088 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 2089 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
2089 pcieUncErrSvrtyReg_t *reg 2090 pcieUncErrSvrtyReg_t *reg
@@ -2107,13 +2108,13 @@ pcieRet_e pcie_write_uncErrSvrty_reg
2107 baseAddr->PCIE_UNCERR_SVRTY = reg->raw = new_val; 2108 baseAddr->PCIE_UNCERR_SVRTY = reg->raw = new_val;
2108 2109
2109 return pcie_range_check_return; 2110 return pcie_range_check_return;
2110} /*pcie_write_uncErrSvrty_reg*/ 2111} /* pciev0_write_uncErrSvrty_reg */
2111 2112
2112 2113
2113/***************************************************************************** 2114/*****************************************************************************
2114 * Read and split up the Correctable Error Status register 2115 * Read and split up the Correctable Error Status register
2115 ****************************************************************************/ 2116 ****************************************************************************/
2116pcieRet_e pcie_read_corErr_reg 2117pcieRet_e pciev0_read_corErr_reg
2117( 2118(
2118 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 2119 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
2119 pcieCorErrReg_t *reg 2120 pcieCorErrReg_t *reg
@@ -2129,12 +2130,12 @@ pcieRet_e pcie_read_corErr_reg
2129 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_CERR_RCVR_ERR_ST, reg->rcvrErrSt); 2130 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_CERR_RCVR_ERR_ST, reg->rcvrErrSt);
2130 2131
2131 return pcie_RET_OK; 2132 return pcie_RET_OK;
2132} /*pcie_read_corErr_reg*/ 2133} /* pciev0_read_corErr_reg */
2133 2134
2134/***************************************************************************** 2135/*****************************************************************************
2135 * Combine and write the Correctable Error Status register 2136 * Combine and write the Correctable Error Status register
2136 ****************************************************************************/ 2137 ****************************************************************************/
2137pcieRet_e pcie_write_corErr_reg 2138pcieRet_e pciev0_write_corErr_reg
2138( 2139(
2139 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 2140 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
2140 pcieCorErrReg_t *reg 2141 pcieCorErrReg_t *reg
@@ -2153,13 +2154,13 @@ pcieRet_e pcie_write_corErr_reg
2153 baseAddr->PCIE_CERR = reg->raw = new_val; 2154 baseAddr->PCIE_CERR = reg->raw = new_val;
2154 2155
2155 return pcie_range_check_return; 2156 return pcie_range_check_return;
2156} /*pcie_write_corErr_reg*/ 2157} /* pciev0_write_corErr_reg */
2157 2158
2158 2159
2159/***************************************************************************** 2160/*****************************************************************************
2160 * Read and split up the Correctable Error Mask register 2161 * Read and split up the Correctable Error Mask register
2161 ****************************************************************************/ 2162 ****************************************************************************/
2162pcieRet_e pcie_read_corErrMask_reg 2163pcieRet_e pciev0_read_corErrMask_reg
2163( 2164(
2164 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 2165 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
2165 pcieCorErrMaskReg_t *reg 2166 pcieCorErrMaskReg_t *reg
@@ -2175,12 +2176,12 @@ pcieRet_e pcie_read_corErrMask_reg
2175 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_CERR_MASK_RCVR_ERR_MSK, reg->rcvrErrMsk); 2176 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_CERR_MASK_RCVR_ERR_MSK, reg->rcvrErrMsk);
2176 2177
2177 return pcie_RET_OK; 2178 return pcie_RET_OK;
2178} /*pcie_read_corErrMask_reg*/ 2179} /* pciev0_read_corErrMask_reg */
2179 2180
2180/***************************************************************************** 2181/*****************************************************************************
2181 * Combine and write the Correctable Error Mask register 2182 * Combine and write the Correctable Error Mask register
2182 ****************************************************************************/ 2183 ****************************************************************************/
2183pcieRet_e pcie_write_corErrMask_reg 2184pcieRet_e pciev0_write_corErrMask_reg
2184( 2185(
2185 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 2186 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
2186 pcieCorErrMaskReg_t *reg 2187 pcieCorErrMaskReg_t *reg
@@ -2199,13 +2200,13 @@ pcieRet_e pcie_write_corErrMask_reg
2199 baseAddr->PCIE_CERR_MASK = reg->raw = new_val; 2200 baseAddr->PCIE_CERR_MASK = reg->raw = new_val;
2200 2201
2201 return pcie_range_check_return; 2202 return pcie_range_check_return;
2202} /*pcie_write_corErrMask_reg*/ 2203} /* pciev0_write_corErrMask_reg */
2203 2204
2204 2205
2205/***************************************************************************** 2206/*****************************************************************************
2206 * Read and split up the Advanced Capabilities and Control register 2207 * Read and split up the Advanced Capabilities and Control register
2207 ****************************************************************************/ 2208 ****************************************************************************/
2208pcieRet_e pcie_read_accr_reg 2209pcieRet_e pciev0_read_accr_reg
2209( 2210(
2210 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 2211 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
2211 pcieAccrReg_t *reg 2212 pcieAccrReg_t *reg
@@ -2220,13 +2221,13 @@ pcieRet_e pcie_read_accr_reg
2220 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_ACCR_FRST_ERR_PTR, reg->erPtr); 2221 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_ACCR_FRST_ERR_PTR, reg->erPtr);
2221 2222
2222 return pcie_RET_OK; 2223 return pcie_RET_OK;
2223} /* pcie_read_accr_reg */ 2224} /* pciev0_read_accr_reg */
2224 2225
2225 2226
2226/***************************************************************************** 2227/*****************************************************************************
2227 * Combine and write the Advanced Capabilities and Control register 2228 * Combine and write the Advanced Capabilities and Control register
2228 ****************************************************************************/ 2229 ****************************************************************************/
2229pcieRet_e pcie_write_accr_reg 2230pcieRet_e pciev0_write_accr_reg
2230( 2231(
2231 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 2232 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
2232 pcieAccrReg_t *reg 2233 pcieAccrReg_t *reg
@@ -2243,28 +2244,28 @@ pcieRet_e pcie_write_accr_reg
2243 2244
2244 baseAddr->PCIE_ACCR = reg->raw = new_val; 2245 baseAddr->PCIE_ACCR = reg->raw = new_val;
2245 return pcie_range_check_return; 2246 return pcie_range_check_return;
2246} /* pcie_write_accr_reg */ 2247} /* pciev0_write_accr_reg */
2247 2248
2248/***************************************************************************** 2249/*****************************************************************************
2249 * Read and split up the Header Log register 2250 * Read and split up the Header Log register
2250 ****************************************************************************/ 2251 ****************************************************************************/
2251pcieRet_e pcie_read_hdrLog_reg 2252pcieRet_e pciev0_read_hdrLog_reg
2252( 2253(
2253 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 2254 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
2254 pcieHdrLogReg_t *reg, 2255 pcieHdrLogReg_t *reg,
2255 int regNum 2256 int regNum
2256) 2257)
2257{ 2258{
2258 uint32_t val = reg->raw = reg->hdrDW = baseAddr->HDR_LOG[regNum]; 2259 reg->raw = reg->hdrDW = baseAddr->HDR_LOG[regNum];
2259 2260
2260 return pcie_RET_OK; 2261 return pcie_RET_OK;
2261} /*pcie_read_hdrLog_reg*/ 2262} /* pciev0_read_hdrLog_reg */
2262 2263
2263 2264
2264/***************************************************************************** 2265/*****************************************************************************
2265 * Read and split up the Root Error Command register 2266 * Read and split up the Root Error Command register
2266 ****************************************************************************/ 2267 ****************************************************************************/
2267pcieRet_e pcie_read_rootErrCmd_reg 2268pcieRet_e pciev0_read_rootErrCmd_reg
2268( 2269(
2269 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 2270 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
2270 pcieRootErrCmdReg_t *reg 2271 pcieRootErrCmdReg_t *reg
@@ -2277,12 +2278,12 @@ pcieRet_e pcie_read_rootErrCmd_reg
2277 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_RC_ERR_CMD_CERR_RPT_EN, reg->cerrRptEn); 2278 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_RC_ERR_CMD_CERR_RPT_EN, reg->cerrRptEn);
2278 2279
2279 return pcie_RET_OK; 2280 return pcie_RET_OK;
2280} /*pcie_read_rootErrCmd_reg*/ 2281} /* pciev0_read_rootErrCmd_reg */
2281 2282
2282/***************************************************************************** 2283/*****************************************************************************
2283 * Combine and write the Root Error Command register 2284 * Combine and write the Root Error Command register
2284 ****************************************************************************/ 2285 ****************************************************************************/
2285pcieRet_e pcie_write_rootErrCmd_reg 2286pcieRet_e pciev0_write_rootErrCmd_reg
2286( 2287(
2287 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 2288 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
2288 pcieRootErrCmdReg_t *reg 2289 pcieRootErrCmdReg_t *reg
@@ -2298,13 +2299,13 @@ pcieRet_e pcie_write_rootErrCmd_reg
2298 baseAddr->RC_ERR_CMD = reg->raw = new_val; 2299 baseAddr->RC_ERR_CMD = reg->raw = new_val;
2299 2300
2300 return pcie_range_check_return; 2301 return pcie_range_check_return;
2301} /*pcie_write_rootErrCmd_reg*/ 2302} /* pciev0_write_rootErrCmd_reg */
2302 2303
2303 2304
2304/***************************************************************************** 2305/*****************************************************************************
2305 * Read and split up the Root Error Status register 2306 * Read and split up the Root Error Status register
2306 ****************************************************************************/ 2307 ****************************************************************************/
2307pcieRet_e pcie_read_rootErrSt_reg 2308pcieRet_e pciev0_read_rootErrSt_reg
2308( 2309(
2309 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 2310 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
2310 pcieRootErrStReg_t *reg 2311 pcieRootErrStReg_t *reg
@@ -2322,12 +2323,12 @@ pcieRet_e pcie_read_rootErrSt_reg
2322 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_RC_ERR_ST_CORR_ERR, reg->corrErr); 2323 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_RC_ERR_ST_CORR_ERR, reg->corrErr);
2323 2324
2324 return pcie_RET_OK; 2325 return pcie_RET_OK;
2325} /*pcie_read_rootErrSt_reg*/ 2326} /* pciev0_read_rootErrSt_reg */
2326 2327
2327/***************************************************************************** 2328/*****************************************************************************
2328 * Combine and write the Root Error Status register 2329 * Combine and write the Root Error Status register
2329 ****************************************************************************/ 2330 ****************************************************************************/
2330pcieRet_e pcie_write_rootErrSt_reg 2331pcieRet_e pciev0_write_rootErrSt_reg
2331( 2332(
2332 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 2333 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
2333 pcieRootErrStReg_t *reg 2334 pcieRootErrStReg_t *reg
@@ -2348,13 +2349,13 @@ pcieRet_e pcie_write_rootErrSt_reg
2348 baseAddr->RC_ERR_ST = reg->raw = new_val; 2349 baseAddr->RC_ERR_ST = reg->raw = new_val;
2349 2350
2350 return pcie_range_check_return; 2351 return pcie_range_check_return;
2351} /*pcie_write_rootErrSt_reg*/ 2352} /* pciev0_write_rootErrSt_reg */
2352 2353
2353 2354
2354/***************************************************************************** 2355/*****************************************************************************
2355 * Read and split up the Error Source Identification register 2356 * Read and split up the Error Source Identification register
2356 ****************************************************************************/ 2357 ****************************************************************************/
2357pcieRet_e pcie_read_errSrcID_reg 2358pcieRet_e pciev0_read_errSrcID_reg
2358( 2359(
2359 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 2360 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
2360 pcieErrSrcIDReg_t *reg 2361 pcieErrSrcIDReg_t *reg
@@ -2366,7 +2367,7 @@ pcieRet_e pcie_read_errSrcID_reg
2366 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_ERR_SRC_ID_CORR_SRC_ID, reg->corrSrcID); 2367 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_ERR_SRC_ID_CORR_SRC_ID, reg->corrSrcID);
2367 2368
2368 return pcie_RET_OK; 2369 return pcie_RET_OK;
2369} /*pcie_read_errSrcID_reg*/ 2370} /* pciev0_read_errSrcID_reg */
2370 2371
2371 2372
2372/***************************************************************************** 2373/*****************************************************************************
@@ -2383,7 +2384,7 @@ pcieRet_e pcie_read_errSrcID_reg
2383/***************************************************************************** 2384/*****************************************************************************
2384 * Read and split up the Ack Latency and Replay Timer register 2385 * Read and split up the Ack Latency and Replay Timer register
2385 ****************************************************************************/ 2386 ****************************************************************************/
2386pcieRet_e pcie_read_plAckTimer_reg 2387pcieRet_e pciev0_read_plAckTimer_reg
2387( 2388(
2388 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 2389 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
2389 pciePlAckTimerReg_t *reg 2390 pciePlAckTimerReg_t *reg
@@ -2395,12 +2396,12 @@ pcieRet_e pcie_read_plAckTimer_reg
2395 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PL_ACKTIMER_RND_TRP_LMT, reg->rndTrpLmt); 2396 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PL_ACKTIMER_RND_TRP_LMT, reg->rndTrpLmt);
2396 2397
2397 return pcie_RET_OK; 2398 return pcie_RET_OK;
2398} /*pcie_read_plAckTimer_reg*/ 2399} /* pciev0_read_plAckTimer_reg */
2399 2400
2400/***************************************************************************** 2401/*****************************************************************************
2401 * Combine and write the Ack Latency and Replay Timer register 2402 * Combine and write the Ack Latency and Replay Timer register
2402 ****************************************************************************/ 2403 ****************************************************************************/
2403pcieRet_e pcie_write_plAckTimer_reg 2404pcieRet_e pciev0_write_plAckTimer_reg
2404( 2405(
2405 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 2406 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
2406 pciePlAckTimerReg_t *reg 2407 pciePlAckTimerReg_t *reg
@@ -2415,27 +2416,27 @@ pcieRet_e pcie_write_plAckTimer_reg
2415 baseAddr->PL_ACKTIMER = reg->raw = new_val; 2416 baseAddr->PL_ACKTIMER = reg->raw = new_val;
2416 2417
2417 return pcie_range_check_return; 2418 return pcie_range_check_return;
2418} /*pcie_write_plAckTimer_reg*/ 2419} /* pciev0_write_plAckTimer_reg */
2419 2420
2420 2421
2421/***************************************************************************** 2422/*****************************************************************************
2422 * Read and split up the Other Message register 2423 * Read and split up the Other Message register
2423 ****************************************************************************/ 2424 ****************************************************************************/
2424pcieRet_e pcie_read_plOMsg_reg 2425pcieRet_e pciev0_read_plOMsg_reg
2425( 2426(
2426 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 2427 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
2427 pciePlOMsgReg_t *reg 2428 pciePlOMsgReg_t *reg
2428) 2429)
2429{ 2430{
2430 uint32_t val = reg->raw = reg->oMsg = baseAddr->PL_OMSG; 2431 reg->raw = reg->oMsg = baseAddr->PL_OMSG;
2431 2432
2432 return pcie_RET_OK; 2433 return pcie_RET_OK;
2433} /*pcie_read_plOMsg_reg*/ 2434} /* pciev0_read_plOMsg_reg */
2434 2435
2435/***************************************************************************** 2436/*****************************************************************************
2436 * Combine and write the Other Message register 2437 * Combine and write the Other Message register
2437 ****************************************************************************/ 2438 ****************************************************************************/
2438pcieRet_e pcie_write_plOMsg_reg 2439pcieRet_e pciev0_write_plOMsg_reg
2439( 2440(
2440 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 2441 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
2441 pciePlOMsgReg_t *reg 2442 pciePlOMsgReg_t *reg
@@ -2444,13 +2445,13 @@ pcieRet_e pcie_write_plOMsg_reg
2444 baseAddr->PL_OMSG = reg->raw = reg->oMsg; 2445 baseAddr->PL_OMSG = reg->raw = reg->oMsg;
2445 2446
2446 return pcie_RET_OK; 2447 return pcie_RET_OK;
2447} /*pcie_write_plOMsg_reg*/ 2448} /* pciev0_write_plOMsg_reg */
2448 2449
2449 2450
2450/***************************************************************************** 2451/*****************************************************************************
2451 * Read and split up the Port Force Link register 2452 * Read and split up the Port Force Link register
2452 ****************************************************************************/ 2453 ****************************************************************************/
2453pcieRet_e pcie_read_plForceLink_reg 2454pcieRet_e pciev0_read_plForceLink_reg
2454( 2455(
2455 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 2456 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
2456 pciePlForceLinkReg_t *reg 2457 pciePlForceLinkReg_t *reg
@@ -2464,12 +2465,12 @@ pcieRet_e pcie_read_plForceLink_reg
2464 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PL_FORCE_LINK_LINK_NUM, reg->linkNum); 2465 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PL_FORCE_LINK_LINK_NUM, reg->linkNum);
2465 2466
2466 return pcie_RET_OK; 2467 return pcie_RET_OK;
2467} /*pcie_read_plForceLink_reg*/ 2468} /* pciev0_read_plForceLink_reg */
2468 2469
2469/***************************************************************************** 2470/*****************************************************************************
2470 * Combine and write the Port Force Link register 2471 * Combine and write the Port Force Link register
2471 ****************************************************************************/ 2472 ****************************************************************************/
2472pcieRet_e pcie_write_plForceLink_reg 2473pcieRet_e pciev0_write_plForceLink_reg
2473( 2474(
2474 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 2475 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
2475 pciePlForceLinkReg_t *reg 2476 pciePlForceLinkReg_t *reg
@@ -2486,13 +2487,13 @@ pcieRet_e pcie_write_plForceLink_reg
2486 baseAddr->PL_FORCE_LINK = reg->raw = new_val; 2487 baseAddr->PL_FORCE_LINK = reg->raw = new_val;
2487 2488
2488 return pcie_range_check_return; 2489 return pcie_range_check_return;
2489} /*pcie_write_plForceLink_reg*/ 2490} /* pciev0_write_plForceLink_reg */
2490 2491
2491 2492
2492/***************************************************************************** 2493/*****************************************************************************
2493 * Read and split up the Ack Frequency register 2494 * Read and split up the Ack Frequency register
2494 ****************************************************************************/ 2495 ****************************************************************************/
2495pcieRet_e pcie_read_ackFreq_reg 2496pcieRet_e pciev0_read_ackFreq_reg
2496( 2497(
2497 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 2498 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
2498 pcieAckFreqReg_t *reg 2499 pcieAckFreqReg_t *reg
@@ -2508,12 +2509,12 @@ pcieRet_e pcie_read_ackFreq_reg
2508 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_ACK_FREQ_ACK_FREQ, reg->ackFreq); 2509 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_ACK_FREQ_ACK_FREQ, reg->ackFreq);
2509 2510
2510 return pcie_RET_OK; 2511 return pcie_RET_OK;
2511} /*pcie_read_ackFreq_reg*/ 2512} /* pciev0_read_ackFreq_reg */
2512 2513
2513/***************************************************************************** 2514/*****************************************************************************
2514 * Combine and write the Ack Frequency register 2515 * Combine and write the Ack Frequency register
2515 ****************************************************************************/ 2516 ****************************************************************************/
2516pcieRet_e pcie_write_ackFreq_reg 2517pcieRet_e pciev0_write_ackFreq_reg
2517( 2518(
2518 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 2519 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
2519 pcieAckFreqReg_t *reg 2520 pcieAckFreqReg_t *reg
@@ -2532,13 +2533,13 @@ pcieRet_e pcie_write_ackFreq_reg
2532 baseAddr->ACK_FREQ = reg->raw = new_val; 2533 baseAddr->ACK_FREQ = reg->raw = new_val;
2533 2534
2534 return pcie_range_check_return; 2535 return pcie_range_check_return;
2535} /*pcie_write_ackFreq_reg*/ 2536} /* pciev0_write_ackFreq_reg */
2536 2537
2537 2538
2538/***************************************************************************** 2539/*****************************************************************************
2539 * Read and split up the Port Link Control register 2540 * Read and split up the Port Link Control register
2540 ****************************************************************************/ 2541 ****************************************************************************/
2541pcieRet_e pcie_read_lnkCtrl_reg 2542pcieRet_e pciev0_read_lnkCtrl_reg
2542( 2543(
2543 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 2544 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
2544 pcieLnkCtrlReg_t *reg 2545 pcieLnkCtrlReg_t *reg
@@ -2556,12 +2557,12 @@ pcieRet_e pcie_read_lnkCtrl_reg
2556 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PL_LINK_CTRL_OMSG_REQ, reg->msgReq); 2557 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PL_LINK_CTRL_OMSG_REQ, reg->msgReq);
2557 2558
2558 return pcie_RET_OK; 2559 return pcie_RET_OK;
2559} /* pcie_read_lnkCtrl_reg */ 2560} /* pciev0_read_lnkCtrl_reg */
2560 2561
2561/***************************************************************************** 2562/*****************************************************************************
2562 * Combine and write the Port Link Control register 2563 * Combine and write the Port Link Control register
2563 ****************************************************************************/ 2564 ****************************************************************************/
2564pcieRet_e pcie_write_lnkCtrl_reg 2565pcieRet_e pciev0_write_lnkCtrl_reg
2565( 2566(
2566 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 2567 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
2567 pcieLnkCtrlReg_t *reg 2568 pcieLnkCtrlReg_t *reg
@@ -2581,13 +2582,13 @@ pcieRet_e pcie_write_lnkCtrl_reg
2581 2582
2582 baseAddr->PL_LINK_CTRL = reg->raw = new_val; 2583 baseAddr->PL_LINK_CTRL = reg->raw = new_val;
2583 return pcie_range_check_return; 2584 return pcie_range_check_return;
2584} /* pcie_write_lnkCtrl_reg */ 2585} /* pciev0_write_lnkCtrl_reg */
2585 2586
2586 2587
2587/***************************************************************************** 2588/*****************************************************************************
2588 * Read and split up the Lane Skew register 2589 * Read and split up the Lane Skew register
2589 ****************************************************************************/ 2590 ****************************************************************************/
2590pcieRet_e pcie_read_laneSkew_reg 2591pcieRet_e pciev0_read_laneSkew_reg
2591( 2592(
2592 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 2593 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
2593 pcieLaneSkewReg_t *reg 2594 pcieLaneSkewReg_t *reg
@@ -2601,12 +2602,12 @@ pcieRet_e pcie_read_laneSkew_reg
2601 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_LANE_SKEW_LANE_SKEW, reg->laneSkew); 2602 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_LANE_SKEW_LANE_SKEW, reg->laneSkew);
2602 2603
2603 return pcie_RET_OK; 2604 return pcie_RET_OK;
2604} /*pcie_read_laneSkew_reg*/ 2605} /* pciev0_read_laneSkew_reg */
2605 2606
2606/***************************************************************************** 2607/*****************************************************************************
2607 * Combine and write the Lane Skew register 2608 * Combine and write the Lane Skew register
2608 ****************************************************************************/ 2609 ****************************************************************************/
2609pcieRet_e pcie_write_laneSkew_reg 2610pcieRet_e pciev0_write_laneSkew_reg
2610( 2611(
2611 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 2612 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
2612 pcieLaneSkewReg_t *reg 2613 pcieLaneSkewReg_t *reg
@@ -2623,13 +2624,13 @@ pcieRet_e pcie_write_laneSkew_reg
2623 baseAddr->LANE_SKEW = reg->raw = new_val; 2624 baseAddr->LANE_SKEW = reg->raw = new_val;
2624 2625
2625 return pcie_range_check_return; 2626 return pcie_range_check_return;
2626} /*pcie_write_laneSkew_reg*/ 2627} /* pciev0_write_laneSkew_reg */
2627 2628
2628 2629
2629/***************************************************************************** 2630/*****************************************************************************
2630 * Read and split up the Symbol Number register 2631 * Read and split up the Symbol Number register
2631 ****************************************************************************/ 2632 ****************************************************************************/
2632pcieRet_e pcie_read_symNum_reg 2633pcieRet_e pciev0_read_symNum_reg
2633( 2634(
2634 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 2635 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
2635 pcieSymNumReg_t *reg 2636 pcieSymNumReg_t *reg
@@ -2646,12 +2647,12 @@ pcieRet_e pcie_read_symNum_reg
2646 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_SYM_NUM_TS_COUNT, reg->tsCount); 2647 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_SYM_NUM_TS_COUNT, reg->tsCount);
2647 2648
2648 return pcie_RET_OK; 2649 return pcie_RET_OK;
2649} /*pcie_read_symNum_reg*/ 2650} /* pciev0_read_symNum_reg */
2650 2651
2651/***************************************************************************** 2652/*****************************************************************************
2652 * Combine and write the Symbol Number register 2653 * Combine and write the Symbol Number register
2653 ****************************************************************************/ 2654 ****************************************************************************/
2654pcieRet_e pcie_write_symNum_reg 2655pcieRet_e pciev0_write_symNum_reg
2655( 2656(
2656 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 2657 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
2657 pcieSymNumReg_t *reg 2658 pcieSymNumReg_t *reg
@@ -2671,13 +2672,13 @@ pcieRet_e pcie_write_symNum_reg
2671 baseAddr->SYM_NUM = reg->raw = new_val; 2672 baseAddr->SYM_NUM = reg->raw = new_val;
2672 2673
2673 return pcie_range_check_return; 2674 return pcie_range_check_return;
2674} /*pcie_write_symNum_reg*/ 2675} /* pciev0_write_symNum_reg */
2675 2676
2676 2677
2677/***************************************************************************** 2678/*****************************************************************************
2678 * Read and split up the Symbol Timer and Filter Mask register 2679 * Read and split up the Symbol Timer and Filter Mask register
2679 ****************************************************************************/ 2680 ****************************************************************************/
2680pcieRet_e pcie_read_symTimerFltMask_reg 2681pcieRet_e pciev0_read_symTimerFltMask_reg
2681( 2682(
2682 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 2683 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
2683 pcieSymTimerFltMaskReg_t *reg 2684 pcieSymTimerFltMaskReg_t *reg
@@ -2705,12 +2706,12 @@ pcieRet_e pcie_read_symTimerFltMask_reg
2705 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_SYMTIMER_FLTMASK_SKP_VALUE, reg->skpValue); 2706 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_SYMTIMER_FLTMASK_SKP_VALUE, reg->skpValue);
2706 2707
2707 return pcie_RET_OK; 2708 return pcie_RET_OK;
2708} /*pcie_read_symTimerFltMask_reg*/ 2709} /* pciev0_read_symTimerFltMask_reg */
2709 2710
2710/***************************************************************************** 2711/*****************************************************************************
2711 * Combine and write the Symbol Timer and Filter Mask register 2712 * Combine and write the Symbol Timer and Filter Mask register
2712 ****************************************************************************/ 2713 ****************************************************************************/
2713pcieRet_e pcie_write_symTimerFltMask_reg 2714pcieRet_e pciev0_write_symTimerFltMask_reg
2714( 2715(
2715 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 2716 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
2716 pcieSymTimerFltMaskReg_t *reg 2717 pcieSymTimerFltMaskReg_t *reg
@@ -2741,13 +2742,13 @@ pcieRet_e pcie_write_symTimerFltMask_reg
2741 baseAddr->SYMTIMER_FLTMASK = reg->raw = new_val; 2742 baseAddr->SYMTIMER_FLTMASK = reg->raw = new_val;
2742 2743
2743 return pcie_range_check_return; 2744 return pcie_range_check_return;
2744} /*pcie_write_symTimerFltMask_reg*/ 2745} /* pciev0_write_symTimerFltMask_reg */
2745 2746
2746 2747
2747/***************************************************************************** 2748/*****************************************************************************
2748 * Read and split up the Filter Mask 2 register 2749 * Read and split up the Filter Mask 2 register
2749 ****************************************************************************/ 2750 ****************************************************************************/
2750pcieRet_e pcie_read_fltMask2_reg 2751pcieRet_e pciev0_read_fltMask2_reg
2751( 2752(
2752 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 2753 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
2753 pcieFltMask2Reg_t *reg 2754 pcieFltMask2Reg_t *reg
@@ -2761,12 +2762,12 @@ pcieRet_e pcie_read_fltMask2_reg
2761 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_FLT_MASK2_VMSG0_DROP, reg->vmsg0Drop); 2762 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_FLT_MASK2_VMSG0_DROP, reg->vmsg0Drop);
2762 2763
2763 return pcie_RET_OK; 2764 return pcie_RET_OK;
2764} /*pcie_read_fltMask2_reg*/ 2765} /* pciev0_read_fltMask2_reg */
2765 2766
2766/***************************************************************************** 2767/*****************************************************************************
2767 * Combine and write the Filter Mask 2 register 2768 * Combine and write the Filter Mask 2 register
2768 ****************************************************************************/ 2769 ****************************************************************************/
2769pcieRet_e pcie_write_fltMask2_reg 2770pcieRet_e pciev0_write_fltMask2_reg
2770( 2771(
2771 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 2772 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
2772 pcieFltMask2Reg_t *reg 2773 pcieFltMask2Reg_t *reg
@@ -2783,13 +2784,13 @@ pcieRet_e pcie_write_fltMask2_reg
2783 baseAddr->FLT_MASK2 = reg->raw = new_val; 2784 baseAddr->FLT_MASK2 = reg->raw = new_val;
2784 2785
2785 return pcie_range_check_return; 2786 return pcie_range_check_return;
2786} /*pcie_write_fltMask2_reg*/ 2787} /* pciev0_write_fltMask2_reg */
2787 2788
2788 2789
2789/***************************************************************************** 2790/*****************************************************************************
2790 * Read and split up the Debug 0 register 2791 * Read and split up the Debug 0 register
2791 ****************************************************************************/ 2792 ****************************************************************************/
2792pcieRet_e pcie_read_debug0_reg 2793pcieRet_e pciev0_read_debug0_reg
2793( 2794(
2794 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 2795 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
2795 pcieDebug0Reg_t *reg 2796 pcieDebug0Reg_t *reg
@@ -2808,13 +2809,13 @@ pcieRet_e pcie_read_debug0_reg
2808 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEBUG0_LTSSM_STATE, reg->ltssmState); 2809 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEBUG0_LTSSM_STATE, reg->ltssmState);
2809 2810
2810 return pcie_RET_OK; 2811 return pcie_RET_OK;
2811} /* pcie_read_debug0_reg */ 2812} /* pciev0_read_debug0_reg */
2812 2813
2813 2814
2814/***************************************************************************** 2815/*****************************************************************************
2815 * Read and split up the Debug 1 register 2816 * Read and split up the Debug 1 register
2816 ****************************************************************************/ 2817 ****************************************************************************/
2817pcieRet_e pcie_read_debug1_reg 2818pcieRet_e pciev0_read_debug1_reg
2818( 2819(
2819 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 2820 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
2820 pcieDebug1Reg_t *reg 2821 pcieDebug1Reg_t *reg
@@ -2839,12 +2840,12 @@ pcieRet_e pcie_read_debug1_reg
2839 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEBUG1_RMLH_RCVD_LANE_REV, reg->rmlhRcvdLaneRev); 2840 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEBUG1_RMLH_RCVD_LANE_REV, reg->rmlhRcvdLaneRev);
2840 2841
2841 return pcie_RET_OK; 2842 return pcie_RET_OK;
2842} /*pcie_read_debug1_reg*/ 2843} /* pciev0_read_debug1_reg */
2843 2844
2844/***************************************************************************** 2845/*****************************************************************************
2845 * Read and split up the Gen 2 register 2846 * Read and split up the Gen 2 register
2846 ****************************************************************************/ 2847 ****************************************************************************/
2847pcieRet_e pcie_read_gen2_reg 2848pcieRet_e pciev0_read_gen2_reg
2848( 2849(
2849 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 2850 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
2850 pcieGen2Reg_t *reg 2851 pcieGen2Reg_t *reg
@@ -2860,12 +2861,12 @@ pcieRet_e pcie_read_gen2_reg
2860 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PL_GEN2_NUM_FTS, reg->numFts); 2861 pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PL_GEN2_NUM_FTS, reg->numFts);
2861 2862
2862 return pcie_RET_OK; 2863 return pcie_RET_OK;
2863} /* pcie_read_gen2_reg */ 2864} /* pciev0_read_gen2_reg */
2864 2865
2865/***************************************************************************** 2866/*****************************************************************************
2866 * Combine and write the Gen 2 register 2867 * Combine and write the Gen 2 register
2867 ****************************************************************************/ 2868 ****************************************************************************/
2868pcieRet_e pcie_write_gen2_reg 2869pcieRet_e pciev0_write_gen2_reg
2869( 2870(
2870 CSL_Pcie_cfg_space_endpointRegs *baseAddr, 2871 CSL_Pcie_cfg_space_endpointRegs *baseAddr,
2871 pcieGen2Reg_t *reg 2872 pcieGen2Reg_t *reg
@@ -2883,7 +2884,7 @@ pcieRet_e pcie_write_gen2_reg
2883 2884
2884 baseAddr->PL_GEN2 = reg->raw = new_val; 2885 baseAddr->PL_GEN2 = reg->raw = new_val;
2885 return pcie_range_check_return; 2886 return pcie_range_check_return;
2886} /* pcie_write_gen2_reg */ 2887} /* pciev0_write_gen2_reg */
2887 2888
2888/* Nothing past this point */ 2889/* Nothing past this point */
2889 2890