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authorRaghu Nambiath2018-08-01 16:47:02 -0500
committerRaghu Nambiath2018-08-01 16:47:02 -0500
commit47e51e9647e28971493d02fb424a483882524d8e (patch)
tree10301138cd88a5f45cbdd01f0267895ebe7023c7
parenta11714517887bda62fab76941f2f32207fad2b05 (diff)
parent9145daffac02e3e9d66475e08a671c2124afab7c (diff)
downloadpruss-lld-47e51e9647e28971493d02fb424a483882524d8e.tar.gz
pruss-lld-47e51e9647e28971493d02fb424a483882524d8e.tar.xz
pruss-lld-47e51e9647e28971493d02fb424a483882524d8e.zip
Merge pull request #53 in PROCESSOR-SDK/pruss-lld from rtox-next to master
* commit '9145daffac02e3e9d66475e08a671c2124afab7c': Update mask to store version in pruicss_create for am65xx revid Updates for SOC files to sync with latest SOC implementation for am57x, am335x, am437x, k2g am65xx: Fixes in pruicss soc file updates Adding support for SOC_AM65XX
-rw-r--r--[-rwxr-xr-x]build/armv7/libpruss_aearmv7.mk0
-rw-r--r--build/makefile.mk6
-rw-r--r--build/makefile_profile.mk2
-rw-r--r--build/makefile_profile_indp.mk2
-rw-r--r--package.xs7
-rw-r--r--pruicss.h38
-rw-r--r--pruss_component.mk3
-rw-r--r--soc/am335x/pruicss_soc.c50
-rw-r--r--soc/am437x/pruicss_soc.c22
-rw-r--r--soc/am571x/pruicss_soc.c50
-rw-r--r--soc/am572x/pruicss_soc.c50
-rw-r--r--soc/am574x/pruicss_soc.c50
-rw-r--r--soc/am65xx/pruicss_soc.c160
-rw-r--r--soc/k2g/pruicss_soc.c18
-rw-r--r--soc/pruicss_v1.h54
-rw-r--r--src/pruicss_drv.c346
-rw-r--r--src/pruicss_intc.c71
17 files changed, 664 insertions, 265 deletions
diff --git a/build/armv7/libpruss_aearmv7.mk b/build/armv7/libpruss_aearmv7.mk
index 0319251..0319251 100755..100644
--- a/build/armv7/libpruss_aearmv7.mk
+++ b/build/armv7/libpruss_aearmv7.mk
diff --git a/build/makefile.mk b/build/makefile.mk
index 4b87f6d..e45769f 100644
--- a/build/makefile.mk
+++ b/build/makefile.mk
@@ -35,18 +35,18 @@ include $(PDK_PRUSS_COMP_PATH)/src/src_files_common.mk
35 35
36MODULE_NAME = pruss 36MODULE_NAME = pruss
37 37
38ifeq ($(SOC),$(filter $(SOC), am571x am572x am437x am335x k2g am574x)) 38ifeq ($(SOC),$(filter $(SOC), am571x am572x am437x am335x k2g am574x am65xx))
39SRCDIR += soc/$(SOC) 39SRCDIR += soc/$(SOC)
40INCDIR += soc 40INCDIR += soc
41# Common source files across all platforms and cores 41# Common source files across all platforms and cores
42 SRCS_COMMON += pruicss_soc.c 42SRCS_COMMON += pruicss_soc.c
43endif 43endif
44 44
45# List all the external components/interfaces, whose interface header files 45# List all the external components/interfaces, whose interface header files
46# need to be included for this component 46# need to be included for this component
47INCLUDE_EXTERNAL_INTERFACES = pdk edma 47INCLUDE_EXTERNAL_INTERFACES = pdk edma
48 48
49ifeq ($(SOC),$(filter $(SOC), am571x am572x am437x am335x k2g am574x)) 49ifeq ($(SOC),$(filter $(SOC), am571x am572x am437x am335x k2g am574x am65xx))
50PACKAGE_SRCS_COMMON += soc/$(SOC) 50PACKAGE_SRCS_COMMON += soc/$(SOC)
51endif 51endif
52 52
diff --git a/build/makefile_profile.mk b/build/makefile_profile.mk
index 3025a6b..ba3665a 100644
--- a/build/makefile_profile.mk
+++ b/build/makefile_profile.mk
@@ -51,7 +51,7 @@ PACKAGE_SRCS_COMMON += soc/$(SOC)
51endif 51endif
52 52
53ifeq ($(BUILDTYPE),$(filter $(BUILDTYPE), profile profiledma)) 53ifeq ($(BUILDTYPE),$(filter $(BUILDTYPE), profile profiledma))
54 ifeq ($(CORE),$(filter $(CORE), a15_0 a9host a8host)) 54 ifeq ($(CORE),$(filter $(CORE), a15_0 a9host a8host mpu1_0))
55 CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS) -finstrument-functions -gdwarf-3 -g -D_ENABLE_BM 55 CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS) -finstrument-functions -gdwarf-3 -g -D_ENABLE_BM
56 else 56 else
57 CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS) --entry_parm=address --exit_hook=ti_utils_exit --exit_parm=address --entry_hook=ti_utils_entry -g -D_ENABLE_BM 57 CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS) --entry_parm=address --exit_hook=ti_utils_exit --exit_parm=address --entry_hook=ti_utils_entry -g -D_ENABLE_BM
diff --git a/build/makefile_profile_indp.mk b/build/makefile_profile_indp.mk
index 0fd6e72..2f8b256 100644
--- a/build/makefile_profile_indp.mk
+++ b/build/makefile_profile_indp.mk
@@ -40,7 +40,7 @@ MODULE_NAME = pruss_profile_indp
40INCLUDE_EXTERNAL_INTERFACES = pdk edma 40INCLUDE_EXTERNAL_INTERFACES = pdk edma
41 41
42ifeq ($(BUILDTYPE),$(filter $(BUILDTYPE), profile profiledma)) 42ifeq ($(BUILDTYPE),$(filter $(BUILDTYPE), profile profiledma))
43 ifeq ($(CORE),$(filter $(CORE), a15_0 a9host a8host)) 43 ifeq ($(CORE),$(filter $(CORE), a15_0 a9host a8host mpu1_0))
44 CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS) -finstrument-functions -gdwarf-3 -g -D_ENABLE_BM 44 CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS) -finstrument-functions -gdwarf-3 -g -D_ENABLE_BM
45 else 45 else
46 CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS) --entry_parm=address --exit_hook=ti_utils_exit --exit_parm=address --entry_hook=ti_utils_entry -g -D_ENABLE_BM 46 CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS) --entry_parm=address --exit_hook=ti_utils_exit --exit_parm=address --entry_hook=ti_utils_entry -g -D_ENABLE_BM
diff --git a/package.xs b/package.xs
index 6e35e6c..7b9bb2f 100644
--- a/package.xs
+++ b/package.xs
@@ -49,7 +49,8 @@ function getLibs(prog)
49 'am574x', 49 'am574x',
50 'am335x', 50 'am335x',
51 'am437x', 51 'am437x',
52 'k2g' 52 'k2g',
53 'am65xx'
53 ]; 54 ];
54 55
55 /* Get the SOC */ 56 /* Get the SOC */
@@ -74,6 +75,10 @@ function getLibs(prog)
74 lib = lib + "/a9"; 75 lib = lib + "/a9";
75 else if (java.lang.String(suffix).contains('a8') ) 76 else if (java.lang.String(suffix).contains('a8') )
76 lib = lib + "/a8"; 77 lib = lib + "/a8";
78 else if (java.lang.String(suffix).contains('a53') )
79 lib = lib + "/a53";
80 else if (java.lang.String(suffix).contains('r5f') )
81 lib = lib + "/r5f";
77 else 82 else
78 throw new Error("\tUnknown target for: " + this.packageBase + lib); 83 throw new Error("\tUnknown target for: " + this.packageBase + lib);
79 84
diff --git a/pruicss.h b/pruicss.h
index d4557c1..44fef2d 100644
--- a/pruicss.h
+++ b/pruicss.h
@@ -415,7 +415,6 @@ void PRUICSS_pinMuxConfig(PRUICSS_Handle handle, uint64_t regVal);
415 * @return 0 in case of successful reset, -1 otherwise. 415 * @return 0 in case of successful reset, -1 otherwise.
416 **/ 416 **/
417int32_t PRUICSS_pruReset(PRUICSS_Handle handle ,uint8_t pruNum); 417int32_t PRUICSS_pruReset(PRUICSS_Handle handle ,uint8_t pruNum);
418
419/** 418/**
420 * @brief Disables PRU: \n 419 * @brief Disables PRU: \n
421 * 420 *
@@ -435,7 +434,15 @@ int32_t PRUICSS_pruDisable(PRUICSS_Handle handle,uint8_t pruNum);
435 * @return 0 in case of successful enable, -1 otherwise. 434 * @return 0 in case of successful enable, -1 otherwise.
436 **/ 435 **/
437int32_t PRUICSS_pruEnable(PRUICSS_Handle handle,uint8_t pruNum); 436int32_t PRUICSS_pruEnable(PRUICSS_Handle handle,uint8_t pruNum);
438 437/**
438 * @brief Enables PRU Cycle Counter: \n
439 *
440 * @param handle Pruss's driver handle
441 * @param pruNum PRU instance number[0 or 1].
442 *
443 * @return 0 in case of successful enable, -1 otherwise.
444 **/
445int32_t PRUICSS_pruCounterEnable(PRUICSS_Handle handle,uint8_t pruNum);
439/** 446/**
440 * 447 *
441 * @brief This function writes the given data to PRU memory 448 * @brief This function writes the given data to PRU memory
@@ -461,7 +468,32 @@ int32_t PRUICSS_pruWriteMemory(PRUICSS_Handle handle,
461 const uint32_t *source_mem, 468 const uint32_t *source_mem,
462 uint32_t bytelength 469 uint32_t bytelength
463 ); 470 );
464 471/**
472 *
473 * @brief This function reads from PRU memory and stores in block of memory
474 *
475 * @param handle Pruss's driver handle
476 * @param pruMem PRU Memory Macro
477 * @param wordoffset Offset at which the read will happen.
478 * @param dest_mem Destination memory[ Array of uint32_tegers ]
479 * @param bytelength Total number of bytes to be read
480 *
481 * pruMem can have values
482 * PRU0_DATARAM\n
483 * PRU0_IRAM\n
484 * PRU1_DATARAM\n
485 * PRU1_IRAM\n
486 * PRUICSS_SHARED_DATARAM
487 * @return word length read or 0 on error.
488 *
489 **/
490int32_t PRUICSS_pruReadMemory(
491 PRUICSS_Handle handle,
492 uint32_t pruMem,
493 uint32_t wordoffset,
494 uint32_t *dest_mem,
495 uint32_t bytelength
496 );
465/** 497/**
466 * 498 *
467 * @brief This function initializes the PRU memory to zero 499 * @brief This function initializes the PRU memory to zero
diff --git a/pruss_component.mk b/pruss_component.mk
index 07a4af4..e854a11 100644
--- a/pruss_component.mk
+++ b/pruss_component.mk
@@ -68,13 +68,14 @@ ifeq ($(pruss_component_make_include), )
68 68
69# under other list 69# under other list
70drvpruss_BOARDLIST = icev2AM335x idkAM437x idkAM571x idkAM572x iceK2G idkAM574x 70drvpruss_BOARDLIST = icev2AM335x idkAM437x idkAM571x idkAM572x iceK2G idkAM574x
71drvpruss_SOCLIST = am574x am572x am571x am437x am335x k2g 71drvpruss_SOCLIST = am574x am572x am571x am437x am335x k2g am65xx
72drvpruss_am574x_CORELIST = c66x a15_0 ipu1_0 pru_0 pru_1 72drvpruss_am574x_CORELIST = c66x a15_0 ipu1_0 pru_0 pru_1
73drvpruss_am572x_CORELIST = c66x a15_0 ipu1_0 pru_0 pru_1 73drvpruss_am572x_CORELIST = c66x a15_0 ipu1_0 pru_0 pru_1
74drvpruss_k2g_CORELIST = c66x a15_0 pru_0 pru_1 74drvpruss_k2g_CORELIST = c66x a15_0 pru_0 pru_1
75drvpruss_am571x_CORELIST = c66x a15_0 ipu1_0 pru_0 pru_1 75drvpruss_am571x_CORELIST = c66x a15_0 ipu1_0 pru_0 pru_1
76drvpruss_am437x_CORELIST = a9host pru_0 pru_1 76drvpruss_am437x_CORELIST = a9host pru_0 pru_1
77drvpruss_am335x_CORELIST = a8host pru_0 pru_1 77drvpruss_am335x_CORELIST = a8host pru_0 pru_1
78drvpruss_am65xx_CORELIST = mpu1_0 mcu1_0
78 79
79############################ 80############################
80# uart package 81# uart package
diff --git a/soc/am335x/pruicss_soc.c b/soc/am335x/pruicss_soc.c
index 02e9f79..b7cb374 100644
--- a/soc/am335x/pruicss_soc.c
+++ b/soc/am335x/pruicss_soc.c
@@ -4,7 +4,7 @@
4 * @brief This is soc specific configuration file . 4 * @brief This is soc specific configuration file .
5 */ 5 */
6/* 6/*
7 * Copyright (c) 2015, Texas Instruments Incorporated 7 * Copyright (c) 2015-2018, Texas Instruments Incorporated
8 * All rights reserved. 8 * All rights reserved.
9 * 9 *
10 * Redistribution and use in source and binary forms, with or without 10 * Redistribution and use in source and binary forms, with or without
@@ -46,27 +46,33 @@
46 46
47const PRUICSS_HwAttrs prussInitCfg = 47const PRUICSS_HwAttrs prussInitCfg =
48{ 48{
49 0x4a300000, 49 0x4a300000,
50 0, 50 0,
51 SOC_PRU_ICSS_PRU0_CTRL_REG, 51 SOC_PRU_ICSS_PRU0_CTRL_REG,
52 SOC_PRU_ICSS_PRU1_CTRL_REG, 52 SOC_PRU_ICSS_PRU1_CTRL_REG,
53 SOC_PRU_ICSS_INTC_REG, 53 SOC_PRU_ICSS_INTC_REG,
54 SOC_PRU_ICSS_CFG_REG, 54 SOC_PRU_ICSS_CFG_REG,
55 SOC_PRU_ICSS_UART_REG, 55 SOC_PRU_ICSS_UART_REG,
56 SOC_PRU_ICSS_IEP_REG, 56 SOC_PRU_ICSS_IEP_REG,
57 SOC_PRU_ICSS_ECAP_REG, 57 SOC_PRU_ICSS_ECAP_REG,
58 SOC_PRU_ICSS_MII_RT_CFG_REG, 58 SOC_PRU_ICSS_MII_RT_CFG_REG,
59 SOC_PRU_ICSS_MII_MDIO_REG, 59 SOC_PRU_ICSS_MII_MDIO_REG,
60 SOC_PRU_ICSS_DATA_RAM0, 60 SOC_PRU_ICSS_DATA_RAM0,
61 SOC_PRU_ICSS_DATA_RAM1, 61 SOC_PRU_ICSS_DATA_RAM1,
62 SOC_PRU_ICSS_INST_RAM0, 62 SOC_PRU_ICSS_INST_RAM0,
63 SOC_PRU_ICSS_INST_RAM1, 63 SOC_PRU_ICSS_INST_RAM1,
64 SOC_PRU_ICSS_SHARED_RAM, 64 SOC_PRU_ICSS_SHARED_RAM,
65 SOC_PRU_ICSS_DATA_RAM0_SIZE, 65 0U,
66 SOC_PRU_ICSS_DATA_RAM1_SIZE, 66 0U,
67 SOC_PRU_ICSS_INST_RAM0_SIZE, 67 0U,
68 SOC_PRU_ICSS_INST_RAM1_SIZE, 68 0U,
69 SOC_PRU_ICSS_SHARED_RAM_SIZE 69 SOC_PRU_ICSS_DATA_RAM0_SIZE,
70 SOC_PRU_ICSS_DATA_RAM1_SIZE,
71 SOC_PRU_ICSS_INST_RAM0_SIZE,
72 SOC_PRU_ICSS_INST_RAM1_SIZE,
73 SOC_PRU_ICSS_SHARED_RAM_SIZE,
74 0U,
75 0U
70}; 76};
71 77
72/* PRUICSS objects */ 78/* PRUICSS objects */
diff --git a/soc/am437x/pruicss_soc.c b/soc/am437x/pruicss_soc.c
index 953c97c..5caa945 100644
--- a/soc/am437x/pruicss_soc.c
+++ b/soc/am437x/pruicss_soc.c
@@ -4,7 +4,7 @@
4 * @brief This is soc specific configuration file . 4 * @brief This is soc specific configuration file .
5 */ 5 */
6/* 6/*
7 * Copyright (c) 2015, Texas Instruments Incorporated 7 * Copyright (c) 2015-2018, Texas Instruments Incorporated
8 * All rights reserved. 8 * All rights reserved.
9 * 9 *
10 * Redistribution and use in source and binary forms, with or without 10 * Redistribution and use in source and binary forms, with or without
@@ -47,7 +47,7 @@ PRUICSS_HwAttrs prussInitCfg[2] =
47{ 47{
48 { 48 {
49 0x54440000, 49 0x54440000,
50 0, 50 0U,
51 SOC_PRU_ICSS0_U_PRU0_CTRL_REG, 51 SOC_PRU_ICSS0_U_PRU0_CTRL_REG,
52 SOC_PRU_ICSS0_U_PRU1_CTRL_REG, 52 SOC_PRU_ICSS0_U_PRU1_CTRL_REG,
53 SOC_PRU_ICSS0_U_INTC_REG, 53 SOC_PRU_ICSS0_U_INTC_REG,
@@ -62,15 +62,21 @@ PRUICSS_HwAttrs prussInitCfg[2] =
62 SOC_PRU_ICSS0_U_INST_RAM0, 62 SOC_PRU_ICSS0_U_INST_RAM0,
63 SOC_PRU_ICSS0_U_INST_RAM1, 63 SOC_PRU_ICSS0_U_INST_RAM1,
64 SOC_PRU_ICSS0_U_SHARED_RAM, 64 SOC_PRU_ICSS0_U_SHARED_RAM,
65 0U,
66 0U,
67 0U,
68 0U,
65 SOC_PRU_ICSS0_U_DATA_RAM0_SIZE, 69 SOC_PRU_ICSS0_U_DATA_RAM0_SIZE,
66 SOC_PRU_ICSS0_U_DATA_RAM1_SIZE, 70 SOC_PRU_ICSS0_U_DATA_RAM1_SIZE,
67 SOC_PRU_ICSS0_U_INST_RAM0_SIZE, 71 SOC_PRU_ICSS0_U_INST_RAM0_SIZE,
68 SOC_PRU_ICSS0_U_INST_RAM1_SIZE, 72 SOC_PRU_ICSS0_U_INST_RAM1_SIZE,
69 SOC_PRU_ICSS0_U_SHARED_RAM_SIZE 73 SOC_PRU_ICSS0_U_SHARED_RAM_SIZE,
74 0U,
75 0U
70 }, 76 },
71 { 77 {
72 0x54400000, 78 0x54400000,
73 0, 79 0U,
74 SOC_PRU_ICSS1_U_PRU0_CTRL_REG, 80 SOC_PRU_ICSS1_U_PRU0_CTRL_REG,
75 SOC_PRU_ICSS1_U_PRU1_CTRL_REG, 81 SOC_PRU_ICSS1_U_PRU1_CTRL_REG,
76 SOC_PRU_ICSS1_U_INTC_REG, 82 SOC_PRU_ICSS1_U_INTC_REG,
@@ -85,11 +91,17 @@ PRUICSS_HwAttrs prussInitCfg[2] =
85 SOC_PRU_ICSS1_U_INST_RAM0, 91 SOC_PRU_ICSS1_U_INST_RAM0,
86 SOC_PRU_ICSS1_U_INST_RAM1, 92 SOC_PRU_ICSS1_U_INST_RAM1,
87 SOC_PRU_ICSS1_U_SHARED_RAM, 93 SOC_PRU_ICSS1_U_SHARED_RAM,
94 0U,
95 0U,
96 0U,
97 0U,
88 SOC_PRU_ICSS1_U_DATA_RAM0_SIZE, 98 SOC_PRU_ICSS1_U_DATA_RAM0_SIZE,
89 SOC_PRU_ICSS1_U_DATA_RAM1_SIZE, 99 SOC_PRU_ICSS1_U_DATA_RAM1_SIZE,
90 SOC_PRU_ICSS1_U_INST_RAM0_SIZE, 100 SOC_PRU_ICSS1_U_INST_RAM0_SIZE,
91 SOC_PRU_ICSS1_U_INST_RAM1_SIZE, 101 SOC_PRU_ICSS1_U_INST_RAM1_SIZE,
92 SOC_PRU_ICSS1_U_SHARED_RAM_SIZE 102 SOC_PRU_ICSS1_U_SHARED_RAM_SIZE,
103 0U,
104 0U
93 } 105 }
94}; 106};
95 107
diff --git a/soc/am571x/pruicss_soc.c b/soc/am571x/pruicss_soc.c
index b0a4834..0dd461f 100644
--- a/soc/am571x/pruicss_soc.c
+++ b/soc/am571x/pruicss_soc.c
@@ -4,7 +4,7 @@
4 * @brief This is soc specific configuration file . 4 * @brief This is soc specific configuration file .
5 */ 5 */
6/* 6/*
7 * Copyright (c) 2015, Texas Instruments Incorporated 7 * Copyright (c) 2015-2018, Texas Instruments Incorporated
8 * All rights reserved. 8 * All rights reserved.
9 * 9 *
10 * Redistribution and use in source and binary forms, with or without 10 * Redistribution and use in source and binary forms, with or without
@@ -64,11 +64,17 @@ PRUICSS_HwAttrs prussInitCfg[2] =
64 CSL_IPU_PRUSS1_U_INST_RAM0_12KB_REGS, 64 CSL_IPU_PRUSS1_U_INST_RAM0_12KB_REGS,
65 CSL_IPU_PRUSS1_U_INST_RAM1_12KB_REGS, 65 CSL_IPU_PRUSS1_U_INST_RAM1_12KB_REGS,
66 CSL_IPU_PRUSS1_U_DATA_RAM_32KB_REGS, 66 CSL_IPU_PRUSS1_U_DATA_RAM_32KB_REGS,
67 0U,
68 0U,
69 0U,
70 0U,
67 CSL_IPU_PRUSS1_U_DATA_RAM0_8KB_SIZE, 71 CSL_IPU_PRUSS1_U_DATA_RAM0_8KB_SIZE,
68 CSL_IPU_PRUSS1_U_DATA_RAM1_8KB_SIZE, 72 CSL_IPU_PRUSS1_U_DATA_RAM1_8KB_SIZE,
69 CSL_IPU_PRUSS1_U_INST_RAM0_12KB_SIZE, 73 CSL_IPU_PRUSS1_U_INST_RAM0_12KB_SIZE,
70 CSL_IPU_PRUSS1_U_INST_RAM1_12KB_SIZE, 74 CSL_IPU_PRUSS1_U_INST_RAM1_12KB_SIZE,
71 CSL_IPU_PRUSS1_U_DATA_RAM_32KB_SIZE 75 CSL_IPU_PRUSS1_U_DATA_RAM_32KB_SIZE,
76 0U,
77 0U
72 }, 78 },
73 { 79 {
74 0x4b280000, 80 0x4b280000,
@@ -87,11 +93,17 @@ PRUICSS_HwAttrs prussInitCfg[2] =
87 CSL_IPU_PRUSS2_U_INST_RAM0_12KB_REGS, 93 CSL_IPU_PRUSS2_U_INST_RAM0_12KB_REGS,
88 CSL_IPU_PRUSS2_U_INST_RAM1_12KB_REGS, 94 CSL_IPU_PRUSS2_U_INST_RAM1_12KB_REGS,
89 CSL_IPU_PRUSS2_U_DATA_RAM_32KB_REGS, 95 CSL_IPU_PRUSS2_U_DATA_RAM_32KB_REGS,
96 0U,
97 0U,
98 0U,
99 0U,
90 CSL_IPU_PRUSS2_U_DATA_RAM0_8KB_SIZE, 100 CSL_IPU_PRUSS2_U_DATA_RAM0_8KB_SIZE,
91 CSL_IPU_PRUSS2_U_DATA_RAM1_8KB_SIZE, 101 CSL_IPU_PRUSS2_U_DATA_RAM1_8KB_SIZE,
92 CSL_IPU_PRUSS2_U_INST_RAM0_12KB_SIZE, 102 CSL_IPU_PRUSS2_U_INST_RAM0_12KB_SIZE,
93 CSL_IPU_PRUSS2_U_INST_RAM1_12KB_SIZE, 103 CSL_IPU_PRUSS2_U_INST_RAM1_12KB_SIZE,
94 CSL_IPU_PRUSS2_U_DATA_RAM_32KB_SIZE 104 CSL_IPU_PRUSS2_U_DATA_RAM_32KB_SIZE,
105 0U,
106 0U
95 } 107 }
96#elif defined (__TMS320C6X__) 108#elif defined (__TMS320C6X__)
97 { 109 {
@@ -111,11 +123,17 @@ PRUICSS_HwAttrs prussInitCfg[2] =
111 CSL_DSP_PRUSS1_U_INST_RAM0_12KB_REGS, 123 CSL_DSP_PRUSS1_U_INST_RAM0_12KB_REGS,
112 CSL_DSP_PRUSS1_U_INST_RAM1_12KB_REGS, 124 CSL_DSP_PRUSS1_U_INST_RAM1_12KB_REGS,
113 CSL_DSP_PRUSS1_U_DATA_RAM_32KB_REGS, 125 CSL_DSP_PRUSS1_U_DATA_RAM_32KB_REGS,
126 0U,
127 0U,
128 0U,
129 0U,
114 CSL_DSP_PRUSS1_U_DATA_RAM0_8KB_SIZE, 130 CSL_DSP_PRUSS1_U_DATA_RAM0_8KB_SIZE,
115 CSL_DSP_PRUSS1_U_DATA_RAM1_8KB_SIZE, 131 CSL_DSP_PRUSS1_U_DATA_RAM1_8KB_SIZE,
116 CSL_DSP_PRUSS1_U_INST_RAM0_12KB_SIZE, 132 CSL_DSP_PRUSS1_U_INST_RAM0_12KB_SIZE,
117 CSL_DSP_PRUSS1_U_INST_RAM1_12KB_SIZE, 133 CSL_DSP_PRUSS1_U_INST_RAM1_12KB_SIZE,
118 CSL_DSP_PRUSS1_U_DATA_RAM_32KB_SIZE 134 CSL_DSP_PRUSS1_U_DATA_RAM_32KB_SIZE,
135 0U,
136 0U
119 }, 137 },
120 { 138 {
121 0x4b280000, 139 0x4b280000,
@@ -134,11 +152,17 @@ PRUICSS_HwAttrs prussInitCfg[2] =
134 CSL_DSP_PRUSS2_U_INST_RAM0_12KB_REGS, 152 CSL_DSP_PRUSS2_U_INST_RAM0_12KB_REGS,
135 CSL_DSP_PRUSS2_U_INST_RAM1_12KB_REGS, 153 CSL_DSP_PRUSS2_U_INST_RAM1_12KB_REGS,
136 CSL_DSP_PRUSS2_U_DATA_RAM_32KB_REGS, 154 CSL_DSP_PRUSS2_U_DATA_RAM_32KB_REGS,
155 0U,
156 0U,
157 0U,
158 0U,
137 CSL_DSP_PRUSS2_U_DATA_RAM0_8KB_SIZE, 159 CSL_DSP_PRUSS2_U_DATA_RAM0_8KB_SIZE,
138 CSL_DSP_PRUSS2_U_DATA_RAM1_8KB_SIZE, 160 CSL_DSP_PRUSS2_U_DATA_RAM1_8KB_SIZE,
139 CSL_DSP_PRUSS2_U_INST_RAM0_12KB_SIZE, 161 CSL_DSP_PRUSS2_U_INST_RAM0_12KB_SIZE,
140 CSL_DSP_PRUSS2_U_INST_RAM1_12KB_SIZE, 162 CSL_DSP_PRUSS2_U_INST_RAM1_12KB_SIZE,
141 CSL_DSP_PRUSS2_U_DATA_RAM_32KB_SIZE 163 CSL_DSP_PRUSS2_U_DATA_RAM_32KB_SIZE,
164 0,
165 0
142 } 166 }
143#else 167#else
144 { 168 {
@@ -158,11 +182,17 @@ PRUICSS_HwAttrs prussInitCfg[2] =
158 CSL_MPU_PRUSS1_U_INST_RAM0_12KB_REGS, 182 CSL_MPU_PRUSS1_U_INST_RAM0_12KB_REGS,
159 CSL_MPU_PRUSS1_U_INST_RAM1_12KB_REGS, 183 CSL_MPU_PRUSS1_U_INST_RAM1_12KB_REGS,
160 CSL_MPU_PRUSS1_U_DATA_RAM_32KB_REGS, 184 CSL_MPU_PRUSS1_U_DATA_RAM_32KB_REGS,
185 0U,
186 0U,
187 0U,
188 0U,
161 CSL_MPU_PRUSS1_U_DATA_RAM0_8KB_SIZE, 189 CSL_MPU_PRUSS1_U_DATA_RAM0_8KB_SIZE,
162 CSL_MPU_PRUSS1_U_DATA_RAM1_8KB_SIZE, 190 CSL_MPU_PRUSS1_U_DATA_RAM1_8KB_SIZE,
163 CSL_MPU_PRUSS1_U_INST_RAM0_12KB_SIZE, 191 CSL_MPU_PRUSS1_U_INST_RAM0_12KB_SIZE,
164 CSL_MPU_PRUSS1_U_INST_RAM1_12KB_SIZE, 192 CSL_MPU_PRUSS1_U_INST_RAM1_12KB_SIZE,
165 CSL_MPU_PRUSS1_U_DATA_RAM_32KB_SIZE 193 CSL_MPU_PRUSS1_U_DATA_RAM_32KB_SIZE,
194 0,
195 0
166 }, 196 },
167 { 197 {
168 0x4b280000, 198 0x4b280000,
@@ -181,11 +211,17 @@ PRUICSS_HwAttrs prussInitCfg[2] =
181 CSL_MPU_PRUSS2_U_INST_RAM0_12KB_REGS, 211 CSL_MPU_PRUSS2_U_INST_RAM0_12KB_REGS,
182 CSL_MPU_PRUSS2_U_INST_RAM1_12KB_REGS, 212 CSL_MPU_PRUSS2_U_INST_RAM1_12KB_REGS,
183 CSL_MPU_PRUSS2_U_DATA_RAM_32KB_REGS, 213 CSL_MPU_PRUSS2_U_DATA_RAM_32KB_REGS,
214 0U,
215 0U,
216 0U,
217 0U,
184 CSL_MPU_PRUSS2_U_DATA_RAM0_8KB_SIZE, 218 CSL_MPU_PRUSS2_U_DATA_RAM0_8KB_SIZE,
185 CSL_MPU_PRUSS2_U_DATA_RAM1_8KB_SIZE, 219 CSL_MPU_PRUSS2_U_DATA_RAM1_8KB_SIZE,
186 CSL_MPU_PRUSS2_U_INST_RAM0_12KB_SIZE, 220 CSL_MPU_PRUSS2_U_INST_RAM0_12KB_SIZE,
187 CSL_MPU_PRUSS2_U_INST_RAM1_12KB_SIZE, 221 CSL_MPU_PRUSS2_U_INST_RAM1_12KB_SIZE,
188 CSL_MPU_PRUSS2_U_DATA_RAM_32KB_SIZE 222 CSL_MPU_PRUSS2_U_DATA_RAM_32KB_SIZE,
223 0,
224 0
189 } 225 }
190#endif 226#endif
191}; 227};
diff --git a/soc/am572x/pruicss_soc.c b/soc/am572x/pruicss_soc.c
index 4b0d9ba..8c31875 100644
--- a/soc/am572x/pruicss_soc.c
+++ b/soc/am572x/pruicss_soc.c
@@ -4,7 +4,7 @@
4 * @brief This is soc specific configuration file . 4 * @brief This is soc specific configuration file .
5 */ 5 */
6/* 6/*
7 * Copyright (c) 2015, Texas Instruments Incorporated 7 * Copyright (c) 2015-2018, Texas Instruments Incorporated
8 * All rights reserved. 8 * All rights reserved.
9 * 9 *
10 * Redistribution and use in source and binary forms, with or without 10 * Redistribution and use in source and binary forms, with or without
@@ -64,11 +64,17 @@ PRUICSS_HwAttrs prussInitCfg[2] =
64 CSL_IPU_PRUSS1_U_INST_RAM0_12KB_REGS, 64 CSL_IPU_PRUSS1_U_INST_RAM0_12KB_REGS,
65 CSL_IPU_PRUSS1_U_INST_RAM1_12KB_REGS, 65 CSL_IPU_PRUSS1_U_INST_RAM1_12KB_REGS,
66 CSL_IPU_PRUSS1_U_DATA_RAM_32KB_REGS, 66 CSL_IPU_PRUSS1_U_DATA_RAM_32KB_REGS,
67 0U,
68 0U,
69 0U,
70 0U,
67 CSL_IPU_PRUSS1_U_DATA_RAM0_8KB_SIZE, 71 CSL_IPU_PRUSS1_U_DATA_RAM0_8KB_SIZE,
68 CSL_IPU_PRUSS1_U_DATA_RAM1_8KB_SIZE, 72 CSL_IPU_PRUSS1_U_DATA_RAM1_8KB_SIZE,
69 CSL_IPU_PRUSS1_U_INST_RAM0_12KB_SIZE, 73 CSL_IPU_PRUSS1_U_INST_RAM0_12KB_SIZE,
70 CSL_IPU_PRUSS1_U_INST_RAM1_12KB_SIZE, 74 CSL_IPU_PRUSS1_U_INST_RAM1_12KB_SIZE,
71 CSL_IPU_PRUSS1_U_DATA_RAM_32KB_SIZE 75 CSL_IPU_PRUSS1_U_DATA_RAM_32KB_SIZE,
76 0U,
77 0U
72 }, 78 },
73 { 79 {
74 0x4b280000, 80 0x4b280000,
@@ -87,11 +93,17 @@ PRUICSS_HwAttrs prussInitCfg[2] =
87 CSL_IPU_PRUSS2_U_INST_RAM0_12KB_REGS, 93 CSL_IPU_PRUSS2_U_INST_RAM0_12KB_REGS,
88 CSL_IPU_PRUSS2_U_INST_RAM1_12KB_REGS, 94 CSL_IPU_PRUSS2_U_INST_RAM1_12KB_REGS,
89 CSL_IPU_PRUSS2_U_DATA_RAM_32KB_REGS, 95 CSL_IPU_PRUSS2_U_DATA_RAM_32KB_REGS,
96 0U,
97 0U,
98 0U,
99 0U,
90 CSL_IPU_PRUSS2_U_DATA_RAM0_8KB_SIZE, 100 CSL_IPU_PRUSS2_U_DATA_RAM0_8KB_SIZE,
91 CSL_IPU_PRUSS2_U_DATA_RAM1_8KB_SIZE, 101 CSL_IPU_PRUSS2_U_DATA_RAM1_8KB_SIZE,
92 CSL_IPU_PRUSS2_U_INST_RAM0_12KB_SIZE, 102 CSL_IPU_PRUSS2_U_INST_RAM0_12KB_SIZE,
93 CSL_IPU_PRUSS2_U_INST_RAM1_12KB_SIZE, 103 CSL_IPU_PRUSS2_U_INST_RAM1_12KB_SIZE,
94 CSL_IPU_PRUSS2_U_DATA_RAM_32KB_SIZE 104 CSL_IPU_PRUSS2_U_DATA_RAM_32KB_SIZE,
105 0U,
106 0U
95 } 107 }
96#elif defined (__TMS320C6X__) 108#elif defined (__TMS320C6X__)
97 { 109 {
@@ -111,11 +123,17 @@ PRUICSS_HwAttrs prussInitCfg[2] =
111 CSL_DSP_PRUSS1_U_INST_RAM0_12KB_REGS, 123 CSL_DSP_PRUSS1_U_INST_RAM0_12KB_REGS,
112 CSL_DSP_PRUSS1_U_INST_RAM1_12KB_REGS, 124 CSL_DSP_PRUSS1_U_INST_RAM1_12KB_REGS,
113 CSL_DSP_PRUSS1_U_DATA_RAM_32KB_REGS, 125 CSL_DSP_PRUSS1_U_DATA_RAM_32KB_REGS,
126 0U,
127 0U,
128 0U,
129 0U,
114 CSL_DSP_PRUSS1_U_DATA_RAM0_8KB_SIZE, 130 CSL_DSP_PRUSS1_U_DATA_RAM0_8KB_SIZE,
115 CSL_DSP_PRUSS1_U_DATA_RAM1_8KB_SIZE, 131 CSL_DSP_PRUSS1_U_DATA_RAM1_8KB_SIZE,
116 CSL_DSP_PRUSS1_U_INST_RAM0_12KB_SIZE, 132 CSL_DSP_PRUSS1_U_INST_RAM0_12KB_SIZE,
117 CSL_DSP_PRUSS1_U_INST_RAM1_12KB_SIZE, 133 CSL_DSP_PRUSS1_U_INST_RAM1_12KB_SIZE,
118 CSL_DSP_PRUSS1_U_DATA_RAM_32KB_SIZE 134 CSL_DSP_PRUSS1_U_DATA_RAM_32KB_SIZE,
135 0U,
136 0U
119 }, 137 },
120 { 138 {
121 0x4b280000, 139 0x4b280000,
@@ -134,11 +152,17 @@ PRUICSS_HwAttrs prussInitCfg[2] =
134 CSL_DSP_PRUSS2_U_INST_RAM0_12KB_REGS, 152 CSL_DSP_PRUSS2_U_INST_RAM0_12KB_REGS,
135 CSL_DSP_PRUSS2_U_INST_RAM1_12KB_REGS, 153 CSL_DSP_PRUSS2_U_INST_RAM1_12KB_REGS,
136 CSL_DSP_PRUSS2_U_DATA_RAM_32KB_REGS, 154 CSL_DSP_PRUSS2_U_DATA_RAM_32KB_REGS,
155 0U,
156 0U,
157 0U,
158 0U,
137 CSL_DSP_PRUSS2_U_DATA_RAM0_8KB_SIZE, 159 CSL_DSP_PRUSS2_U_DATA_RAM0_8KB_SIZE,
138 CSL_DSP_PRUSS2_U_DATA_RAM1_8KB_SIZE, 160 CSL_DSP_PRUSS2_U_DATA_RAM1_8KB_SIZE,
139 CSL_DSP_PRUSS2_U_INST_RAM0_12KB_SIZE, 161 CSL_DSP_PRUSS2_U_INST_RAM0_12KB_SIZE,
140 CSL_DSP_PRUSS2_U_INST_RAM1_12KB_SIZE, 162 CSL_DSP_PRUSS2_U_INST_RAM1_12KB_SIZE,
141 CSL_DSP_PRUSS2_U_DATA_RAM_32KB_SIZE 163 CSL_DSP_PRUSS2_U_DATA_RAM_32KB_SIZE,
164 0U,
165 0U
142 } 166 }
143#else 167#else
144 { 168 {
@@ -158,11 +182,17 @@ PRUICSS_HwAttrs prussInitCfg[2] =
158 CSL_MPU_PRUSS1_U_INST_RAM0_12KB_REGS, 182 CSL_MPU_PRUSS1_U_INST_RAM0_12KB_REGS,
159 CSL_MPU_PRUSS1_U_INST_RAM1_12KB_REGS, 183 CSL_MPU_PRUSS1_U_INST_RAM1_12KB_REGS,
160 CSL_MPU_PRUSS1_U_DATA_RAM_32KB_REGS, 184 CSL_MPU_PRUSS1_U_DATA_RAM_32KB_REGS,
185 0U,
186 0U,
187 0U,
188 0U,
161 CSL_MPU_PRUSS1_U_DATA_RAM0_8KB_SIZE, 189 CSL_MPU_PRUSS1_U_DATA_RAM0_8KB_SIZE,
162 CSL_MPU_PRUSS1_U_DATA_RAM1_8KB_SIZE, 190 CSL_MPU_PRUSS1_U_DATA_RAM1_8KB_SIZE,
163 CSL_MPU_PRUSS1_U_INST_RAM0_12KB_SIZE, 191 CSL_MPU_PRUSS1_U_INST_RAM0_12KB_SIZE,
164 CSL_MPU_PRUSS1_U_INST_RAM1_12KB_SIZE, 192 CSL_MPU_PRUSS1_U_INST_RAM1_12KB_SIZE,
165 CSL_MPU_PRUSS1_U_DATA_RAM_32KB_SIZE 193 CSL_MPU_PRUSS1_U_DATA_RAM_32KB_SIZE,
194 0U,
195 0U
166 }, 196 },
167 { 197 {
168 0x4b280000, 198 0x4b280000,
@@ -181,11 +211,17 @@ PRUICSS_HwAttrs prussInitCfg[2] =
181 CSL_MPU_PRUSS2_U_INST_RAM0_12KB_REGS, 211 CSL_MPU_PRUSS2_U_INST_RAM0_12KB_REGS,
182 CSL_MPU_PRUSS2_U_INST_RAM1_12KB_REGS, 212 CSL_MPU_PRUSS2_U_INST_RAM1_12KB_REGS,
183 CSL_MPU_PRUSS2_U_DATA_RAM_32KB_REGS, 213 CSL_MPU_PRUSS2_U_DATA_RAM_32KB_REGS,
214 0U,
215 0U,
216 0U,
217 0U,
184 CSL_MPU_PRUSS2_U_DATA_RAM0_8KB_SIZE, 218 CSL_MPU_PRUSS2_U_DATA_RAM0_8KB_SIZE,
185 CSL_MPU_PRUSS2_U_DATA_RAM1_8KB_SIZE, 219 CSL_MPU_PRUSS2_U_DATA_RAM1_8KB_SIZE,
186 CSL_MPU_PRUSS2_U_INST_RAM0_12KB_SIZE, 220 CSL_MPU_PRUSS2_U_INST_RAM0_12KB_SIZE,
187 CSL_MPU_PRUSS2_U_INST_RAM1_12KB_SIZE, 221 CSL_MPU_PRUSS2_U_INST_RAM1_12KB_SIZE,
188 CSL_MPU_PRUSS2_U_DATA_RAM_32KB_SIZE 222 CSL_MPU_PRUSS2_U_DATA_RAM_32KB_SIZE,
223 0U,
224 0U
189 } 225 }
190#endif 226#endif
191}; 227};
diff --git a/soc/am574x/pruicss_soc.c b/soc/am574x/pruicss_soc.c
index 8142cca..049767f 100644
--- a/soc/am574x/pruicss_soc.c
+++ b/soc/am574x/pruicss_soc.c
@@ -4,7 +4,7 @@
4 * @brief This is soc specific configuration file . 4 * @brief This is soc specific configuration file .
5 */ 5 */
6/* 6/*
7 * Copyright (c) 2017, Texas Instruments Incorporated 7 * Copyright (c) 2017-2018, Texas Instruments Incorporated
8 * All rights reserved. 8 * All rights reserved.
9 * 9 *
10 * Redistribution and use in source and binary forms, with or without 10 * Redistribution and use in source and binary forms, with or without
@@ -64,11 +64,17 @@ PRUICSS_HwAttrs prussInitCfg[2] =
64 CSL_IPU_PRUSS1_U_INST_RAM0_12KB_REGS, 64 CSL_IPU_PRUSS1_U_INST_RAM0_12KB_REGS,
65 CSL_IPU_PRUSS1_U_INST_RAM1_12KB_REGS, 65 CSL_IPU_PRUSS1_U_INST_RAM1_12KB_REGS,
66 CSL_IPU_PRUSS1_U_DATA_RAM_32KB_REGS, 66 CSL_IPU_PRUSS1_U_DATA_RAM_32KB_REGS,
67 0U,
68 0U,
69 0U,
70 0U,
67 CSL_IPU_PRUSS1_U_DATA_RAM0_8KB_SIZE, 71 CSL_IPU_PRUSS1_U_DATA_RAM0_8KB_SIZE,
68 CSL_IPU_PRUSS1_U_DATA_RAM1_8KB_SIZE, 72 CSL_IPU_PRUSS1_U_DATA_RAM1_8KB_SIZE,
69 CSL_IPU_PRUSS1_U_INST_RAM0_12KB_SIZE, 73 CSL_IPU_PRUSS1_U_INST_RAM0_12KB_SIZE,
70 CSL_IPU_PRUSS1_U_INST_RAM1_12KB_SIZE, 74 CSL_IPU_PRUSS1_U_INST_RAM1_12KB_SIZE,
71 CSL_IPU_PRUSS1_U_DATA_RAM_32KB_SIZE 75 CSL_IPU_PRUSS1_U_DATA_RAM_32KB_SIZE,
76 0U,
77 0U
72 }, 78 },
73 { 79 {
74 0x4b280000, 80 0x4b280000,
@@ -87,11 +93,17 @@ PRUICSS_HwAttrs prussInitCfg[2] =
87 CSL_IPU_PRUSS2_U_INST_RAM0_12KB_REGS, 93 CSL_IPU_PRUSS2_U_INST_RAM0_12KB_REGS,
88 CSL_IPU_PRUSS2_U_INST_RAM1_12KB_REGS, 94 CSL_IPU_PRUSS2_U_INST_RAM1_12KB_REGS,
89 CSL_IPU_PRUSS2_U_DATA_RAM_32KB_REGS, 95 CSL_IPU_PRUSS2_U_DATA_RAM_32KB_REGS,
96 0U,
97 0U,
98 0U,
99 0U,
90 CSL_IPU_PRUSS2_U_DATA_RAM0_8KB_SIZE, 100 CSL_IPU_PRUSS2_U_DATA_RAM0_8KB_SIZE,
91 CSL_IPU_PRUSS2_U_DATA_RAM1_8KB_SIZE, 101 CSL_IPU_PRUSS2_U_DATA_RAM1_8KB_SIZE,
92 CSL_IPU_PRUSS2_U_INST_RAM0_12KB_SIZE, 102 CSL_IPU_PRUSS2_U_INST_RAM0_12KB_SIZE,
93 CSL_IPU_PRUSS2_U_INST_RAM1_12KB_SIZE, 103 CSL_IPU_PRUSS2_U_INST_RAM1_12KB_SIZE,
94 CSL_IPU_PRUSS2_U_DATA_RAM_32KB_SIZE 104 CSL_IPU_PRUSS2_U_DATA_RAM_32KB_SIZE,
105 0U,
106 0U
95 } 107 }
96#elif defined (__TMS320C6X__) 108#elif defined (__TMS320C6X__)
97 { 109 {
@@ -111,11 +123,17 @@ PRUICSS_HwAttrs prussInitCfg[2] =
111 CSL_DSP_PRUSS1_U_INST_RAM0_12KB_REGS, 123 CSL_DSP_PRUSS1_U_INST_RAM0_12KB_REGS,
112 CSL_DSP_PRUSS1_U_INST_RAM1_12KB_REGS, 124 CSL_DSP_PRUSS1_U_INST_RAM1_12KB_REGS,
113 CSL_DSP_PRUSS1_U_DATA_RAM_32KB_REGS, 125 CSL_DSP_PRUSS1_U_DATA_RAM_32KB_REGS,
126 0U,
127 0U,
128 0U,
129 0U,
114 CSL_DSP_PRUSS1_U_DATA_RAM0_8KB_SIZE, 130 CSL_DSP_PRUSS1_U_DATA_RAM0_8KB_SIZE,
115 CSL_DSP_PRUSS1_U_DATA_RAM1_8KB_SIZE, 131 CSL_DSP_PRUSS1_U_DATA_RAM1_8KB_SIZE,
116 CSL_DSP_PRUSS1_U_INST_RAM0_12KB_SIZE, 132 CSL_DSP_PRUSS1_U_INST_RAM0_12KB_SIZE,
117 CSL_DSP_PRUSS1_U_INST_RAM1_12KB_SIZE, 133 CSL_DSP_PRUSS1_U_INST_RAM1_12KB_SIZE,
118 CSL_DSP_PRUSS1_U_DATA_RAM_32KB_SIZE 134 CSL_DSP_PRUSS1_U_DATA_RAM_32KB_SIZE,
135 0U,
136 0U
119 }, 137 },
120 { 138 {
121 0x4b280000, 139 0x4b280000,
@@ -134,11 +152,17 @@ PRUICSS_HwAttrs prussInitCfg[2] =
134 CSL_DSP_PRUSS2_U_INST_RAM0_12KB_REGS, 152 CSL_DSP_PRUSS2_U_INST_RAM0_12KB_REGS,
135 CSL_DSP_PRUSS2_U_INST_RAM1_12KB_REGS, 153 CSL_DSP_PRUSS2_U_INST_RAM1_12KB_REGS,
136 CSL_DSP_PRUSS2_U_DATA_RAM_32KB_REGS, 154 CSL_DSP_PRUSS2_U_DATA_RAM_32KB_REGS,
155 0U,
156 0U,
157 0U,
158 0U,
137 CSL_DSP_PRUSS2_U_DATA_RAM0_8KB_SIZE, 159 CSL_DSP_PRUSS2_U_DATA_RAM0_8KB_SIZE,
138 CSL_DSP_PRUSS2_U_DATA_RAM1_8KB_SIZE, 160 CSL_DSP_PRUSS2_U_DATA_RAM1_8KB_SIZE,
139 CSL_DSP_PRUSS2_U_INST_RAM0_12KB_SIZE, 161 CSL_DSP_PRUSS2_U_INST_RAM0_12KB_SIZE,
140 CSL_DSP_PRUSS2_U_INST_RAM1_12KB_SIZE, 162 CSL_DSP_PRUSS2_U_INST_RAM1_12KB_SIZE,
141 CSL_DSP_PRUSS2_U_DATA_RAM_32KB_SIZE 163 CSL_DSP_PRUSS2_U_DATA_RAM_32KB_SIZE,
164 0U,
165 0U
142 } 166 }
143#else 167#else
144 { 168 {
@@ -158,11 +182,17 @@ PRUICSS_HwAttrs prussInitCfg[2] =
158 CSL_MPU_PRUSS1_U_INST_RAM0_12KB_REGS, 182 CSL_MPU_PRUSS1_U_INST_RAM0_12KB_REGS,
159 CSL_MPU_PRUSS1_U_INST_RAM1_12KB_REGS, 183 CSL_MPU_PRUSS1_U_INST_RAM1_12KB_REGS,
160 CSL_MPU_PRUSS1_U_DATA_RAM_32KB_REGS, 184 CSL_MPU_PRUSS1_U_DATA_RAM_32KB_REGS,
185 0U,
186 0U,
187 0U,
188 0U,
161 CSL_MPU_PRUSS1_U_DATA_RAM0_8KB_SIZE, 189 CSL_MPU_PRUSS1_U_DATA_RAM0_8KB_SIZE,
162 CSL_MPU_PRUSS1_U_DATA_RAM1_8KB_SIZE, 190 CSL_MPU_PRUSS1_U_DATA_RAM1_8KB_SIZE,
163 CSL_MPU_PRUSS1_U_INST_RAM0_12KB_SIZE, 191 CSL_MPU_PRUSS1_U_INST_RAM0_12KB_SIZE,
164 CSL_MPU_PRUSS1_U_INST_RAM1_12KB_SIZE, 192 CSL_MPU_PRUSS1_U_INST_RAM1_12KB_SIZE,
165 CSL_MPU_PRUSS1_U_DATA_RAM_32KB_SIZE 193 CSL_MPU_PRUSS1_U_DATA_RAM_32KB_SIZE,
194 0U,
195 0U
166 }, 196 },
167 { 197 {
168 0x4b280000, 198 0x4b280000,
@@ -181,11 +211,17 @@ PRUICSS_HwAttrs prussInitCfg[2] =
181 CSL_MPU_PRUSS2_U_INST_RAM0_12KB_REGS, 211 CSL_MPU_PRUSS2_U_INST_RAM0_12KB_REGS,
182 CSL_MPU_PRUSS2_U_INST_RAM1_12KB_REGS, 212 CSL_MPU_PRUSS2_U_INST_RAM1_12KB_REGS,
183 CSL_MPU_PRUSS2_U_DATA_RAM_32KB_REGS, 213 CSL_MPU_PRUSS2_U_DATA_RAM_32KB_REGS,
214 0U,
215 0U,
216 0U,
217 0U,
184 CSL_MPU_PRUSS2_U_DATA_RAM0_8KB_SIZE, 218 CSL_MPU_PRUSS2_U_DATA_RAM0_8KB_SIZE,
185 CSL_MPU_PRUSS2_U_DATA_RAM1_8KB_SIZE, 219 CSL_MPU_PRUSS2_U_DATA_RAM1_8KB_SIZE,
186 CSL_MPU_PRUSS2_U_INST_RAM0_12KB_SIZE, 220 CSL_MPU_PRUSS2_U_INST_RAM0_12KB_SIZE,
187 CSL_MPU_PRUSS2_U_INST_RAM1_12KB_SIZE, 221 CSL_MPU_PRUSS2_U_INST_RAM1_12KB_SIZE,
188 CSL_MPU_PRUSS2_U_DATA_RAM_32KB_SIZE 222 CSL_MPU_PRUSS2_U_DATA_RAM_32KB_SIZE,
223 0U,
224 0U
189 } 225 }
190#endif 226#endif
191}; 227};
diff --git a/soc/am65xx/pruicss_soc.c b/soc/am65xx/pruicss_soc.c
new file mode 100644
index 0000000..71f3997
--- /dev/null
+++ b/soc/am65xx/pruicss_soc.c
@@ -0,0 +1,160 @@
1/**
2 * @file pruicss_soc.c
3 *
4 * @brief This is device specific configuration file .
5 */
6/*
7 * Copyright (c) 2017-2018, Texas Instruments Incorporated
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 *
14 * * Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 *
17 * * Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 *
21 * * Neither the name of Texas Instruments Incorporated nor the names of
22 * its contributors may be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
27 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
29 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
30 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
31 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
32 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
33 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
34 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
35 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37/** ============================================================================*/
38
39
40#include <stdint.h>
41#include <ti/drv/pruss/pruicss.h>
42#include <ti/drv/pruss/soc/pruicss_v1.h>
43
44
45
46#include <ti/csl/soc/am65xx/src/cslr_soc.h>
47
48/* PRUICSS configuration structure */
49PRUICSS_HwAttrs prussInitCfg[3] =
50{
51 {
52 CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE, /* baseAddr */
53 0, /* version */
54 CSL_PRU_ICSSG0_PR1_PDSP0_IRAM_BASE, /* prussPru0CtrlRegBase */
55 CSL_PRU_ICSSG0_PR1_PDSP1_IRAM_BASE, /* prussPru1CtrlRegBase */
56 CSL_PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV_BASE, /* prussIntcRegBase */
57 CSL_PRU_ICSSG0_PR1_CFG_SLV_BASE, /* prussCfgRegBase */
58 CSL_PRU_ICSSG0_PR1_ICSS_UART_UART_SLV_BASE, /* prussUartRegBase */
59 CSL_PRU_ICSSG0_IEP0_BASE, /* prussIepRegBase */
60 CSL_PRU_ICSSG0_PR1_ICSS_ECAP0_ECAP_SLV_BASE, /* prussEcapRegBase */
61 CSL_PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_CFG_BASE, /* prussMiiRtCfgRegBase */
62 CSL_PRU_ICSSG0_PR1_MDIO_V1P7_MDIO_BASE, /* prussMiiMdioRegBase */
63 CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE, /* prussPru0DramBase */
64 CSL_PRU_ICSSG0_DRAM1_SLV_RAM_BASE, /* prussPru1DramBase */
65 CSL_PRU_ICSSG0_PR1_PDSP0_IRAM_RAM_BASE, /* prussPru0IramBase */
66 CSL_PRU_ICSSG0_PR1_PDSP1_IRAM_RAM_BASE, /* prussPru1IramBase */
67 CSL_PRU_ICSSG0_RAM_SLV_RAM_BASE, /* prussSharedDramBase */
68 CSL_PRU_ICSSG0_PR1_RTU0_PR1_RTU0_IRAM_RAM_BASE, /* prussRtu0IramBase */
69 CSL_PRU_ICSSG0_PR1_RTU1_PR1_RTU1_IRAM_RAM_BASE, /* prussRtu1IramBase */
70 CSL_PRU_ICSSG0_PR1_RTU0_PR1_RTU0_IRAM_BASE, /* prussRtu0CtrlRegBase */
71 CSL_PRU_ICSSG0_PR1_RTU1_PR1_RTU1_IRAM_BASE, /* prussRtu1CtrlRegBase */
72 CSL_PRU_ICSSG0_DRAM0_SLV_RAM_SIZE, /* prussPru0DramSize */
73 CSL_PRU_ICSSG0_DRAM1_SLV_RAM_SIZE, /* prussPru1DramSize */
74 CSL_PRU_ICSSG0_PR1_PDSP0_IRAM_SIZE, /* prussPru0IramSize */
75 CSL_PRU_ICSSG0_PR1_PDSP1_IRAM_SIZE, /* prussPru1IramSize */
76 CSL_PRU_ICSSG0_RAM_SLV_RAM_SIZE, /* prussSharedDramSize */
77 CSL_PRU_ICSSG0_PR1_RTU0_PR1_RTU0_IRAM_RAM_SIZE, /* prussRtu0IramSize */
78 CSL_PRU_ICSSG0_PR1_RTU1_PR1_RTU1_IRAM_RAM_SIZE /* prussRtu1IramSize */
79 },
80 {
81 CSL_PRU_ICSSG1_DRAM0_SLV_RAM_BASE, /* baseAddr */
82 0, /* version */
83 CSL_PRU_ICSSG1_PR1_PDSP0_IRAM_BASE, /* prussPru0CtrlRegBase */
84 CSL_PRU_ICSSG1_PR1_PDSP1_IRAM_BASE, /* prussPru1CtrlRegBase */
85 CSL_PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV_BASE, /* prussIntcRegBase */
86 CSL_PRU_ICSSG1_PR1_CFG_SLV_BASE, /* prussCfgRegBase */
87 CSL_PRU_ICSSG1_PR1_ICSS_UART_UART_SLV_BASE, /* prussUartRegBase */
88 CSL_PRU_ICSSG1_IEP0_BASE, /* prussIepRegBase */
89 CSL_PRU_ICSSG1_PR1_ICSS_ECAP0_ECAP_SLV_BASE, /* prussEcapRegBase */
90 CSL_PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_CFG_BASE, /* prussMiiRtCfgRegBase */
91 CSL_PRU_ICSSG1_PR1_MDIO_V1P7_MDIO_BASE, /* prussMiiMdioRegBase */
92 CSL_PRU_ICSSG1_DRAM0_SLV_RAM_BASE, /* prussPru0DramBase */
93 CSL_PRU_ICSSG1_DRAM1_SLV_RAM_BASE, /* prussPru1DramBase */
94 CSL_PRU_ICSSG1_PR1_PDSP0_IRAM_RAM_BASE, /* prussPru0IramBase */
95 CSL_PRU_ICSSG1_PR1_PDSP1_IRAM_RAM_BASE, /* prussPru1IramBase */
96 CSL_PRU_ICSSG1_RAM_SLV_RAM_BASE, /* prussSharedDramBase */
97 CSL_PRU_ICSSG1_PR1_RTU0_PR1_RTU0_IRAM_RAM_BASE, /* prussRtu0IramBase */
98 CSL_PRU_ICSSG1_PR1_RTU1_PR1_RTU1_IRAM_RAM_BASE, /* prussRtu1IramBase */
99 CSL_PRU_ICSSG1_PR1_RTU0_PR1_RTU0_IRAM_BASE, /* prussRtu0CtrlRegBase */
100 CSL_PRU_ICSSG1_PR1_RTU1_PR1_RTU1_IRAM_BASE, /* prussRtu1CtrlRegBase */
101 CSL_PRU_ICSSG1_DRAM0_SLV_RAM_SIZE, /* prussPru0DramSize */
102 CSL_PRU_ICSSG1_DRAM1_SLV_RAM_SIZE, /* prussPru1DramSize */
103 CSL_PRU_ICSSG1_PR1_PDSP0_IRAM_SIZE, /* prussPru0IramSize */
104 CSL_PRU_ICSSG1_PR1_PDSP1_IRAM_SIZE, /* prussPru1IramSize */
105 CSL_PRU_ICSSG1_RAM_SLV_RAM_SIZE, /* prussSharedDramSize */
106 CSL_PRU_ICSSG1_PR1_RTU0_PR1_RTU0_IRAM_RAM_SIZE, /* prussRtu0IramSize */
107 CSL_PRU_ICSSG1_PR1_RTU1_PR1_RTU1_IRAM_RAM_SIZE /* prussRtu1IramSize */
108 },
109 {
110 CSL_PRU_ICSSG2_DRAM0_SLV_RAM_BASE, /* baseAddr */
111 0, /* version */
112 CSL_PRU_ICSSG2_PR1_PDSP0_IRAM_BASE, /* prussPru0CtrlRegBase */
113 CSL_PRU_ICSSG2_PR1_PDSP1_IRAM_BASE, /* prussPru1CtrlRegBase */
114 CSL_PRU_ICSSG2_PR1_ICSS_INTC_INTC_SLV_BASE, /* prussIntcRegBase */
115 CSL_PRU_ICSSG2_PR1_CFG_SLV_BASE, /* prussCfgRegBase */
116 CSL_PRU_ICSSG2_PR1_ICSS_UART_UART_SLV_BASE, /* prussUartRegBase */
117 CSL_PRU_ICSSG2_IEP0_BASE, /* prussIepRegBase */
118 CSL_PRU_ICSSG2_PR1_ICSS_ECAP0_ECAP_SLV_BASE, /* prussEcapRegBase */
119 CSL_PRU_ICSSG2_PR1_MII_RT_PR1_MII_RT_CFG_BASE, /* prussMiiRtCfgRegBase */
120 CSL_PRU_ICSSG2_PR1_MDIO_V1P7_MDIO_BASE, /* prussMiiMdioRegBase */
121 CSL_PRU_ICSSG2_DRAM0_SLV_RAM_BASE, /* prussPru0DramBase */
122 CSL_PRU_ICSSG2_DRAM1_SLV_RAM_BASE, /* prussPru1DramBase */
123 CSL_PRU_ICSSG2_PR1_PDSP0_IRAM_RAM_BASE, /* prussPru0IramBase */
124 CSL_PRU_ICSSG2_PR1_PDSP1_IRAM_RAM_BASE, /* prussPru1IramBase */
125 CSL_PRU_ICSSG2_RAM_SLV_RAM_BASE, /* prussSharedDramBase */
126 CSL_PRU_ICSSG2_PR1_RTU0_PR1_RTU0_IRAM_RAM_BASE, /* prussRtu0IramBase */
127 CSL_PRU_ICSSG2_PR1_RTU1_PR1_RTU1_IRAM_RAM_BASE, /* prussRtu1IramBase */
128 CSL_PRU_ICSSG2_PR1_RTU0_PR1_RTU0_IRAM_BASE, /* prussRtu0CtrlRegBase */
129 CSL_PRU_ICSSG2_PR1_RTU1_PR1_RTU1_IRAM_BASE, /* prussRtu1CtrlRegBase */
130 CSL_PRU_ICSSG2_DRAM0_SLV_RAM_SIZE, /* prussPru0DramSize */
131 CSL_PRU_ICSSG2_DRAM1_SLV_RAM_SIZE, /* prussPru1DramSize */
132 CSL_PRU_ICSSG2_PR1_PDSP0_IRAM_SIZE, /* prussPru0IramSize */
133 CSL_PRU_ICSSG2_PR1_PDSP1_IRAM_SIZE, /* prussPru1IramSize */
134 CSL_PRU_ICSSG2_RAM_SLV_RAM_SIZE, /* prussSharedDramSize */
135 CSL_PRU_ICSSG2_PR1_RTU0_PR1_RTU0_IRAM_RAM_SIZE, /* prussRtu0IramSize */
136 CSL_PRU_ICSSG2_PR1_RTU1_PR1_RTU1_IRAM_RAM_SIZE /* prussRtu1IramSize */
137 }
138};
139
140/* PRUICSS objects */
141PRUICSS_V1_Object prussObjects[PRUICCSS_INSTANCE_MAX];
142
143/* PRUICSS configuration structure */
144PRUICSS_Config pruss_config[PRUICCSS_INSTANCE_MAX] = {
145 {
146 &prussObjects[0],
147 &prussInitCfg[0]
148 },
149 {
150 &prussObjects[1],
151 &prussInitCfg[1]
152 },
153 {
154 &prussObjects[2],
155 &prussInitCfg[2]
156 }
157};
158
159
160
diff --git a/soc/k2g/pruicss_soc.c b/soc/k2g/pruicss_soc.c
index 8a7123a..4f39705 100644
--- a/soc/k2g/pruicss_soc.c
+++ b/soc/k2g/pruicss_soc.c
@@ -4,7 +4,7 @@
4 * @brief This is device specific configuration file . 4 * @brief This is device specific configuration file .
5 */ 5 */
6/* 6/*
7 * Copyright (c) 2016, Texas Instruments Incorporated 7 * Copyright (c) 2016-2018, Texas Instruments Incorporated
8 * All rights reserved. 8 * All rights reserved.
9 * 9 *
10 * Redistribution and use in source and binary forms, with or without 10 * Redistribution and use in source and binary forms, with or without
@@ -65,11 +65,17 @@ PRUICSS_HwAttrs prussInitCfg[2] =
65 CSL_ICSS_0_INST_RAM_16KB_0_REGS, 65 CSL_ICSS_0_INST_RAM_16KB_0_REGS,
66 CSL_ICSS_0_INST_RAM_16KB_1_REGS, 66 CSL_ICSS_0_INST_RAM_16KB_1_REGS,
67 CSL_ICSS_0_DATA_RAM_64KB_REGS, 67 CSL_ICSS_0_DATA_RAM_64KB_REGS,
68 0U,
69 0U,
70 0U,
71 0U,
68 CSL_ICSS_0_DATA_RAM_8KB_0_REGS_SIZE, 72 CSL_ICSS_0_DATA_RAM_8KB_0_REGS_SIZE,
69 CSL_ICSS_0_DATA_RAM_8KB_1_REGS_SIZE, 73 CSL_ICSS_0_DATA_RAM_8KB_1_REGS_SIZE,
70 CSL_ICSS_0_INST_RAM_16KB_0_REGS_SIZE, 74 CSL_ICSS_0_INST_RAM_16KB_0_REGS_SIZE,
71 CSL_ICSS_0_INST_RAM_16KB_1_REGS_SIZE, 75 CSL_ICSS_0_INST_RAM_16KB_1_REGS_SIZE,
72 CSL_ICSS_0_DATA_RAM_64KB_REGS_SIZE 76 CSL_ICSS_0_DATA_RAM_64KB_REGS_SIZE,
77 0U,
78 0U,
73 }, 79 },
74 { 80 {
75 CSL_ICSS_1_DATA_RAM_8KB_0_REGS, 81 CSL_ICSS_1_DATA_RAM_8KB_0_REGS,
@@ -88,11 +94,17 @@ PRUICSS_HwAttrs prussInitCfg[2] =
88 CSL_ICSS_1_INST_RAM_16KB_0_REGS, 94 CSL_ICSS_1_INST_RAM_16KB_0_REGS,
89 CSL_ICSS_1_INST_RAM_16KB_1_REGS, 95 CSL_ICSS_1_INST_RAM_16KB_1_REGS,
90 CSL_ICSS_1_DATA_RAM_64KB_REGS, 96 CSL_ICSS_1_DATA_RAM_64KB_REGS,
97 0U,
98 0U,
99 0U,
100 0U,
91 CSL_ICSS_0_DATA_RAM_8KB_0_REGS_SIZE, 101 CSL_ICSS_0_DATA_RAM_8KB_0_REGS_SIZE,
92 CSL_ICSS_0_DATA_RAM_8KB_1_REGS_SIZE, 102 CSL_ICSS_0_DATA_RAM_8KB_1_REGS_SIZE,
93 CSL_ICSS_0_INST_RAM_16KB_0_REGS_SIZE, 103 CSL_ICSS_0_INST_RAM_16KB_0_REGS_SIZE,
94 CSL_ICSS_0_INST_RAM_16KB_1_REGS_SIZE, 104 CSL_ICSS_0_INST_RAM_16KB_1_REGS_SIZE,
95 CSL_ICSS_0_DATA_RAM_64KB_REGS_SIZE 105 CSL_ICSS_0_DATA_RAM_64KB_REGS_SIZE,
106 0U,
107 0U
96 } 108 }
97}; 109};
98 110
diff --git a/soc/pruicss_v1.h b/soc/pruicss_v1.h
index 44d2bef..3af9932 100644
--- a/soc/pruicss_v1.h
+++ b/soc/pruicss_v1.h
@@ -56,9 +56,9 @@ typedef struct PRUICSS_V1_Object_s
56{ 56{
57 57
58 uint32_t pruicss_version; 58 uint32_t pruicss_version;
59 int32_t instance; /* PRUICSS write semaphore*/ 59 int32_t instance; /* PRUICSS write semaphore*/
60 void* pruBinBuff[2]; /* Buffer data pointer */ 60 void* pruBinBuff[4]; /* Buffer data pointer */
61 uint32_t buffLen[2]; 61 uint32_t buffLen[4];
62 PRUICSS_IrqFunMap pruEvntOutFnMapArray[PRUICSS_MAX_WAIT_EVENTS]; 62 PRUICSS_IrqFunMap pruEvntOutFnMapArray[PRUICSS_MAX_WAIT_EVENTS];
63 63
64 }PRUICSS_V1_Object; 64 }PRUICSS_V1_Object;
@@ -70,37 +70,45 @@ typedef struct PRUICSS_V1_Object_s
70 */ 70 */
71typedef struct PRUICSS_HWAttrs { 71typedef struct PRUICSS_HWAttrs {
72 /*PRUICSS Peripheral's base address for each PRUICSS instance*/ 72 /*PRUICSS Peripheral's base address for each PRUICSS instance*/
73 uint32_t baseAddr; 73 uintptr_t baseAddr;
74 74
75 uint32_t version; 75 uint32_t version;
76 76
77 uint32_t prussPru0CtrlRegBase; 77 uintptr_t prussPru0CtrlRegBase;
78 78
79 uint32_t prussPru1CtrlRegBase; 79 uintptr_t prussPru1CtrlRegBase;
80 80
81 uint32_t prussIntcRegBase; 81 uintptr_t prussIntcRegBase;
82 82
83 uint32_t prussCfgRegBase; 83 uintptr_t prussCfgRegBase;
84 84
85 uint32_t prussUartRegBase; 85 uintptr_t prussUartRegBase;
86 86
87 uint32_t prussIepRegBase; 87 uintptr_t prussIepRegBase;
88 88
89 uint32_t prussEcapRegBase; 89 uintptr_t prussEcapRegBase;
90 90
91 uint32_t prussMiiRtCfgRegBase; 91 uintptr_t prussMiiRtCfgRegBase;
92 92
93 uint32_t prussMiiMdioRegBase; 93 uintptr_t prussMiiMdioRegBase;
94 94
95 uint32_t prussPru0DramBase; 95 uintptr_t prussPru0DramBase;
96 96
97 uint32_t prussPru1DramBase; 97 uintptr_t prussPru1DramBase;
98 98
99 uint32_t prussPru0IramBase; 99 uintptr_t prussPru0IramBase;
100 100
101 uint32_t prussPru1IramBase; 101 uintptr_t prussPru1IramBase;
102 102
103 uint32_t prussSharedDramBase; 103 uintptr_t prussSharedDramBase;
104
105 uintptr_t prussRtu0IramBase;
106
107 uintptr_t prussRtu1IramBase;
108
109 uintptr_t prussRtu0CtrlRegBase;
110
111 uintptr_t prussRtu1CtrlRegBase;
104 112
105 uint32_t prussPru0DramSize; 113 uint32_t prussPru0DramSize;
106 114
@@ -111,6 +119,11 @@ typedef struct PRUICSS_HWAttrs {
111 uint32_t prussPru1IramSize; 119 uint32_t prussPru1IramSize;
112 120
113 uint32_t prussSharedDramSize; 121 uint32_t prussSharedDramSize;
122
123 uint32_t prussRtu0IramSize;
124
125 uint32_t prussRtu1IramSize;
126
114} PRUICSS_HwAttrs; 127} PRUICSS_HwAttrs;
115 128
116 129
@@ -120,13 +133,14 @@ typedef enum PRUSS_PruCores_s
120{ 133{
121 PRUICCSS_PRU0, 134 PRUICCSS_PRU0,
122 PRUICCSS_PRU1, 135 PRUICCSS_PRU1,
136 PRUICCSS_RTU0,
137 PRUICCSS_RTU1,
123 PRUICSS_MAX_PRU 138 PRUICSS_MAX_PRU
124}PRUSS_PruCores; 139}PRUSS_PruCores;
125 140
126
127#define PRU_ICSS_DATARAM(n) (0x00000U + ((n) * 0x02000U)) 141#define PRU_ICSS_DATARAM(n) (0x00000U + ((n) * 0x02000U))
128#define PRU_ICSS_SHARED_RAM (0x10000U) 142#define PRU_ICSS_SHARED_RAM (0x10000U)
129#define PRU_ICSS_IRAM(n) (0x34000U + ((n) * 0x04000U)) 143#define PRU_ICSS_IRAM(n) (((n) < 2U) ? (0x34000U + ((n) * 0x04000U)) : (0x4000U + ((n)-2U) * 0x2000U))
130 144
131#define PRU_ICSS_REVISION_MAJOR_MASK (0x00000700) 145#define PRU_ICSS_REVISION_MAJOR_MASK (0x00000700)
132#define PRU_ICSS_REVISION_MINOR_MASK (0x0000003F) 146#define PRU_ICSS_REVISION_MINOR_MASK (0x0000003F)
diff --git a/src/pruicss_drv.c b/src/pruicss_drv.c
index 2e7636a..5794d1a 100644
--- a/src/pruicss_drv.c
+++ b/src/pruicss_drv.c
@@ -1,5 +1,5 @@
1/* 1/*
2* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ 2* Copyright (C) 2015-2018 Texas Instruments Incorporated - http://www.ti.com/
3* 3*
4* 4*
5* Redistribution and use in source and binary forms, with or without 5* Redistribution and use in source and binary forms, with or without
@@ -39,10 +39,12 @@
39 * PRU instance, Load program to PRU and Write to PRU memory. 39 * PRU instance, Load program to PRU and Write to PRU memory.
40 ============================================================================*/ 40 ============================================================================*/
41#include <stdint.h> 41#include <stdint.h>
42#include <string.h>
42#include <ti/drv/pruss/pruicss.h> 43#include <ti/drv/pruss/pruicss.h>
43#include <ti/drv/pruss/soc/pruicss_v1.h> 44#include <ti/drv/pruss/soc/pruicss_v1.h>
44#include <ti/drv/pruss/src/pruicss_osal.h> 45#include <ti/drv/pruss/src/pruicss_osal.h>
45 46
47#include <ti/csl/cslr.h>
46#include <ti/csl/src/ip/icss/V1/cslr_icss_pru_ctrl.h> 48#include <ti/csl/src/ip/icss/V1/cslr_icss_pru_ctrl.h>
47#include <ti/csl/src/ip/icss/V1/cslr_icss_intc.h> 49#include <ti/csl/src/ip/icss/V1/cslr_icss_intc.h>
48#include <ti/csl/src/ip/icss/V1/cslr_icss_cfg.h> 50#include <ti/csl/src/ip/icss/V1/cslr_icss_cfg.h>
@@ -58,6 +60,47 @@
58/* Value that needs to be written to bit 0 of PRU_ICSS CTRL register to soft reset PRU*/ 60/* Value that needs to be written to bit 0 of PRU_ICSS CTRL register to soft reset PRU*/
59#define PRUICSS_PRU_SOFT_RESET_VAL ((uint32_t)0U) 61#define PRUICSS_PRU_SOFT_RESET_VAL ((uint32_t)0U)
60 62
63static uintptr_t pruicss_get_ctrl_addr (PRUICSS_HwAttrs const *hwAttrs,
64 int32_t instance,
65 uint8_t pruNum);
66
67static uintptr_t pruicss_get_ctrl_addr (PRUICSS_HwAttrs const *hwAttrs,
68 int32_t instance,
69 uint8_t pruNum)
70{
71 uintptr_t baseaddr;
72
73 if ((instance >= PRUICCSS_INSTANCE_ONE) && (instance <= PRUICCSS_INSTANCE_MAX))
74 {
75 if(PRUICCSS_PRU0 == pruNum)
76 {
77 baseaddr = hwAttrs->prussPru0CtrlRegBase;
78 }
79 else if(PRUICCSS_PRU1 == pruNum)
80 {
81 baseaddr = hwAttrs->prussPru1CtrlRegBase;
82 }
83 else if(PRUICCSS_RTU0 == pruNum)
84 {
85 baseaddr = hwAttrs->prussRtu0CtrlRegBase;
86 }
87 else if(PRUICCSS_RTU1 == pruNum)
88 {
89 baseaddr = hwAttrs->prussRtu1CtrlRegBase;
90 }
91 else
92 {
93 baseaddr = 0;
94 }
95 }
96 else
97 {
98 baseaddr = 0;
99 }
100
101 return baseaddr;
102}
103
61/**************************************************************************/ 104/**************************************************************************/
62/* API FUNCTION DEFINITIONS */ 105/* API FUNCTION DEFINITIONS */
63/**************************************************************************/ 106/**************************************************************************/
@@ -69,19 +112,21 @@
69 * 112 *
70 * @return PRUICSS handle. \n 113 * @return PRUICSS handle. \n
71 */ 114 */
72PRUICSS_Handle PRUICSS_create(PRUICSS_Config *config ,int32_t instance) 115PRUICSS_Handle PRUICSS_create(PRUICSS_Config *config, int32_t instance)
73{ 116{
74 PRUICSS_Handle handle; 117 PRUICSS_Handle handle;
75 PRUICSS_V1_Object *object; 118 PRUICSS_V1_Object *object;
76 PRUICSS_HwAttrs const *hwAttrs; 119 PRUICSS_HwAttrs const *hwAttrs;
77 uint32_t temp_addr = 0U; 120 uintptr_t temp_addr = 0U;
121 uint32_t temp_val;
78 122
79 handle = (PRUICSS_Config *)&config[instance-1]; 123 handle = (PRUICSS_Config *)&config[instance-1];
80 hwAttrs = (PRUICSS_HwAttrs const *)handle->hwAttrs; 124 hwAttrs = (PRUICSS_HwAttrs const *)handle->hwAttrs;
81 object = (PRUICSS_V1_Object*)handle->object; 125 object = (PRUICSS_V1_Object*)handle->object;
82 object->instance = instance; 126 object->instance = instance;
83 temp_addr = (hwAttrs->prussCfgRegBase + CSL_ICSSCFG_REVID); 127 temp_addr = (hwAttrs->prussCfgRegBase + CSL_ICSSCFG_REVID);
84 object->pruicss_version = HWREG(temp_addr) & 0x7ffU; 128 temp_val = CSL_REG32_RD(temp_addr) & 0xFFFFU;
129 object->pruicss_version = temp_val;
85 return(&config[instance-1]); 130 return(&config[instance-1]);
86 131
87} 132}
@@ -107,7 +152,7 @@ int32_t PRUICSS_setPRUBuffer( PRUICSS_Handle handle,
107 152
108 PRUICSS_V1_Object *object; 153 PRUICSS_V1_Object *object;
109 int32_t ret_val = 0; 154 int32_t ret_val = 0;
110 object = (PRUICSS_V1_Object*)handle->object; 155 object = (PRUICSS_V1_Object *)handle->object;
111 156
112 if((pruNum >= PRUICSS_MAX_PRU ) || (buffer == 0)) 157 if((pruNum >= PRUICSS_MAX_PRU ) || (buffer == 0))
113 { 158 {
@@ -130,64 +175,35 @@ int32_t PRUICSS_setPRUBuffer( PRUICSS_Handle handle,
130 * 175 *
131 * @return 0 in case of successful reset, -1 otherwise. 176 * @return 0 in case of successful reset, -1 otherwise.
132 */ 177 */
133int32_t PRUICSS_pruReset(PRUICSS_Handle handle,uint8_t pruNum) 178int32_t PRUICSS_pruReset(PRUICSS_Handle handle, uint8_t pruNum)
134{ 179{
135 uint32_t baseaddr; 180 uintptr_t baseaddr;
136 PRUICSS_V1_Object *object; 181 PRUICSS_V1_Object *object;
137 PRUICSS_HwAttrs const *hwAttrs; 182 PRUICSS_HwAttrs const *hwAttrs;
138 int32_t ret_val = PRUICSS_RETURN_SUCCESS; 183 int32_t ret_val = PRUICSS_RETURN_SUCCESS;
139 184
140 object = (PRUICSS_V1_Object*)handle->object; 185 object = (PRUICSS_V1_Object *)handle->object;
141 hwAttrs = (PRUICSS_HwAttrs const *)handle->hwAttrs; 186 hwAttrs = (PRUICSS_HwAttrs const *)handle->hwAttrs;
142 187
143 if(pruNum >= PRUICSS_MAX_PRU) 188 if(pruNum >= PRUICSS_MAX_PRU)
144 { 189 {
145 ret_val = PRUICSS_RETURN_FAILURE; 190 ret_val = PRUICSS_RETURN_FAILURE;
146 } 191 }
147 else 192 else
148 { 193 {
149 if(object->instance == PRUICCSS_INSTANCE_ONE) 194 baseaddr = pruicss_get_ctrl_addr (hwAttrs, object->instance, pruNum);
150 { 195 if(baseaddr != 0)
151 if(PRUICCSS_PRU0 == pruNum) 196 {
152 { 197 HW_WR_FIELD32((baseaddr), CSL_ICSSPRUCTRL_CONTROL_ENABLE, CSL_ICSSPRUCTRL_CONTROL_ENABLE_RESETVAL);
153 baseaddr = hwAttrs->prussPru0CtrlRegBase;
154 }
155 else if(PRUICCSS_PRU1 == pruNum)
156 {
157 baseaddr = hwAttrs->prussPru1CtrlRegBase;
158 }
159 else
160 {
161 ret_val = PRUICSS_RETURN_FAILURE;
162 }
163 }
164 else if(object->instance == PRUICCSS_INSTANCE_TWO)
165 {
166 if(PRUICCSS_PRU0 == pruNum)
167 {
168 baseaddr = hwAttrs->prussPru0CtrlRegBase;
169 }
170 else if(PRUICCSS_PRU1 == pruNum)
171 {
172 baseaddr = hwAttrs->prussPru1CtrlRegBase;
173 }
174 else
175 {
176 ret_val = PRUICSS_RETURN_FAILURE;
177 }
178 }
179 else
180 {
181 ret_val = PRUICSS_RETURN_FAILURE;
182 }
183 if(ret_val == PRUICSS_RETURN_SUCCESS)
184 {
185 HW_WR_FIELD32((baseaddr), CSL_ICSSPRUCTRL_CONTROL_SOFT_RST_N, PRUICSS_PRU_SOFT_RESET_VAL); 198 HW_WR_FIELD32((baseaddr), CSL_ICSSPRUCTRL_CONTROL_SOFT_RST_N, PRUICSS_PRU_SOFT_RESET_VAL);
186 } 199 }
200 else
201 {
202 ret_val = PRUICSS_RETURN_FAILURE;
203 }
187 } 204 }
188 return ret_val; 205 return ret_val;
189} 206}
190
191/** 207/**
192 * @brief Disables PRU: \n 208 * @brief Disables PRU: \n
193 * 209 *
@@ -196,14 +212,14 @@ int32_t PRUICSS_pruReset(PRUICSS_Handle handle,uint8_t pruNum)
196 * 212 *
197 * @return 0 in case of successful disable, -1 otherwise. 213 * @return 0 in case of successful disable, -1 otherwise.
198 **/ 214 **/
199 int32_t PRUICSS_pruDisable(PRUICSS_Handle handle,uint8_t pruNum) 215 int32_t PRUICSS_pruDisable(PRUICSS_Handle handle, uint8_t pruNum)
200{ 216{
201 uint32_t baseaddr; 217 uintptr_t baseaddr = 0;
202 PRUICSS_V1_Object *object; 218 PRUICSS_V1_Object *object;
203 PRUICSS_HwAttrs const *hwAttrs; 219 PRUICSS_HwAttrs const *hwAttrs;
204 int32_t ret_val = PRUICSS_RETURN_SUCCESS; 220 int32_t ret_val = PRUICSS_RETURN_SUCCESS;
205 221
206 object = (PRUICSS_V1_Object*)handle->object; 222 object = (PRUICSS_V1_Object *)handle->object;
207 hwAttrs = (PRUICSS_HwAttrs const *)handle->hwAttrs; 223 hwAttrs = (PRUICSS_HwAttrs const *)handle->hwAttrs;
208 224
209 if(pruNum >= PRUICSS_MAX_PRU) 225 if(pruNum >= PRUICSS_MAX_PRU)
@@ -212,49 +228,19 @@ int32_t PRUICSS_pruReset(PRUICSS_Handle handle,uint8_t pruNum)
212 } 228 }
213 else 229 else
214 { 230 {
215 if(object->instance == PRUICCSS_INSTANCE_ONE) 231 baseaddr = pruicss_get_ctrl_addr (hwAttrs, object->instance, pruNum);
216 {
217 if(PRUICCSS_PRU0 == pruNum)
218 {
219 baseaddr = hwAttrs->prussPru0CtrlRegBase;
220 }
221 else if(PRUICCSS_PRU1 == pruNum)
222 {
223 baseaddr = hwAttrs->prussPru1CtrlRegBase;
224 }
225 else
226 {
227 ret_val = PRUICSS_RETURN_FAILURE;
228 }
229 }
230 else if(object->instance == PRUICCSS_INSTANCE_TWO)
231 {
232 if(PRUICCSS_PRU0 == pruNum)
233 {
234 baseaddr = hwAttrs->prussPru0CtrlRegBase;
235 }
236 else if(PRUICCSS_PRU1 == pruNum)
237 {
238 baseaddr = hwAttrs->prussPru1CtrlRegBase;
239 }
240 else
241 {
242 ret_val = PRUICSS_RETURN_FAILURE;
243 }
244 }
245 else
246 {
247 ret_val = PRUICSS_RETURN_FAILURE;
248 }
249 232
250 if(ret_val == PRUICSS_RETURN_SUCCESS) 233 if(baseaddr != 0)
251 { 234 {
252 HW_WR_FIELD32((baseaddr), CSL_ICSSPRUCTRL_CONTROL_ENABLE, CSL_ICSSPRUCTRL_CONTROL_ENABLE_RESETVAL); 235 HW_WR_FIELD32((baseaddr), CSL_ICSSPRUCTRL_CONTROL_ENABLE, CSL_ICSSPRUCTRL_CONTROL_ENABLE_RESETVAL);
253 } 236 }
237 else
238 {
239 ret_val = PRUICSS_RETURN_FAILURE;
240 }
254 } 241 }
255 return ret_val; 242 return ret_val;
256} 243}
257
258/** 244/**
259 * @brief Enables PRU: \n 245 * @brief Enables PRU: \n
260 * 246 *
@@ -265,12 +251,12 @@ int32_t PRUICSS_pruReset(PRUICSS_Handle handle,uint8_t pruNum)
265 **/ 251 **/
266int32_t PRUICSS_pruEnable(PRUICSS_Handle handle,uint8_t pruNum) 252int32_t PRUICSS_pruEnable(PRUICSS_Handle handle,uint8_t pruNum)
267{ 253{
268 uint32_t baseaddr; 254 uintptr_t baseaddr;
269 PRUICSS_V1_Object *object; 255 PRUICSS_V1_Object *object;
270 PRUICSS_HwAttrs const *hwAttrs; 256 PRUICSS_HwAttrs const *hwAttrs;
271 int32_t ret_val = PRUICSS_RETURN_SUCCESS; 257 int32_t ret_val = PRUICSS_RETURN_SUCCESS;
272 258
273 object = (PRUICSS_V1_Object*)handle->object; 259 object = (PRUICSS_V1_Object *)handle->object;
274 hwAttrs = (PRUICSS_HwAttrs const *)handle->hwAttrs; 260 hwAttrs = (PRUICSS_HwAttrs const *)handle->hwAttrs;
275 261
276 if(pruNum >= PRUICSS_MAX_PRU) 262 if(pruNum >= PRUICSS_MAX_PRU)
@@ -279,49 +265,54 @@ int32_t PRUICSS_pruEnable(PRUICSS_Handle handle,uint8_t pruNum)
279 } 265 }
280 else 266 else
281 { 267 {
282 if(object->instance == PRUICCSS_INSTANCE_ONE) 268 baseaddr = pruicss_get_ctrl_addr (hwAttrs, object->instance, pruNum);
269 if(baseaddr != 0)
283 { 270 {
284 if(PRUICCSS_PRU0 == pruNum) 271 HW_WR_FIELD32((baseaddr), CSL_ICSSPRUCTRL_CONTROL_ENABLE, CSL_ICSSPRUCTRL_CONTROL_ENABLE_MAX);
285 {
286 baseaddr = hwAttrs->prussPru0CtrlRegBase;
287 }
288 else if(PRUICCSS_PRU1 == pruNum)
289 {
290 baseaddr = hwAttrs->prussPru1CtrlRegBase;
291 }
292 else
293 {
294 ret_val = PRUICSS_RETURN_FAILURE;
295 }
296 } 272 }
297 else if(object->instance == PRUICCSS_INSTANCE_TWO) 273 else
298 { 274 {
299 if(PRUICCSS_PRU0 == pruNum) 275 ret_val = PRUICSS_RETURN_FAILURE;
300 {
301 baseaddr = hwAttrs->prussPru0CtrlRegBase;
302 }
303 else if(PRUICCSS_PRU1 == pruNum)
304 {
305 baseaddr = hwAttrs->prussPru1CtrlRegBase;
306 }
307 else
308 {
309 ret_val = PRUICSS_RETURN_FAILURE;
310 }
311 } 276 }
312 else 277 }
278 return ret_val;
279}
280/**
281 * @brief Enables PRU Cycle Counter: \n
282 *
283 * @param handle Pruss's driver handle
284 * @param pruNum PRU instance number[0 or 1].
285 *
286 * @return 0 in case of successful enable, -1 otherwise.
287 **/
288int32_t PRUICSS_pruCounterEnable(PRUICSS_Handle handle, uint8_t pruNum)
289{
290 uintptr_t baseaddr;
291 PRUICSS_V1_Object *object;
292 PRUICSS_HwAttrs const *hwAttrs;
293 int32_t ret_val = PRUICSS_RETURN_SUCCESS;
294
295 object = (PRUICSS_V1_Object *)handle->object;
296 hwAttrs = (const PRUICSS_HwAttrs *)handle->hwAttrs;
297
298 if(pruNum >= PRUICSS_MAX_PRU)
299 {
300 ret_val = PRUICSS_RETURN_FAILURE;
301 }
302 else
303 {
304 baseaddr = pruicss_get_ctrl_addr (hwAttrs, object->instance, pruNum);
305 if(baseaddr != 0)
313 { 306 {
314 ret_val = PRUICSS_RETURN_FAILURE; 307 HW_WR_FIELD32((baseaddr), CSL_ICSSPRUCTRL_CONTROL_COUNTER_ENABLE, CSL_ICSSPRUCTRL_CONTROL_COUNTER_ENABLE_MAX);
315 } 308 }
316 if(ret_val == PRUICSS_RETURN_SUCCESS) 309 else
317 { 310 {
318 HW_WR_FIELD32((baseaddr), CSL_ICSSPRUCTRL_CONTROL_ENABLE, CSL_ICSSPRUCTRL_CONTROL_ENABLE_MAX); 311 ret_val = PRUICSS_RETURN_FAILURE;
319 } 312 }
320 } 313 }
321 return ret_val; 314 return ret_val;
322} 315}
323
324
325/** 316/**
326 * 317 *
327 * @brief This function writes the given data to PRU memory 318 * @brief This function writes the given data to PRU memory
@@ -350,9 +341,9 @@ int32_t PRUICSS_pruWriteMemory(
350 ) 341 )
351{ 342{
352 343
353 uint32_t addr; 344 uintptr_t addr;
354 PRUICSS_HwAttrs const *hwAttrs; 345 PRUICSS_HwAttrs const *hwAttrs;
355 uint32_t temp_addr = 0U; 346 uintptr_t temp_addr = 0U;
356 uint32_t i, wordlength; 347 uint32_t i, wordlength;
357 hwAttrs = (PRUICSS_HwAttrs const *)handle->hwAttrs; 348 hwAttrs = (PRUICSS_HwAttrs const *)handle->hwAttrs;
358 int32_t ret = 0; 349 int32_t ret = 0;
@@ -368,17 +359,21 @@ int32_t PRUICSS_pruWriteMemory(
368 addr = hwAttrs->prussPru1IramBase; 359 addr = hwAttrs->prussPru1IramBase;
369 } else if (pruMem == PRU_ICSS_SHARED_RAM) { 360 } else if (pruMem == PRU_ICSS_SHARED_RAM) {
370 addr = hwAttrs->prussSharedDramBase; 361 addr = hwAttrs->prussSharedDramBase;
362 } else if (pruMem == PRU_ICSS_IRAM(2U)) {
363 addr = hwAttrs->prussRtu0IramBase;
364 } else if (pruMem == PRU_ICSS_IRAM(3U)) {
365 addr = hwAttrs->prussRtu1IramBase;
371 } else { 366 } else {
372 ret = -(int32_t)1; 367 ret = PRUICSS_RETURN_FAILURE;
373 wordlength = 0U; 368 wordlength = 0U;
374 } 369 }
375 370
376 if (ret != -(int32_t)1) 371 if (ret != PRUICSS_RETURN_FAILURE)
377 { 372 {
378 for (i = 0; i < wordlength; i++) 373 for (i = 0; i < wordlength; i++)
379 { 374 {
380 temp_addr = (addr + (i << 2) + wordoffset); 375 temp_addr = (addr + (i << 2) + wordoffset);
381 HWREG(temp_addr) = source_mem[i]; 376 CSL_REG32_WR(temp_addr, source_mem[i]);
382 } 377 }
383 } 378 }
384 return (int32_t)wordlength; 379 return (int32_t)wordlength;
@@ -443,7 +438,66 @@ int32_t PRUICSS_pruInitMemory(
443 438
444 return size; 439 return size;
445} 440}
441/**
442 *
443 * @brief This function reads from PRU memory and stores in block of memory
444 *
445 * @param handle Pruss's driver handle
446 * @param pruMem PRU Memory Macro
447 * @param wordoffset Offset at which the read will happen.
448 * @param dest_mem Destination memory[ Array of uint32_tegers ]
449 * @param bytelength Total number of bytes to be read
450 *
451 * pruMem can have values
452 * PRU0_DATARAM\n
453 * PRU0_IRAM\n
454 * PRU1_DATARAM\n
455 * PRU1_IRAM\n
456 * PRUICSS_SHARED_DATARAM
457 * @return word length read or 0 on error.
458 *
459 **/
460int32_t PRUICSS_pruReadMemory(
461 PRUICSS_Handle handle,
462 uint32_t pruMem,
463 uint32_t wordoffset,
464 uint32_t *dest_mem,
465 uint32_t bytelength
466 )
467{
468 uintptr_t addr;
469 PRUICSS_HwAttrs const *hwAttrs;
470 uintptr_t temp_addr = 0U;
446 471
472 hwAttrs = (const PRUICSS_HwAttrs *)handle->hwAttrs;
473 uint32_t i, wordlength;
474
475 wordlength = (bytelength + 3U) >> 2U;
476
477 if (pruMem == PRU_ICSS_DATARAM(0U)) {
478 addr = hwAttrs->prussPru0DramBase;
479 } else if (pruMem == PRU_ICSS_IRAM(0U)) {
480 addr = hwAttrs->prussPru0IramBase;
481 } else if (pruMem == PRU_ICSS_DATARAM(1U)) {
482 addr = hwAttrs->prussPru1DramBase;
483 } else if (pruMem == PRU_ICSS_IRAM(1U)) {
484 addr = hwAttrs->prussPru1IramBase;
485 } else if (pruMem == PRUICSS_SHARED_DATARAM) {
486 addr = hwAttrs->prussSharedDramBase;
487 } else if (pruMem == PRU_ICSS_IRAM(2U)) {
488 addr = hwAttrs->prussRtu0IramBase;
489 } else if (pruMem == PRU_ICSS_IRAM(3U)) {
490 addr = hwAttrs->prussRtu1IramBase;
491 } else {
492 return -1;
493 }
494 for (i = 0; i < wordlength; i++)
495 {
496 temp_addr = (addr + (i << 2) + wordoffset);
497 dest_mem[i] = CSL_REG32_RD(temp_addr);
498 }
499 return wordlength;
500}
447 501
448/** 502/**
449 * @brief This function Generates an INTC event \n 503 * @brief This function Generates an INTC event \n
@@ -455,14 +509,14 @@ int32_t PRUICSS_pruInitMemory(
455 **/ 509 **/
456int32_t PRUICSS_pruSendEvent(PRUICSS_Handle handle,uint32_t eventnum) 510int32_t PRUICSS_pruSendEvent(PRUICSS_Handle handle,uint32_t eventnum)
457{ 511{
458 uint32_t baseaddr; 512 uintptr_t baseaddr;
459 PRUICSS_V1_Object *object; 513 PRUICSS_V1_Object *object;
460 PRUICSS_HwAttrs const *hwAttrs; 514 PRUICSS_HwAttrs const *hwAttrs;
461 int32_t ret_val = PRUICSS_RETURN_SUCCESS; 515 int32_t ret_val = PRUICSS_RETURN_SUCCESS;
462 uint32_t temp_addr = 0U; 516 uintptr_t temp_addr = 0U;
463 uint32_t temp_var = 0U; 517 uint32_t temp_var = 0U;
464 518
465 object = (PRUICSS_V1_Object*)handle->object; 519 object = (PRUICSS_V1_Object *)handle->object;
466 hwAttrs = (PRUICSS_HwAttrs const *)handle->hwAttrs; 520 hwAttrs = (PRUICSS_HwAttrs const *)handle->hwAttrs;
467 521
468 if(object->instance == PRUICCSS_INSTANCE_ONE) 522 if(object->instance == PRUICCSS_INSTANCE_ONE)
@@ -506,12 +560,12 @@ int32_t PRUICSS_pruSendEvent(PRUICSS_Handle handle,uint32_t eventnum)
506 **/ 560 **/
507int32_t PRUICSS_pruClearEvent(PRUICSS_Handle handle,uint32_t eventnum) 561int32_t PRUICSS_pruClearEvent(PRUICSS_Handle handle,uint32_t eventnum)
508{ 562{
509 uint32_t baseaddr; 563 uintptr_t baseaddr;
510 PRUICSS_HwAttrs const *hwAttrs; 564 PRUICSS_HwAttrs const *hwAttrs;
511 PRUICSS_V1_Object *object; 565 PRUICSS_V1_Object *object;
512 int32_t ret_val = PRUICSS_RETURN_SUCCESS; 566 int32_t ret_val = PRUICSS_RETURN_SUCCESS;
513 567
514 object = (PRUICSS_V1_Object*)handle->object; 568 object = (PRUICSS_V1_Object *)handle->object;
515 hwAttrs = (PRUICSS_HwAttrs const *)handle->hwAttrs; 569 hwAttrs = (PRUICSS_HwAttrs const *)handle->hwAttrs;
516 570
517 baseaddr = hwAttrs->baseAddr; 571 baseaddr = hwAttrs->baseAddr;
@@ -549,7 +603,7 @@ int32_t PRUICSS_pruWaitEvent(PRUICSS_Handle handle,uint32_t pruEvtoutNum )
549 PRUICSS_V1_Object *object; 603 PRUICSS_V1_Object *object;
550 int32_t ret_val = PRUICSS_RETURN_SUCCESS; 604 int32_t ret_val = PRUICSS_RETURN_SUCCESS;
551 605
552 object = (PRUICSS_V1_Object*)handle->object; 606 object = (PRUICSS_V1_Object *)handle->object;
553 607
554 if(pruEvtoutNum >= PRUICSS_MAX_WAIT_EVENTS) 608 if(pruEvtoutNum >= PRUICSS_MAX_WAIT_EVENTS)
555 { 609 {
@@ -577,9 +631,9 @@ int32_t PRUICSS_pruWaitEvent(PRUICSS_Handle handle,uint32_t pruEvtoutNum )
577 **/ 631 **/
578int32_t PRUICSS_mapPruMem(PRUICSS_Handle handle,uint32_t pru_ram_id, void **address) 632int32_t PRUICSS_mapPruMem(PRUICSS_Handle handle,uint32_t pru_ram_id, void **address)
579{ 633{
580 uint32_t baseaddr; 634 uintptr_t baseaddr;
581 PRUICSS_HwAttrs const *hwAttrs; 635 PRUICSS_HwAttrs const *hwAttrs;
582 uint32_t temp_addr = 0U; 636 uintptr_t temp_addr = 0U;
583 int32_t ret_val = PRUICSS_RETURN_SUCCESS; 637 int32_t ret_val = PRUICSS_RETURN_SUCCESS;
584 638
585 hwAttrs = (PRUICSS_HwAttrs const *)handle->hwAttrs; 639 hwAttrs = (PRUICSS_HwAttrs const *)handle->hwAttrs;
@@ -625,7 +679,7 @@ int32_t PRUICSS_mapPruMem(PRUICSS_Handle handle,uint32_t pru_ram_id, void **addr
625 PRUICSS_HwAttrs const *hwAttrs; 679 PRUICSS_HwAttrs const *hwAttrs;
626 int32_t ret_val = PRUICSS_RETURN_SUCCESS; 680 int32_t ret_val = PRUICSS_RETURN_SUCCESS;
627 681
628 object = (PRUICSS_V1_Object*)handle->object; 682 object = (PRUICSS_V1_Object *)handle->object;
629 hwAttrs = (PRUICSS_HwAttrs const *)handle->hwAttrs; 683 hwAttrs = (PRUICSS_HwAttrs const *)handle->hwAttrs;
630 684
631 if(object->instance == PRUICCSS_INSTANCE_ONE) { 685 if(object->instance == PRUICCSS_INSTANCE_ONE) {
@@ -692,11 +746,11 @@ int32_t PRUICSS_mapPruMem(PRUICSS_Handle handle,uint32_t pru_ram_id, void **addr
692 746
693void PRUICSS_enableOCPMasterAccess(PRUICSS_Handle handle ) 747void PRUICSS_enableOCPMasterAccess(PRUICSS_Handle handle )
694{ 748{
695 uint32_t baseaddr =0U; 749 uintptr_t baseaddr =0U;
696 PRUICSS_V1_Object *object; 750 PRUICSS_V1_Object *object;
697 PRUICSS_HwAttrs const *hwAttrs; 751 PRUICSS_HwAttrs const *hwAttrs;
698 752
699 object = (PRUICSS_V1_Object*)handle->object; 753 object = (PRUICSS_V1_Object *)handle->object;
700 hwAttrs = (PRUICSS_HwAttrs const *)handle->hwAttrs; 754 hwAttrs = (PRUICSS_HwAttrs const *)handle->hwAttrs;
701 755
702 if(object->instance == PRUICCSS_INSTANCE_ONE) 756 if(object->instance == PRUICCSS_INSTANCE_ONE)
@@ -731,7 +785,7 @@ uint32_t PRUICSS_detectHWVersion(void)
731uint32_t PRUICSS_getICSSVersion(PRUICSS_Handle handle) 785uint32_t PRUICSS_getICSSVersion(PRUICSS_Handle handle)
732{ 786{
733 PRUICSS_V1_Object *object; 787 PRUICSS_V1_Object *object;
734 object = (PRUICSS_V1_Object*)handle->object; 788 object = (PRUICSS_V1_Object *)handle->object;
735 return object->pruicss_version; 789 return object->pruicss_version;
736} 790}
737 791
@@ -751,7 +805,7 @@ int32_t PRUICSS_pruExecProgram(PRUICSS_Handle handle,int32_t pruNum)
751 PRUICSS_V1_Object *object; 805 PRUICSS_V1_Object *object;
752 int32_t ret_val = PRUICSS_RETURN_SUCCESS; 806 int32_t ret_val = PRUICSS_RETURN_SUCCESS;
753 807
754 object = (PRUICSS_V1_Object*)handle->object; 808 object = (PRUICSS_V1_Object *)handle->object;
755 if((pruNum >= PRUICSS_MAX_PRU) || (object->pruBinBuff[pruNum] == 0) || (object->buffLen[pruNum] == 0)) 809 if((pruNum >= PRUICSS_MAX_PRU) || (object->pruBinBuff[pruNum] == 0) || (object->buffLen[pruNum] == 0))
756 { 810 {
757 ret_val = PRUICSS_RETURN_FAILURE; 811 ret_val = PRUICSS_RETURN_FAILURE;
@@ -804,12 +858,12 @@ int32_t PRUICSS_pruExecProgram(PRUICSS_Handle handle,int32_t pruNum)
804 **/ 858 **/
805void PRUICSS_pinMuxConfig(PRUICSS_Handle handle, uint64_t regVal) 859void PRUICSS_pinMuxConfig(PRUICSS_Handle handle, uint64_t regVal)
806{ 860{
807 uint32_t baseaddr = 0U; 861 uintptr_t baseaddr = 0U;
808 862
809 PRUICSS_V1_Object *object; 863 PRUICSS_V1_Object *object;
810 PRUICSS_HwAttrs const *hwAttrs; 864 PRUICSS_HwAttrs const *hwAttrs;
811 865
812 object = (PRUICSS_V1_Object*)handle->object; 866 object = (PRUICSS_V1_Object *)handle->object;
813 hwAttrs = (PRUICSS_HwAttrs const *)handle->hwAttrs; 867 hwAttrs = (PRUICSS_HwAttrs const *)handle->hwAttrs;
814 868
815 if(object->instance == PRUICCSS_INSTANCE_ONE) 869 if(object->instance == PRUICCSS_INSTANCE_ONE)
diff --git a/src/pruicss_intc.c b/src/pruicss_intc.c
index f2ccc1b..d681dd4 100644
--- a/src/pruicss_intc.c
+++ b/src/pruicss_intc.c
@@ -7,7 +7,7 @@
7 */ 7 */
8 8
9/* 9/*
10* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ 10* Copyright (C) 2015-2018 Texas Instruments Incorporated - http://www.ti.com/
11* 11*
12* 12*
13* Redistribution and use in source and binary forms, with or without 13* Redistribution and use in source and binary forms, with or without
@@ -79,7 +79,7 @@ static void PRUICSS_intcSetCmr(uint8_t sysevt,
79 uint8_t channel, 79 uint8_t channel,
80 uint8_t polarity, 80 uint8_t polarity,
81 uint8_t type, 81 uint8_t type,
82 uint32_t baseaddr); 82 uintptr_t baseaddr);
83/** 83/**
84 * \brief Sets Channel-Host Map registers: \n 84 * \brief Sets Channel-Host Map registers: \n
85 * 85 *
@@ -91,7 +91,7 @@ static void PRUICSS_intcSetCmr(uint8_t sysevt,
91 */ 91 */
92static void PRUICSS_intcSetHmr(uint8_t channel, 92static void PRUICSS_intcSetHmr(uint8_t channel,
93 uint8_t host, 93 uint8_t host,
94 uint32_t baseaddr); 94 uintptr_t baseaddr);
95 95
96/** 96/**
97 * \brief PRUICSS interrupt handler 97 * \brief PRUICSS interrupt handler
@@ -123,17 +123,17 @@ static void PRUICSS_hwiIntHandler(uintptr_t ptrPpruEvtoutNum);
123 */ 123 */
124int32_t PRUICSS_pruIntcInit(PRUICSS_Handle handle, const PRUICSS_IntcInitData * prussintc_init_data) 124int32_t PRUICSS_pruIntcInit(PRUICSS_Handle handle, const PRUICSS_IntcInitData * prussintc_init_data)
125{ 125{
126 uint32_t baseaddr; 126 uintptr_t baseaddr;
127 PRUICSS_HwAttrs const *hwAttrs; 127 PRUICSS_HwAttrs const *hwAttrs;
128 PRUICSS_V1_Object *object; 128 PRUICSS_V1_Object *object;
129 129
130 uint32_t i = 0, mask1 = 0, mask2 = 0; 130 uint32_t i = 0, mask1 = 0, mask2 = 0;
131 131
132 uint32_t temp_addr = 0U; 132 uintptr_t temp_addr = 0U;
133 133
134 int32_t ret_val = PRUICSS_RETURN_SUCCESS; 134 int32_t ret_val = PRUICSS_RETURN_SUCCESS;
135 135
136 object = (PRUICSS_V1_Object*)handle->object; 136 object = (PRUICSS_V1_Object *)handle->object;
137 hwAttrs = (PRUICSS_HwAttrs const *)handle->hwAttrs; 137 hwAttrs = (PRUICSS_HwAttrs const *)handle->hwAttrs;
138 baseaddr = hwAttrs->baseAddr; 138 baseaddr = hwAttrs->baseAddr;
139 139
@@ -163,7 +163,7 @@ int32_t PRUICSS_pruIntcInit(PRUICSS_Handle handle, const PRUICSS_IntcInitData *
163 for (i = 0; i < (PRUICSS_NUM_PRU_SYS_EVTS + 3U) >> 2; i++) 163 for (i = 0; i < (PRUICSS_NUM_PRU_SYS_EVTS + 3U) >> 2; i++)
164 { 164 {
165 temp_addr = ((baseaddr + CSL_ICSSINTC_CMR0 ) + (i << 2)); 165 temp_addr = ((baseaddr + CSL_ICSSINTC_CMR0 ) + (i << 2));
166 HWREG(temp_addr) = 0; 166 CSL_REG32_WR(temp_addr, 0);
167 } 167 }
168 for (i = 0; 168 for (i = 0;
169 ((prussintc_init_data->sysevt_to_channel_map[i].sysevt != 0xFF) 169 ((prussintc_init_data->sysevt_to_channel_map[i].sysevt != 0xFF)
@@ -180,7 +180,7 @@ int32_t PRUICSS_pruIntcInit(PRUICSS_Handle handle, const PRUICSS_IntcInitData *
180 for (i = 0; i < (PRUICSS_NUM_PRU_HOSTS + 3U) >> 2; i++) 180 for (i = 0; i < (PRUICSS_NUM_PRU_HOSTS + 3U) >> 2; i++)
181 { 181 {
182 temp_addr = (baseaddr + CSL_ICSSINTC_HMR0 + (i << 2)); 182 temp_addr = (baseaddr + CSL_ICSSINTC_HMR0 + (i << 2));
183 HWREG(temp_addr) = 0; 183 CSL_REG32_WR(temp_addr, 0);
184 } 184 }
185 for (i = 0; 185 for (i = 0;
186 ((i<PRUICSS_NUM_PRU_HOSTS) && 186 ((i<PRUICSS_NUM_PRU_HOSTS) &&
@@ -337,7 +337,7 @@ int32_t PRUICSS_registerIrqHandler2(PRUICSS_Handle handle,
337 SemaphoreP_Params semParams; 337 SemaphoreP_Params semParams;
338 HwiP_Handle hwiHandle = NULL; 338 HwiP_Handle hwiHandle = NULL;
339 void* semHandle = NULL; 339 void* semHandle = NULL;
340 object = (PRUICSS_V1_Object*)handle->object; 340 object = (PRUICSS_V1_Object *)handle->object;
341 HwiP_Params hwiInputParams; 341 HwiP_Params hwiInputParams;
342 MuxIntcP_inParams muxInParams; 342 MuxIntcP_inParams muxInParams;
343 MuxIntcP_outParams muxOutParams; 343 MuxIntcP_outParams muxOutParams;
@@ -445,41 +445,41 @@ static void PRUICSS_intcSetCmr( uint8_t sysevt,
445 uint8_t channel, 445 uint8_t channel,
446 uint8_t polarity, 446 uint8_t polarity,
447 uint8_t type, 447 uint8_t type,
448 uint32_t baseaddr) 448 uintptr_t baseaddr)
449{ 449{
450 uint32_t temp_addr1 = 0U; 450 uintptr_t temp_addr1 = 0U;
451 uint32_t temp_addr2 = 0U; 451 uintptr_t temp_addr2 = 0U;
452 452
453 temp_addr1 = ((baseaddr)+(CSL_ICSSINTC_CMR0 + (((uint32_t)sysevt) & ~((uint32_t)0x3U)))); 453 temp_addr1 = ((baseaddr)+(CSL_ICSSINTC_CMR0 + (((uint32_t)sysevt) & ~((uint32_t)0x3U))));
454 HWREG(temp_addr1) |= ((((uint32_t)channel) & ((uint32_t)0xFU)) << ((((uint32_t)sysevt) & ((uint32_t)0x3U)) << 3U)); 454 CSL_REG32_WR(temp_addr1, CSL_REG32_RD(temp_addr1) | ((((uint32_t)channel) & ((uint32_t)0xFU)) << ((((uint32_t)sysevt) & ((uint32_t)0x3U)) << 3U)));
455 455
456 if(sysevt < 32U) 456 if(sysevt < 32U)
457 { 457 {
458 temp_addr1 = (baseaddr + CSL_ICSSINTC_SIPR0); 458 temp_addr1 = (baseaddr + CSL_ICSSINTC_SIPR0);
459 temp_addr2 = (baseaddr + CSL_ICSSINTC_SITR0); 459 temp_addr2 = (baseaddr + CSL_ICSSINTC_SITR0);
460 HWREG(temp_addr1) &= ~(((uint32_t)polarity) << sysevt); 460 CSL_REG32_WR(temp_addr1, CSL_REG32_RD (temp_addr1) & ~(((uint32_t)polarity) << sysevt));
461 HWREG(temp_addr2) &= ~(((uint32_t)type) << sysevt); 461 CSL_REG32_WR(temp_addr2, CSL_REG32_RD (temp_addr2) & ~(((uint32_t)type) << sysevt));
462 } 462 }
463 else 463 else
464 { 464 {
465 temp_addr1 = (baseaddr + CSL_ICSSINTC_SIPR1); 465 temp_addr1 = (baseaddr + CSL_ICSSINTC_SIPR1);
466 temp_addr2 = (baseaddr + CSL_ICSSINTC_SITR1); 466 temp_addr2 = (baseaddr + CSL_ICSSINTC_SITR1);
467 HWREG(temp_addr1) &= ~(((uint32_t)polarity) << (sysevt - 32U)); 467 CSL_REG32_WR(temp_addr1, CSL_REG32_RD(temp_addr1) & ~(((uint32_t)polarity) << (sysevt - 32U)));
468 HWREG(temp_addr2) &= ~(((uint32_t)type) << (sysevt - 32U)); 468 CSL_REG32_WR(temp_addr2, CSL_REG32_RD(temp_addr2) & ~(((uint32_t)type) << (sysevt - 32U)));
469 } 469 }
470} 470}
471 471
472 472
473static void PRUICSS_intcSetHmr( uint8_t channel, 473static void PRUICSS_intcSetHmr( uint8_t channel,
474 uint8_t host, 474 uint8_t host,
475 uint32_t baseaddr) 475 uintptr_t baseaddr)
476{ 476{
477 uint32_t temp_addr1 = 0U; 477 uintptr_t temp_addr1 = 0U;
478 uint32_t temp_addr2 = 0U; 478 uintptr_t temp_addr2 = 0U;
479 479
480 temp_addr1 = ((baseaddr) + (CSL_ICSSINTC_HMR0 + (((uint32_t)channel) & ~((uint32_t)0x3U)))); 480 temp_addr1 = ((baseaddr) + (CSL_ICSSINTC_HMR0 + (((uint32_t)channel) & ~((uint32_t)0x3U))));
481 temp_addr2 = ((baseaddr) + (CSL_ICSSINTC_HMR0 + (((uint32_t)channel) & ~((uint32_t)0x3U)))); 481 temp_addr2 = ((baseaddr) + (CSL_ICSSINTC_HMR0 + (((uint32_t)channel) & ~((uint32_t)0x3U))));
482 HWREG(temp_addr1) = HWREG(temp_addr2) | ((((uint32_t)host) & ((uint32_t)0xFU)) << ((((uint32_t)channel) & ((uint32_t)0x3U)) << 3U)); 482 CSL_REG32_WR(temp_addr1, CSL_REG32_RD(temp_addr2) | ((((uint32_t)host) & ((uint32_t)0xFU)) << ((((uint32_t)channel) & ((uint32_t)0x3U)) << 3U)));
483} 483}
484 484
485/** 485/**
@@ -491,21 +491,22 @@ static void PRUICSS_intcSetHmr( uint8_t channel,
491 */ 491 */
492int32_t PRUICSS_pruIntcClear(PRUICSS_Handle handle) 492int32_t PRUICSS_pruIntcClear(PRUICSS_Handle handle)
493{ 493{
494 uint32_t baseaddr; 494 uintptr_t baseaddr;
495 PRUICSS_HwAttrs const *hwAttrs; 495 PRUICSS_HwAttrs const *hwAttrs;
496 PRUICSS_V1_Object *object; 496 PRUICSS_V1_Object *object;
497 497
498 uint32_t i = 0; 498 uint32_t i = 0;
499 499
500 uint32_t temp_addr = 0U; 500 uintptr_t temp_addr = 0U;
501 501
502 int32_t ret_val = PRUICSS_RETURN_SUCCESS; 502 int32_t ret_val = PRUICSS_RETURN_SUCCESS;
503 503
504 /* verify the handle */ 504 /* verify the handle */
505 if (handle != NULL) 505 if (handle != NULL)
506 { 506 {
507 object = (PRUICSS_V1_Object*)handle->object; 507 object = (PRUICSS_V1_Object *)handle->object;
508 hwAttrs = (PRUICSS_HwAttrs const *)handle->hwAttrs; 508 hwAttrs = (PRUICSS_HwAttrs const *)handle->hwAttrs;
509
509 /* verify the instance */ 510 /* verify the instance */
510 if ((object->instance == PRUICCSS_INSTANCE_ONE) || (object->instance == PRUICCSS_INSTANCE_TWO)) 511 if ((object->instance == PRUICCSS_INSTANCE_ONE) || (object->instance == PRUICCSS_INSTANCE_TWO))
511 { 512 {
@@ -521,32 +522,26 @@ int32_t PRUICSS_pruIntcClear(PRUICSS_Handle handle)
521 for (i = 0; i < PRUICSS_NUM_PRU_SYS_EVTS >> 2; i++) 522 for (i = 0; i < PRUICSS_NUM_PRU_SYS_EVTS >> 2; i++)
522 { 523 {
523 temp_addr = ((baseaddr + CSL_ICSSINTC_CMR0 ) + (i << 2)); 524 temp_addr = ((baseaddr + CSL_ICSSINTC_CMR0 ) + (i << 2));
524 HWREG(temp_addr) = 0; 525 CSL_REG32_WR(temp_addr, 0);
525 } 526 }
526 527
527 for (i = 0; i < (PRUICSS_NUM_PRU_HOSTS + 3U) >> 2; i++) 528 for (i = 0; i < (PRUICSS_NUM_PRU_HOSTS + 3U) >> 2; i++)
528 { 529 {
529 temp_addr = (baseaddr + CSL_ICSSINTC_HMR0 + (i << 2)); 530 temp_addr = (baseaddr + CSL_ICSSINTC_HMR0 + (i << 2));
530 HWREG(temp_addr) = 0; 531 CSL_REG32_WR(temp_addr, 0);
531 } 532 }
532 533
533 temp_addr = baseaddr + CSL_ICSSINTC_ESR0; 534 CSL_REG32_WR(baseaddr + CSL_ICSSINTC_ESR0, 0);
534 HWREG(temp_addr) = 0;
535 535
536 temp_addr = baseaddr + CSL_ICSSINTC_SECR0; 536 CSL_REG32_WR(baseaddr + CSL_ICSSINTC_SECR0, 0);
537 HWREG(temp_addr) = 0;
538 537
539 temp_addr = baseaddr + CSL_ICSSINTC_ERS1; 538 CSL_REG32_WR(baseaddr + CSL_ICSSINTC_ERS1, 0);
540 HWREG(temp_addr) = 0;
541 539
542 temp_addr = baseaddr + CSL_ICSSINTC_SECR1; 540 CSL_REG32_WR(baseaddr + CSL_ICSSINTC_SECR1, 0);
543 HWREG(temp_addr) = 0;
544 541
545 temp_addr = baseaddr + CSL_ICSSINTC_HIER; 542 CSL_REG32_WR(baseaddr + CSL_ICSSINTC_HIER, 0);
546 HWREG(temp_addr) = 0;
547 543
548 temp_addr = baseaddr + CSL_ICSSINTC_GER; 544 CSL_REG32_WR(baseaddr + CSL_ICSSINTC_GER, 0);
549 HWREG(temp_addr) = 0;
550 } 545 }
551 else 546 else
552 { 547 {