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author | Hao Zhang | 2018-06-05 16:14:33 -0500 |
---|---|---|
committer | Hao Zhang | 2018-06-05 16:14:33 -0500 |
commit | 7f58fb87ea8462e0de97f8e7f3bac478cd6e66c8 (patch) | |
tree | b0200f0788db425a4a7e1acb7df9a7432922d79a | |
parent | a0e5e8d726282fb477ed0bff0b27a3dca1a7eef5 (diff) | |
parent | bcddfcab144e5c6a9c3d1445af3fb76032e8e4a6 (diff) | |
download | pruss-lld-7f58fb87ea8462e0de97f8e7f3bac478cd6e66c8.tar.gz pruss-lld-7f58fb87ea8462e0de97f8e7f3bac478cd6e66c8.tar.xz pruss-lld-7f58fb87ea8462e0de97f8e7f3bac478cd6e66c8.zip |
Merge pull request #47 in PROCESSOR-SDK/pruss-lld from rtos-next-review to rtos-next
* commit 'bcddfcab144e5c6a9c3d1445af3fb76032e8e4a6':
Adding support for SOC_AM65XX
-rw-r--r--[-rwxr-xr-x] | build/armv7/libpruss_aearmv7.mk | 0 | ||||
-rw-r--r-- | build/makefile.mk | 6 | ||||
-rw-r--r-- | build/makefile_profile.mk | 2 | ||||
-rw-r--r-- | build/makefile_profile_indp.mk | 2 | ||||
-rw-r--r-- | package.xs | 7 | ||||
-rw-r--r-- | pruicss.h | 38 | ||||
-rw-r--r-- | pruss_component.mk | 3 | ||||
-rw-r--r-- | soc/am335x/pruicss_soc.c | 10 | ||||
-rw-r--r-- | soc/am437x/pruicss_soc.c | 24 | ||||
-rw-r--r-- | soc/am571x/pruicss_soc.c | 30 | ||||
-rw-r--r-- | soc/am572x/pruicss_soc.c | 60 | ||||
-rw-r--r-- | soc/am574x/pruicss_soc.c | 50 | ||||
-rw-r--r-- | soc/am65xx/pruicss_soc.c | 142 | ||||
-rw-r--r-- | soc/k2g/pruicss_soc.c | 20 | ||||
-rw-r--r-- | soc/pruicss_v1.h | 58 | ||||
-rw-r--r-- | src/pruicss_drv.c | 345 | ||||
-rw-r--r-- | src/pruicss_intc.c | 71 |
17 files changed, 633 insertions, 235 deletions
diff --git a/build/armv7/libpruss_aearmv7.mk b/build/armv7/libpruss_aearmv7.mk index 0319251..0319251 100755..100644 --- a/build/armv7/libpruss_aearmv7.mk +++ b/build/armv7/libpruss_aearmv7.mk | |||
diff --git a/build/makefile.mk b/build/makefile.mk index 4b87f6d..e45769f 100644 --- a/build/makefile.mk +++ b/build/makefile.mk | |||
@@ -35,18 +35,18 @@ include $(PDK_PRUSS_COMP_PATH)/src/src_files_common.mk | |||
35 | 35 | ||
36 | MODULE_NAME = pruss | 36 | MODULE_NAME = pruss |
37 | 37 | ||
38 | ifeq ($(SOC),$(filter $(SOC), am571x am572x am437x am335x k2g am574x)) | 38 | ifeq ($(SOC),$(filter $(SOC), am571x am572x am437x am335x k2g am574x am65xx)) |
39 | SRCDIR += soc/$(SOC) | 39 | SRCDIR += soc/$(SOC) |
40 | INCDIR += soc | 40 | INCDIR += soc |
41 | # Common source files across all platforms and cores | 41 | # Common source files across all platforms and cores |
42 | SRCS_COMMON += pruicss_soc.c | 42 | SRCS_COMMON += pruicss_soc.c |
43 | endif | 43 | endif |
44 | 44 | ||
45 | # List all the external components/interfaces, whose interface header files | 45 | # List all the external components/interfaces, whose interface header files |
46 | # need to be included for this component | 46 | # need to be included for this component |
47 | INCLUDE_EXTERNAL_INTERFACES = pdk edma | 47 | INCLUDE_EXTERNAL_INTERFACES = pdk edma |
48 | 48 | ||
49 | ifeq ($(SOC),$(filter $(SOC), am571x am572x am437x am335x k2g am574x)) | 49 | ifeq ($(SOC),$(filter $(SOC), am571x am572x am437x am335x k2g am574x am65xx)) |
50 | PACKAGE_SRCS_COMMON += soc/$(SOC) | 50 | PACKAGE_SRCS_COMMON += soc/$(SOC) |
51 | endif | 51 | endif |
52 | 52 | ||
diff --git a/build/makefile_profile.mk b/build/makefile_profile.mk index 3025a6b..ba3665a 100644 --- a/build/makefile_profile.mk +++ b/build/makefile_profile.mk | |||
@@ -51,7 +51,7 @@ PACKAGE_SRCS_COMMON += soc/$(SOC) | |||
51 | endif | 51 | endif |
52 | 52 | ||
53 | ifeq ($(BUILDTYPE),$(filter $(BUILDTYPE), profile profiledma)) | 53 | ifeq ($(BUILDTYPE),$(filter $(BUILDTYPE), profile profiledma)) |
54 | ifeq ($(CORE),$(filter $(CORE), a15_0 a9host a8host)) | 54 | ifeq ($(CORE),$(filter $(CORE), a15_0 a9host a8host mpu1_0)) |
55 | CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS) -finstrument-functions -gdwarf-3 -g -D_ENABLE_BM | 55 | CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS) -finstrument-functions -gdwarf-3 -g -D_ENABLE_BM |
56 | else | 56 | else |
57 | CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS) --entry_parm=address --exit_hook=ti_utils_exit --exit_parm=address --entry_hook=ti_utils_entry -g -D_ENABLE_BM | 57 | CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS) --entry_parm=address --exit_hook=ti_utils_exit --exit_parm=address --entry_hook=ti_utils_entry -g -D_ENABLE_BM |
diff --git a/build/makefile_profile_indp.mk b/build/makefile_profile_indp.mk index 0fd6e72..2f8b256 100644 --- a/build/makefile_profile_indp.mk +++ b/build/makefile_profile_indp.mk | |||
@@ -40,7 +40,7 @@ MODULE_NAME = pruss_profile_indp | |||
40 | INCLUDE_EXTERNAL_INTERFACES = pdk edma | 40 | INCLUDE_EXTERNAL_INTERFACES = pdk edma |
41 | 41 | ||
42 | ifeq ($(BUILDTYPE),$(filter $(BUILDTYPE), profile profiledma)) | 42 | ifeq ($(BUILDTYPE),$(filter $(BUILDTYPE), profile profiledma)) |
43 | ifeq ($(CORE),$(filter $(CORE), a15_0 a9host a8host)) | 43 | ifeq ($(CORE),$(filter $(CORE), a15_0 a9host a8host mpu1_0)) |
44 | CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS) -finstrument-functions -gdwarf-3 -g -D_ENABLE_BM | 44 | CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS) -finstrument-functions -gdwarf-3 -g -D_ENABLE_BM |
45 | else | 45 | else |
46 | CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS) --entry_parm=address --exit_hook=ti_utils_exit --exit_parm=address --entry_hook=ti_utils_entry -g -D_ENABLE_BM | 46 | CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS) --entry_parm=address --exit_hook=ti_utils_exit --exit_parm=address --entry_hook=ti_utils_entry -g -D_ENABLE_BM |
@@ -49,7 +49,8 @@ function getLibs(prog) | |||
49 | 'am574x', | 49 | 'am574x', |
50 | 'am335x', | 50 | 'am335x', |
51 | 'am437x', | 51 | 'am437x', |
52 | 'k2g' | 52 | 'k2g', |
53 | 'am65xx' | ||
53 | ]; | 54 | ]; |
54 | 55 | ||
55 | /* Get the SOC */ | 56 | /* Get the SOC */ |
@@ -74,6 +75,10 @@ function getLibs(prog) | |||
74 | lib = lib + "/a9"; | 75 | lib = lib + "/a9"; |
75 | else if (java.lang.String(suffix).contains('a8') ) | 76 | else if (java.lang.String(suffix).contains('a8') ) |
76 | lib = lib + "/a8"; | 77 | lib = lib + "/a8"; |
78 | else if (java.lang.String(suffix).contains('a53') ) | ||
79 | lib = lib + "/a53"; | ||
80 | else if (java.lang.String(suffix).contains('r5f') ) | ||
81 | lib = lib + "/r5f"; | ||
77 | else | 82 | else |
78 | throw new Error("\tUnknown target for: " + this.packageBase + lib); | 83 | throw new Error("\tUnknown target for: " + this.packageBase + lib); |
79 | 84 | ||
@@ -415,7 +415,6 @@ void PRUICSS_pinMuxConfig(PRUICSS_Handle handle, uint64_t regVal); | |||
415 | * @return 0 in case of successful reset, -1 otherwise. | 415 | * @return 0 in case of successful reset, -1 otherwise. |
416 | **/ | 416 | **/ |
417 | int32_t PRUICSS_pruReset(PRUICSS_Handle handle ,uint8_t pruNum); | 417 | int32_t PRUICSS_pruReset(PRUICSS_Handle handle ,uint8_t pruNum); |
418 | |||
419 | /** | 418 | /** |
420 | * @brief Disables PRU: \n | 419 | * @brief Disables PRU: \n |
421 | * | 420 | * |
@@ -435,7 +434,15 @@ int32_t PRUICSS_pruDisable(PRUICSS_Handle handle,uint8_t pruNum); | |||
435 | * @return 0 in case of successful enable, -1 otherwise. | 434 | * @return 0 in case of successful enable, -1 otherwise. |
436 | **/ | 435 | **/ |
437 | int32_t PRUICSS_pruEnable(PRUICSS_Handle handle,uint8_t pruNum); | 436 | int32_t PRUICSS_pruEnable(PRUICSS_Handle handle,uint8_t pruNum); |
438 | 437 | /** | |
438 | * @brief Enables PRU Cycle Counter: \n | ||
439 | * | ||
440 | * @param handle Pruss's driver handle | ||
441 | * @param pruNum PRU instance number[0 or 1]. | ||
442 | * | ||
443 | * @return 0 in case of successful enable, -1 otherwise. | ||
444 | **/ | ||
445 | int32_t PRUICSS_pruCounterEnable(PRUICSS_Handle handle,uint8_t pruNum); | ||
439 | /** | 446 | /** |
440 | * | 447 | * |
441 | * @brief This function writes the given data to PRU memory | 448 | * @brief This function writes the given data to PRU memory |
@@ -461,7 +468,32 @@ int32_t PRUICSS_pruWriteMemory(PRUICSS_Handle handle, | |||
461 | const uint32_t *source_mem, | 468 | const uint32_t *source_mem, |
462 | uint32_t bytelength | 469 | uint32_t bytelength |
463 | ); | 470 | ); |
464 | 471 | /** | |
472 | * | ||
473 | * @brief This function reads from PRU memory and stores in block of memory | ||
474 | * | ||
475 | * @param handle Pruss's driver handle | ||
476 | * @param pruMem PRU Memory Macro | ||
477 | * @param wordoffset Offset at which the read will happen. | ||
478 | * @param dest_mem Destination memory[ Array of uint32_tegers ] | ||
479 | * @param bytelength Total number of bytes to be read | ||
480 | * | ||
481 | * pruMem can have values | ||
482 | * PRU0_DATARAM\n | ||
483 | * PRU0_IRAM\n | ||
484 | * PRU1_DATARAM\n | ||
485 | * PRU1_IRAM\n | ||
486 | * PRUICSS_SHARED_DATARAM | ||
487 | * @return word length read or 0 on error. | ||
488 | * | ||
489 | **/ | ||
490 | int32_t PRUICSS_pruReadMemory( | ||
491 | PRUICSS_Handle handle, | ||
492 | uint32_t pruMem, | ||
493 | uint32_t wordoffset, | ||
494 | uint32_t *dest_mem, | ||
495 | uint32_t bytelength | ||
496 | ); | ||
465 | /** | 497 | /** |
466 | * | 498 | * |
467 | * @brief This function initializes the PRU memory to zero | 499 | * @brief This function initializes the PRU memory to zero |
diff --git a/pruss_component.mk b/pruss_component.mk index 07a4af4..e854a11 100644 --- a/pruss_component.mk +++ b/pruss_component.mk | |||
@@ -68,13 +68,14 @@ ifeq ($(pruss_component_make_include), ) | |||
68 | 68 | ||
69 | # under other list | 69 | # under other list |
70 | drvpruss_BOARDLIST = icev2AM335x idkAM437x idkAM571x idkAM572x iceK2G idkAM574x | 70 | drvpruss_BOARDLIST = icev2AM335x idkAM437x idkAM571x idkAM572x iceK2G idkAM574x |
71 | drvpruss_SOCLIST = am574x am572x am571x am437x am335x k2g | 71 | drvpruss_SOCLIST = am574x am572x am571x am437x am335x k2g am65xx |
72 | drvpruss_am574x_CORELIST = c66x a15_0 ipu1_0 pru_0 pru_1 | 72 | drvpruss_am574x_CORELIST = c66x a15_0 ipu1_0 pru_0 pru_1 |
73 | drvpruss_am572x_CORELIST = c66x a15_0 ipu1_0 pru_0 pru_1 | 73 | drvpruss_am572x_CORELIST = c66x a15_0 ipu1_0 pru_0 pru_1 |
74 | drvpruss_k2g_CORELIST = c66x a15_0 pru_0 pru_1 | 74 | drvpruss_k2g_CORELIST = c66x a15_0 pru_0 pru_1 |
75 | drvpruss_am571x_CORELIST = c66x a15_0 ipu1_0 pru_0 pru_1 | 75 | drvpruss_am571x_CORELIST = c66x a15_0 ipu1_0 pru_0 pru_1 |
76 | drvpruss_am437x_CORELIST = a9host pru_0 pru_1 | 76 | drvpruss_am437x_CORELIST = a9host pru_0 pru_1 |
77 | drvpruss_am335x_CORELIST = a8host pru_0 pru_1 | 77 | drvpruss_am335x_CORELIST = a8host pru_0 pru_1 |
78 | drvpruss_am65xx_CORELIST = mpu1_0 mcu1_0 | ||
78 | 79 | ||
79 | ############################ | 80 | ############################ |
80 | # uart package | 81 | # uart package |
diff --git a/soc/am335x/pruicss_soc.c b/soc/am335x/pruicss_soc.c index 02e9f79..a58f7b1 100644 --- a/soc/am335x/pruicss_soc.c +++ b/soc/am335x/pruicss_soc.c | |||
@@ -62,11 +62,19 @@ const PRUICSS_HwAttrs prussInitCfg = | |||
62 | SOC_PRU_ICSS_INST_RAM0, | 62 | SOC_PRU_ICSS_INST_RAM0, |
63 | SOC_PRU_ICSS_INST_RAM1, | 63 | SOC_PRU_ICSS_INST_RAM1, |
64 | SOC_PRU_ICSS_SHARED_RAM, | 64 | SOC_PRU_ICSS_SHARED_RAM, |
65 | 0U, | ||
66 | 0U, | ||
67 | 0U, | ||
68 | 0U, | ||
65 | SOC_PRU_ICSS_DATA_RAM0_SIZE, | 69 | SOC_PRU_ICSS_DATA_RAM0_SIZE, |
66 | SOC_PRU_ICSS_DATA_RAM1_SIZE, | 70 | SOC_PRU_ICSS_DATA_RAM1_SIZE, |
67 | SOC_PRU_ICSS_INST_RAM0_SIZE, | 71 | SOC_PRU_ICSS_INST_RAM0_SIZE, |
68 | SOC_PRU_ICSS_INST_RAM1_SIZE, | 72 | SOC_PRU_ICSS_INST_RAM1_SIZE, |
69 | SOC_PRU_ICSS_SHARED_RAM_SIZE | 73 | SOC_PRU_ICSS_SHARED_RAM_SIZE, |
74 | 0U, | ||
75 | 0U, | ||
76 | 0U, | ||
77 | 0U | ||
70 | }; | 78 | }; |
71 | 79 | ||
72 | /* PRUICSS objects */ | 80 | /* PRUICSS objects */ |
diff --git a/soc/am437x/pruicss_soc.c b/soc/am437x/pruicss_soc.c index 953c97c..942b46c 100644 --- a/soc/am437x/pruicss_soc.c +++ b/soc/am437x/pruicss_soc.c | |||
@@ -47,7 +47,7 @@ PRUICSS_HwAttrs prussInitCfg[2] = | |||
47 | { | 47 | { |
48 | { | 48 | { |
49 | 0x54440000, | 49 | 0x54440000, |
50 | 0, | 50 | 0U, |
51 | SOC_PRU_ICSS0_U_PRU0_CTRL_REG, | 51 | SOC_PRU_ICSS0_U_PRU0_CTRL_REG, |
52 | SOC_PRU_ICSS0_U_PRU1_CTRL_REG, | 52 | SOC_PRU_ICSS0_U_PRU1_CTRL_REG, |
53 | SOC_PRU_ICSS0_U_INTC_REG, | 53 | SOC_PRU_ICSS0_U_INTC_REG, |
@@ -62,15 +62,23 @@ PRUICSS_HwAttrs prussInitCfg[2] = | |||
62 | SOC_PRU_ICSS0_U_INST_RAM0, | 62 | SOC_PRU_ICSS0_U_INST_RAM0, |
63 | SOC_PRU_ICSS0_U_INST_RAM1, | 63 | SOC_PRU_ICSS0_U_INST_RAM1, |
64 | SOC_PRU_ICSS0_U_SHARED_RAM, | 64 | SOC_PRU_ICSS0_U_SHARED_RAM, |
65 | 0U, | ||
66 | 0U, | ||
67 | 0U, | ||
68 | 0U, | ||
65 | SOC_PRU_ICSS0_U_DATA_RAM0_SIZE, | 69 | SOC_PRU_ICSS0_U_DATA_RAM0_SIZE, |
66 | SOC_PRU_ICSS0_U_DATA_RAM1_SIZE, | 70 | SOC_PRU_ICSS0_U_DATA_RAM1_SIZE, |
67 | SOC_PRU_ICSS0_U_INST_RAM0_SIZE, | 71 | SOC_PRU_ICSS0_U_INST_RAM0_SIZE, |
68 | SOC_PRU_ICSS0_U_INST_RAM1_SIZE, | 72 | SOC_PRU_ICSS0_U_INST_RAM1_SIZE, |
69 | SOC_PRU_ICSS0_U_SHARED_RAM_SIZE | 73 | SOC_PRU_ICSS0_U_SHARED_RAM_SIZE, |
74 | 0U, | ||
75 | 0U, | ||
76 | 0U, | ||
77 | 0U | ||
70 | }, | 78 | }, |
71 | { | 79 | { |
72 | 0x54400000, | 80 | 0x54400000, |
73 | 0, | 81 | 0U, |
74 | SOC_PRU_ICSS1_U_PRU0_CTRL_REG, | 82 | SOC_PRU_ICSS1_U_PRU0_CTRL_REG, |
75 | SOC_PRU_ICSS1_U_PRU1_CTRL_REG, | 83 | SOC_PRU_ICSS1_U_PRU1_CTRL_REG, |
76 | SOC_PRU_ICSS1_U_INTC_REG, | 84 | SOC_PRU_ICSS1_U_INTC_REG, |
@@ -85,11 +93,19 @@ PRUICSS_HwAttrs prussInitCfg[2] = | |||
85 | SOC_PRU_ICSS1_U_INST_RAM0, | 93 | SOC_PRU_ICSS1_U_INST_RAM0, |
86 | SOC_PRU_ICSS1_U_INST_RAM1, | 94 | SOC_PRU_ICSS1_U_INST_RAM1, |
87 | SOC_PRU_ICSS1_U_SHARED_RAM, | 95 | SOC_PRU_ICSS1_U_SHARED_RAM, |
96 | 0U, | ||
97 | 0U, | ||
98 | 0U, | ||
99 | 0U, | ||
88 | SOC_PRU_ICSS1_U_DATA_RAM0_SIZE, | 100 | SOC_PRU_ICSS1_U_DATA_RAM0_SIZE, |
89 | SOC_PRU_ICSS1_U_DATA_RAM1_SIZE, | 101 | SOC_PRU_ICSS1_U_DATA_RAM1_SIZE, |
90 | SOC_PRU_ICSS1_U_INST_RAM0_SIZE, | 102 | SOC_PRU_ICSS1_U_INST_RAM0_SIZE, |
91 | SOC_PRU_ICSS1_U_INST_RAM1_SIZE, | 103 | SOC_PRU_ICSS1_U_INST_RAM1_SIZE, |
92 | SOC_PRU_ICSS1_U_SHARED_RAM_SIZE | 104 | SOC_PRU_ICSS1_U_SHARED_RAM_SIZE, |
105 | 0U, | ||
106 | 0U, | ||
107 | 0U, | ||
108 | 0U | ||
93 | } | 109 | } |
94 | }; | 110 | }; |
95 | 111 | ||
diff --git a/soc/am571x/pruicss_soc.c b/soc/am571x/pruicss_soc.c index b0a4834..a6b2761 100644 --- a/soc/am571x/pruicss_soc.c +++ b/soc/am571x/pruicss_soc.c | |||
@@ -64,11 +64,19 @@ PRUICSS_HwAttrs prussInitCfg[2] = | |||
64 | CSL_IPU_PRUSS1_U_INST_RAM0_12KB_REGS, | 64 | CSL_IPU_PRUSS1_U_INST_RAM0_12KB_REGS, |
65 | CSL_IPU_PRUSS1_U_INST_RAM1_12KB_REGS, | 65 | CSL_IPU_PRUSS1_U_INST_RAM1_12KB_REGS, |
66 | CSL_IPU_PRUSS1_U_DATA_RAM_32KB_REGS, | 66 | CSL_IPU_PRUSS1_U_DATA_RAM_32KB_REGS, |
67 | 0U, | ||
68 | 0U, | ||
69 | 0U, | ||
70 | 0U, | ||
67 | CSL_IPU_PRUSS1_U_DATA_RAM0_8KB_SIZE, | 71 | CSL_IPU_PRUSS1_U_DATA_RAM0_8KB_SIZE, |
68 | CSL_IPU_PRUSS1_U_DATA_RAM1_8KB_SIZE, | 72 | CSL_IPU_PRUSS1_U_DATA_RAM1_8KB_SIZE, |
69 | CSL_IPU_PRUSS1_U_INST_RAM0_12KB_SIZE, | 73 | CSL_IPU_PRUSS1_U_INST_RAM0_12KB_SIZE, |
70 | CSL_IPU_PRUSS1_U_INST_RAM1_12KB_SIZE, | 74 | CSL_IPU_PRUSS1_U_INST_RAM1_12KB_SIZE, |
71 | CSL_IPU_PRUSS1_U_DATA_RAM_32KB_SIZE | 75 | CSL_IPU_PRUSS1_U_DATA_RAM_32KB_SIZE, |
76 | 0U, | ||
77 | 0U, | ||
78 | 0U, | ||
79 | 0U | ||
72 | }, | 80 | }, |
73 | { | 81 | { |
74 | 0x4b280000, | 82 | 0x4b280000, |
@@ -87,11 +95,19 @@ PRUICSS_HwAttrs prussInitCfg[2] = | |||
87 | CSL_IPU_PRUSS2_U_INST_RAM0_12KB_REGS, | 95 | CSL_IPU_PRUSS2_U_INST_RAM0_12KB_REGS, |
88 | CSL_IPU_PRUSS2_U_INST_RAM1_12KB_REGS, | 96 | CSL_IPU_PRUSS2_U_INST_RAM1_12KB_REGS, |
89 | CSL_IPU_PRUSS2_U_DATA_RAM_32KB_REGS, | 97 | CSL_IPU_PRUSS2_U_DATA_RAM_32KB_REGS, |
98 | 0U, | ||
99 | 0U, | ||
100 | 0U, | ||
101 | 0U, | ||
90 | CSL_IPU_PRUSS2_U_DATA_RAM0_8KB_SIZE, | 102 | CSL_IPU_PRUSS2_U_DATA_RAM0_8KB_SIZE, |
91 | CSL_IPU_PRUSS2_U_DATA_RAM1_8KB_SIZE, | 103 | CSL_IPU_PRUSS2_U_DATA_RAM1_8KB_SIZE, |
92 | CSL_IPU_PRUSS2_U_INST_RAM0_12KB_SIZE, | 104 | CSL_IPU_PRUSS2_U_INST_RAM0_12KB_SIZE, |
93 | CSL_IPU_PRUSS2_U_INST_RAM1_12KB_SIZE, | 105 | CSL_IPU_PRUSS2_U_INST_RAM1_12KB_SIZE, |
94 | CSL_IPU_PRUSS2_U_DATA_RAM_32KB_SIZE | 106 | CSL_IPU_PRUSS2_U_DATA_RAM_32KB_SIZE, |
107 | 0U, | ||
108 | 0U, | ||
109 | 0U, | ||
110 | 0U | ||
95 | } | 111 | } |
96 | #elif defined (__TMS320C6X__) | 112 | #elif defined (__TMS320C6X__) |
97 | { | 113 | { |
@@ -111,11 +127,19 @@ PRUICSS_HwAttrs prussInitCfg[2] = | |||
111 | CSL_DSP_PRUSS1_U_INST_RAM0_12KB_REGS, | 127 | CSL_DSP_PRUSS1_U_INST_RAM0_12KB_REGS, |
112 | CSL_DSP_PRUSS1_U_INST_RAM1_12KB_REGS, | 128 | CSL_DSP_PRUSS1_U_INST_RAM1_12KB_REGS, |
113 | CSL_DSP_PRUSS1_U_DATA_RAM_32KB_REGS, | 129 | CSL_DSP_PRUSS1_U_DATA_RAM_32KB_REGS, |
130 | 0U, | ||
131 | 0U, | ||
132 | 0U, | ||
133 | 0U, | ||
114 | CSL_DSP_PRUSS1_U_DATA_RAM0_8KB_SIZE, | 134 | CSL_DSP_PRUSS1_U_DATA_RAM0_8KB_SIZE, |
115 | CSL_DSP_PRUSS1_U_DATA_RAM1_8KB_SIZE, | 135 | CSL_DSP_PRUSS1_U_DATA_RAM1_8KB_SIZE, |
116 | CSL_DSP_PRUSS1_U_INST_RAM0_12KB_SIZE, | 136 | CSL_DSP_PRUSS1_U_INST_RAM0_12KB_SIZE, |
117 | CSL_DSP_PRUSS1_U_INST_RAM1_12KB_SIZE, | 137 | CSL_DSP_PRUSS1_U_INST_RAM1_12KB_SIZE, |
118 | CSL_DSP_PRUSS1_U_DATA_RAM_32KB_SIZE | 138 | CSL_DSP_PRUSS1_U_DATA_RAM_32KB_SIZE, |
139 | 0U, | ||
140 | 0U, | ||
141 | 0U, | ||
142 | 0U | ||
119 | }, | 143 | }, |
120 | { | 144 | { |
121 | 0x4b280000, | 145 | 0x4b280000, |
diff --git a/soc/am572x/pruicss_soc.c b/soc/am572x/pruicss_soc.c index 4b0d9ba..d5d7c26 100644 --- a/soc/am572x/pruicss_soc.c +++ b/soc/am572x/pruicss_soc.c | |||
@@ -64,11 +64,19 @@ PRUICSS_HwAttrs prussInitCfg[2] = | |||
64 | CSL_IPU_PRUSS1_U_INST_RAM0_12KB_REGS, | 64 | CSL_IPU_PRUSS1_U_INST_RAM0_12KB_REGS, |
65 | CSL_IPU_PRUSS1_U_INST_RAM1_12KB_REGS, | 65 | CSL_IPU_PRUSS1_U_INST_RAM1_12KB_REGS, |
66 | CSL_IPU_PRUSS1_U_DATA_RAM_32KB_REGS, | 66 | CSL_IPU_PRUSS1_U_DATA_RAM_32KB_REGS, |
67 | 0U, | ||
68 | 0U, | ||
69 | 0U, | ||
70 | 0U, | ||
67 | CSL_IPU_PRUSS1_U_DATA_RAM0_8KB_SIZE, | 71 | CSL_IPU_PRUSS1_U_DATA_RAM0_8KB_SIZE, |
68 | CSL_IPU_PRUSS1_U_DATA_RAM1_8KB_SIZE, | 72 | CSL_IPU_PRUSS1_U_DATA_RAM1_8KB_SIZE, |
69 | CSL_IPU_PRUSS1_U_INST_RAM0_12KB_SIZE, | 73 | CSL_IPU_PRUSS1_U_INST_RAM0_12KB_SIZE, |
70 | CSL_IPU_PRUSS1_U_INST_RAM1_12KB_SIZE, | 74 | CSL_IPU_PRUSS1_U_INST_RAM1_12KB_SIZE, |
71 | CSL_IPU_PRUSS1_U_DATA_RAM_32KB_SIZE | 75 | CSL_IPU_PRUSS1_U_DATA_RAM_32KB_SIZE, |
76 | 0U, | ||
77 | 0U, | ||
78 | 0U, | ||
79 | 0U | ||
72 | }, | 80 | }, |
73 | { | 81 | { |
74 | 0x4b280000, | 82 | 0x4b280000, |
@@ -87,11 +95,19 @@ PRUICSS_HwAttrs prussInitCfg[2] = | |||
87 | CSL_IPU_PRUSS2_U_INST_RAM0_12KB_REGS, | 95 | CSL_IPU_PRUSS2_U_INST_RAM0_12KB_REGS, |
88 | CSL_IPU_PRUSS2_U_INST_RAM1_12KB_REGS, | 96 | CSL_IPU_PRUSS2_U_INST_RAM1_12KB_REGS, |
89 | CSL_IPU_PRUSS2_U_DATA_RAM_32KB_REGS, | 97 | CSL_IPU_PRUSS2_U_DATA_RAM_32KB_REGS, |
98 | 0U, | ||
99 | 0U, | ||
100 | 0U, | ||
101 | 0U, | ||
90 | CSL_IPU_PRUSS2_U_DATA_RAM0_8KB_SIZE, | 102 | CSL_IPU_PRUSS2_U_DATA_RAM0_8KB_SIZE, |
91 | CSL_IPU_PRUSS2_U_DATA_RAM1_8KB_SIZE, | 103 | CSL_IPU_PRUSS2_U_DATA_RAM1_8KB_SIZE, |
92 | CSL_IPU_PRUSS2_U_INST_RAM0_12KB_SIZE, | 104 | CSL_IPU_PRUSS2_U_INST_RAM0_12KB_SIZE, |
93 | CSL_IPU_PRUSS2_U_INST_RAM1_12KB_SIZE, | 105 | CSL_IPU_PRUSS2_U_INST_RAM1_12KB_SIZE, |
94 | CSL_IPU_PRUSS2_U_DATA_RAM_32KB_SIZE | 106 | CSL_IPU_PRUSS2_U_DATA_RAM_32KB_SIZE, |
107 | 0U, | ||
108 | 0U, | ||
109 | 0U, | ||
110 | 0U | ||
95 | } | 111 | } |
96 | #elif defined (__TMS320C6X__) | 112 | #elif defined (__TMS320C6X__) |
97 | { | 113 | { |
@@ -111,11 +127,19 @@ PRUICSS_HwAttrs prussInitCfg[2] = | |||
111 | CSL_DSP_PRUSS1_U_INST_RAM0_12KB_REGS, | 127 | CSL_DSP_PRUSS1_U_INST_RAM0_12KB_REGS, |
112 | CSL_DSP_PRUSS1_U_INST_RAM1_12KB_REGS, | 128 | CSL_DSP_PRUSS1_U_INST_RAM1_12KB_REGS, |
113 | CSL_DSP_PRUSS1_U_DATA_RAM_32KB_REGS, | 129 | CSL_DSP_PRUSS1_U_DATA_RAM_32KB_REGS, |
130 | 0U, | ||
131 | 0U, | ||
132 | 0U, | ||
133 | 0U, | ||
114 | CSL_DSP_PRUSS1_U_DATA_RAM0_8KB_SIZE, | 134 | CSL_DSP_PRUSS1_U_DATA_RAM0_8KB_SIZE, |
115 | CSL_DSP_PRUSS1_U_DATA_RAM1_8KB_SIZE, | 135 | CSL_DSP_PRUSS1_U_DATA_RAM1_8KB_SIZE, |
116 | CSL_DSP_PRUSS1_U_INST_RAM0_12KB_SIZE, | 136 | CSL_DSP_PRUSS1_U_INST_RAM0_12KB_SIZE, |
117 | CSL_DSP_PRUSS1_U_INST_RAM1_12KB_SIZE, | 137 | CSL_DSP_PRUSS1_U_INST_RAM1_12KB_SIZE, |
118 | CSL_DSP_PRUSS1_U_DATA_RAM_32KB_SIZE | 138 | CSL_DSP_PRUSS1_U_DATA_RAM_32KB_SIZE, |
139 | 0U, | ||
140 | 0U, | ||
141 | 0U, | ||
142 | 0U | ||
119 | }, | 143 | }, |
120 | { | 144 | { |
121 | 0x4b280000, | 145 | 0x4b280000, |
@@ -134,11 +158,19 @@ PRUICSS_HwAttrs prussInitCfg[2] = | |||
134 | CSL_DSP_PRUSS2_U_INST_RAM0_12KB_REGS, | 158 | CSL_DSP_PRUSS2_U_INST_RAM0_12KB_REGS, |
135 | CSL_DSP_PRUSS2_U_INST_RAM1_12KB_REGS, | 159 | CSL_DSP_PRUSS2_U_INST_RAM1_12KB_REGS, |
136 | CSL_DSP_PRUSS2_U_DATA_RAM_32KB_REGS, | 160 | CSL_DSP_PRUSS2_U_DATA_RAM_32KB_REGS, |
161 | 0U, | ||
162 | 0U, | ||
163 | 0U, | ||
164 | 0U, | ||
137 | CSL_DSP_PRUSS2_U_DATA_RAM0_8KB_SIZE, | 165 | CSL_DSP_PRUSS2_U_DATA_RAM0_8KB_SIZE, |
138 | CSL_DSP_PRUSS2_U_DATA_RAM1_8KB_SIZE, | 166 | CSL_DSP_PRUSS2_U_DATA_RAM1_8KB_SIZE, |
139 | CSL_DSP_PRUSS2_U_INST_RAM0_12KB_SIZE, | 167 | CSL_DSP_PRUSS2_U_INST_RAM0_12KB_SIZE, |
140 | CSL_DSP_PRUSS2_U_INST_RAM1_12KB_SIZE, | 168 | CSL_DSP_PRUSS2_U_INST_RAM1_12KB_SIZE, |
141 | CSL_DSP_PRUSS2_U_DATA_RAM_32KB_SIZE | 169 | CSL_DSP_PRUSS2_U_DATA_RAM_32KB_SIZE, |
170 | 0U, | ||
171 | 0U, | ||
172 | 0U, | ||
173 | 0U | ||
142 | } | 174 | } |
143 | #else | 175 | #else |
144 | { | 176 | { |
@@ -158,11 +190,19 @@ PRUICSS_HwAttrs prussInitCfg[2] = | |||
158 | CSL_MPU_PRUSS1_U_INST_RAM0_12KB_REGS, | 190 | CSL_MPU_PRUSS1_U_INST_RAM0_12KB_REGS, |
159 | CSL_MPU_PRUSS1_U_INST_RAM1_12KB_REGS, | 191 | CSL_MPU_PRUSS1_U_INST_RAM1_12KB_REGS, |
160 | CSL_MPU_PRUSS1_U_DATA_RAM_32KB_REGS, | 192 | CSL_MPU_PRUSS1_U_DATA_RAM_32KB_REGS, |
193 | 0U, | ||
194 | 0U, | ||
195 | 0U, | ||
196 | 0U, | ||
161 | CSL_MPU_PRUSS1_U_DATA_RAM0_8KB_SIZE, | 197 | CSL_MPU_PRUSS1_U_DATA_RAM0_8KB_SIZE, |
162 | CSL_MPU_PRUSS1_U_DATA_RAM1_8KB_SIZE, | 198 | CSL_MPU_PRUSS1_U_DATA_RAM1_8KB_SIZE, |
163 | CSL_MPU_PRUSS1_U_INST_RAM0_12KB_SIZE, | 199 | CSL_MPU_PRUSS1_U_INST_RAM0_12KB_SIZE, |
164 | CSL_MPU_PRUSS1_U_INST_RAM1_12KB_SIZE, | 200 | CSL_MPU_PRUSS1_U_INST_RAM1_12KB_SIZE, |
165 | CSL_MPU_PRUSS1_U_DATA_RAM_32KB_SIZE | 201 | CSL_MPU_PRUSS1_U_DATA_RAM_32KB_SIZE, |
202 | 0U, | ||
203 | 0U, | ||
204 | 0U, | ||
205 | 0U | ||
166 | }, | 206 | }, |
167 | { | 207 | { |
168 | 0x4b280000, | 208 | 0x4b280000, |
@@ -181,11 +221,19 @@ PRUICSS_HwAttrs prussInitCfg[2] = | |||
181 | CSL_MPU_PRUSS2_U_INST_RAM0_12KB_REGS, | 221 | CSL_MPU_PRUSS2_U_INST_RAM0_12KB_REGS, |
182 | CSL_MPU_PRUSS2_U_INST_RAM1_12KB_REGS, | 222 | CSL_MPU_PRUSS2_U_INST_RAM1_12KB_REGS, |
183 | CSL_MPU_PRUSS2_U_DATA_RAM_32KB_REGS, | 223 | CSL_MPU_PRUSS2_U_DATA_RAM_32KB_REGS, |
224 | 0U, | ||
225 | 0U, | ||
226 | 0U, | ||
227 | 0U, | ||
184 | CSL_MPU_PRUSS2_U_DATA_RAM0_8KB_SIZE, | 228 | CSL_MPU_PRUSS2_U_DATA_RAM0_8KB_SIZE, |
185 | CSL_MPU_PRUSS2_U_DATA_RAM1_8KB_SIZE, | 229 | CSL_MPU_PRUSS2_U_DATA_RAM1_8KB_SIZE, |
186 | CSL_MPU_PRUSS2_U_INST_RAM0_12KB_SIZE, | 230 | CSL_MPU_PRUSS2_U_INST_RAM0_12KB_SIZE, |
187 | CSL_MPU_PRUSS2_U_INST_RAM1_12KB_SIZE, | 231 | CSL_MPU_PRUSS2_U_INST_RAM1_12KB_SIZE, |
188 | CSL_MPU_PRUSS2_U_DATA_RAM_32KB_SIZE | 232 | CSL_MPU_PRUSS2_U_DATA_RAM_32KB_SIZE, |
233 | 0U, | ||
234 | 0U, | ||
235 | 0U, | ||
236 | 0U | ||
189 | } | 237 | } |
190 | #endif | 238 | #endif |
191 | }; | 239 | }; |
diff --git a/soc/am574x/pruicss_soc.c b/soc/am574x/pruicss_soc.c index 8142cca..c61a917 100644 --- a/soc/am574x/pruicss_soc.c +++ b/soc/am574x/pruicss_soc.c | |||
@@ -87,11 +87,19 @@ PRUICSS_HwAttrs prussInitCfg[2] = | |||
87 | CSL_IPU_PRUSS2_U_INST_RAM0_12KB_REGS, | 87 | CSL_IPU_PRUSS2_U_INST_RAM0_12KB_REGS, |
88 | CSL_IPU_PRUSS2_U_INST_RAM1_12KB_REGS, | 88 | CSL_IPU_PRUSS2_U_INST_RAM1_12KB_REGS, |
89 | CSL_IPU_PRUSS2_U_DATA_RAM_32KB_REGS, | 89 | CSL_IPU_PRUSS2_U_DATA_RAM_32KB_REGS, |
90 | 0U, | ||
91 | 0U, | ||
92 | 0U, | ||
93 | 0U, | ||
90 | CSL_IPU_PRUSS2_U_DATA_RAM0_8KB_SIZE, | 94 | CSL_IPU_PRUSS2_U_DATA_RAM0_8KB_SIZE, |
91 | CSL_IPU_PRUSS2_U_DATA_RAM1_8KB_SIZE, | 95 | CSL_IPU_PRUSS2_U_DATA_RAM1_8KB_SIZE, |
92 | CSL_IPU_PRUSS2_U_INST_RAM0_12KB_SIZE, | 96 | CSL_IPU_PRUSS2_U_INST_RAM0_12KB_SIZE, |
93 | CSL_IPU_PRUSS2_U_INST_RAM1_12KB_SIZE, | 97 | CSL_IPU_PRUSS2_U_INST_RAM1_12KB_SIZE, |
94 | CSL_IPU_PRUSS2_U_DATA_RAM_32KB_SIZE | 98 | CSL_IPU_PRUSS2_U_DATA_RAM_32KB_SIZE, |
99 | 0U, | ||
100 | 0U, | ||
101 | 0U, | ||
102 | 0U | ||
95 | } | 103 | } |
96 | #elif defined (__TMS320C6X__) | 104 | #elif defined (__TMS320C6X__) |
97 | { | 105 | { |
@@ -111,11 +119,19 @@ PRUICSS_HwAttrs prussInitCfg[2] = | |||
111 | CSL_DSP_PRUSS1_U_INST_RAM0_12KB_REGS, | 119 | CSL_DSP_PRUSS1_U_INST_RAM0_12KB_REGS, |
112 | CSL_DSP_PRUSS1_U_INST_RAM1_12KB_REGS, | 120 | CSL_DSP_PRUSS1_U_INST_RAM1_12KB_REGS, |
113 | CSL_DSP_PRUSS1_U_DATA_RAM_32KB_REGS, | 121 | CSL_DSP_PRUSS1_U_DATA_RAM_32KB_REGS, |
122 | 0U, | ||
123 | 0U, | ||
124 | 0U, | ||
125 | 0U, | ||
114 | CSL_DSP_PRUSS1_U_DATA_RAM0_8KB_SIZE, | 126 | CSL_DSP_PRUSS1_U_DATA_RAM0_8KB_SIZE, |
115 | CSL_DSP_PRUSS1_U_DATA_RAM1_8KB_SIZE, | 127 | CSL_DSP_PRUSS1_U_DATA_RAM1_8KB_SIZE, |
116 | CSL_DSP_PRUSS1_U_INST_RAM0_12KB_SIZE, | 128 | CSL_DSP_PRUSS1_U_INST_RAM0_12KB_SIZE, |
117 | CSL_DSP_PRUSS1_U_INST_RAM1_12KB_SIZE, | 129 | CSL_DSP_PRUSS1_U_INST_RAM1_12KB_SIZE, |
118 | CSL_DSP_PRUSS1_U_DATA_RAM_32KB_SIZE | 130 | CSL_DSP_PRUSS1_U_DATA_RAM_32KB_SIZE, |
131 | 0U, | ||
132 | 0U, | ||
133 | 0U, | ||
134 | 0U | ||
119 | }, | 135 | }, |
120 | { | 136 | { |
121 | 0x4b280000, | 137 | 0x4b280000, |
@@ -134,11 +150,19 @@ PRUICSS_HwAttrs prussInitCfg[2] = | |||
134 | CSL_DSP_PRUSS2_U_INST_RAM0_12KB_REGS, | 150 | CSL_DSP_PRUSS2_U_INST_RAM0_12KB_REGS, |
135 | CSL_DSP_PRUSS2_U_INST_RAM1_12KB_REGS, | 151 | CSL_DSP_PRUSS2_U_INST_RAM1_12KB_REGS, |
136 | CSL_DSP_PRUSS2_U_DATA_RAM_32KB_REGS, | 152 | CSL_DSP_PRUSS2_U_DATA_RAM_32KB_REGS, |
153 | 0U, | ||
154 | 0U, | ||
155 | 0U, | ||
156 | 0U, | ||
137 | CSL_DSP_PRUSS2_U_DATA_RAM0_8KB_SIZE, | 157 | CSL_DSP_PRUSS2_U_DATA_RAM0_8KB_SIZE, |
138 | CSL_DSP_PRUSS2_U_DATA_RAM1_8KB_SIZE, | 158 | CSL_DSP_PRUSS2_U_DATA_RAM1_8KB_SIZE, |
139 | CSL_DSP_PRUSS2_U_INST_RAM0_12KB_SIZE, | 159 | CSL_DSP_PRUSS2_U_INST_RAM0_12KB_SIZE, |
140 | CSL_DSP_PRUSS2_U_INST_RAM1_12KB_SIZE, | 160 | CSL_DSP_PRUSS2_U_INST_RAM1_12KB_SIZE, |
141 | CSL_DSP_PRUSS2_U_DATA_RAM_32KB_SIZE | 161 | CSL_DSP_PRUSS2_U_DATA_RAM_32KB_SIZE, |
162 | 0U, | ||
163 | 0U, | ||
164 | 0U, | ||
165 | 0U | ||
142 | } | 166 | } |
143 | #else | 167 | #else |
144 | { | 168 | { |
@@ -158,11 +182,19 @@ PRUICSS_HwAttrs prussInitCfg[2] = | |||
158 | CSL_MPU_PRUSS1_U_INST_RAM0_12KB_REGS, | 182 | CSL_MPU_PRUSS1_U_INST_RAM0_12KB_REGS, |
159 | CSL_MPU_PRUSS1_U_INST_RAM1_12KB_REGS, | 183 | CSL_MPU_PRUSS1_U_INST_RAM1_12KB_REGS, |
160 | CSL_MPU_PRUSS1_U_DATA_RAM_32KB_REGS, | 184 | CSL_MPU_PRUSS1_U_DATA_RAM_32KB_REGS, |
185 | 0U, | ||
186 | 0U, | ||
187 | 0U, | ||
188 | 0U, | ||
161 | CSL_MPU_PRUSS1_U_DATA_RAM0_8KB_SIZE, | 189 | CSL_MPU_PRUSS1_U_DATA_RAM0_8KB_SIZE, |
162 | CSL_MPU_PRUSS1_U_DATA_RAM1_8KB_SIZE, | 190 | CSL_MPU_PRUSS1_U_DATA_RAM1_8KB_SIZE, |
163 | CSL_MPU_PRUSS1_U_INST_RAM0_12KB_SIZE, | 191 | CSL_MPU_PRUSS1_U_INST_RAM0_12KB_SIZE, |
164 | CSL_MPU_PRUSS1_U_INST_RAM1_12KB_SIZE, | 192 | CSL_MPU_PRUSS1_U_INST_RAM1_12KB_SIZE, |
165 | CSL_MPU_PRUSS1_U_DATA_RAM_32KB_SIZE | 193 | CSL_MPU_PRUSS1_U_DATA_RAM_32KB_SIZE, |
194 | 0U, | ||
195 | 0U, | ||
196 | 0U, | ||
197 | 0U | ||
166 | }, | 198 | }, |
167 | { | 199 | { |
168 | 0x4b280000, | 200 | 0x4b280000, |
@@ -181,11 +213,19 @@ PRUICSS_HwAttrs prussInitCfg[2] = | |||
181 | CSL_MPU_PRUSS2_U_INST_RAM0_12KB_REGS, | 213 | CSL_MPU_PRUSS2_U_INST_RAM0_12KB_REGS, |
182 | CSL_MPU_PRUSS2_U_INST_RAM1_12KB_REGS, | 214 | CSL_MPU_PRUSS2_U_INST_RAM1_12KB_REGS, |
183 | CSL_MPU_PRUSS2_U_DATA_RAM_32KB_REGS, | 215 | CSL_MPU_PRUSS2_U_DATA_RAM_32KB_REGS, |
216 | 0U, | ||
217 | 0U, | ||
218 | 0U, | ||
219 | 0U, | ||
184 | CSL_MPU_PRUSS2_U_DATA_RAM0_8KB_SIZE, | 220 | CSL_MPU_PRUSS2_U_DATA_RAM0_8KB_SIZE, |
185 | CSL_MPU_PRUSS2_U_DATA_RAM1_8KB_SIZE, | 221 | CSL_MPU_PRUSS2_U_DATA_RAM1_8KB_SIZE, |
186 | CSL_MPU_PRUSS2_U_INST_RAM0_12KB_SIZE, | 222 | CSL_MPU_PRUSS2_U_INST_RAM0_12KB_SIZE, |
187 | CSL_MPU_PRUSS2_U_INST_RAM1_12KB_SIZE, | 223 | CSL_MPU_PRUSS2_U_INST_RAM1_12KB_SIZE, |
188 | CSL_MPU_PRUSS2_U_DATA_RAM_32KB_SIZE | 224 | CSL_MPU_PRUSS2_U_DATA_RAM_32KB_SIZE, |
225 | 0U, | ||
226 | 0U, | ||
227 | 0U, | ||
228 | 0U | ||
189 | } | 229 | } |
190 | #endif | 230 | #endif |
191 | }; | 231 | }; |
diff --git a/soc/am65xx/pruicss_soc.c b/soc/am65xx/pruicss_soc.c new file mode 100644 index 0000000..be7c384 --- /dev/null +++ b/soc/am65xx/pruicss_soc.c | |||
@@ -0,0 +1,142 @@ | |||
1 | /** | ||
2 | * @file pruicss_soc.c | ||
3 | * | ||
4 | * @brief This is device specific configuration file . | ||
5 | */ | ||
6 | /* | ||
7 | * Copyright (c) 2017, Texas Instruments Incorporated | ||
8 | * All rights reserved. | ||
9 | * | ||
10 | * Redistribution and use in source and binary forms, with or without | ||
11 | * modification, are permitted provided that the following conditions | ||
12 | * are met: | ||
13 | * | ||
14 | * * Redistributions of source code must retain the above copyright | ||
15 | * notice, this list of conditions and the following disclaimer. | ||
16 | * | ||
17 | * * Redistributions in binary form must reproduce the above copyright | ||
18 | * notice, this list of conditions and the following disclaimer in the | ||
19 | * documentation and/or other materials provided with the distribution. | ||
20 | * | ||
21 | * * Neither the name of Texas Instruments Incorporated nor the names of | ||
22 | * its contributors may be used to endorse or promote products derived | ||
23 | * from this software without specific prior written permission. | ||
24 | * | ||
25 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | ||
26 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, | ||
27 | * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR | ||
28 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR | ||
29 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, | ||
30 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, | ||
31 | * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; | ||
32 | * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, | ||
33 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR | ||
34 | * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, | ||
35 | * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
36 | */ | ||
37 | /** ============================================================================*/ | ||
38 | |||
39 | |||
40 | #include <stdint.h> | ||
41 | #include <ti/drv/pruss/pruicss.h> | ||
42 | #include <ti/drv/pruss/soc/pruicss_v1.h> | ||
43 | |||
44 | |||
45 | |||
46 | #include <ti/csl/soc/am65xx/src/cslr_soc.h> | ||
47 | #ifdef BORG_ENV | ||
48 | #include "../../tests/platform.h" /* borg csl base */ | ||
49 | #endif | ||
50 | |||
51 | /* PRUICSS configuration structure */ | ||
52 | PRUICSS_HwAttrs prussInitCfg[3] = | ||
53 | { | ||
54 | { | ||
55 | CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE, /* baseAddr */ | ||
56 | 0, /* version */ | ||
57 | CSL_PRU_ICSSG0_PR1_PDSP0_IRAM_BASE, /* prussPru0CtrlRegBase */ | ||
58 | CSL_PRU_ICSSG0_PR1_PDSP1_IRAM_BASE, /* prussPru1CtrlRegBase */ | ||
59 | CSL_PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV_BASE, /* prussIntcRegBase */ | ||
60 | CSL_PRU_ICSSG0_PR1_CFG_SLV_BASE, /* prussCfgRegBase */ | ||
61 | CSL_PRU_ICSSG0_PR1_ICSS_UART_UART_SLV_BASE, /* prussUartRegBase */ | ||
62 | CSL_PRU_ICSSG0_IEP0_BASE, /* prussIepRegBase */ | ||
63 | CSL_PRU_ICSSG0_PR1_ICSS_ECAP0_ECAP_SLV_BASE, /* prussEcapRegBase */ | ||
64 | CSL_PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_CFG_BASE, /* prussMiiRtCfgRegBase */ | ||
65 | CSL_PRU_ICSSG0_PR1_MDIO_V1P7_MDIO_BASE, /* prussMiiMdioRegBase */ | ||
66 | CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE, /* prussPru0DramBase */ | ||
67 | CSL_PRU_ICSSG0_DRAM1_SLV_RAM_BASE, /* prussPru1DramBase */ | ||
68 | CSL_PRU_ICSSG0_PR1_PDSP0_IRAM_RAM_BASE, /* prussPru0IramBase */ | ||
69 | CSL_PRU_ICSSG0_PR1_PDSP1_IRAM_RAM_BASE, /* prussPru1IramBase */ | ||
70 | CSL_PRU_ICSSG0_RAM_SLV_RAM_BASE, /* prussSharedDramBase */ | ||
71 | CSL_PRU_ICSSG0_PR1_RTU0_PR1_RTU0_IRAM_RAM_BASE, /* prussRtu0IramBase */ | ||
72 | CSL_PRU_ICSSG0_PR1_RTU1_PR1_RTU1_IRAM_RAM_BASE, /* prussRtu1IramBase */ | ||
73 | CSL_PRU_ICSSG0_PR1_RTU0_PR1_RTU0_IRAM_BASE, /* prussRtu0CtrlRegBase */ | ||
74 | CSL_PRU_ICSSG0_PR1_RTU1_PR1_RTU1_IRAM_BASE /* prussRtu1CtrlRegBase */ | ||
75 | }, | ||
76 | { | ||
77 | CSL_PRU_ICSSG1_DRAM0_SLV_RAM_BASE, /* baseAddr */ | ||
78 | 0, /* version */ | ||
79 | CSL_PRU_ICSSG1_PR1_PDSP0_IRAM_BASE, /* prussPru0CtrlRegBase */ | ||
80 | CSL_PRU_ICSSG1_PR1_PDSP1_IRAM_BASE, /* prussPru1CtrlRegBase */ | ||
81 | CSL_PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV_BASE, /* prussIntcRegBase */ | ||
82 | CSL_PRU_ICSSG1_PR1_CFG_SLV_BASE, /* prussCfgRegBase */ | ||
83 | CSL_PRU_ICSSG1_PR1_ICSS_UART_UART_SLV_BASE, /* prussUartRegBase */ | ||
84 | CSL_PRU_ICSSG1_IEP0_BASE, /* prussIepRegBase */ | ||
85 | CSL_PRU_ICSSG1_PR1_ICSS_ECAP0_ECAP_SLV_BASE, /* prussEcapRegBase */ | ||
86 | CSL_PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_CFG_BASE, /* prussMiiRtCfgRegBase */ | ||
87 | CSL_PRU_ICSSG1_PR1_MDIO_V1P7_MDIO_BASE, /* prussMiiMdioRegBase */ | ||
88 | CSL_PRU_ICSSG1_DRAM0_SLV_RAM_BASE, /* prussPru0DramBase */ | ||
89 | CSL_PRU_ICSSG1_DRAM1_SLV_RAM_BASE, /* prussPru1DramBase */ | ||
90 | CSL_PRU_ICSSG1_PR1_PDSP0_IRAM_RAM_BASE, /* prussPru0IramBase */ | ||
91 | CSL_PRU_ICSSG1_PR1_PDSP1_IRAM_RAM_BASE, /* prussPru1IramBase */ | ||
92 | CSL_PRU_ICSSG1_RAM_SLV_RAM_BASE, /* prussSharedDramBase */ | ||
93 | CSL_PRU_ICSSG1_PR1_RTU0_PR1_RTU0_IRAM_RAM_BASE, /* prussRtu0IramBase */ | ||
94 | CSL_PRU_ICSSG1_PR1_RTU1_PR1_RTU1_IRAM_RAM_BASE, /* prussRtu1IramBase */ | ||
95 | CSL_PRU_ICSSG1_PR1_RTU0_PR1_RTU0_IRAM_BASE, /* prussRtu0CtrlRegBase */ | ||
96 | CSL_PRU_ICSSG1_PR1_RTU1_PR1_RTU1_IRAM_BASE /* prussRtu1CtrlRegBase */ | ||
97 | }, | ||
98 | { | ||
99 | CSL_PRU_ICSSG2_DRAM0_SLV_RAM_BASE, /* baseAddr */ | ||
100 | 0, /* version */ | ||
101 | CSL_PRU_ICSSG2_PR1_PDSP0_IRAM_BASE, /* prussPru0CtrlRegBase */ | ||
102 | CSL_PRU_ICSSG2_PR1_PDSP1_IRAM_BASE, /* prussPru1CtrlRegBase */ | ||
103 | CSL_PRU_ICSSG2_PR1_ICSS_INTC_INTC_SLV_BASE, /* prussIntcRegBase */ | ||
104 | CSL_PRU_ICSSG2_PR1_CFG_SLV_BASE, /* prussCfgRegBase */ | ||
105 | CSL_PRU_ICSSG2_PR1_ICSS_UART_UART_SLV_BASE, /* prussUartRegBase */ | ||
106 | CSL_PRU_ICSSG2_IEP0_BASE, /* prussIepRegBase */ | ||
107 | CSL_PRU_ICSSG2_PR1_ICSS_ECAP0_ECAP_SLV_BASE, /* prussEcapRegBase */ | ||
108 | CSL_PRU_ICSSG2_PR1_MII_RT_PR1_MII_RT_CFG_BASE, /* prussMiiRtCfgRegBase */ | ||
109 | CSL_PRU_ICSSG2_PR1_MDIO_V1P7_MDIO_BASE, /* prussMiiMdioRegBase */ | ||
110 | CSL_PRU_ICSSG2_DRAM0_SLV_RAM_BASE, /* prussPru0DramBase */ | ||
111 | CSL_PRU_ICSSG2_DRAM1_SLV_RAM_BASE, /* prussPru1DramBase */ | ||
112 | CSL_PRU_ICSSG2_PR1_PDSP0_IRAM_RAM_BASE, /* prussPru0IramBase */ | ||
113 | CSL_PRU_ICSSG2_PR1_PDSP1_IRAM_RAM_BASE, /* prussPru1IramBase */ | ||
114 | CSL_PRU_ICSSG2_RAM_SLV_RAM_BASE, /* prussSharedDramBase */ | ||
115 | CSL_PRU_ICSSG2_PR1_RTU0_PR1_RTU0_IRAM_RAM_BASE, /* prussRtu0IramBase */ | ||
116 | CSL_PRU_ICSSG2_PR1_RTU1_PR1_RTU1_IRAM_RAM_BASE, /* prussRtu1IramBase */ | ||
117 | CSL_PRU_ICSSG2_PR1_RTU0_PR1_RTU0_IRAM_BASE, /* prussRtu0CtrlRegBase */ | ||
118 | CSL_PRU_ICSSG2_PR1_RTU1_PR1_RTU1_IRAM_BASE /* prussRtu1CtrlRegBase */ | ||
119 | } | ||
120 | }; | ||
121 | |||
122 | /* PRUICSS objects */ | ||
123 | PRUICSS_V1_Object prussObjects[PRUICCSS_INSTANCE_MAX]; | ||
124 | |||
125 | /* PRUICSS configuration structure */ | ||
126 | PRUICSS_Config pruss_config[PRUICCSS_INSTANCE_MAX] = { | ||
127 | { | ||
128 | &prussObjects[0], | ||
129 | &prussInitCfg[0] | ||
130 | }, | ||
131 | { | ||
132 | &prussObjects[1], | ||
133 | &prussInitCfg[1] | ||
134 | }, | ||
135 | { | ||
136 | &prussObjects[2], | ||
137 | &prussInitCfg[2] | ||
138 | } | ||
139 | }; | ||
140 | |||
141 | |||
142 | |||
diff --git a/soc/k2g/pruicss_soc.c b/soc/k2g/pruicss_soc.c index 8a7123a..eefe767 100644 --- a/soc/k2g/pruicss_soc.c +++ b/soc/k2g/pruicss_soc.c | |||
@@ -65,11 +65,19 @@ PRUICSS_HwAttrs prussInitCfg[2] = | |||
65 | CSL_ICSS_0_INST_RAM_16KB_0_REGS, | 65 | CSL_ICSS_0_INST_RAM_16KB_0_REGS, |
66 | CSL_ICSS_0_INST_RAM_16KB_1_REGS, | 66 | CSL_ICSS_0_INST_RAM_16KB_1_REGS, |
67 | CSL_ICSS_0_DATA_RAM_64KB_REGS, | 67 | CSL_ICSS_0_DATA_RAM_64KB_REGS, |
68 | 0U, | ||
69 | 0U, | ||
70 | 0U, | ||
71 | 0U, | ||
68 | CSL_ICSS_0_DATA_RAM_8KB_0_REGS_SIZE, | 72 | CSL_ICSS_0_DATA_RAM_8KB_0_REGS_SIZE, |
69 | CSL_ICSS_0_DATA_RAM_8KB_1_REGS_SIZE, | 73 | CSL_ICSS_0_DATA_RAM_8KB_1_REGS_SIZE, |
70 | CSL_ICSS_0_INST_RAM_16KB_0_REGS_SIZE, | 74 | CSL_ICSS_0_INST_RAM_16KB_0_REGS_SIZE, |
71 | CSL_ICSS_0_INST_RAM_16KB_1_REGS_SIZE, | 75 | CSL_ICSS_0_INST_RAM_16KB_1_REGS_SIZE, |
72 | CSL_ICSS_0_DATA_RAM_64KB_REGS_SIZE | 76 | CSL_ICSS_0_DATA_RAM_64KB_REGS_SIZE, |
77 | 0U, | ||
78 | 0U, | ||
79 | 0U, | ||
80 | 0U, | ||
73 | }, | 81 | }, |
74 | { | 82 | { |
75 | CSL_ICSS_1_DATA_RAM_8KB_0_REGS, | 83 | CSL_ICSS_1_DATA_RAM_8KB_0_REGS, |
@@ -88,11 +96,19 @@ PRUICSS_HwAttrs prussInitCfg[2] = | |||
88 | CSL_ICSS_1_INST_RAM_16KB_0_REGS, | 96 | CSL_ICSS_1_INST_RAM_16KB_0_REGS, |
89 | CSL_ICSS_1_INST_RAM_16KB_1_REGS, | 97 | CSL_ICSS_1_INST_RAM_16KB_1_REGS, |
90 | CSL_ICSS_1_DATA_RAM_64KB_REGS, | 98 | CSL_ICSS_1_DATA_RAM_64KB_REGS, |
99 | 0U, | ||
100 | 0U, | ||
101 | 0U, | ||
102 | 0U, | ||
91 | CSL_ICSS_0_DATA_RAM_8KB_0_REGS_SIZE, | 103 | CSL_ICSS_0_DATA_RAM_8KB_0_REGS_SIZE, |
92 | CSL_ICSS_0_DATA_RAM_8KB_1_REGS_SIZE, | 104 | CSL_ICSS_0_DATA_RAM_8KB_1_REGS_SIZE, |
93 | CSL_ICSS_0_INST_RAM_16KB_0_REGS_SIZE, | 105 | CSL_ICSS_0_INST_RAM_16KB_0_REGS_SIZE, |
94 | CSL_ICSS_0_INST_RAM_16KB_1_REGS_SIZE, | 106 | CSL_ICSS_0_INST_RAM_16KB_1_REGS_SIZE, |
95 | CSL_ICSS_0_DATA_RAM_64KB_REGS_SIZE | 107 | CSL_ICSS_0_DATA_RAM_64KB_REGS_SIZE, |
108 | 0U, | ||
109 | 0U, | ||
110 | 0U, | ||
111 | 0U | ||
96 | } | 112 | } |
97 | }; | 113 | }; |
98 | 114 | ||
diff --git a/soc/pruicss_v1.h b/soc/pruicss_v1.h index 44d2bef..0607ec0 100644 --- a/soc/pruicss_v1.h +++ b/soc/pruicss_v1.h | |||
@@ -56,9 +56,9 @@ typedef struct PRUICSS_V1_Object_s | |||
56 | { | 56 | { |
57 | 57 | ||
58 | uint32_t pruicss_version; | 58 | uint32_t pruicss_version; |
59 | int32_t instance; /* PRUICSS write semaphore*/ | 59 | int32_t instance; /* PRUICSS write semaphore*/ |
60 | void* pruBinBuff[2]; /* Buffer data pointer */ | 60 | void* pruBinBuff[4]; /* Buffer data pointer */ |
61 | uint32_t buffLen[2]; | 61 | uint32_t buffLen[4]; |
62 | PRUICSS_IrqFunMap pruEvntOutFnMapArray[PRUICSS_MAX_WAIT_EVENTS]; | 62 | PRUICSS_IrqFunMap pruEvntOutFnMapArray[PRUICSS_MAX_WAIT_EVENTS]; |
63 | 63 | ||
64 | }PRUICSS_V1_Object; | 64 | }PRUICSS_V1_Object; |
@@ -70,37 +70,45 @@ typedef struct PRUICSS_V1_Object_s | |||
70 | */ | 70 | */ |
71 | typedef struct PRUICSS_HWAttrs { | 71 | typedef struct PRUICSS_HWAttrs { |
72 | /*PRUICSS Peripheral's base address for each PRUICSS instance*/ | 72 | /*PRUICSS Peripheral's base address for each PRUICSS instance*/ |
73 | uint32_t baseAddr; | 73 | uintptr_t baseAddr; |
74 | 74 | ||
75 | uint32_t version; | 75 | uint32_t version; |
76 | 76 | ||
77 | uint32_t prussPru0CtrlRegBase; | 77 | uintptr_t prussPru0CtrlRegBase; |
78 | 78 | ||
79 | uint32_t prussPru1CtrlRegBase; | 79 | uintptr_t prussPru1CtrlRegBase; |
80 | 80 | ||
81 | uint32_t prussIntcRegBase; | 81 | uintptr_t prussIntcRegBase; |
82 | 82 | ||
83 | uint32_t prussCfgRegBase; | 83 | uintptr_t prussCfgRegBase; |
84 | 84 | ||
85 | uint32_t prussUartRegBase; | 85 | uintptr_t prussUartRegBase; |
86 | 86 | ||
87 | uint32_t prussIepRegBase; | 87 | uintptr_t prussIepRegBase; |
88 | 88 | ||
89 | uint32_t prussEcapRegBase; | 89 | uintptr_t prussEcapRegBase; |
90 | 90 | ||
91 | uint32_t prussMiiRtCfgRegBase; | 91 | uintptr_t prussMiiRtCfgRegBase; |
92 | 92 | ||
93 | uint32_t prussMiiMdioRegBase; | 93 | uintptr_t prussMiiMdioRegBase; |
94 | 94 | ||
95 | uint32_t prussPru0DramBase; | 95 | uintptr_t prussPru0DramBase; |
96 | 96 | ||
97 | uint32_t prussPru1DramBase; | 97 | uintptr_t prussPru1DramBase; |
98 | 98 | ||
99 | uint32_t prussPru0IramBase; | 99 | uintptr_t prussPru0IramBase; |
100 | 100 | ||
101 | uint32_t prussPru1IramBase; | 101 | uintptr_t prussPru1IramBase; |
102 | 102 | ||
103 | uint32_t prussSharedDramBase; | 103 | uintptr_t prussSharedDramBase; |
104 | |||
105 | uintptr_t prussRtu0IramBase; | ||
106 | |||
107 | uintptr_t prussRtu1IramBase; | ||
108 | |||
109 | uintptr_t prussRtu0CtrlRegBase; | ||
110 | |||
111 | uintptr_t prussRtu1CtrlRegBase; | ||
104 | 112 | ||
105 | uint32_t prussPru0DramSize; | 113 | uint32_t prussPru0DramSize; |
106 | 114 | ||
@@ -111,6 +119,15 @@ typedef struct PRUICSS_HWAttrs { | |||
111 | uint32_t prussPru1IramSize; | 119 | uint32_t prussPru1IramSize; |
112 | 120 | ||
113 | uint32_t prussSharedDramSize; | 121 | uint32_t prussSharedDramSize; |
122 | |||
123 | uint32_t prussRtu0DramSize; | ||
124 | |||
125 | uint32_t prussRtu1DramSize; | ||
126 | |||
127 | uint32_t prussRtu0IramSize; | ||
128 | |||
129 | uint32_t prussRtu1IramSize; | ||
130 | |||
114 | } PRUICSS_HwAttrs; | 131 | } PRUICSS_HwAttrs; |
115 | 132 | ||
116 | 133 | ||
@@ -120,13 +137,14 @@ typedef enum PRUSS_PruCores_s | |||
120 | { | 137 | { |
121 | PRUICCSS_PRU0, | 138 | PRUICCSS_PRU0, |
122 | PRUICCSS_PRU1, | 139 | PRUICCSS_PRU1, |
140 | PRUICCSS_RTU0, | ||
141 | PRUICCSS_RTU1, | ||
123 | PRUICSS_MAX_PRU | 142 | PRUICSS_MAX_PRU |
124 | }PRUSS_PruCores; | 143 | }PRUSS_PruCores; |
125 | 144 | ||
126 | |||
127 | #define PRU_ICSS_DATARAM(n) (0x00000U + ((n) * 0x02000U)) | 145 | #define PRU_ICSS_DATARAM(n) (0x00000U + ((n) * 0x02000U)) |
128 | #define PRU_ICSS_SHARED_RAM (0x10000U) | 146 | #define PRU_ICSS_SHARED_RAM (0x10000U) |
129 | #define PRU_ICSS_IRAM(n) (0x34000U + ((n) * 0x04000U)) | 147 | #define PRU_ICSS_IRAM(n) (((n) < 2U) ? (0x34000U + ((n) * 0x04000U)) : (0x4000U + ((n)-2U) * 0x2000U)) |
130 | 148 | ||
131 | #define PRU_ICSS_REVISION_MAJOR_MASK (0x00000700) | 149 | #define PRU_ICSS_REVISION_MAJOR_MASK (0x00000700) |
132 | #define PRU_ICSS_REVISION_MINOR_MASK (0x0000003F) | 150 | #define PRU_ICSS_REVISION_MINOR_MASK (0x0000003F) |
diff --git a/src/pruicss_drv.c b/src/pruicss_drv.c index ae81a0d..79f6905 100644 --- a/src/pruicss_drv.c +++ b/src/pruicss_drv.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ | 2 | * Copyright (C) 2015-2018 Texas Instruments Incorporated - http://www.ti.com/ |
3 | * | 3 | * |
4 | * | 4 | * |
5 | * Redistribution and use in source and binary forms, with or without | 5 | * Redistribution and use in source and binary forms, with or without |
@@ -39,6 +39,7 @@ | |||
39 | * PRU instance, Load program to PRU and Write to PRU memory. | 39 | * PRU instance, Load program to PRU and Write to PRU memory. |
40 | ============================================================================*/ | 40 | ============================================================================*/ |
41 | #include <stdint.h> | 41 | #include <stdint.h> |
42 | #include <string.h> | ||
42 | #include <ti/drv/pruss/pruicss.h> | 43 | #include <ti/drv/pruss/pruicss.h> |
43 | #include <ti/drv/pruss/soc/pruicss_v1.h> | 44 | #include <ti/drv/pruss/soc/pruicss_v1.h> |
44 | #include <ti/drv/pruss/src/pruicss_osal.h> | 45 | #include <ti/drv/pruss/src/pruicss_osal.h> |
@@ -58,6 +59,47 @@ | |||
58 | /* Value that needs to be written to bit 0 of PRU_ICSS CTRL register to soft reset PRU*/ | 59 | /* Value that needs to be written to bit 0 of PRU_ICSS CTRL register to soft reset PRU*/ |
59 | #define PRUICSS_PRU_SOFT_RESET_VAL ((uint32_t)0U) | 60 | #define PRUICSS_PRU_SOFT_RESET_VAL ((uint32_t)0U) |
60 | 61 | ||
62 | static uintptr_t pruicss_get_ctrl_addr (PRUICSS_HwAttrs const *hwAttrs, | ||
63 | int32_t instance, | ||
64 | uint8_t pruNum); | ||
65 | |||
66 | static uintptr_t pruicss_get_ctrl_addr (PRUICSS_HwAttrs const *hwAttrs, | ||
67 | int32_t instance, | ||
68 | uint8_t pruNum) | ||
69 | { | ||
70 | uintptr_t baseaddr; | ||
71 | |||
72 | if ((instance >= PRUICCSS_INSTANCE_ONE) && (instance <= PRUICCSS_INSTANCE_MAX)) | ||
73 | { | ||
74 | if(PRUICCSS_PRU0 == pruNum) | ||
75 | { | ||
76 | baseaddr = hwAttrs->prussPru0CtrlRegBase; | ||
77 | } | ||
78 | else if(PRUICCSS_PRU1 == pruNum) | ||
79 | { | ||
80 | baseaddr = hwAttrs->prussPru1CtrlRegBase; | ||
81 | } | ||
82 | else if(PRUICCSS_RTU0 == pruNum) | ||
83 | { | ||
84 | baseaddr = hwAttrs->prussRtu0CtrlRegBase; | ||
85 | } | ||
86 | else if(PRUICCSS_RTU1 == pruNum) | ||
87 | { | ||
88 | baseaddr = hwAttrs->prussRtu1CtrlRegBase; | ||
89 | } | ||
90 | else | ||
91 | { | ||
92 | baseaddr = 0; | ||
93 | } | ||
94 | } | ||
95 | else | ||
96 | { | ||
97 | baseaddr = 0; | ||
98 | } | ||
99 | |||
100 | return baseaddr; | ||
101 | } | ||
102 | |||
61 | /**************************************************************************/ | 103 | /**************************************************************************/ |
62 | /* API FUNCTION DEFINITIONS */ | 104 | /* API FUNCTION DEFINITIONS */ |
63 | /**************************************************************************/ | 105 | /**************************************************************************/ |
@@ -69,19 +111,21 @@ | |||
69 | * | 111 | * |
70 | * @return PRUICSS handle. \n | 112 | * @return PRUICSS handle. \n |
71 | */ | 113 | */ |
72 | PRUICSS_Handle PRUICSS_create(PRUICSS_Config *config ,int32_t instance) | 114 | PRUICSS_Handle PRUICSS_create(PRUICSS_Config *config, int32_t instance) |
73 | { | 115 | { |
74 | PRUICSS_Handle handle; | 116 | PRUICSS_Handle handle; |
75 | PRUICSS_V1_Object *object; | 117 | PRUICSS_V1_Object *object; |
76 | PRUICSS_HwAttrs const *hwAttrs; | 118 | PRUICSS_HwAttrs const *hwAttrs; |
77 | uint32_t temp_addr = 0U; | 119 | uintptr_t temp_addr = 0U; |
120 | uint32_t temp_val; | ||
78 | 121 | ||
79 | handle = (PRUICSS_Config *)&config[instance-1]; | 122 | handle = (PRUICSS_Config *)&config[instance-1]; |
80 | hwAttrs = (PRUICSS_HwAttrs const *)handle->hwAttrs; | 123 | hwAttrs = (PRUICSS_HwAttrs const *)handle->hwAttrs; |
81 | object = (PRUICSS_V1_Object*)handle->object; | 124 | object = (PRUICSS_V1_Object*)handle->object; |
82 | object->instance = instance; | 125 | object->instance = instance; |
83 | temp_addr = (hwAttrs->prussCfgRegBase + CSL_ICSSCFG_REVID); | 126 | temp_addr = (hwAttrs->prussCfgRegBase + CSL_ICSSCFG_REVID); |
84 | object->pruicss_version = HWREG(temp_addr) & 0x7ffU; | 127 | temp_val = CSL_REG32_RD(temp_addr) & 0x7ffU; |
128 | object->pruicss_version = temp_val; | ||
85 | return(&config[instance-1]); | 129 | return(&config[instance-1]); |
86 | 130 | ||
87 | } | 131 | } |
@@ -107,7 +151,7 @@ int32_t PRUICSS_setPRUBuffer( PRUICSS_Handle handle, | |||
107 | 151 | ||
108 | PRUICSS_V1_Object *object; | 152 | PRUICSS_V1_Object *object; |
109 | int32_t ret_val = 0; | 153 | int32_t ret_val = 0; |
110 | object = (PRUICSS_V1_Object*)handle->object; | 154 | object = (PRUICSS_V1_Object *)handle->object; |
111 | 155 | ||
112 | if((pruNum >= PRUICSS_MAX_PRU ) || (buffer == 0)) | 156 | if((pruNum >= PRUICSS_MAX_PRU ) || (buffer == 0)) |
113 | { | 157 | { |
@@ -130,64 +174,35 @@ int32_t PRUICSS_setPRUBuffer( PRUICSS_Handle handle, | |||
130 | * | 174 | * |
131 | * @return 0 in case of successful reset, -1 otherwise. | 175 | * @return 0 in case of successful reset, -1 otherwise. |
132 | */ | 176 | */ |
133 | int32_t PRUICSS_pruReset(PRUICSS_Handle handle,uint8_t pruNum) | 177 | int32_t PRUICSS_pruReset(PRUICSS_Handle handle, uint8_t pruNum) |
134 | { | 178 | { |
135 | uint32_t baseaddr; | 179 | uintptr_t baseaddr; |
136 | PRUICSS_V1_Object *object; | 180 | PRUICSS_V1_Object *object; |
137 | PRUICSS_HwAttrs const *hwAttrs; | 181 | PRUICSS_HwAttrs const *hwAttrs; |
138 | int32_t ret_val = PRUICSS_RETURN_SUCCESS; | 182 | int32_t ret_val = PRUICSS_RETURN_SUCCESS; |
139 | 183 | ||
140 | object = (PRUICSS_V1_Object*)handle->object; | 184 | object = (PRUICSS_V1_Object *)handle->object; |
141 | hwAttrs = (PRUICSS_HwAttrs const *)handle->hwAttrs; | 185 | hwAttrs = (PRUICSS_HwAttrs const *)handle->hwAttrs; |
142 | 186 | ||
143 | if(pruNum >= PRUICSS_MAX_PRU) | 187 | if(pruNum >= PRUICSS_MAX_PRU) |
144 | { | 188 | { |
145 | ret_val = PRUICSS_RETURN_FAILURE; | 189 | ret_val = PRUICSS_RETURN_FAILURE; |
146 | } | 190 | } |
147 | else | 191 | else |
148 | { | 192 | { |
149 | if(object->instance == PRUICCSS_INSTANCE_ONE) | 193 | baseaddr = pruicss_get_ctrl_addr (hwAttrs, object->instance, pruNum); |
150 | { | 194 | if(baseaddr != 0) |
151 | if(PRUICCSS_PRU0 == pruNum) | 195 | { |
152 | { | 196 | HW_WR_FIELD32((baseaddr), CSL_ICSSPRUCTRL_CONTROL_ENABLE, CSL_ICSSPRUCTRL_CONTROL_ENABLE_RESETVAL); |
153 | baseaddr = hwAttrs->prussPru0CtrlRegBase; | ||
154 | } | ||
155 | else if(PRUICCSS_PRU1 == pruNum) | ||
156 | { | ||
157 | baseaddr = hwAttrs->prussPru1CtrlRegBase; | ||
158 | } | ||
159 | else | ||
160 | { | ||
161 | ret_val = PRUICSS_RETURN_FAILURE; | ||
162 | } | ||
163 | } | ||
164 | else if(object->instance == PRUICCSS_INSTANCE_TWO) | ||
165 | { | ||
166 | if(PRUICCSS_PRU0 == pruNum) | ||
167 | { | ||
168 | baseaddr = hwAttrs->prussPru0CtrlRegBase; | ||
169 | } | ||
170 | else if(PRUICCSS_PRU1 == pruNum) | ||
171 | { | ||
172 | baseaddr = hwAttrs->prussPru1CtrlRegBase; | ||
173 | } | ||
174 | else | ||
175 | { | ||
176 | ret_val = PRUICSS_RETURN_FAILURE; | ||
177 | } | ||
178 | } | ||
179 | else | ||
180 | { | ||
181 | ret_val = PRUICSS_RETURN_FAILURE; | ||
182 | } | ||
183 | if(ret_val == PRUICSS_RETURN_SUCCESS) | ||
184 | { | ||
185 | HW_WR_FIELD32((baseaddr), CSL_ICSSPRUCTRL_CONTROL_SOFT_RST_N, PRUICSS_PRU_SOFT_RESET_VAL); | 197 | HW_WR_FIELD32((baseaddr), CSL_ICSSPRUCTRL_CONTROL_SOFT_RST_N, PRUICSS_PRU_SOFT_RESET_VAL); |
186 | } | 198 | } |
199 | else | ||
200 | { | ||
201 | ret_val = PRUICSS_RETURN_FAILURE; | ||
202 | } | ||
187 | } | 203 | } |
188 | return ret_val; | 204 | return ret_val; |
189 | } | 205 | } |
190 | |||
191 | /** | 206 | /** |
192 | * @brief Disables PRU: \n | 207 | * @brief Disables PRU: \n |
193 | * | 208 | * |
@@ -196,14 +211,14 @@ int32_t PRUICSS_pruReset(PRUICSS_Handle handle,uint8_t pruNum) | |||
196 | * | 211 | * |
197 | * @return 0 in case of successful disable, -1 otherwise. | 212 | * @return 0 in case of successful disable, -1 otherwise. |
198 | **/ | 213 | **/ |
199 | int32_t PRUICSS_pruDisable(PRUICSS_Handle handle,uint8_t pruNum) | 214 | int32_t PRUICSS_pruDisable(PRUICSS_Handle handle, uint8_t pruNum) |
200 | { | 215 | { |
201 | uint32_t baseaddr; | 216 | uintptr_t baseaddr = 0; |
202 | PRUICSS_V1_Object *object; | 217 | PRUICSS_V1_Object *object; |
203 | PRUICSS_HwAttrs const *hwAttrs; | 218 | PRUICSS_HwAttrs const *hwAttrs; |
204 | int32_t ret_val = PRUICSS_RETURN_SUCCESS; | 219 | int32_t ret_val = PRUICSS_RETURN_SUCCESS; |
205 | 220 | ||
206 | object = (PRUICSS_V1_Object*)handle->object; | 221 | object = (PRUICSS_V1_Object *)handle->object; |
207 | hwAttrs = (PRUICSS_HwAttrs const *)handle->hwAttrs; | 222 | hwAttrs = (PRUICSS_HwAttrs const *)handle->hwAttrs; |
208 | 223 | ||
209 | if(pruNum >= PRUICSS_MAX_PRU) | 224 | if(pruNum >= PRUICSS_MAX_PRU) |
@@ -212,49 +227,19 @@ int32_t PRUICSS_pruReset(PRUICSS_Handle handle,uint8_t pruNum) | |||
212 | } | 227 | } |
213 | else | 228 | else |
214 | { | 229 | { |
215 | if(object->instance == PRUICCSS_INSTANCE_ONE) | 230 | baseaddr = pruicss_get_ctrl_addr (hwAttrs, object->instance, pruNum); |
216 | { | ||
217 | if(PRUICCSS_PRU0 == pruNum) | ||
218 | { | ||
219 | baseaddr = hwAttrs->prussPru0CtrlRegBase; | ||
220 | } | ||
221 | else if(PRUICCSS_PRU1 == pruNum) | ||
222 | { | ||
223 | baseaddr = hwAttrs->prussPru1CtrlRegBase; | ||
224 | } | ||
225 | else | ||
226 | { | ||
227 | ret_val = PRUICSS_RETURN_FAILURE; | ||
228 | } | ||
229 | } | ||
230 | else if(object->instance == PRUICCSS_INSTANCE_TWO) | ||
231 | { | ||
232 | if(PRUICCSS_PRU0 == pruNum) | ||
233 | { | ||
234 | baseaddr = hwAttrs->prussPru0CtrlRegBase; | ||
235 | } | ||
236 | else if(PRUICCSS_PRU1 == pruNum) | ||
237 | { | ||
238 | baseaddr = hwAttrs->prussPru1CtrlRegBase; | ||
239 | } | ||
240 | else | ||
241 | { | ||
242 | ret_val = PRUICSS_RETURN_FAILURE; | ||
243 | } | ||
244 | } | ||
245 | else | ||
246 | { | ||
247 | ret_val = PRUICSS_RETURN_FAILURE; | ||
248 | } | ||
249 | 231 | ||
250 | if(ret_val == PRUICSS_RETURN_SUCCESS) | 232 | if(baseaddr != 0) |
251 | { | 233 | { |
252 | HW_WR_FIELD32((baseaddr), CSL_ICSSPRUCTRL_CONTROL_ENABLE, CSL_ICSSPRUCTRL_CONTROL_ENABLE_RESETVAL); | 234 | HW_WR_FIELD32((baseaddr), CSL_ICSSPRUCTRL_CONTROL_ENABLE, CSL_ICSSPRUCTRL_CONTROL_ENABLE_RESETVAL); |
253 | } | 235 | } |
236 | else | ||
237 | { | ||
238 | ret_val = PRUICSS_RETURN_FAILURE; | ||
239 | } | ||
254 | } | 240 | } |
255 | return ret_val; | 241 | return ret_val; |
256 | } | 242 | } |
257 | |||
258 | /** | 243 | /** |
259 | * @brief Enables PRU: \n | 244 | * @brief Enables PRU: \n |
260 | * | 245 | * |
@@ -265,12 +250,12 @@ int32_t PRUICSS_pruReset(PRUICSS_Handle handle,uint8_t pruNum) | |||
265 | **/ | 250 | **/ |
266 | int32_t PRUICSS_pruEnable(PRUICSS_Handle handle,uint8_t pruNum) | 251 | int32_t PRUICSS_pruEnable(PRUICSS_Handle handle,uint8_t pruNum) |
267 | { | 252 | { |
268 | uint32_t baseaddr; | 253 | uintptr_t baseaddr; |
269 | PRUICSS_V1_Object *object; | 254 | PRUICSS_V1_Object *object; |
270 | PRUICSS_HwAttrs const *hwAttrs; | 255 | PRUICSS_HwAttrs const *hwAttrs; |
271 | int32_t ret_val = PRUICSS_RETURN_SUCCESS; | 256 | int32_t ret_val = PRUICSS_RETURN_SUCCESS; |
272 | 257 | ||
273 | object = (PRUICSS_V1_Object*)handle->object; | 258 | object = (PRUICSS_V1_Object *)handle->object; |
274 | hwAttrs = (PRUICSS_HwAttrs const *)handle->hwAttrs; | 259 | hwAttrs = (PRUICSS_HwAttrs const *)handle->hwAttrs; |
275 | 260 | ||
276 | if(pruNum >= PRUICSS_MAX_PRU) | 261 | if(pruNum >= PRUICSS_MAX_PRU) |
@@ -279,49 +264,54 @@ int32_t PRUICSS_pruEnable(PRUICSS_Handle handle,uint8_t pruNum) | |||
279 | } | 264 | } |
280 | else | 265 | else |
281 | { | 266 | { |
282 | if(object->instance == PRUICCSS_INSTANCE_ONE) | 267 | baseaddr = pruicss_get_ctrl_addr (hwAttrs, object->instance, pruNum); |
268 | if(baseaddr != 0) | ||
283 | { | 269 | { |
284 | if(PRUICCSS_PRU0 == pruNum) | 270 | HW_WR_FIELD32((baseaddr), CSL_ICSSPRUCTRL_CONTROL_ENABLE, CSL_ICSSPRUCTRL_CONTROL_ENABLE_MAX); |
285 | { | ||
286 | baseaddr = hwAttrs->prussPru0CtrlRegBase; | ||
287 | } | ||
288 | else if(PRUICCSS_PRU1 == pruNum) | ||
289 | { | ||
290 | baseaddr = hwAttrs->prussPru1CtrlRegBase; | ||
291 | } | ||
292 | else | ||
293 | { | ||
294 | ret_val = PRUICSS_RETURN_FAILURE; | ||
295 | } | ||
296 | } | 271 | } |
297 | else if(object->instance == PRUICCSS_INSTANCE_TWO) | 272 | else |
298 | { | 273 | { |
299 | if(PRUICCSS_PRU0 == pruNum) | 274 | ret_val = PRUICSS_RETURN_FAILURE; |
300 | { | ||
301 | baseaddr = hwAttrs->prussPru0CtrlRegBase; | ||
302 | } | ||
303 | else if(PRUICCSS_PRU1 == pruNum) | ||
304 | { | ||
305 | baseaddr = hwAttrs->prussPru1CtrlRegBase; | ||
306 | } | ||
307 | else | ||
308 | { | ||
309 | ret_val = PRUICSS_RETURN_FAILURE; | ||
310 | } | ||
311 | } | 275 | } |
312 | else | 276 | } |
277 | return ret_val; | ||
278 | } | ||
279 | /** | ||
280 | * @brief Enables PRU Cycle Counter: \n | ||
281 | * | ||
282 | * @param handle Pruss's driver handle | ||
283 | * @param pruNum PRU instance number[0 or 1]. | ||
284 | * | ||
285 | * @return 0 in case of successful enable, -1 otherwise. | ||
286 | **/ | ||
287 | int32_t PRUICSS_pruCounterEnable(PRUICSS_Handle handle, uint8_t pruNum) | ||
288 | { | ||
289 | uintptr_t baseaddr; | ||
290 | PRUICSS_V1_Object *object; | ||
291 | PRUICSS_HwAttrs const *hwAttrs; | ||
292 | int32_t ret_val = PRUICSS_RETURN_SUCCESS; | ||
293 | |||
294 | object = (PRUICSS_V1_Object *)handle->object; | ||
295 | hwAttrs = (const PRUICSS_HwAttrs *)handle->hwAttrs; | ||
296 | |||
297 | if(pruNum >= PRUICSS_MAX_PRU) | ||
298 | { | ||
299 | ret_val = PRUICSS_RETURN_FAILURE; | ||
300 | } | ||
301 | else | ||
302 | { | ||
303 | baseaddr = pruicss_get_ctrl_addr (hwAttrs, object->instance, pruNum); | ||
304 | if(baseaddr != 0) | ||
313 | { | 305 | { |
314 | ret_val = PRUICSS_RETURN_FAILURE; | 306 | HW_WR_FIELD32((baseaddr), CSL_ICSSPRUCTRL_CONTROL_COUNTER_ENABLE, CSL_ICSSPRUCTRL_CONTROL_COUNTER_ENABLE_MAX); |
315 | } | 307 | } |
316 | if(ret_val == PRUICSS_RETURN_SUCCESS) | 308 | else |
317 | { | 309 | { |
318 | HW_WR_FIELD32((baseaddr), CSL_ICSSPRUCTRL_CONTROL_ENABLE, CSL_ICSSPRUCTRL_CONTROL_ENABLE_MAX); | 310 | ret_val = PRUICSS_RETURN_FAILURE; |
319 | } | 311 | } |
320 | } | 312 | } |
321 | return ret_val; | 313 | return ret_val; |
322 | } | 314 | } |
323 | |||
324 | |||
325 | /** | 315 | /** |
326 | * | 316 | * |
327 | * @brief This function writes the given data to PRU memory | 317 | * @brief This function writes the given data to PRU memory |
@@ -350,9 +340,9 @@ int32_t PRUICSS_pruWriteMemory( | |||
350 | ) | 340 | ) |
351 | { | 341 | { |
352 | 342 | ||
353 | uint32_t addr; | 343 | uintptr_t addr; |
354 | PRUICSS_HwAttrs const *hwAttrs; | 344 | PRUICSS_HwAttrs const *hwAttrs; |
355 | uint32_t temp_addr = 0U; | 345 | uintptr_t temp_addr = 0U; |
356 | uint32_t i, wordlength; | 346 | uint32_t i, wordlength; |
357 | hwAttrs = (PRUICSS_HwAttrs const *)handle->hwAttrs; | 347 | hwAttrs = (PRUICSS_HwAttrs const *)handle->hwAttrs; |
358 | int32_t ret = 0; | 348 | int32_t ret = 0; |
@@ -368,17 +358,21 @@ int32_t PRUICSS_pruWriteMemory( | |||
368 | addr = hwAttrs->prussPru1IramBase; | 358 | addr = hwAttrs->prussPru1IramBase; |
369 | } else if (pruMem == PRU_ICSS_SHARED_RAM) { | 359 | } else if (pruMem == PRU_ICSS_SHARED_RAM) { |
370 | addr = hwAttrs->prussSharedDramBase; | 360 | addr = hwAttrs->prussSharedDramBase; |
361 | } else if (pruMem == PRU_ICSS_IRAM(2U)) { | ||
362 | addr = hwAttrs->prussRtu0IramBase; | ||
363 | } else if (pruMem == PRU_ICSS_IRAM(3U)) { | ||
364 | addr = hwAttrs->prussRtu1IramBase; | ||
371 | } else { | 365 | } else { |
372 | ret = -(int32_t)1; | 366 | ret = PRUICSS_RETURN_FAILURE; |
373 | wordlength = 0U; | 367 | wordlength = 0U; |
374 | } | 368 | } |
375 | 369 | ||
376 | if (ret != -(int32_t)1) | 370 | if (ret != PRUICSS_RETURN_FAILURE) |
377 | { | 371 | { |
378 | for (i = 0; i < wordlength; i++) | 372 | for (i = 0; i < wordlength; i++) |
379 | { | 373 | { |
380 | temp_addr = (addr + (i << 2) + wordoffset); | 374 | temp_addr = (addr + (i << 2) + wordoffset); |
381 | HWREG(temp_addr) = source_mem[i]; | 375 | CSL_REG32_WR(temp_addr, source_mem[i]); |
382 | } | 376 | } |
383 | } | 377 | } |
384 | return (int32_t)wordlength; | 378 | return (int32_t)wordlength; |
@@ -443,7 +437,66 @@ int32_t PRUICSS_pruInitMemory( | |||
443 | 437 | ||
444 | return size; | 438 | return size; |
445 | } | 439 | } |
440 | /** | ||
441 | * | ||
442 | * @brief This function reads from PRU memory and stores in block of memory | ||
443 | * | ||
444 | * @param handle Pruss's driver handle | ||
445 | * @param pruMem PRU Memory Macro | ||
446 | * @param wordoffset Offset at which the read will happen. | ||
447 | * @param dest_mem Destination memory[ Array of uint32_tegers ] | ||
448 | * @param bytelength Total number of bytes to be read | ||
449 | * | ||
450 | * pruMem can have values | ||
451 | * PRU0_DATARAM\n | ||
452 | * PRU0_IRAM\n | ||
453 | * PRU1_DATARAM\n | ||
454 | * PRU1_IRAM\n | ||
455 | * PRUICSS_SHARED_DATARAM | ||
456 | * @return word length read or 0 on error. | ||
457 | * | ||
458 | **/ | ||
459 | int32_t PRUICSS_pruReadMemory( | ||
460 | PRUICSS_Handle handle, | ||
461 | uint32_t pruMem, | ||
462 | uint32_t wordoffset, | ||
463 | uint32_t *dest_mem, | ||
464 | uint32_t bytelength | ||
465 | ) | ||
466 | { | ||
467 | uintptr_t addr; | ||
468 | PRUICSS_HwAttrs const *hwAttrs; | ||
469 | uintptr_t temp_addr = 0U; | ||
446 | 470 | ||
471 | hwAttrs = (const PRUICSS_HwAttrs *)handle->hwAttrs; | ||
472 | uint32_t i, wordlength; | ||
473 | |||
474 | wordlength = (bytelength + 3U) >> 2U; | ||
475 | |||
476 | if (pruMem == PRU_ICSS_DATARAM(0U)) { | ||
477 | addr = hwAttrs->prussPru0DramBase; | ||
478 | } else if (pruMem == PRU_ICSS_IRAM(0U)) { | ||
479 | addr = hwAttrs->prussPru0IramBase; | ||
480 | } else if (pruMem == PRU_ICSS_DATARAM(1U)) { | ||
481 | addr = hwAttrs->prussPru1DramBase; | ||
482 | } else if (pruMem == PRU_ICSS_IRAM(1U)) { | ||
483 | addr = hwAttrs->prussPru1IramBase; | ||
484 | } else if (pruMem == PRUICSS_SHARED_DATARAM) { | ||
485 | addr = hwAttrs->prussSharedDramBase; | ||
486 | } else if (pruMem == PRU_ICSS_IRAM(2U)) { | ||
487 | addr = hwAttrs->prussRtu0IramBase; | ||
488 | } else if (pruMem == PRU_ICSS_IRAM(3U)) { | ||
489 | addr = hwAttrs->prussRtu1IramBase; | ||
490 | } else { | ||
491 | return -1; | ||
492 | } | ||
493 | for (i = 0; i < wordlength; i++) | ||
494 | { | ||
495 | temp_addr = (addr + (i << 2) + wordoffset); | ||
496 | dest_mem[i] = CSL_REG32_RD(temp_addr); | ||
497 | } | ||
498 | return wordlength; | ||
499 | } | ||
447 | 500 | ||
448 | /** | 501 | /** |
449 | * @brief This function Generates an INTC event \n | 502 | * @brief This function Generates an INTC event \n |
@@ -455,14 +508,14 @@ int32_t PRUICSS_pruInitMemory( | |||
455 | **/ | 508 | **/ |
456 | int32_t PRUICSS_pruSendEvent(PRUICSS_Handle handle,uint32_t eventnum) | 509 | int32_t PRUICSS_pruSendEvent(PRUICSS_Handle handle,uint32_t eventnum) |
457 | { | 510 | { |
458 | uint32_t baseaddr; | 511 | uintptr_t baseaddr; |
459 | PRUICSS_V1_Object *object; | 512 | PRUICSS_V1_Object *object; |
460 | PRUICSS_HwAttrs const *hwAttrs; | 513 | PRUICSS_HwAttrs const *hwAttrs; |
461 | int32_t ret_val = PRUICSS_RETURN_SUCCESS; | 514 | int32_t ret_val = PRUICSS_RETURN_SUCCESS; |
462 | uint32_t temp_addr = 0U; | 515 | uintptr_t temp_addr = 0U; |
463 | uint32_t temp_var = 0U; | 516 | uint32_t temp_var = 0U; |
464 | 517 | ||
465 | object = (PRUICSS_V1_Object*)handle->object; | 518 | object = (PRUICSS_V1_Object *)handle->object; |
466 | hwAttrs = (PRUICSS_HwAttrs const *)handle->hwAttrs; | 519 | hwAttrs = (PRUICSS_HwAttrs const *)handle->hwAttrs; |
467 | 520 | ||
468 | if(object->instance == PRUICCSS_INSTANCE_ONE) | 521 | if(object->instance == PRUICCSS_INSTANCE_ONE) |
@@ -506,12 +559,12 @@ int32_t PRUICSS_pruSendEvent(PRUICSS_Handle handle,uint32_t eventnum) | |||
506 | **/ | 559 | **/ |
507 | int32_t PRUICSS_pruClearEvent(PRUICSS_Handle handle,uint32_t eventnum) | 560 | int32_t PRUICSS_pruClearEvent(PRUICSS_Handle handle,uint32_t eventnum) |
508 | { | 561 | { |
509 | uint32_t baseaddr; | 562 | uintptr_t baseaddr; |
510 | PRUICSS_HwAttrs const *hwAttrs; | 563 | PRUICSS_HwAttrs const *hwAttrs; |
511 | PRUICSS_V1_Object *object; | 564 | PRUICSS_V1_Object *object; |
512 | int32_t ret_val = PRUICSS_RETURN_SUCCESS; | 565 | int32_t ret_val = PRUICSS_RETURN_SUCCESS; |
513 | 566 | ||
514 | object = (PRUICSS_V1_Object*)handle->object; | 567 | object = (PRUICSS_V1_Object *)handle->object; |
515 | hwAttrs = (PRUICSS_HwAttrs const *)handle->hwAttrs; | 568 | hwAttrs = (PRUICSS_HwAttrs const *)handle->hwAttrs; |
516 | 569 | ||
517 | baseaddr = hwAttrs->baseAddr; | 570 | baseaddr = hwAttrs->baseAddr; |
@@ -549,7 +602,7 @@ int32_t PRUICSS_pruWaitEvent(PRUICSS_Handle handle,uint32_t pruEvtoutNum ) | |||
549 | PRUICSS_V1_Object *object; | 602 | PRUICSS_V1_Object *object; |
550 | int32_t ret_val = PRUICSS_RETURN_SUCCESS; | 603 | int32_t ret_val = PRUICSS_RETURN_SUCCESS; |
551 | 604 | ||
552 | object = (PRUICSS_V1_Object*)handle->object; | 605 | object = (PRUICSS_V1_Object *)handle->object; |
553 | 606 | ||
554 | if(pruEvtoutNum >= PRUICSS_MAX_WAIT_EVENTS) | 607 | if(pruEvtoutNum >= PRUICSS_MAX_WAIT_EVENTS) |
555 | { | 608 | { |
@@ -577,9 +630,9 @@ int32_t PRUICSS_pruWaitEvent(PRUICSS_Handle handle,uint32_t pruEvtoutNum ) | |||
577 | **/ | 630 | **/ |
578 | int32_t PRUICSS_mapPruMem(PRUICSS_Handle handle,uint32_t pru_ram_id, void **address) | 631 | int32_t PRUICSS_mapPruMem(PRUICSS_Handle handle,uint32_t pru_ram_id, void **address) |
579 | { | 632 | { |
580 | uint32_t baseaddr; | 633 | uintptr_t baseaddr; |
581 | PRUICSS_HwAttrs const *hwAttrs; | 634 | PRUICSS_HwAttrs const *hwAttrs; |
582 | uint32_t temp_addr = 0U; | 635 | uintptr_t temp_addr = 0U; |
583 | int32_t ret_val = PRUICSS_RETURN_SUCCESS; | 636 | int32_t ret_val = PRUICSS_RETURN_SUCCESS; |
584 | 637 | ||
585 | hwAttrs = (PRUICSS_HwAttrs const *)handle->hwAttrs; | 638 | hwAttrs = (PRUICSS_HwAttrs const *)handle->hwAttrs; |
@@ -625,7 +678,7 @@ int32_t PRUICSS_mapPruMem(PRUICSS_Handle handle,uint32_t pru_ram_id, void **addr | |||
625 | PRUICSS_HwAttrs const *hwAttrs; | 678 | PRUICSS_HwAttrs const *hwAttrs; |
626 | int32_t ret_val = PRUICSS_RETURN_SUCCESS; | 679 | int32_t ret_val = PRUICSS_RETURN_SUCCESS; |
627 | 680 | ||
628 | object = (PRUICSS_V1_Object*)handle->object; | 681 | object = (PRUICSS_V1_Object *)handle->object; |
629 | hwAttrs = (PRUICSS_HwAttrs const *)handle->hwAttrs; | 682 | hwAttrs = (PRUICSS_HwAttrs const *)handle->hwAttrs; |
630 | 683 | ||
631 | if(object->instance == PRUICCSS_INSTANCE_ONE) { | 684 | if(object->instance == PRUICCSS_INSTANCE_ONE) { |
@@ -692,11 +745,11 @@ int32_t PRUICSS_mapPruMem(PRUICSS_Handle handle,uint32_t pru_ram_id, void **addr | |||
692 | 745 | ||
693 | void PRUICSS_enableOCPMasterAccess(PRUICSS_Handle handle ) | 746 | void PRUICSS_enableOCPMasterAccess(PRUICSS_Handle handle ) |
694 | { | 747 | { |
695 | uint32_t baseaddr =0U; | 748 | uintptr_t baseaddr =0U; |
696 | PRUICSS_V1_Object *object; | 749 | PRUICSS_V1_Object *object; |
697 | PRUICSS_HwAttrs const *hwAttrs; | 750 | PRUICSS_HwAttrs const *hwAttrs; |
698 | 751 | ||
699 | object = (PRUICSS_V1_Object*)handle->object; | 752 | object = (PRUICSS_V1_Object *)handle->object; |
700 | hwAttrs = (PRUICSS_HwAttrs const *)handle->hwAttrs; | 753 | hwAttrs = (PRUICSS_HwAttrs const *)handle->hwAttrs; |
701 | 754 | ||
702 | if(object->instance == PRUICCSS_INSTANCE_ONE) | 755 | if(object->instance == PRUICCSS_INSTANCE_ONE) |
@@ -731,7 +784,7 @@ uint32_t PRUICSS_detectHWVersion(void) | |||
731 | uint32_t PRUICSS_getICSSVersion(PRUICSS_Handle handle) | 784 | uint32_t PRUICSS_getICSSVersion(PRUICSS_Handle handle) |
732 | { | 785 | { |
733 | PRUICSS_V1_Object *object; | 786 | PRUICSS_V1_Object *object; |
734 | object = (PRUICSS_V1_Object*)handle->object; | 787 | object = (PRUICSS_V1_Object *)handle->object; |
735 | return object->pruicss_version; | 788 | return object->pruicss_version; |
736 | } | 789 | } |
737 | 790 | ||
@@ -751,7 +804,7 @@ int32_t PRUICSS_pruExecProgram(PRUICSS_Handle handle,int32_t pruNum) | |||
751 | PRUICSS_V1_Object *object; | 804 | PRUICSS_V1_Object *object; |
752 | int32_t ret_val = PRUICSS_RETURN_SUCCESS; | 805 | int32_t ret_val = PRUICSS_RETURN_SUCCESS; |
753 | 806 | ||
754 | object = (PRUICSS_V1_Object*)handle->object; | 807 | object = (PRUICSS_V1_Object *)handle->object; |
755 | if((pruNum >= PRUICSS_MAX_PRU) || (object->pruBinBuff[pruNum] == 0) || (object->buffLen[pruNum] == 0)) | 808 | if((pruNum >= PRUICSS_MAX_PRU) || (object->pruBinBuff[pruNum] == 0) || (object->buffLen[pruNum] == 0)) |
756 | { | 809 | { |
757 | ret_val = PRUICSS_RETURN_FAILURE; | 810 | ret_val = PRUICSS_RETURN_FAILURE; |
@@ -805,12 +858,12 @@ int32_t PRUICSS_pruExecProgram(PRUICSS_Handle handle,int32_t pruNum) | |||
805 | **/ | 858 | **/ |
806 | void PRUICSS_pinMuxConfig(PRUICSS_Handle handle, uint64_t regVal) | 859 | void PRUICSS_pinMuxConfig(PRUICSS_Handle handle, uint64_t regVal) |
807 | { | 860 | { |
808 | uint32_t baseaddr = 0U; | 861 | uintptr_t baseaddr = 0U; |
809 | 862 | ||
810 | PRUICSS_V1_Object *object; | 863 | PRUICSS_V1_Object *object; |
811 | PRUICSS_HwAttrs const *hwAttrs; | 864 | PRUICSS_HwAttrs const *hwAttrs; |
812 | 865 | ||
813 | object = (PRUICSS_V1_Object*)handle->object; | 866 | object = (PRUICSS_V1_Object *)handle->object; |
814 | hwAttrs = (PRUICSS_HwAttrs const *)handle->hwAttrs; | 867 | hwAttrs = (PRUICSS_HwAttrs const *)handle->hwAttrs; |
815 | 868 | ||
816 | if(object->instance == PRUICCSS_INSTANCE_ONE) | 869 | if(object->instance == PRUICCSS_INSTANCE_ONE) |
diff --git a/src/pruicss_intc.c b/src/pruicss_intc.c index 95a4ac6..7f5b804 100644 --- a/src/pruicss_intc.c +++ b/src/pruicss_intc.c | |||
@@ -7,7 +7,7 @@ | |||
7 | */ | 7 | */ |
8 | 8 | ||
9 | /* | 9 | /* |
10 | * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ | 10 | * Copyright (C) 2015-2018 Texas Instruments Incorporated - http://www.ti.com/ |
11 | * | 11 | * |
12 | * | 12 | * |
13 | * Redistribution and use in source and binary forms, with or without | 13 | * Redistribution and use in source and binary forms, with or without |
@@ -79,7 +79,7 @@ static void PRUICSS_intcSetCmr(uint8_t sysevt, | |||
79 | uint8_t channel, | 79 | uint8_t channel, |
80 | uint8_t polarity, | 80 | uint8_t polarity, |
81 | uint8_t type, | 81 | uint8_t type, |
82 | uint32_t baseaddr); | 82 | uintptr_t baseaddr); |
83 | /** | 83 | /** |
84 | * \brief Sets Channel-Host Map registers: \n | 84 | * \brief Sets Channel-Host Map registers: \n |
85 | * | 85 | * |
@@ -91,7 +91,7 @@ static void PRUICSS_intcSetCmr(uint8_t sysevt, | |||
91 | */ | 91 | */ |
92 | static void PRUICSS_intcSetHmr(uint8_t channel, | 92 | static void PRUICSS_intcSetHmr(uint8_t channel, |
93 | uint8_t host, | 93 | uint8_t host, |
94 | uint32_t baseaddr); | 94 | uintptr_t baseaddr); |
95 | 95 | ||
96 | /** | 96 | /** |
97 | * \brief PRUICSS interrupt handler | 97 | * \brief PRUICSS interrupt handler |
@@ -123,17 +123,17 @@ static void PRUICSS_hwiIntHandler(uintptr_t ptrPpruEvtoutNum); | |||
123 | */ | 123 | */ |
124 | int32_t PRUICSS_pruIntcInit(PRUICSS_Handle handle, const PRUICSS_IntcInitData * prussintc_init_data) | 124 | int32_t PRUICSS_pruIntcInit(PRUICSS_Handle handle, const PRUICSS_IntcInitData * prussintc_init_data) |
125 | { | 125 | { |
126 | uint32_t baseaddr; | 126 | uintptr_t baseaddr; |
127 | PRUICSS_HwAttrs const *hwAttrs; | 127 | PRUICSS_HwAttrs const *hwAttrs; |
128 | PRUICSS_V1_Object *object; | 128 | PRUICSS_V1_Object *object; |
129 | 129 | ||
130 | uint32_t i = 0, mask1 = 0, mask2 = 0; | 130 | uint32_t i = 0, mask1 = 0, mask2 = 0; |
131 | 131 | ||
132 | uint32_t temp_addr = 0U; | 132 | uintptr_t temp_addr = 0U; |
133 | 133 | ||
134 | int32_t ret_val = PRUICSS_RETURN_SUCCESS; | 134 | int32_t ret_val = PRUICSS_RETURN_SUCCESS; |
135 | 135 | ||
136 | object = (PRUICSS_V1_Object*)handle->object; | 136 | object = (PRUICSS_V1_Object *)handle->object; |
137 | hwAttrs = (PRUICSS_HwAttrs const *)handle->hwAttrs; | 137 | hwAttrs = (PRUICSS_HwAttrs const *)handle->hwAttrs; |
138 | baseaddr = hwAttrs->baseAddr; | 138 | baseaddr = hwAttrs->baseAddr; |
139 | 139 | ||
@@ -163,7 +163,7 @@ int32_t PRUICSS_pruIntcInit(PRUICSS_Handle handle, const PRUICSS_IntcInitData * | |||
163 | for (i = 0; i < (PRUICSS_NUM_PRU_SYS_EVTS + 3U) >> 2; i++) | 163 | for (i = 0; i < (PRUICSS_NUM_PRU_SYS_EVTS + 3U) >> 2; i++) |
164 | { | 164 | { |
165 | temp_addr = ((baseaddr + CSL_ICSSINTC_CMR0 ) + (i << 2)); | 165 | temp_addr = ((baseaddr + CSL_ICSSINTC_CMR0 ) + (i << 2)); |
166 | HWREG(temp_addr) = 0; | 166 | CSL_REG32_WR(temp_addr, 0); |
167 | } | 167 | } |
168 | for (i = 0; | 168 | for (i = 0; |
169 | ((prussintc_init_data->sysevt_to_channel_map[i].sysevt != 0xFF) | 169 | ((prussintc_init_data->sysevt_to_channel_map[i].sysevt != 0xFF) |
@@ -180,7 +180,7 @@ int32_t PRUICSS_pruIntcInit(PRUICSS_Handle handle, const PRUICSS_IntcInitData * | |||
180 | for (i = 0; i < (PRUICSS_NUM_PRU_HOSTS + 3U) >> 2; i++) | 180 | for (i = 0; i < (PRUICSS_NUM_PRU_HOSTS + 3U) >> 2; i++) |
181 | { | 181 | { |
182 | temp_addr = (baseaddr + CSL_ICSSINTC_HMR0 + (i << 2)); | 182 | temp_addr = (baseaddr + CSL_ICSSINTC_HMR0 + (i << 2)); |
183 | HWREG(temp_addr) = 0; | 183 | CSL_REG32_WR(temp_addr, 0); |
184 | } | 184 | } |
185 | for (i = 0; | 185 | for (i = 0; |
186 | ((i<PRUICSS_NUM_PRU_HOSTS) && | 186 | ((i<PRUICSS_NUM_PRU_HOSTS) && |
@@ -334,7 +334,7 @@ int32_t PRUICSS_registerIrqHandler2(PRUICSS_Handle handle, | |||
334 | SemaphoreP_Params semParams; | 334 | SemaphoreP_Params semParams; |
335 | HwiP_Handle hwiHandle = NULL; | 335 | HwiP_Handle hwiHandle = NULL; |
336 | void* semHandle = NULL; | 336 | void* semHandle = NULL; |
337 | object = (PRUICSS_V1_Object*)handle->object; | 337 | object = (PRUICSS_V1_Object *)handle->object; |
338 | HwiP_Params hwiInputParams; | 338 | HwiP_Params hwiInputParams; |
339 | MuxIntcP_inParams muxInParams; | 339 | MuxIntcP_inParams muxInParams; |
340 | MuxIntcP_outParams muxOutParams; | 340 | MuxIntcP_outParams muxOutParams; |
@@ -439,41 +439,41 @@ static void PRUICSS_intcSetCmr( uint8_t sysevt, | |||
439 | uint8_t channel, | 439 | uint8_t channel, |
440 | uint8_t polarity, | 440 | uint8_t polarity, |
441 | uint8_t type, | 441 | uint8_t type, |
442 | uint32_t baseaddr) | 442 | uintptr_t baseaddr) |
443 | { | 443 | { |
444 | uint32_t temp_addr1 = 0U; | 444 | uintptr_t temp_addr1 = 0U; |
445 | uint32_t temp_addr2 = 0U; | 445 | uintptr_t temp_addr2 = 0U; |
446 | 446 | ||
447 | temp_addr1 = ((baseaddr)+(CSL_ICSSINTC_CMR0 + (((uint32_t)sysevt) & ~((uint32_t)0x3U)))); | 447 | temp_addr1 = ((baseaddr)+(CSL_ICSSINTC_CMR0 + (((uint32_t)sysevt) & ~((uint32_t)0x3U)))); |
448 | HWREG(temp_addr1) |= ((((uint32_t)channel) & ((uint32_t)0xFU)) << ((((uint32_t)sysevt) & ((uint32_t)0x3U)) << 3U)); | 448 | CSL_REG32_WR(temp_addr1, CSL_REG32_RD(temp_addr1) | ((((uint32_t)channel) & ((uint32_t)0xFU)) << ((((uint32_t)sysevt) & ((uint32_t)0x3U)) << 3U))); |
449 | 449 | ||
450 | if(sysevt < 32U) | 450 | if(sysevt < 32U) |
451 | { | 451 | { |
452 | temp_addr1 = (baseaddr + CSL_ICSSINTC_SIPR0); | 452 | temp_addr1 = (baseaddr + CSL_ICSSINTC_SIPR0); |
453 | temp_addr2 = (baseaddr + CSL_ICSSINTC_SITR0); | 453 | temp_addr2 = (baseaddr + CSL_ICSSINTC_SITR0); |
454 | HWREG(temp_addr1) &= ~(((uint32_t)polarity) << sysevt); | 454 | CSL_REG32_WR(temp_addr1, CSL_REG32_RD (temp_addr1) & ~(((uint32_t)polarity) << sysevt)); |
455 | HWREG(temp_addr2) &= ~(((uint32_t)type) << sysevt); | 455 | CSL_REG32_WR(temp_addr2, CSL_REG32_RD (temp_addr2) & ~(((uint32_t)type) << sysevt)); |
456 | } | 456 | } |
457 | else | 457 | else |
458 | { | 458 | { |
459 | temp_addr1 = (baseaddr + CSL_ICSSINTC_SIPR1); | 459 | temp_addr1 = (baseaddr + CSL_ICSSINTC_SIPR1); |
460 | temp_addr2 = (baseaddr + CSL_ICSSINTC_SITR1); | 460 | temp_addr2 = (baseaddr + CSL_ICSSINTC_SITR1); |
461 | HWREG(temp_addr1) &= ~(((uint32_t)polarity) << (sysevt - 32U)); | 461 | CSL_REG32_WR(temp_addr1, CSL_REG32_RD(temp_addr1) & ~(((uint32_t)polarity) << (sysevt - 32U))); |
462 | HWREG(temp_addr2) &= ~(((uint32_t)type) << (sysevt - 32U)); | 462 | CSL_REG32_WR(temp_addr2, CSL_REG32_RD(temp_addr2) & ~(((uint32_t)type) << (sysevt - 32U))); |
463 | } | 463 | } |
464 | } | 464 | } |
465 | 465 | ||
466 | 466 | ||
467 | static void PRUICSS_intcSetHmr( uint8_t channel, | 467 | static void PRUICSS_intcSetHmr( uint8_t channel, |
468 | uint8_t host, | 468 | uint8_t host, |
469 | uint32_t baseaddr) | 469 | uintptr_t baseaddr) |
470 | { | 470 | { |
471 | uint32_t temp_addr1 = 0U; | 471 | uintptr_t temp_addr1 = 0U; |
472 | uint32_t temp_addr2 = 0U; | 472 | uintptr_t temp_addr2 = 0U; |
473 | 473 | ||
474 | temp_addr1 = ((baseaddr) + (CSL_ICSSINTC_HMR0 + (((uint32_t)channel) & ~((uint32_t)0x3U)))); | 474 | temp_addr1 = ((baseaddr) + (CSL_ICSSINTC_HMR0 + (((uint32_t)channel) & ~((uint32_t)0x3U)))); |
475 | temp_addr2 = ((baseaddr) + (CSL_ICSSINTC_HMR0 + (((uint32_t)channel) & ~((uint32_t)0x3U)))); | 475 | temp_addr2 = ((baseaddr) + (CSL_ICSSINTC_HMR0 + (((uint32_t)channel) & ~((uint32_t)0x3U)))); |
476 | HWREG(temp_addr1) = HWREG(temp_addr2) | ((((uint32_t)host) & ((uint32_t)0xFU)) << ((((uint32_t)channel) & ((uint32_t)0x3U)) << 3U)); | 476 | CSL_REG32_WR(temp_addr1, CSL_REG32_RD(temp_addr2) | ((((uint32_t)host) & ((uint32_t)0xFU)) << ((((uint32_t)channel) & ((uint32_t)0x3U)) << 3U))); |
477 | } | 477 | } |
478 | 478 | ||
479 | /** | 479 | /** |
@@ -485,21 +485,22 @@ static void PRUICSS_intcSetHmr( uint8_t channel, | |||
485 | */ | 485 | */ |
486 | int32_t PRUICSS_pruIntcClear(PRUICSS_Handle handle) | 486 | int32_t PRUICSS_pruIntcClear(PRUICSS_Handle handle) |
487 | { | 487 | { |
488 | uint32_t baseaddr; | 488 | uintptr_t baseaddr; |
489 | PRUICSS_HwAttrs const *hwAttrs; | 489 | PRUICSS_HwAttrs const *hwAttrs; |
490 | PRUICSS_V1_Object *object; | 490 | PRUICSS_V1_Object *object; |
491 | 491 | ||
492 | uint32_t i = 0; | 492 | uint32_t i = 0; |
493 | 493 | ||
494 | uint32_t temp_addr = 0U; | 494 | uintptr_t temp_addr = 0U; |
495 | 495 | ||
496 | int32_t ret_val = PRUICSS_RETURN_SUCCESS; | 496 | int32_t ret_val = PRUICSS_RETURN_SUCCESS; |
497 | 497 | ||
498 | /* verify the handle */ | 498 | /* verify the handle */ |
499 | if (handle != NULL) | 499 | if (handle != NULL) |
500 | { | 500 | { |
501 | object = (PRUICSS_V1_Object*)handle->object; | 501 | object = (PRUICSS_V1_Object *)handle->object; |
502 | hwAttrs = (PRUICSS_HwAttrs const *)handle->hwAttrs; | 502 | hwAttrs = (PRUICSS_HwAttrs const *)handle->hwAttrs; |
503 | |||
503 | /* verify the instance */ | 504 | /* verify the instance */ |
504 | if ((object->instance == PRUICCSS_INSTANCE_ONE) || (object->instance == PRUICCSS_INSTANCE_TWO)) | 505 | if ((object->instance == PRUICCSS_INSTANCE_ONE) || (object->instance == PRUICCSS_INSTANCE_TWO)) |
505 | { | 506 | { |
@@ -515,32 +516,26 @@ int32_t PRUICSS_pruIntcClear(PRUICSS_Handle handle) | |||
515 | for (i = 0; i < PRUICSS_NUM_PRU_SYS_EVTS >> 2; i++) | 516 | for (i = 0; i < PRUICSS_NUM_PRU_SYS_EVTS >> 2; i++) |
516 | { | 517 | { |
517 | temp_addr = ((baseaddr + CSL_ICSSINTC_CMR0 ) + (i << 2)); | 518 | temp_addr = ((baseaddr + CSL_ICSSINTC_CMR0 ) + (i << 2)); |
518 | HWREG(temp_addr) = 0; | 519 | CSL_REG32_WR(temp_addr, 0); |
519 | } | 520 | } |
520 | 521 | ||
521 | for (i = 0; i < (PRUICSS_NUM_PRU_HOSTS + 3U) >> 2; i++) | 522 | for (i = 0; i < (PRUICSS_NUM_PRU_HOSTS + 3U) >> 2; i++) |
522 | { | 523 | { |
523 | temp_addr = (baseaddr + CSL_ICSSINTC_HMR0 + (i << 2)); | 524 | temp_addr = (baseaddr + CSL_ICSSINTC_HMR0 + (i << 2)); |
524 | HWREG(temp_addr) = 0; | 525 | CSL_REG32_WR(temp_addr, 0); |
525 | } | 526 | } |
526 | 527 | ||
527 | temp_addr = baseaddr + CSL_ICSSINTC_ESR0; | 528 | CSL_REG32_WR(baseaddr + CSL_ICSSINTC_ESR0, 0); |
528 | HWREG(temp_addr) = 0; | ||
529 | 529 | ||
530 | temp_addr = baseaddr + CSL_ICSSINTC_SECR0; | 530 | CSL_REG32_WR(baseaddr + CSL_ICSSINTC_SECR0, 0); |
531 | HWREG(temp_addr) = 0; | ||
532 | 531 | ||
533 | temp_addr = baseaddr + CSL_ICSSINTC_ERS1; | 532 | CSL_REG32_WR(baseaddr + CSL_ICSSINTC_ERS1, 0); |
534 | HWREG(temp_addr) = 0; | ||
535 | 533 | ||
536 | temp_addr = baseaddr + CSL_ICSSINTC_SECR1; | 534 | CSL_REG32_WR(baseaddr + CSL_ICSSINTC_SECR1, 0); |
537 | HWREG(temp_addr) = 0; | ||
538 | 535 | ||
539 | temp_addr = baseaddr + CSL_ICSSINTC_HIER; | 536 | CSL_REG32_WR(baseaddr + CSL_ICSSINTC_HIER, 0); |
540 | HWREG(temp_addr) = 0; | ||
541 | 537 | ||
542 | temp_addr = baseaddr + CSL_ICSSINTC_GER; | 538 | CSL_REG32_WR(baseaddr + CSL_ICSSINTC_GER, 0); |
543 | HWREG(temp_addr) = 0; | ||
544 | } | 539 | } |
545 | else | 540 | else |
546 | { | 541 | { |