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authorMahesh Radhakrishnan2018-06-19 09:52:09 -0500
committerMahesh Radhakrishnan2018-06-19 09:52:09 -0500
commitab45c8e64f159f6869cc87d264455a919d61a83b (patch)
tree7e5f23b29b27aab647b9fd9fec5e1d599c808a55
parent7f58fb87ea8462e0de97f8e7f3bac478cd6e66c8 (diff)
parentbbea0b8aabfd107971738529f63815dbe778c2ed (diff)
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Merge pull request #48 in PROCESSOR-SDK/pruss-lld from review_PRSDK-4115 to rtos-next
* commit 'bbea0b8aabfd107971738529f63815dbe778c2ed': Updates for SOC files to sync with latest SOC implementation for am57x, am335x, am437x, k2g am65xx: Fixes in pruicss soc file updates
-rw-r--r--soc/am335x/pruicss_soc.c58
-rw-r--r--soc/am437x/pruicss_soc.c6
-rw-r--r--soc/am571x/pruicss_soc.c32
-rw-r--r--soc/am572x/pruicss_soc.c18
-rw-r--r--soc/am574x/pruicss_soc.c20
-rw-r--r--soc/am65xx/pruicss_soc.c38
-rw-r--r--soc/k2g/pruicss_soc.c6
-rw-r--r--soc/pruicss_v1.h4
-rw-r--r--src/pruicss_drv.c1
9 files changed, 92 insertions, 91 deletions
diff --git a/soc/am335x/pruicss_soc.c b/soc/am335x/pruicss_soc.c
index a58f7b1..b7cb374 100644
--- a/soc/am335x/pruicss_soc.c
+++ b/soc/am335x/pruicss_soc.c
@@ -4,7 +4,7 @@
4 * @brief This is soc specific configuration file . 4 * @brief This is soc specific configuration file .
5 */ 5 */
6/* 6/*
7 * Copyright (c) 2015, Texas Instruments Incorporated 7 * Copyright (c) 2015-2018, Texas Instruments Incorporated
8 * All rights reserved. 8 * All rights reserved.
9 * 9 *
10 * Redistribution and use in source and binary forms, with or without 10 * Redistribution and use in source and binary forms, with or without
@@ -46,35 +46,33 @@
46 46
47const PRUICSS_HwAttrs prussInitCfg = 47const PRUICSS_HwAttrs prussInitCfg =
48{ 48{
49 0x4a300000, 49 0x4a300000,
50 0, 50 0,
51 SOC_PRU_ICSS_PRU0_CTRL_REG, 51 SOC_PRU_ICSS_PRU0_CTRL_REG,
52 SOC_PRU_ICSS_PRU1_CTRL_REG, 52 SOC_PRU_ICSS_PRU1_CTRL_REG,
53 SOC_PRU_ICSS_INTC_REG, 53 SOC_PRU_ICSS_INTC_REG,
54 SOC_PRU_ICSS_CFG_REG, 54 SOC_PRU_ICSS_CFG_REG,
55 SOC_PRU_ICSS_UART_REG, 55 SOC_PRU_ICSS_UART_REG,
56 SOC_PRU_ICSS_IEP_REG, 56 SOC_PRU_ICSS_IEP_REG,
57 SOC_PRU_ICSS_ECAP_REG, 57 SOC_PRU_ICSS_ECAP_REG,
58 SOC_PRU_ICSS_MII_RT_CFG_REG, 58 SOC_PRU_ICSS_MII_RT_CFG_REG,
59 SOC_PRU_ICSS_MII_MDIO_REG, 59 SOC_PRU_ICSS_MII_MDIO_REG,
60 SOC_PRU_ICSS_DATA_RAM0, 60 SOC_PRU_ICSS_DATA_RAM0,
61 SOC_PRU_ICSS_DATA_RAM1, 61 SOC_PRU_ICSS_DATA_RAM1,
62 SOC_PRU_ICSS_INST_RAM0, 62 SOC_PRU_ICSS_INST_RAM0,
63 SOC_PRU_ICSS_INST_RAM1, 63 SOC_PRU_ICSS_INST_RAM1,
64 SOC_PRU_ICSS_SHARED_RAM, 64 SOC_PRU_ICSS_SHARED_RAM,
65 0U, 65 0U,
66 0U, 66 0U,
67 0U, 67 0U,
68 0U, 68 0U,
69 SOC_PRU_ICSS_DATA_RAM0_SIZE, 69 SOC_PRU_ICSS_DATA_RAM0_SIZE,
70 SOC_PRU_ICSS_DATA_RAM1_SIZE, 70 SOC_PRU_ICSS_DATA_RAM1_SIZE,
71 SOC_PRU_ICSS_INST_RAM0_SIZE, 71 SOC_PRU_ICSS_INST_RAM0_SIZE,
72 SOC_PRU_ICSS_INST_RAM1_SIZE, 72 SOC_PRU_ICSS_INST_RAM1_SIZE,
73 SOC_PRU_ICSS_SHARED_RAM_SIZE, 73 SOC_PRU_ICSS_SHARED_RAM_SIZE,
74 0U, 74 0U,
75 0U, 75 0U
76 0U,
77 0U
78}; 76};
79 77
80/* PRUICSS objects */ 78/* PRUICSS objects */
diff --git a/soc/am437x/pruicss_soc.c b/soc/am437x/pruicss_soc.c
index 942b46c..5caa945 100644
--- a/soc/am437x/pruicss_soc.c
+++ b/soc/am437x/pruicss_soc.c
@@ -4,7 +4,7 @@
4 * @brief This is soc specific configuration file . 4 * @brief This is soc specific configuration file .
5 */ 5 */
6/* 6/*
7 * Copyright (c) 2015, Texas Instruments Incorporated 7 * Copyright (c) 2015-2018, Texas Instruments Incorporated
8 * All rights reserved. 8 * All rights reserved.
9 * 9 *
10 * Redistribution and use in source and binary forms, with or without 10 * Redistribution and use in source and binary forms, with or without
@@ -72,8 +72,6 @@ PRUICSS_HwAttrs prussInitCfg[2] =
72 SOC_PRU_ICSS0_U_INST_RAM1_SIZE, 72 SOC_PRU_ICSS0_U_INST_RAM1_SIZE,
73 SOC_PRU_ICSS0_U_SHARED_RAM_SIZE, 73 SOC_PRU_ICSS0_U_SHARED_RAM_SIZE,
74 0U, 74 0U,
75 0U,
76 0U,
77 0U 75 0U
78 }, 76 },
79 { 77 {
@@ -103,8 +101,6 @@ PRUICSS_HwAttrs prussInitCfg[2] =
103 SOC_PRU_ICSS1_U_INST_RAM1_SIZE, 101 SOC_PRU_ICSS1_U_INST_RAM1_SIZE,
104 SOC_PRU_ICSS1_U_SHARED_RAM_SIZE, 102 SOC_PRU_ICSS1_U_SHARED_RAM_SIZE,
105 0U, 103 0U,
106 0U,
107 0U,
108 0U 104 0U
109 } 105 }
110}; 106};
diff --git a/soc/am571x/pruicss_soc.c b/soc/am571x/pruicss_soc.c
index a6b2761..0dd461f 100644
--- a/soc/am571x/pruicss_soc.c
+++ b/soc/am571x/pruicss_soc.c
@@ -4,7 +4,7 @@
4 * @brief This is soc specific configuration file . 4 * @brief This is soc specific configuration file .
5 */ 5 */
6/* 6/*
7 * Copyright (c) 2015, Texas Instruments Incorporated 7 * Copyright (c) 2015-2018, Texas Instruments Incorporated
8 * All rights reserved. 8 * All rights reserved.
9 * 9 *
10 * Redistribution and use in source and binary forms, with or without 10 * Redistribution and use in source and binary forms, with or without
@@ -74,8 +74,6 @@ PRUICSS_HwAttrs prussInitCfg[2] =
74 CSL_IPU_PRUSS1_U_INST_RAM1_12KB_SIZE, 74 CSL_IPU_PRUSS1_U_INST_RAM1_12KB_SIZE,
75 CSL_IPU_PRUSS1_U_DATA_RAM_32KB_SIZE, 75 CSL_IPU_PRUSS1_U_DATA_RAM_32KB_SIZE,
76 0U, 76 0U,
77 0U,
78 0U,
79 0U 77 0U
80 }, 78 },
81 { 79 {
@@ -105,8 +103,6 @@ PRUICSS_HwAttrs prussInitCfg[2] =
105 CSL_IPU_PRUSS2_U_INST_RAM1_12KB_SIZE, 103 CSL_IPU_PRUSS2_U_INST_RAM1_12KB_SIZE,
106 CSL_IPU_PRUSS2_U_DATA_RAM_32KB_SIZE, 104 CSL_IPU_PRUSS2_U_DATA_RAM_32KB_SIZE,
107 0U, 105 0U,
108 0U,
109 0U,
110 0U 106 0U
111 } 107 }
112#elif defined (__TMS320C6X__) 108#elif defined (__TMS320C6X__)
@@ -137,8 +133,6 @@ PRUICSS_HwAttrs prussInitCfg[2] =
137 CSL_DSP_PRUSS1_U_INST_RAM1_12KB_SIZE, 133 CSL_DSP_PRUSS1_U_INST_RAM1_12KB_SIZE,
138 CSL_DSP_PRUSS1_U_DATA_RAM_32KB_SIZE, 134 CSL_DSP_PRUSS1_U_DATA_RAM_32KB_SIZE,
139 0U, 135 0U,
140 0U,
141 0U,
142 0U 136 0U
143 }, 137 },
144 { 138 {
@@ -158,11 +152,17 @@ PRUICSS_HwAttrs prussInitCfg[2] =
158 CSL_DSP_PRUSS2_U_INST_RAM0_12KB_REGS, 152 CSL_DSP_PRUSS2_U_INST_RAM0_12KB_REGS,
159 CSL_DSP_PRUSS2_U_INST_RAM1_12KB_REGS, 153 CSL_DSP_PRUSS2_U_INST_RAM1_12KB_REGS,
160 CSL_DSP_PRUSS2_U_DATA_RAM_32KB_REGS, 154 CSL_DSP_PRUSS2_U_DATA_RAM_32KB_REGS,
155 0U,
156 0U,
157 0U,
158 0U,
161 CSL_DSP_PRUSS2_U_DATA_RAM0_8KB_SIZE, 159 CSL_DSP_PRUSS2_U_DATA_RAM0_8KB_SIZE,
162 CSL_DSP_PRUSS2_U_DATA_RAM1_8KB_SIZE, 160 CSL_DSP_PRUSS2_U_DATA_RAM1_8KB_SIZE,
163 CSL_DSP_PRUSS2_U_INST_RAM0_12KB_SIZE, 161 CSL_DSP_PRUSS2_U_INST_RAM0_12KB_SIZE,
164 CSL_DSP_PRUSS2_U_INST_RAM1_12KB_SIZE, 162 CSL_DSP_PRUSS2_U_INST_RAM1_12KB_SIZE,
165 CSL_DSP_PRUSS2_U_DATA_RAM_32KB_SIZE 163 CSL_DSP_PRUSS2_U_DATA_RAM_32KB_SIZE,
164 0,
165 0
166 } 166 }
167#else 167#else
168 { 168 {
@@ -182,11 +182,17 @@ PRUICSS_HwAttrs prussInitCfg[2] =
182 CSL_MPU_PRUSS1_U_INST_RAM0_12KB_REGS, 182 CSL_MPU_PRUSS1_U_INST_RAM0_12KB_REGS,
183 CSL_MPU_PRUSS1_U_INST_RAM1_12KB_REGS, 183 CSL_MPU_PRUSS1_U_INST_RAM1_12KB_REGS,
184 CSL_MPU_PRUSS1_U_DATA_RAM_32KB_REGS, 184 CSL_MPU_PRUSS1_U_DATA_RAM_32KB_REGS,
185 0U,
186 0U,
187 0U,
188 0U,
185 CSL_MPU_PRUSS1_U_DATA_RAM0_8KB_SIZE, 189 CSL_MPU_PRUSS1_U_DATA_RAM0_8KB_SIZE,
186 CSL_MPU_PRUSS1_U_DATA_RAM1_8KB_SIZE, 190 CSL_MPU_PRUSS1_U_DATA_RAM1_8KB_SIZE,
187 CSL_MPU_PRUSS1_U_INST_RAM0_12KB_SIZE, 191 CSL_MPU_PRUSS1_U_INST_RAM0_12KB_SIZE,
188 CSL_MPU_PRUSS1_U_INST_RAM1_12KB_SIZE, 192 CSL_MPU_PRUSS1_U_INST_RAM1_12KB_SIZE,
189 CSL_MPU_PRUSS1_U_DATA_RAM_32KB_SIZE 193 CSL_MPU_PRUSS1_U_DATA_RAM_32KB_SIZE,
194 0,
195 0
190 }, 196 },
191 { 197 {
192 0x4b280000, 198 0x4b280000,
@@ -205,11 +211,17 @@ PRUICSS_HwAttrs prussInitCfg[2] =
205 CSL_MPU_PRUSS2_U_INST_RAM0_12KB_REGS, 211 CSL_MPU_PRUSS2_U_INST_RAM0_12KB_REGS,
206 CSL_MPU_PRUSS2_U_INST_RAM1_12KB_REGS, 212 CSL_MPU_PRUSS2_U_INST_RAM1_12KB_REGS,
207 CSL_MPU_PRUSS2_U_DATA_RAM_32KB_REGS, 213 CSL_MPU_PRUSS2_U_DATA_RAM_32KB_REGS,
214 0U,
215 0U,
216 0U,
217 0U,
208 CSL_MPU_PRUSS2_U_DATA_RAM0_8KB_SIZE, 218 CSL_MPU_PRUSS2_U_DATA_RAM0_8KB_SIZE,
209 CSL_MPU_PRUSS2_U_DATA_RAM1_8KB_SIZE, 219 CSL_MPU_PRUSS2_U_DATA_RAM1_8KB_SIZE,
210 CSL_MPU_PRUSS2_U_INST_RAM0_12KB_SIZE, 220 CSL_MPU_PRUSS2_U_INST_RAM0_12KB_SIZE,
211 CSL_MPU_PRUSS2_U_INST_RAM1_12KB_SIZE, 221 CSL_MPU_PRUSS2_U_INST_RAM1_12KB_SIZE,
212 CSL_MPU_PRUSS2_U_DATA_RAM_32KB_SIZE 222 CSL_MPU_PRUSS2_U_DATA_RAM_32KB_SIZE,
223 0,
224 0
213 } 225 }
214#endif 226#endif
215}; 227};
diff --git a/soc/am572x/pruicss_soc.c b/soc/am572x/pruicss_soc.c
index d5d7c26..8c31875 100644
--- a/soc/am572x/pruicss_soc.c
+++ b/soc/am572x/pruicss_soc.c
@@ -4,7 +4,7 @@
4 * @brief This is soc specific configuration file . 4 * @brief This is soc specific configuration file .
5 */ 5 */
6/* 6/*
7 * Copyright (c) 2015, Texas Instruments Incorporated 7 * Copyright (c) 2015-2018, Texas Instruments Incorporated
8 * All rights reserved. 8 * All rights reserved.
9 * 9 *
10 * Redistribution and use in source and binary forms, with or without 10 * Redistribution and use in source and binary forms, with or without
@@ -74,8 +74,6 @@ PRUICSS_HwAttrs prussInitCfg[2] =
74 CSL_IPU_PRUSS1_U_INST_RAM1_12KB_SIZE, 74 CSL_IPU_PRUSS1_U_INST_RAM1_12KB_SIZE,
75 CSL_IPU_PRUSS1_U_DATA_RAM_32KB_SIZE, 75 CSL_IPU_PRUSS1_U_DATA_RAM_32KB_SIZE,
76 0U, 76 0U,
77 0U,
78 0U,
79 0U 77 0U
80 }, 78 },
81 { 79 {
@@ -105,8 +103,6 @@ PRUICSS_HwAttrs prussInitCfg[2] =
105 CSL_IPU_PRUSS2_U_INST_RAM1_12KB_SIZE, 103 CSL_IPU_PRUSS2_U_INST_RAM1_12KB_SIZE,
106 CSL_IPU_PRUSS2_U_DATA_RAM_32KB_SIZE, 104 CSL_IPU_PRUSS2_U_DATA_RAM_32KB_SIZE,
107 0U, 105 0U,
108 0U,
109 0U,
110 0U 106 0U
111 } 107 }
112#elif defined (__TMS320C6X__) 108#elif defined (__TMS320C6X__)
@@ -137,8 +133,6 @@ PRUICSS_HwAttrs prussInitCfg[2] =
137 CSL_DSP_PRUSS1_U_INST_RAM1_12KB_SIZE, 133 CSL_DSP_PRUSS1_U_INST_RAM1_12KB_SIZE,
138 CSL_DSP_PRUSS1_U_DATA_RAM_32KB_SIZE, 134 CSL_DSP_PRUSS1_U_DATA_RAM_32KB_SIZE,
139 0U, 135 0U,
140 0U,
141 0U,
142 0U 136 0U
143 }, 137 },
144 { 138 {
@@ -167,10 +161,8 @@ PRUICSS_HwAttrs prussInitCfg[2] =
167 CSL_DSP_PRUSS2_U_INST_RAM0_12KB_SIZE, 161 CSL_DSP_PRUSS2_U_INST_RAM0_12KB_SIZE,
168 CSL_DSP_PRUSS2_U_INST_RAM1_12KB_SIZE, 162 CSL_DSP_PRUSS2_U_INST_RAM1_12KB_SIZE,
169 CSL_DSP_PRUSS2_U_DATA_RAM_32KB_SIZE, 163 CSL_DSP_PRUSS2_U_DATA_RAM_32KB_SIZE,
170 0U, 164 0U,
171 0U, 165 0U
172 0U,
173 0U
174 } 166 }
175#else 167#else
176 { 168 {
@@ -200,8 +192,6 @@ PRUICSS_HwAttrs prussInitCfg[2] =
200 CSL_MPU_PRUSS1_U_INST_RAM1_12KB_SIZE, 192 CSL_MPU_PRUSS1_U_INST_RAM1_12KB_SIZE,
201 CSL_MPU_PRUSS1_U_DATA_RAM_32KB_SIZE, 193 CSL_MPU_PRUSS1_U_DATA_RAM_32KB_SIZE,
202 0U, 194 0U,
203 0U,
204 0U,
205 0U 195 0U
206 }, 196 },
207 { 197 {
@@ -231,8 +221,6 @@ PRUICSS_HwAttrs prussInitCfg[2] =
231 CSL_MPU_PRUSS2_U_INST_RAM1_12KB_SIZE, 221 CSL_MPU_PRUSS2_U_INST_RAM1_12KB_SIZE,
232 CSL_MPU_PRUSS2_U_DATA_RAM_32KB_SIZE, 222 CSL_MPU_PRUSS2_U_DATA_RAM_32KB_SIZE,
233 0U, 223 0U,
234 0U,
235 0U,
236 0U 224 0U
237 } 225 }
238#endif 226#endif
diff --git a/soc/am574x/pruicss_soc.c b/soc/am574x/pruicss_soc.c
index c61a917..049767f 100644
--- a/soc/am574x/pruicss_soc.c
+++ b/soc/am574x/pruicss_soc.c
@@ -4,7 +4,7 @@
4 * @brief This is soc specific configuration file . 4 * @brief This is soc specific configuration file .
5 */ 5 */
6/* 6/*
7 * Copyright (c) 2017, Texas Instruments Incorporated 7 * Copyright (c) 2017-2018, Texas Instruments Incorporated
8 * All rights reserved. 8 * All rights reserved.
9 * 9 *
10 * Redistribution and use in source and binary forms, with or without 10 * Redistribution and use in source and binary forms, with or without
@@ -64,11 +64,17 @@ PRUICSS_HwAttrs prussInitCfg[2] =
64 CSL_IPU_PRUSS1_U_INST_RAM0_12KB_REGS, 64 CSL_IPU_PRUSS1_U_INST_RAM0_12KB_REGS,
65 CSL_IPU_PRUSS1_U_INST_RAM1_12KB_REGS, 65 CSL_IPU_PRUSS1_U_INST_RAM1_12KB_REGS,
66 CSL_IPU_PRUSS1_U_DATA_RAM_32KB_REGS, 66 CSL_IPU_PRUSS1_U_DATA_RAM_32KB_REGS,
67 0U,
68 0U,
69 0U,
70 0U,
67 CSL_IPU_PRUSS1_U_DATA_RAM0_8KB_SIZE, 71 CSL_IPU_PRUSS1_U_DATA_RAM0_8KB_SIZE,
68 CSL_IPU_PRUSS1_U_DATA_RAM1_8KB_SIZE, 72 CSL_IPU_PRUSS1_U_DATA_RAM1_8KB_SIZE,
69 CSL_IPU_PRUSS1_U_INST_RAM0_12KB_SIZE, 73 CSL_IPU_PRUSS1_U_INST_RAM0_12KB_SIZE,
70 CSL_IPU_PRUSS1_U_INST_RAM1_12KB_SIZE, 74 CSL_IPU_PRUSS1_U_INST_RAM1_12KB_SIZE,
71 CSL_IPU_PRUSS1_U_DATA_RAM_32KB_SIZE 75 CSL_IPU_PRUSS1_U_DATA_RAM_32KB_SIZE,
76 0U,
77 0U
72 }, 78 },
73 { 79 {
74 0x4b280000, 80 0x4b280000,
@@ -97,8 +103,6 @@ PRUICSS_HwAttrs prussInitCfg[2] =
97 CSL_IPU_PRUSS2_U_INST_RAM1_12KB_SIZE, 103 CSL_IPU_PRUSS2_U_INST_RAM1_12KB_SIZE,
98 CSL_IPU_PRUSS2_U_DATA_RAM_32KB_SIZE, 104 CSL_IPU_PRUSS2_U_DATA_RAM_32KB_SIZE,
99 0U, 105 0U,
100 0U,
101 0U,
102 0U 106 0U
103 } 107 }
104#elif defined (__TMS320C6X__) 108#elif defined (__TMS320C6X__)
@@ -129,8 +133,6 @@ PRUICSS_HwAttrs prussInitCfg[2] =
129 CSL_DSP_PRUSS1_U_INST_RAM1_12KB_SIZE, 133 CSL_DSP_PRUSS1_U_INST_RAM1_12KB_SIZE,
130 CSL_DSP_PRUSS1_U_DATA_RAM_32KB_SIZE, 134 CSL_DSP_PRUSS1_U_DATA_RAM_32KB_SIZE,
131 0U, 135 0U,
132 0U,
133 0U,
134 0U 136 0U
135 }, 137 },
136 { 138 {
@@ -160,8 +162,6 @@ PRUICSS_HwAttrs prussInitCfg[2] =
160 CSL_DSP_PRUSS2_U_INST_RAM1_12KB_SIZE, 162 CSL_DSP_PRUSS2_U_INST_RAM1_12KB_SIZE,
161 CSL_DSP_PRUSS2_U_DATA_RAM_32KB_SIZE, 163 CSL_DSP_PRUSS2_U_DATA_RAM_32KB_SIZE,
162 0U, 164 0U,
163 0U,
164 0U,
165 0U 165 0U
166 } 166 }
167#else 167#else
@@ -192,8 +192,6 @@ PRUICSS_HwAttrs prussInitCfg[2] =
192 CSL_MPU_PRUSS1_U_INST_RAM1_12KB_SIZE, 192 CSL_MPU_PRUSS1_U_INST_RAM1_12KB_SIZE,
193 CSL_MPU_PRUSS1_U_DATA_RAM_32KB_SIZE, 193 CSL_MPU_PRUSS1_U_DATA_RAM_32KB_SIZE,
194 0U, 194 0U,
195 0U,
196 0U,
197 0U 195 0U
198 }, 196 },
199 { 197 {
@@ -223,8 +221,6 @@ PRUICSS_HwAttrs prussInitCfg[2] =
223 CSL_MPU_PRUSS2_U_INST_RAM1_12KB_SIZE, 221 CSL_MPU_PRUSS2_U_INST_RAM1_12KB_SIZE,
224 CSL_MPU_PRUSS2_U_DATA_RAM_32KB_SIZE, 222 CSL_MPU_PRUSS2_U_DATA_RAM_32KB_SIZE,
225 0U, 223 0U,
226 0U,
227 0U,
228 0U 224 0U
229 } 225 }
230#endif 226#endif
diff --git a/soc/am65xx/pruicss_soc.c b/soc/am65xx/pruicss_soc.c
index be7c384..71f3997 100644
--- a/soc/am65xx/pruicss_soc.c
+++ b/soc/am65xx/pruicss_soc.c
@@ -4,7 +4,7 @@
4 * @brief This is device specific configuration file . 4 * @brief This is device specific configuration file .
5 */ 5 */
6/* 6/*
7 * Copyright (c) 2017, Texas Instruments Incorporated 7 * Copyright (c) 2017-2018, Texas Instruments Incorporated
8 * All rights reserved. 8 * All rights reserved.
9 * 9 *
10 * Redistribution and use in source and binary forms, with or without 10 * Redistribution and use in source and binary forms, with or without
@@ -44,16 +44,13 @@
44 44
45 45
46#include <ti/csl/soc/am65xx/src/cslr_soc.h> 46#include <ti/csl/soc/am65xx/src/cslr_soc.h>
47#ifdef BORG_ENV
48#include "../../tests/platform.h" /* borg csl base */
49#endif
50 47
51/* PRUICSS configuration structure */ 48/* PRUICSS configuration structure */
52PRUICSS_HwAttrs prussInitCfg[3] = 49PRUICSS_HwAttrs prussInitCfg[3] =
53{ 50{
54 { 51 {
55 CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE, /* baseAddr */ 52 CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE, /* baseAddr */
56 0, /* version */ 53 0, /* version */
57 CSL_PRU_ICSSG0_PR1_PDSP0_IRAM_BASE, /* prussPru0CtrlRegBase */ 54 CSL_PRU_ICSSG0_PR1_PDSP0_IRAM_BASE, /* prussPru0CtrlRegBase */
58 CSL_PRU_ICSSG0_PR1_PDSP1_IRAM_BASE, /* prussPru1CtrlRegBase */ 55 CSL_PRU_ICSSG0_PR1_PDSP1_IRAM_BASE, /* prussPru1CtrlRegBase */
59 CSL_PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV_BASE, /* prussIntcRegBase */ 56 CSL_PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV_BASE, /* prussIntcRegBase */
@@ -71,11 +68,18 @@ PRUICSS_HwAttrs prussInitCfg[3] =
71 CSL_PRU_ICSSG0_PR1_RTU0_PR1_RTU0_IRAM_RAM_BASE, /* prussRtu0IramBase */ 68 CSL_PRU_ICSSG0_PR1_RTU0_PR1_RTU0_IRAM_RAM_BASE, /* prussRtu0IramBase */
72 CSL_PRU_ICSSG0_PR1_RTU1_PR1_RTU1_IRAM_RAM_BASE, /* prussRtu1IramBase */ 69 CSL_PRU_ICSSG0_PR1_RTU1_PR1_RTU1_IRAM_RAM_BASE, /* prussRtu1IramBase */
73 CSL_PRU_ICSSG0_PR1_RTU0_PR1_RTU0_IRAM_BASE, /* prussRtu0CtrlRegBase */ 70 CSL_PRU_ICSSG0_PR1_RTU0_PR1_RTU0_IRAM_BASE, /* prussRtu0CtrlRegBase */
74 CSL_PRU_ICSSG0_PR1_RTU1_PR1_RTU1_IRAM_BASE /* prussRtu1CtrlRegBase */ 71 CSL_PRU_ICSSG0_PR1_RTU1_PR1_RTU1_IRAM_BASE, /* prussRtu1CtrlRegBase */
72 CSL_PRU_ICSSG0_DRAM0_SLV_RAM_SIZE, /* prussPru0DramSize */
73 CSL_PRU_ICSSG0_DRAM1_SLV_RAM_SIZE, /* prussPru1DramSize */
74 CSL_PRU_ICSSG0_PR1_PDSP0_IRAM_SIZE, /* prussPru0IramSize */
75 CSL_PRU_ICSSG0_PR1_PDSP1_IRAM_SIZE, /* prussPru1IramSize */
76 CSL_PRU_ICSSG0_RAM_SLV_RAM_SIZE, /* prussSharedDramSize */
77 CSL_PRU_ICSSG0_PR1_RTU0_PR1_RTU0_IRAM_RAM_SIZE, /* prussRtu0IramSize */
78 CSL_PRU_ICSSG0_PR1_RTU1_PR1_RTU1_IRAM_RAM_SIZE /* prussRtu1IramSize */
75 }, 79 },
76 { 80 {
77 CSL_PRU_ICSSG1_DRAM0_SLV_RAM_BASE, /* baseAddr */ 81 CSL_PRU_ICSSG1_DRAM0_SLV_RAM_BASE, /* baseAddr */
78 0, /* version */ 82 0, /* version */
79 CSL_PRU_ICSSG1_PR1_PDSP0_IRAM_BASE, /* prussPru0CtrlRegBase */ 83 CSL_PRU_ICSSG1_PR1_PDSP0_IRAM_BASE, /* prussPru0CtrlRegBase */
80 CSL_PRU_ICSSG1_PR1_PDSP1_IRAM_BASE, /* prussPru1CtrlRegBase */ 84 CSL_PRU_ICSSG1_PR1_PDSP1_IRAM_BASE, /* prussPru1CtrlRegBase */
81 CSL_PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV_BASE, /* prussIntcRegBase */ 85 CSL_PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV_BASE, /* prussIntcRegBase */
@@ -93,11 +97,18 @@ PRUICSS_HwAttrs prussInitCfg[3] =
93 CSL_PRU_ICSSG1_PR1_RTU0_PR1_RTU0_IRAM_RAM_BASE, /* prussRtu0IramBase */ 97 CSL_PRU_ICSSG1_PR1_RTU0_PR1_RTU0_IRAM_RAM_BASE, /* prussRtu0IramBase */
94 CSL_PRU_ICSSG1_PR1_RTU1_PR1_RTU1_IRAM_RAM_BASE, /* prussRtu1IramBase */ 98 CSL_PRU_ICSSG1_PR1_RTU1_PR1_RTU1_IRAM_RAM_BASE, /* prussRtu1IramBase */
95 CSL_PRU_ICSSG1_PR1_RTU0_PR1_RTU0_IRAM_BASE, /* prussRtu0CtrlRegBase */ 99 CSL_PRU_ICSSG1_PR1_RTU0_PR1_RTU0_IRAM_BASE, /* prussRtu0CtrlRegBase */
96 CSL_PRU_ICSSG1_PR1_RTU1_PR1_RTU1_IRAM_BASE /* prussRtu1CtrlRegBase */ 100 CSL_PRU_ICSSG1_PR1_RTU1_PR1_RTU1_IRAM_BASE, /* prussRtu1CtrlRegBase */
101 CSL_PRU_ICSSG1_DRAM0_SLV_RAM_SIZE, /* prussPru0DramSize */
102 CSL_PRU_ICSSG1_DRAM1_SLV_RAM_SIZE, /* prussPru1DramSize */
103 CSL_PRU_ICSSG1_PR1_PDSP0_IRAM_SIZE, /* prussPru0IramSize */
104 CSL_PRU_ICSSG1_PR1_PDSP1_IRAM_SIZE, /* prussPru1IramSize */
105 CSL_PRU_ICSSG1_RAM_SLV_RAM_SIZE, /* prussSharedDramSize */
106 CSL_PRU_ICSSG1_PR1_RTU0_PR1_RTU0_IRAM_RAM_SIZE, /* prussRtu0IramSize */
107 CSL_PRU_ICSSG1_PR1_RTU1_PR1_RTU1_IRAM_RAM_SIZE /* prussRtu1IramSize */
97 }, 108 },
98 { 109 {
99 CSL_PRU_ICSSG2_DRAM0_SLV_RAM_BASE, /* baseAddr */ 110 CSL_PRU_ICSSG2_DRAM0_SLV_RAM_BASE, /* baseAddr */
100 0, /* version */ 111 0, /* version */
101 CSL_PRU_ICSSG2_PR1_PDSP0_IRAM_BASE, /* prussPru0CtrlRegBase */ 112 CSL_PRU_ICSSG2_PR1_PDSP0_IRAM_BASE, /* prussPru0CtrlRegBase */
102 CSL_PRU_ICSSG2_PR1_PDSP1_IRAM_BASE, /* prussPru1CtrlRegBase */ 113 CSL_PRU_ICSSG2_PR1_PDSP1_IRAM_BASE, /* prussPru1CtrlRegBase */
103 CSL_PRU_ICSSG2_PR1_ICSS_INTC_INTC_SLV_BASE, /* prussIntcRegBase */ 114 CSL_PRU_ICSSG2_PR1_ICSS_INTC_INTC_SLV_BASE, /* prussIntcRegBase */
@@ -115,7 +126,14 @@ PRUICSS_HwAttrs prussInitCfg[3] =
115 CSL_PRU_ICSSG2_PR1_RTU0_PR1_RTU0_IRAM_RAM_BASE, /* prussRtu0IramBase */ 126 CSL_PRU_ICSSG2_PR1_RTU0_PR1_RTU0_IRAM_RAM_BASE, /* prussRtu0IramBase */
116 CSL_PRU_ICSSG2_PR1_RTU1_PR1_RTU1_IRAM_RAM_BASE, /* prussRtu1IramBase */ 127 CSL_PRU_ICSSG2_PR1_RTU1_PR1_RTU1_IRAM_RAM_BASE, /* prussRtu1IramBase */
117 CSL_PRU_ICSSG2_PR1_RTU0_PR1_RTU0_IRAM_BASE, /* prussRtu0CtrlRegBase */ 128 CSL_PRU_ICSSG2_PR1_RTU0_PR1_RTU0_IRAM_BASE, /* prussRtu0CtrlRegBase */
118 CSL_PRU_ICSSG2_PR1_RTU1_PR1_RTU1_IRAM_BASE /* prussRtu1CtrlRegBase */ 129 CSL_PRU_ICSSG2_PR1_RTU1_PR1_RTU1_IRAM_BASE, /* prussRtu1CtrlRegBase */
130 CSL_PRU_ICSSG2_DRAM0_SLV_RAM_SIZE, /* prussPru0DramSize */
131 CSL_PRU_ICSSG2_DRAM1_SLV_RAM_SIZE, /* prussPru1DramSize */
132 CSL_PRU_ICSSG2_PR1_PDSP0_IRAM_SIZE, /* prussPru0IramSize */
133 CSL_PRU_ICSSG2_PR1_PDSP1_IRAM_SIZE, /* prussPru1IramSize */
134 CSL_PRU_ICSSG2_RAM_SLV_RAM_SIZE, /* prussSharedDramSize */
135 CSL_PRU_ICSSG2_PR1_RTU0_PR1_RTU0_IRAM_RAM_SIZE, /* prussRtu0IramSize */
136 CSL_PRU_ICSSG2_PR1_RTU1_PR1_RTU1_IRAM_RAM_SIZE /* prussRtu1IramSize */
119 } 137 }
120}; 138};
121 139
diff --git a/soc/k2g/pruicss_soc.c b/soc/k2g/pruicss_soc.c
index eefe767..4f39705 100644
--- a/soc/k2g/pruicss_soc.c
+++ b/soc/k2g/pruicss_soc.c
@@ -4,7 +4,7 @@
4 * @brief This is device specific configuration file . 4 * @brief This is device specific configuration file .
5 */ 5 */
6/* 6/*
7 * Copyright (c) 2016, Texas Instruments Incorporated 7 * Copyright (c) 2016-2018, Texas Instruments Incorporated
8 * All rights reserved. 8 * All rights reserved.
9 * 9 *
10 * Redistribution and use in source and binary forms, with or without 10 * Redistribution and use in source and binary forms, with or without
@@ -76,8 +76,6 @@ PRUICSS_HwAttrs prussInitCfg[2] =
76 CSL_ICSS_0_DATA_RAM_64KB_REGS_SIZE, 76 CSL_ICSS_0_DATA_RAM_64KB_REGS_SIZE,
77 0U, 77 0U,
78 0U, 78 0U,
79 0U,
80 0U,
81 }, 79 },
82 { 80 {
83 CSL_ICSS_1_DATA_RAM_8KB_0_REGS, 81 CSL_ICSS_1_DATA_RAM_8KB_0_REGS,
@@ -106,8 +104,6 @@ PRUICSS_HwAttrs prussInitCfg[2] =
106 CSL_ICSS_0_INST_RAM_16KB_1_REGS_SIZE, 104 CSL_ICSS_0_INST_RAM_16KB_1_REGS_SIZE,
107 CSL_ICSS_0_DATA_RAM_64KB_REGS_SIZE, 105 CSL_ICSS_0_DATA_RAM_64KB_REGS_SIZE,
108 0U, 106 0U,
109 0U,
110 0U,
111 0U 107 0U
112 } 108 }
113}; 109};
diff --git a/soc/pruicss_v1.h b/soc/pruicss_v1.h
index 0607ec0..3af9932 100644
--- a/soc/pruicss_v1.h
+++ b/soc/pruicss_v1.h
@@ -120,10 +120,6 @@ typedef struct PRUICSS_HWAttrs {
120 120
121 uint32_t prussSharedDramSize; 121 uint32_t prussSharedDramSize;
122 122
123 uint32_t prussRtu0DramSize;
124
125 uint32_t prussRtu1DramSize;
126
127 uint32_t prussRtu0IramSize; 123 uint32_t prussRtu0IramSize;
128 124
129 uint32_t prussRtu1IramSize; 125 uint32_t prussRtu1IramSize;
diff --git a/src/pruicss_drv.c b/src/pruicss_drv.c
index 79f6905..d033f3c 100644
--- a/src/pruicss_drv.c
+++ b/src/pruicss_drv.c
@@ -44,6 +44,7 @@
44#include <ti/drv/pruss/soc/pruicss_v1.h> 44#include <ti/drv/pruss/soc/pruicss_v1.h>
45#include <ti/drv/pruss/src/pruicss_osal.h> 45#include <ti/drv/pruss/src/pruicss_osal.h>
46 46
47#include <ti/csl/cslr.h>
47#include <ti/csl/src/ip/icss/V1/cslr_icss_pru_ctrl.h> 48#include <ti/csl/src/ip/icss/V1/cslr_icss_pru_ctrl.h>
48#include <ti/csl/src/ip/icss/V1/cslr_icss_intc.h> 49#include <ti/csl/src/ip/icss/V1/cslr_icss_intc.h>
49#include <ti/csl/src/ip/icss/V1/cslr_icss_cfg.h> 50#include <ti/csl/src/ip/icss/V1/cslr_icss_cfg.h>