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authorTinku Mannan2018-06-13 11:24:16 -0500
committerTinku Mannan2018-06-13 12:17:23 -0500
commitf4837e9efdfa52f72c0702e6eb3f361adb2a4f4b (patch)
tree5af9ff1b6cf8814ed86764c1ccc3b9de81255e72
parent7f58fb87ea8462e0de97f8e7f3bac478cd6e66c8 (diff)
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am65xx: Fixes in pruicss soc file updates
-rw-r--r--soc/am65xx/pruicss_soc.c36
-rw-r--r--soc/pruicss_v1.h4
2 files changed, 27 insertions, 13 deletions
diff --git a/soc/am65xx/pruicss_soc.c b/soc/am65xx/pruicss_soc.c
index be7c384..b022ca5 100644
--- a/soc/am65xx/pruicss_soc.c
+++ b/soc/am65xx/pruicss_soc.c
@@ -44,16 +44,13 @@
44 44
45 45
46#include <ti/csl/soc/am65xx/src/cslr_soc.h> 46#include <ti/csl/soc/am65xx/src/cslr_soc.h>
47#ifdef BORG_ENV
48#include "../../tests/platform.h" /* borg csl base */
49#endif
50 47
51/* PRUICSS configuration structure */ 48/* PRUICSS configuration structure */
52PRUICSS_HwAttrs prussInitCfg[3] = 49PRUICSS_HwAttrs prussInitCfg[3] =
53{ 50{
54 { 51 {
55 CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE, /* baseAddr */ 52 CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE, /* baseAddr */
56 0, /* version */ 53 0, /* version */
57 CSL_PRU_ICSSG0_PR1_PDSP0_IRAM_BASE, /* prussPru0CtrlRegBase */ 54 CSL_PRU_ICSSG0_PR1_PDSP0_IRAM_BASE, /* prussPru0CtrlRegBase */
58 CSL_PRU_ICSSG0_PR1_PDSP1_IRAM_BASE, /* prussPru1CtrlRegBase */ 55 CSL_PRU_ICSSG0_PR1_PDSP1_IRAM_BASE, /* prussPru1CtrlRegBase */
59 CSL_PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV_BASE, /* prussIntcRegBase */ 56 CSL_PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV_BASE, /* prussIntcRegBase */
@@ -71,11 +68,18 @@ PRUICSS_HwAttrs prussInitCfg[3] =
71 CSL_PRU_ICSSG0_PR1_RTU0_PR1_RTU0_IRAM_RAM_BASE, /* prussRtu0IramBase */ 68 CSL_PRU_ICSSG0_PR1_RTU0_PR1_RTU0_IRAM_RAM_BASE, /* prussRtu0IramBase */
72 CSL_PRU_ICSSG0_PR1_RTU1_PR1_RTU1_IRAM_RAM_BASE, /* prussRtu1IramBase */ 69 CSL_PRU_ICSSG0_PR1_RTU1_PR1_RTU1_IRAM_RAM_BASE, /* prussRtu1IramBase */
73 CSL_PRU_ICSSG0_PR1_RTU0_PR1_RTU0_IRAM_BASE, /* prussRtu0CtrlRegBase */ 70 CSL_PRU_ICSSG0_PR1_RTU0_PR1_RTU0_IRAM_BASE, /* prussRtu0CtrlRegBase */
74 CSL_PRU_ICSSG0_PR1_RTU1_PR1_RTU1_IRAM_BASE /* prussRtu1CtrlRegBase */ 71 CSL_PRU_ICSSG0_PR1_RTU1_PR1_RTU1_IRAM_BASE, /* prussRtu1CtrlRegBase */
72 CSL_PRU_ICSSG0_DRAM0_SLV_RAM_SIZE, /* prussPru0DramSize */
73 CSL_PRU_ICSSG0_DRAM1_SLV_RAM_SIZE, /* prussPru1DramSize */
74 CSL_PRU_ICSSG0_PR1_PDSP0_IRAM_SIZE, /* prussPru0IramSize */
75 CSL_PRU_ICSSG0_PR1_PDSP1_IRAM_SIZE, /* prussPru1IramSize */
76 CSL_PRU_ICSSG0_RAM_SLV_RAM_SIZE, /* prussSharedDramSize */
77 CSL_PRU_ICSSG0_PR1_RTU0_PR1_RTU0_IRAM_RAM_SIZE, /* prussRtu0IramSize */
78 CSL_PRU_ICSSG0_PR1_RTU1_PR1_RTU1_IRAM_RAM_SIZE /* prussRtu1IramSize */
75 }, 79 },
76 { 80 {
77 CSL_PRU_ICSSG1_DRAM0_SLV_RAM_BASE, /* baseAddr */ 81 CSL_PRU_ICSSG1_DRAM0_SLV_RAM_BASE, /* baseAddr */
78 0, /* version */ 82 0, /* version */
79 CSL_PRU_ICSSG1_PR1_PDSP0_IRAM_BASE, /* prussPru0CtrlRegBase */ 83 CSL_PRU_ICSSG1_PR1_PDSP0_IRAM_BASE, /* prussPru0CtrlRegBase */
80 CSL_PRU_ICSSG1_PR1_PDSP1_IRAM_BASE, /* prussPru1CtrlRegBase */ 84 CSL_PRU_ICSSG1_PR1_PDSP1_IRAM_BASE, /* prussPru1CtrlRegBase */
81 CSL_PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV_BASE, /* prussIntcRegBase */ 85 CSL_PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV_BASE, /* prussIntcRegBase */
@@ -93,11 +97,18 @@ PRUICSS_HwAttrs prussInitCfg[3] =
93 CSL_PRU_ICSSG1_PR1_RTU0_PR1_RTU0_IRAM_RAM_BASE, /* prussRtu0IramBase */ 97 CSL_PRU_ICSSG1_PR1_RTU0_PR1_RTU0_IRAM_RAM_BASE, /* prussRtu0IramBase */
94 CSL_PRU_ICSSG1_PR1_RTU1_PR1_RTU1_IRAM_RAM_BASE, /* prussRtu1IramBase */ 98 CSL_PRU_ICSSG1_PR1_RTU1_PR1_RTU1_IRAM_RAM_BASE, /* prussRtu1IramBase */
95 CSL_PRU_ICSSG1_PR1_RTU0_PR1_RTU0_IRAM_BASE, /* prussRtu0CtrlRegBase */ 99 CSL_PRU_ICSSG1_PR1_RTU0_PR1_RTU0_IRAM_BASE, /* prussRtu0CtrlRegBase */
96 CSL_PRU_ICSSG1_PR1_RTU1_PR1_RTU1_IRAM_BASE /* prussRtu1CtrlRegBase */ 100 CSL_PRU_ICSSG1_PR1_RTU1_PR1_RTU1_IRAM_BASE, /* prussRtu1CtrlRegBase */
101 CSL_PRU_ICSSG1_DRAM0_SLV_RAM_SIZE, /* prussPru0DramSize */
102 CSL_PRU_ICSSG1_DRAM1_SLV_RAM_SIZE, /* prussPru1DramSize */
103 CSL_PRU_ICSSG1_PR1_PDSP0_IRAM_SIZE, /* prussPru0IramSize */
104 CSL_PRU_ICSSG1_PR1_PDSP1_IRAM_SIZE, /* prussPru1IramSize */
105 CSL_PRU_ICSSG1_RAM_SLV_RAM_SIZE, /* prussSharedDramSize */
106 CSL_PRU_ICSSG1_PR1_RTU0_PR1_RTU0_IRAM_RAM_SIZE, /* prussRtu0IramSize */
107 CSL_PRU_ICSSG1_PR1_RTU1_PR1_RTU1_IRAM_RAM_SIZE /* prussRtu1IramSize */
97 }, 108 },
98 { 109 {
99 CSL_PRU_ICSSG2_DRAM0_SLV_RAM_BASE, /* baseAddr */ 110 CSL_PRU_ICSSG2_DRAM0_SLV_RAM_BASE, /* baseAddr */
100 0, /* version */ 111 0, /* version */
101 CSL_PRU_ICSSG2_PR1_PDSP0_IRAM_BASE, /* prussPru0CtrlRegBase */ 112 CSL_PRU_ICSSG2_PR1_PDSP0_IRAM_BASE, /* prussPru0CtrlRegBase */
102 CSL_PRU_ICSSG2_PR1_PDSP1_IRAM_BASE, /* prussPru1CtrlRegBase */ 113 CSL_PRU_ICSSG2_PR1_PDSP1_IRAM_BASE, /* prussPru1CtrlRegBase */
103 CSL_PRU_ICSSG2_PR1_ICSS_INTC_INTC_SLV_BASE, /* prussIntcRegBase */ 114 CSL_PRU_ICSSG2_PR1_ICSS_INTC_INTC_SLV_BASE, /* prussIntcRegBase */
@@ -115,7 +126,14 @@ PRUICSS_HwAttrs prussInitCfg[3] =
115 CSL_PRU_ICSSG2_PR1_RTU0_PR1_RTU0_IRAM_RAM_BASE, /* prussRtu0IramBase */ 126 CSL_PRU_ICSSG2_PR1_RTU0_PR1_RTU0_IRAM_RAM_BASE, /* prussRtu0IramBase */
116 CSL_PRU_ICSSG2_PR1_RTU1_PR1_RTU1_IRAM_RAM_BASE, /* prussRtu1IramBase */ 127 CSL_PRU_ICSSG2_PR1_RTU1_PR1_RTU1_IRAM_RAM_BASE, /* prussRtu1IramBase */
117 CSL_PRU_ICSSG2_PR1_RTU0_PR1_RTU0_IRAM_BASE, /* prussRtu0CtrlRegBase */ 128 CSL_PRU_ICSSG2_PR1_RTU0_PR1_RTU0_IRAM_BASE, /* prussRtu0CtrlRegBase */
118 CSL_PRU_ICSSG2_PR1_RTU1_PR1_RTU1_IRAM_BASE /* prussRtu1CtrlRegBase */ 129 CSL_PRU_ICSSG2_PR1_RTU1_PR1_RTU1_IRAM_BASE, /* prussRtu1CtrlRegBase */
130 CSL_PRU_ICSSG2_DRAM0_SLV_RAM_SIZE, /* prussPru0DramSize */
131 CSL_PRU_ICSSG2_DRAM1_SLV_RAM_SIZE, /* prussPru1DramSize */
132 CSL_PRU_ICSSG2_PR1_PDSP0_IRAM_SIZE, /* prussPru0IramSize */
133 CSL_PRU_ICSSG2_PR1_PDSP1_IRAM_SIZE, /* prussPru1IramSize */
134 CSL_PRU_ICSSG2_RAM_SLV_RAM_SIZE, /* prussSharedDramSize */
135 CSL_PRU_ICSSG2_PR1_RTU0_PR1_RTU0_IRAM_RAM_SIZE, /* prussRtu0IramSize */
136 CSL_PRU_ICSSG2_PR1_RTU1_PR1_RTU1_IRAM_RAM_SIZE /* prussRtu1IramSize */
119 } 137 }
120}; 138};
121 139
diff --git a/soc/pruicss_v1.h b/soc/pruicss_v1.h
index 0607ec0..3af9932 100644
--- a/soc/pruicss_v1.h
+++ b/soc/pruicss_v1.h
@@ -120,10 +120,6 @@ typedef struct PRUICSS_HWAttrs {
120 120
121 uint32_t prussSharedDramSize; 121 uint32_t prussSharedDramSize;
122 122
123 uint32_t prussRtu0DramSize;
124
125 uint32_t prussRtu1DramSize;
126
127 uint32_t prussRtu0IramSize; 123 uint32_t prussRtu0IramSize;
128 124
129 uint32_t prussRtu1IramSize; 125 uint32_t prussRtu1IramSize;