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author | Tinku Mannan | 2018-03-09 09:29:27 -0600 |
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committer | Tinku Mannan | 2018-03-09 09:29:27 -0600 |
commit | 20f92cb4a3a78814932685604ce0175bb84cb7d2 (patch) | |
tree | c0bb5c9294287369d5707d19b7a172ad40ecbd99 | |
parent | 49716e2cbce87176932016b68728767026311d1c (diff) | |
download | pruss-lld-20f92cb4a3a78814932685604ce0175bb84cb7d2.tar.gz pruss-lld-20f92cb4a3a78814932685604ce0175bb84cb7d2.tar.xz pruss-lld-20f92cb4a3a78814932685604ce0175bb84cb7d2.zip |
iceK2G SORTE: Update to use correct PHY adddreses in ARM example
-rw-r--r-- | example/apps/sorte/src/main.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/example/apps/sorte/src/main.c b/example/apps/sorte/src/main.c index 2479ece..9e7f81b 100644 --- a/example/apps/sorte/src/main.c +++ b/example/apps/sorte/src/main.c | |||
@@ -264,6 +264,19 @@ void prussAppSorteMdioInit(void) | |||
264 | PRUICSS_HwAttrs const *hwAttrs; | 264 | PRUICSS_HwAttrs const *hwAttrs; |
265 | hwAttrs = pruIcss1Handle->hwAttrs; | 265 | hwAttrs = pruIcss1Handle->hwAttrs; |
266 | 266 | ||
267 | #if defined(iceK2G) | ||
268 | /*write MDIO configuration (phy addresses) to shadow area in pruss shared memory */ | ||
269 | HWREG(hwAttrs->prussSharedDramBase+ CSL_MDIO_CONTROL_REG) = (uint32_t) \ | ||
270 | (BOARD_ICSS_EMAC_PORT2_PHY_ADDR | \ | ||
271 | (BOARD_ICSS_EMAC_PORT3_PHY_ADDR<<8) | \ | ||
272 | (0<<16) | \ | ||
273 | (0<<24)); | ||
274 | /*Enable MDIO link interrupts for pru-icss PHY's, clear any pending interrupt */ | ||
275 | UART_printf("PHY2: %d, PHY3: %d\n", BOARD_ICSS_EMAC_PORT2_PHY_ADDR, BOARD_ICSS_EMAC_PORT3_PHY_ADDR); | ||
276 | HWREG(hwAttrs->prussMiiMdioRegBase + CSL_ICSSMIIMDIO_USERPHYSEL0) = 0x40 | BOARD_ICSS_EMAC_PORT2_PHY_ADDR; | ||
277 | HWREG(hwAttrs->prussMiiMdioRegBase + CSL_ICSSMIIMDIO_USERPHYSEL1) = 0x40 | BOARD_ICSS_EMAC_PORT3_PHY_ADDR; | ||
278 | HWREG(hwAttrs->prussMiiMdioRegBase + CSL_ICSSMIIMDIO_USERINTMASKED) = (1<<BOARD_ICSS_EMAC_PORT2_PHY_ADDR) | (1<<BOARD_ICSS_EMAC_PORT3_PHY_ADDR); | ||
279 | #else | ||
267 | /*write MDIO configuration (phy addresses) to shadow area in pruss shared memory */ | 280 | /*write MDIO configuration (phy addresses) to shadow area in pruss shared memory */ |
268 | HWREG(hwAttrs->prussSharedDramBase+ CSL_MDIO_CONTROL_REG) = (uint32_t) \ | 281 | HWREG(hwAttrs->prussSharedDramBase+ CSL_MDIO_CONTROL_REG) = (uint32_t) \ |
269 | (BOARD_ICSS_EMAC_PORT0_PHY_ADDR | \ | 282 | (BOARD_ICSS_EMAC_PORT0_PHY_ADDR | \ |
@@ -271,9 +284,11 @@ void prussAppSorteMdioInit(void) | |||
271 | (0<<16) | \ | 284 | (0<<16) | \ |
272 | (0<<24)); | 285 | (0<<24)); |
273 | /*Enable MDIO link interrupts for pru-icss PHY's, clear any pending interrupt */ | 286 | /*Enable MDIO link interrupts for pru-icss PHY's, clear any pending interrupt */ |
287 | UART_printf("PHY0: %d, PHY1: %d\n", BOARD_ICSS_EMAC_PORT0_PHY_ADDR, BOARD_ICSS_EMAC_PORT1_PHY_ADDR); | ||
274 | HWREG(hwAttrs->prussMiiMdioRegBase + CSL_ICSSMIIMDIO_USERPHYSEL0) = 0x40 | BOARD_ICSS_EMAC_PORT0_PHY_ADDR; | 288 | HWREG(hwAttrs->prussMiiMdioRegBase + CSL_ICSSMIIMDIO_USERPHYSEL0) = 0x40 | BOARD_ICSS_EMAC_PORT0_PHY_ADDR; |
275 | HWREG(hwAttrs->prussMiiMdioRegBase + CSL_ICSSMIIMDIO_USERPHYSEL1) = 0x40 | BOARD_ICSS_EMAC_PORT1_PHY_ADDR; | 289 | HWREG(hwAttrs->prussMiiMdioRegBase + CSL_ICSSMIIMDIO_USERPHYSEL1) = 0x40 | BOARD_ICSS_EMAC_PORT1_PHY_ADDR; |
276 | HWREG(hwAttrs->prussMiiMdioRegBase + CSL_ICSSMIIMDIO_USERINTMASKED) = (1<<BOARD_ICSS_EMAC_PORT0_PHY_ADDR) | (1<<BOARD_ICSS_EMAC_PORT1_PHY_ADDR); | 290 | HWREG(hwAttrs->prussMiiMdioRegBase + CSL_ICSSMIIMDIO_USERINTMASKED) = (1<<BOARD_ICSS_EMAC_PORT0_PHY_ADDR) | (1<<BOARD_ICSS_EMAC_PORT1_PHY_ADDR); |
291 | #endif | ||
277 | } | 292 | } |
278 | 293 | ||
279 | /** | 294 | /** |