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authorFrank Livingston2019-05-17 18:24:49 -0500
committerFrank Livingston2019-05-17 18:24:49 -0500
commit397d24e3defab49b79acada8fae0ff493a2546ef (patch)
treecad9dd24e134b4230a3e6548948815949b1b48ee
parentf1dcd52451ee2c208be5272e4d691a74f9d33219 (diff)
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PRSDK-5738:Cosmetic updates
Signed-off-by: Frank Livingston <frank-livingston@ti.com>
-rw-r--r--example/apps/icssg_pwm/firmware/src/iepPwm.c17
-rw-r--r--example/apps/icssg_pwm/firmware/src/iepPwmFwRegs.c40
2 files changed, 21 insertions, 36 deletions
diff --git a/example/apps/icssg_pwm/firmware/src/iepPwm.c b/example/apps/icssg_pwm/firmware/src/iepPwm.c
index eaa3069..233ef65 100644
--- a/example/apps/icssg_pwm/firmware/src/iepPwm.c
+++ b/example/apps/icssg_pwm/firmware/src/iepPwm.c
@@ -675,9 +675,6 @@ Int32 initIepPwm(
675 /* Clear reconfiguration flags whether set or not */ 675 /* Clear reconfiguration flags whether set or not */
676 pIepPwmFwRegs->IEP_PWM_RECFG = 0; 676 pIepPwmFwRegs->IEP_PWM_RECFG = 0;
677 677
678 /* Set init flag to enable execution of LHS Reconfiguration for Initialization */
679 //pIcssgIepPwmObj->iepPwmLhsInitFlag = TRUE;
680
681 /* Enable IEP Counter */ 678 /* Enable IEP Counter */
682 pIcssgIepPwmObj->pIepHwRegs->GLOBAL_CFG_REG |= 0x1; 679 pIcssgIepPwmObj->pIepHwRegs->GLOBAL_CFG_REG |= 0x1;
683 } 680 }
@@ -729,7 +726,6 @@ void initIepPwmSm(
729 IcssgIepPwmObj *pIcssgIepPwmObj 726 IcssgIepPwmObj *pIcssgIepPwmObj
730) 727)
731{ 728{
732 //pIcssgIepPwmObj->iepPwmState = IEP_SM_STATE_LHS;
733 pIcssgIepPwmObj->iepPwmState = IEP_SM_STATE_INIT; 729 pIcssgIepPwmObj->iepPwmState = IEP_SM_STATE_INIT;
734} 730}
735 731
@@ -801,7 +797,7 @@ Int32 execIepPwmSm(
801 /* Update state to Right-Hand Side */ 797 /* Update state to Right-Hand Side */
802 pIcssgIepPwmObj->iepPwmState = IEP_SM_STATE_RHS; 798 pIcssgIepPwmObj->iepPwmState = IEP_SM_STATE_RHS;
803 } 799 }
804 else { // IEP_STS_RECFG_PRD_COUNT 800 else { /* IEP_STS_RECFG_PRD_COUNT */
805 /* Update State to Init */ 801 /* Update State to Init */
806 pIcssgIepPwmObj->iepPwmState = IEP_SM_STATE_INIT; 802 pIcssgIepPwmObj->iepPwmState = IEP_SM_STATE_INIT;
807 } 803 }
@@ -840,7 +836,6 @@ static void iepPwmLhs(
840 IcssgIepPwmObj *pIcssgIepPwmObj 836 IcssgIepPwmObj *pIcssgIepPwmObj
841) 837)
842{ 838{
843 //CSL_icss_g_pr1_iep1_slvRegs *pIepHwRegs = pIcssgIepPwmObj->pIepHwRegs;
844 Uint32 *pIepPwmDcCount; 839 Uint32 *pIepPwmDcCount;
845 Uint16 *pIepPwmDbCount; 840 Uint16 *pIepPwmDbCount;
846 volatile uint32_t *pShadowReg; 841 volatile uint32_t *pShadowReg;
@@ -1472,8 +1467,8 @@ static Int32 calcAndLatchIepPwmDcLhsRhsCount(
1472 if ((pIcssgIepPwmObj->iepPwmMode >> dPwmIdx) & 0x1) { 1467 if ((pIcssgIepPwmObj->iepPwmMode >> dPwmIdx) & 0x1) {
1473 /* Differential PWM */ 1468 /* Differential PWM */
1474 1469
1475 // Check if reconfiguration bit set. 1470 /* Check if reconfiguration bit set.
1476 // For Differential PWM, only "even" reconfiguration bits checked for each PWM pair. 1471 For Differential PWM, only "even" reconfiguration bits checked for each PWM pair. */
1477 if ((recfgDcCount >> pwmIdx) & 0x1) { 1472 if ((recfgDcCount >> pwmIdx) & 0x1) {
1478 dcCount = *pIepPwmDcCount; 1473 dcCount = *pIepPwmDcCount;
1479 if ((dcCount > 0) && (dcCount < pwmPeriodCount)) { 1474 if ((dcCount > 0) && (dcCount < pwmPeriodCount)) {
@@ -2264,7 +2259,7 @@ static Int32 getActionTableRowDiff(
2264 } 2259 }
2265 else if (iepPwmDcCountOld == 0) { /* old DC count is 0 */ 2260 else if (iepPwmDcCountOld == 0) { /* old DC count is 0 */
2266 if ((iepPwmDcCountNew > 0) && (iepPwmDcCountNew < pwmPeriodCount)) { 2261 if ((iepPwmDcCountNew > 0) && (iepPwmDcCountNew < pwmPeriodCount)) {
2267 //=* new DC count !=0, !=100 */ 2262 /* new DC count !=0, !=100 */
2268 *pRowIdx = AT_Row05_DcOld0_DcNewY; 2263 *pRowIdx = AT_Row05_DcOld0_DcNewY;
2269 } 2264 }
2270 else if (iepPwmDcCountNew == 0) { 2265 else if (iepPwmDcCountNew == 0) {
@@ -2584,14 +2579,14 @@ static void execRhsActionStash(
2584 case RHS_ACTION_Set_CmpSr_GtPrd_And_DisableSrUpdate: 2579 case RHS_ACTION_Set_CmpSr_GtPrd_And_DisableSrUpdate:
2585 dcLhsY = pIepPwmDcCountRhs[pwmIdx]; 2580 dcLhsY = pIepPwmDcCountRhs[pwmIdx];
2586 2581
2587 // Write same LHS value to both CMP Shadow Registers in differential pair 2582 /* Write same LHS value to both CMP Shadow Registers in differential pair */
2588 pCmpSr = pIepCmpSrAddr[pwmIdx]; 2583 pCmpSr = pIepCmpSrAddr[pwmIdx];
2589 *pCmpSr = iepPwmPeriodCount; 2584 *pCmpSr = iepPwmPeriodCount;
2590 pwmIdx++; 2585 pwmIdx++;
2591 pCmpSr = pIepCmpSrAddr[pwmIdx]; 2586 pCmpSr = pIepCmpSrAddr[pwmIdx];
2592 *pCmpSr = iepPwmPeriodCount; 2587 *pCmpSr = iepPwmPeriodCount;
2593 2588
2594 // Enable CMP SR update 2589 /* Enable CMP SR update */
2595 *pIepPwmDiffUpdEn &= ~(1<<dPwmIdx); /* Disable CMP SR update */ 2590 *pIepPwmDiffUpdEn &= ~(1<<dPwmIdx); /* Disable CMP SR update */
2596 break; 2591 break;
2597 2592
diff --git a/example/apps/icssg_pwm/firmware/src/iepPwmFwRegs.c b/example/apps/icssg_pwm/firmware/src/iepPwmFwRegs.c
index 41bc4ad..65f78b7 100644
--- a/example/apps/icssg_pwm/firmware/src/iepPwmFwRegs.c
+++ b/example/apps/icssg_pwm/firmware/src/iepPwmFwRegs.c
@@ -44,16 +44,6 @@
44#define DEF_DC_COUNT ( 0x0007A120 ) /* Default DC Count, 50% Duty Cycle PWM freq 1 kHz */ 44#define DEF_DC_COUNT ( 0x0007A120 ) /* Default DC Count, 50% Duty Cycle PWM freq 1 kHz */
45#define DEF_DB_COUNT ( 0x0A00 ) /* Default DB Count, 2.56 usec. */ 45#define DEF_DB_COUNT ( 0x0A00 ) /* Default DB Count, 2.56 usec. */
46 46
47// FL: Debug
48//#define DEF_PRD_COUNT ( 0x000F4240 ) /* Default Period Count, PWM freq 1 kHz */
49//#define DEF_DC_COUNT ( 0x00000000 ) /* Default DC Count, 0% Duty Cycle PWM freq 1 kHz */
50//#define DEF_DC_COUNT ( 0x00000F42 ) /* Default DC Count, 0.390625% Duty Cycle PWM freq 1 kHz */
51#define DBG_DEF_DC_COUNT1 ( 0x0003D090 ) /* Default DC Count, 25% Duty Cycle PWM freq 1 kHz */
52#define DBG_DEF_DC_COUNT2 ( 0x0007A120 ) /* Default DC Count, 50% Duty Cycle PWM freq 1 kHz */
53#define DBG_DEF_DC_COUNT3 ( 0x000B71B0 ) /* Default DC Count, 75% Duty Cycle PWM freq 1 kHz */
54//#define DEF_DC_COUNT ( 0x000F32FE ) /* Default DC Count, 99.609375% Duty Cycle PWM freq 1 kHz */
55//#define DEF_DC_COUNT ( 0x000F4240 ) /* Default DC Count, 100% Duty Cycle PWM freq 1 kHz */
56
57/* FW Info register defaults */ 47/* FW Info register defaults */
58#pragma RETAIN(gIepPwmInfoFwRegs) 48#pragma RETAIN(gIepPwmInfoFwRegs)
59#pragma DATA_SECTION(gIepPwmInfoFwRegs, ".initDataFwRegs") 49#pragma DATA_SECTION(gIepPwmInfoFwRegs, ".initDataFwRegs")
@@ -84,9 +74,9 @@ const IepPwmFwRegs gIep0PwmFwRegs =
84 DEF_PWM_MODE, /* IEP0_PWM_MODE */ 74 DEF_PWM_MODE, /* IEP0_PWM_MODE */
85 DEF_PWM_EN, /* IEP0_PWM_EN */ 75 DEF_PWM_EN, /* IEP0_PWM_EN */
86 DEF_PRD_COUNT, /* IEP0_PWM_PRD_COUNT */ 76 DEF_PRD_COUNT, /* IEP0_PWM_PRD_COUNT */
87 DBG_DEF_DC_COUNT1, /* IEP0_PWM0_DC_COUNT */ 77 DEF_DC_COUNT, /* IEP0_PWM0_DC_COUNT */
88 DBG_DEF_DC_COUNT2, /* IEP0_PWM1_DC_COUNT */ 78 DEF_DC_COUNT, /* IEP0_PWM1_DC_COUNT */
89 DBG_DEF_DC_COUNT3, /* IEP0_PWM2_DC_COUNT */ 79 DEF_DC_COUNT, /* IEP0_PWM2_DC_COUNT */
90 DEF_DC_COUNT, /* IEP0_PWM3_DC_COUNT */ 80 DEF_DC_COUNT, /* IEP0_PWM3_DC_COUNT */
91 DEF_DC_COUNT, /* IEP0_PWM4_DC_COUNT */ 81 DEF_DC_COUNT, /* IEP0_PWM4_DC_COUNT */
92 DEF_DC_COUNT, /* IEP0_PWM5_DC_COUNT */ 82 DEF_DC_COUNT, /* IEP0_PWM5_DC_COUNT */
@@ -113,18 +103,18 @@ const IepPwmFwRegs gIep1PwmFwRegs =
113 DEF_PWM_MODE, /* IEP1_PWM_MODE */ 103 DEF_PWM_MODE, /* IEP1_PWM_MODE */
114 DEF_PWM_EN, /* IEP1_PWM_EN */ 104 DEF_PWM_EN, /* IEP1_PWM_EN */
115 DEF_PRD_COUNT, /* IEP1_PWM_PRD_COUNT */ 105 DEF_PRD_COUNT, /* IEP1_PWM_PRD_COUNT */
116 DBG_DEF_DC_COUNT1, /* IEP1_PWM0_DC_COUNT */ 106 DEF_DC_COUNT, /* IEP1_PWM0_DC_COUNT */
117 DBG_DEF_DC_COUNT2, /* IEP1_PWM1_DC_COUNT */ 107 DEF_DC_COUNT, /* IEP1_PWM1_DC_COUNT */
118 DBG_DEF_DC_COUNT3, /* IEP1_PWM2_DC_COUNT */ 108 DEF_DC_COUNT, /* IEP1_PWM2_DC_COUNT */
119 DBG_DEF_DC_COUNT1, /* IEP1_PWM3_DC_COUNT */ 109 DEF_DC_COUNT, /* IEP1_PWM3_DC_COUNT */
120 DBG_DEF_DC_COUNT2, /* IEP1_PWM4_DC_COUNT */ 110 DEF_DC_COUNT, /* IEP1_PWM4_DC_COUNT */
121 DBG_DEF_DC_COUNT3, /* IEP1_PWM5_DC_COUNT */ 111 DEF_DC_COUNT, /* IEP1_PWM5_DC_COUNT */
122 DBG_DEF_DC_COUNT1, /* IEP1_PWM6_DC_COUNT */ 112 DEF_DC_COUNT, /* IEP1_PWM6_DC_COUNT */
123 DBG_DEF_DC_COUNT2, /* IEP1_PWM7_DC_COUNT */ 113 DEF_DC_COUNT, /* IEP1_PWM7_DC_COUNT */
124 DBG_DEF_DC_COUNT3, /* IEP1_PWM8_DC_COUNT */ 114 DEF_DC_COUNT, /* IEP1_PWM8_DC_COUNT */
125 DBG_DEF_DC_COUNT1, /* IEP1_PWM9_DC_COUNT */ 115 DEF_DC_COUNT, /* IEP1_PWM9_DC_COUNT */
126 DBG_DEF_DC_COUNT2, /* IEP1_PWM10_DC_COUNT */ 116 DEF_DC_COUNT, /* IEP1_PWM10_DC_COUNT */
127 DBG_DEF_DC_COUNT3, /* IEP1_PWM11_DC_COUNT */ 117 DEF_DC_COUNT, /* IEP1_PWM11_DC_COUNT */
128 DEF_DB_COUNT, /* IEP1_PWM0_1_DEADBAND */ 118 DEF_DB_COUNT, /* IEP1_PWM0_1_DEADBAND */
129 DEF_DB_COUNT, /* IEP1_PWM2_3_DEADBAND */ 119 DEF_DB_COUNT, /* IEP1_PWM2_3_DEADBAND */
130 DEF_DB_COUNT, /* IEP1_PWM4_5_DEADBAND */ 120 DEF_DB_COUNT, /* IEP1_PWM4_5_DEADBAND */