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authorFrank Livingston2019-05-20 15:53:17 -0500
committerFrank Livingston2019-05-20 15:53:17 -0500
commit5aeb7663b2986719405e11a38fda5dab126e3cc0 (patch)
tree72066affc8e687a9ff24067ccbcfbad63efc2b6f
parentafcbb2869a71c959e81877917e1ce4f7b59ca6f0 (diff)
downloadpruss-lld-5aeb7663b2986719405e11a38fda5dab126e3cc0.tar.gz
pruss-lld-5aeb7663b2986719405e11a38fda5dab126e3cc0.tar.xz
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PRSDK-5738:Add Host I/F API header file.
Signed-off-by: Frank Livingston <frank-livingston@ti.com>
-rw-r--r--example/apps/icssg_pwm/firmware/src/icssg_iep_pwm.h270
-rw-r--r--example/apps/icssg_pwm/firmware/src/iepPwm.c23
-rw-r--r--example/apps/icssg_pwm/firmware/src/iepPwmFwRegs.h20
3 files changed, 282 insertions, 31 deletions
diff --git a/example/apps/icssg_pwm/firmware/src/icssg_iep_pwm.h b/example/apps/icssg_pwm/firmware/src/icssg_iep_pwm.h
new file mode 100644
index 0000000..d9bb294
--- /dev/null
+++ b/example/apps/icssg_pwm/firmware/src/icssg_iep_pwm.h
@@ -0,0 +1,270 @@
1/*
2 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the
15 * distribution.
16 *
17 * * Neither the name of Texas Instruments Incorporated nor the names of
18 * its contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34#ifndef _ICSSG_IEP_PWM_H_
35#define _ICSSG_IEP_PWM_H_
36
37/*
38 * Firmware global registers
39 */
40
41/* Firmware Information Registers */
42#define ICSSG_IEPPWM_FW_MAGIC_NUMBER_ADDR ( 0x0000 )
43#define ICSSG_IEPPWM_FW_TYPE_ADDR ( 0x0004 )
44#define ICSSG_IEPPWM_FW_VERSION_ADDR ( 0x0008 )
45#define ICSSG_IEPPWM_FW_FEATURE_ADDR ( 0x000C )
46#define ICSSG_IEPPWM_FW_EXT_FEATURE_ADDR ( 0x0010 )
47
48/* PWM Control/Status Registers */
49#define ICSSG_IEPPWM_PWM_CTRL_ADDR ( 0x0014 )
50#define ICSSG_IEPPWM_PWM_STAT_ADDR ( 0x0018 )
51
52/*
53 * Firmware global register bit fields
54 */
55/* Firmware Magic Number */
56#define FW_MAGIC_NUM_BYTE0_MASK ( 0xF )
57#define FW_MAGIC_NUM_BYTE1_MASK ( 0xF )
58#define FW_MAGIC_NUM_BYTE2_MASK ( 0xF )
59#define FW_MAGIC_NUM_BYTE3_MASK ( 0xF )
60#define FW_MAGIC_NUM_MN_BYTE0_SHIFT ( 0 )
61#define FW_MAGIC_NUM_MN_BYTE0_MASK ( FW_MAGIC_NUM_BYTE0_MASK << FW_MAGIC_NUM_MN_BYTE0_SHIFT )
62#define FW_MAGIC_NUM_MN_BYTE1_SHIFT ( 8 )
63#define FW_MAGIC_NUM_MN_BYTE1_MASK ( FW_MAGIC_NUM_BYTE1_MASK << FW_MAGIC_NUM_MN_BYTE1_SHIFT )
64#define FW_MAGIC_NUM_MN_BYTE2_SHIFT ( 16 )
65#define FW_MAGIC_NUM_MN_BYTE2_MASK ( FW_MAGIC_NUM_BYTE2_MASK << FW_MAGIC_NUM_MN_BYTE2_SHIFT )
66#define FW_MAGIC_NUM_MN_BYTE3_SHIFT ( 24 )
67#define FW_MAGIC_NUM_MN_BYTE3_MASK ( FW_MAGIC_NUM_BYTE3_MASK << FW_MAGIC_NUM_MN_BYTE3_SHIFT )
68
69/* Firmware Type */
70#define FW_PROTOCOL_TYPE_VERSION_MASK ( 0xF )
71#define FW_PROTOCOL_TYPE_MASK ( 0xFF )
72#define FW_ICSS_VERSION_MASK ( 0xF )
73#define FW_TYPE_FW_PROTOCOL_TYPE_VERSION_SHIFT ( 0 )
74#define FW_TYPE_FW_PROTOCOL_TYPE_VERSION_MASK ( FW_PROTOCOL_TYPE_VERSION_MASK << FW_TYPE_FW_PROTOCOL_TYPE_VERSION_SHIFT )
75#define FW_TYPE_FW_PROTOCOL_TYPE_SHIFT ( 8 )
76#define FW_TYPE_FW_PROTOCOL_TYPE_MASK ( FW_PROTOCOL_TYPE_MASK << FW_TYPE_FW_PROTOCOL_TYPE_SHIFT )
77#define FW_TYPE_FW_ICSS_VERSION_SHIFT ( 24 )
78#define FW_TYPE_FW_ICSS_VERSION_MASK ( FW_ICSS_VERSION_MASK << FW_TYPE_FW_ICSS_VERSION_SHIFT )
79
80/* Firmware Version */
81#define FW_VER_BUILD_MASK ( 0xF )
82#define FW_VER_MINOR_MASK ( 0xFF )
83#define FW_VER_MAJOR_MASK ( 0x7F )
84#define FW_REL_OR_INT_VER_MASK ( 0x1 )
85#define FW_VERSION_FW_VER_BUILD_SHIFT ( 0 )
86#define FW_VERSION_FW_VER_BUILD_MASK ( FW_VER_BUILD_MASK << FW_VERSION_FW_VER_BUILD_SHIFT )
87#define FW_VERSION_FW_VER_MINOR_SHIFT ( 8 )
88#define FW_VERSION_FW_VER_MINOR_MASK ( FW_VER_MINOR_MASK << FW_VERSION_FW_VER_MINOR_SHIFT )
89#define FW_VERSION_FW_VER_MAJOR_SHIFT ( 24 )
90#define FW_VERSION_FW_VER_MAJOR_MASK ( FW_VER_MAJOR_MASK << FW_VERSION_FW_VER_MAJOR_SHIFT )
91#define FW_VERSION_FW_REL_OR_INT_VER_SHIFT ( 31 )
92#define FW_VERSION_FW_REL_OR_INT_VER_MASK ( FW_REL_OR_INT_VER_MASK << FW_VERSION_FW_REL_OR_INT_VER_SHIFT )
93
94/* Firmware Feature */
95#define FW_NUM_PWMS_MASK ( 0x1F )
96#define FW_FEATURE_FW_NUM_PWMS_SHIFT ( 0 )
97#define FW_FEATURE_FW_NUM_PWMS_MASK ( FW_NUM_PWMS_MASK << FW_FEATURE_FW_NUM_PWMS_SHIFT )
98
99/* PWM_CTRL */
100#define IEP_PWM_GBL_EN_MASK ( 0x1 )
101#define PWM_CTRL_IEP0_PWM_GBL_EN_SHIFT ( 0 )
102#define PWM_CTRL_IEP0_PWM_GBL_EN_MASK ( IEP_PWM_GBL_EN_MASK << PWM_CTRL_IEP0_PWM_GBL_EN_SHIFT )
103#define PWM_CTRL_IEP1_PWM_GBL_EN_SHIFT ( 1 )
104#define PWM_CTRL_IEP1_PWM_GBL_EN_MASK ( IEP_PWM_GBL_EN_MASK << PWM_CTRL_IEP1_PWM_GBL_EN_SHIFT )
105
106/* PWM_STAT */
107#define IEP_PWM_GBL_EN_MASK ( 0x1 )
108#define FW_INIT_MASK ( 0x1 )
109#define PWM_STAT_IEP0_PWM_GBL_EN_SHIFT ( 0 )
110#define PWM_STAT_IEP0_PWM_GBL_EN_MASK ( IEP_PWM_GBL_EN_MASK << PWM_STAT_IEP0_PWM_GBL_EN_SHIFT )
111#define PWM_STAT_IEP1_PWM_GBL_EN_SHIFT ( 1 )
112#define PWM_STAT_IEP1_PWM_GBL_EN_MASK ( IEP_PWM_GBL_EN_MASK << PWM_STAT_IEP1_PWM_GBL_EN_SHIFT )
113#define PWM_STAT_FW_INIT_SHIFT ( 2 )
114#define PWM_STAT_FW_INIT_MASK ( FW_INIT_MASK << PWM_STAT_FW_INIT_SHIFT )
115
116
117/*
118 * Firmware IEP PWM instance registers
119 */
120
121/* IEP PWM register offsets */
122#define IEP_PWM_RECFG_OFFSET ( 0 )
123#define IEP_PWM_MODE_OFFSET ( 4 )
124#define IEP_PWM_EN_OFFSET ( 8 )
125#define IEP_PWM_PRD_COUNT_OFFSET ( 12 )
126#define IEP_PWM0_DC_COUNT_OFFSET ( 16 )
127#define IEP_PWM1_DC_COUNT_OFFSET ( 20 )
128#define IEP_PWM2_DC_COUNT_OFFSET ( 24 )
129#define IEP_PWM3_DC_COUNT_OFFSET ( 28 )
130#define IEP_PWM4_DC_COUNT_OFFSET ( 32 )
131#define IEP_PWM5_DC_COUNT_OFFSET ( 36 )
132#define IEP_PWM6_DC_COUNT_OFFSET ( 40 )
133#define IEP_PWM7_DC_COUNT_OFFSET ( 44 )
134#define IEP_PWM8_DC_COUNT_OFFSET ( 48 )
135#define IEP_PWM9_DC_COUNT_OFFSET ( 52 )
136#define IEP_PWM10_DC_COUNT_OFFSET ( 56 )
137#define IEP_PWM11_DC_COUNT_OFFSET ( 60 )
138#define IEP_PWM0_1_DB_COUNT_OFFSET ( 62 )
139#define IEP_PWM2_3_DB_COUNT_OFFSET ( 64 )
140#define IEP_PWM4_5_DB_COUNT_OFFSET ( 68 )
141#define IEP_PWM6_7_DB_COUNT_OFFSET ( 70 )
142#define IEP_PWM8_9_DB_COUNT_OFFSET ( 72 )
143#define IEP_PWM10_11_DB_COUNT_OFFSET ( 74 )
144
145/* IEP0 PWM register addresses */
146#define ICSSG_PWM_IEP0_PWM_BASE_ADDR ( 0x001C )
147#define ICSSG_PWM_IEP0_PWM_RECFG ( ICSSG_PWM_IEP0_PWM_BASE_ADDR + IEP_PWM_RECFG_OFFSET )
148#define ICSSG_PWM_IEP0_PWM_MODE ( ICSSG_PWM_IEP0_PWM_BASE_ADDR + IEP_PWM_MODE_OFFSET )
149#define ICSSG_PWM_IEP0_PWM_EN ( ICSSG_PWM_IEP0_PWM_BASE_ADDR + IEP_PWM_EN_OFFSET )
150#define ICSSG_PWM_IEP0_PWM_PRD_COUNT ( ICSSG_PWM_IEP0_PWM_BASE_ADDR + IEP_PWM_PRD_COUNT_OFFSET )
151#define ICSSG_PWM_IEP0_PWM0_DC_COUNT ( ICSSG_PWM_IEP0_PWM_BASE_ADDR + IEP_PWM0_DC_COUNT_OFFSET )
152#define ICSSG_PWM_IEP0_PWM1_DC_COUNT ( ICSSG_PWM_IEP0_PWM_BASE_ADDR + IEP_PWM1_DC_COUNT_OFFSET )
153#define ICSSG_PWM_IEP0_PWM2_DC_COUNT ( ICSSG_PWM_IEP0_PWM_BASE_ADDR + IEP_PWM2_DC_COUNT_OFFSET )
154#define ICSSG_PWM_IEP0_PWM3_DC_COUNT ( ICSSG_PWM_IEP0_PWM_BASE_ADDR + IEP_PWM3_DC_COUNT_OFFSET )
155#define ICSSG_PWM_IEP0_PWM4_DC_COUNT ( ICSSG_PWM_IEP0_PWM_BASE_ADDR + IEP_PWM4_DC_COUNT_OFFSET )
156#define ICSSG_PWM_IEP0_PWM5_DC_COUNT ( ICSSG_PWM_IEP0_PWM_BASE_ADDR + IEP_PWM5_DC_COUNT_OFFSET )
157#define ICSSG_PWM_IEP0_PWM6_DC_COUNT ( ICSSG_PWM_IEP0_PWM_BASE_ADDR + IEP_PWM6_DC_COUNT_OFFSET )
158#define ICSSG_PWM_IEP0_PWM7_DC_COUNT ( ICSSG_PWM_IEP0_PWM_BASE_ADDR + IEP_PWM7_DC_COUNT_OFFSET )
159#define ICSSG_PWM_IEP0_PWM8_DC_COUNT ( ICSSG_PWM_IEP0_PWM_BASE_ADDR + IEP_PWM8_DC_COUNT_OFFSET )
160#define ICSSG_PWM_IEP0_PWM9_DC_COUNT ( ICSSG_PWM_IEP0_PWM_BASE_ADDR + IEP_PWM9_DC_COUNT_OFFSET )
161#define ICSSG_PWM_IEP0_PWM10_DC_COUNT ( ICSSG_PWM_IEP0_PWM_BASE_ADDR + IEP_PWM10_DC_COUNT_OFFSET )
162#define ICSSG_PWM_IEP0_PWM11_DC_COUNT ( ICSSG_PWM_IEP0_PWM_BASE_ADDR + IEP_PWM11_DC_COUNT_OFFSET )
163#define ICSSG_PWM_IEP0_PWM0_1_DB_COUNT ( ICSSG_PWM_IEP0_PWM_BASE_ADDR + IEP_PWM0_1_DB_COUNT_OFFSET )
164#define ICSSG_PWM_IEP0_PWM2_3_DB_COUNT ( ICSSG_PWM_IEP0_PWM_BASE_ADDR + IEP_PWM2_3_DB_COUNT_OFFSET )
165#define ICSSG_PWM_IEP0_PWM4_5_DB_COUNT ( ICSSG_PWM_IEP0_PWM_BASE_ADDR + IEP_PWM4_5_DB_COUNT_OFFSET )
166#define ICSSG_PWM_IEP0_PWM6_7_DB_COUNT ( ICSSG_PWM_IEP0_PWM_BASE_ADDR + IEP_PWM6_7_DB_COUNT_OFFSET )
167#define ICSSG_PWM_IEP0_PWM8_9_DB_COUNT ( ICSSG_PWM_IEP0_PWM_BASE_ADDR + IEP_PWM8_9_DB_COUNT_OFFSET )
168#define ICSSG_PWM_IEP0_PWM10_11_DB_COUNT ( ICSSG_PWM_IEP0_PWM_BASE_ADDR + IEP_PWM10_11_DB_COUNT_OFFSET )
169
170/* IEP1 PWM register addresses */
171#define ICSSG_PWM_IEP1_PWM_BASE_ADDR ( 0x0068 )
172#define ICSSG_PWM_IEP1_PWM_RECFG ( ICSSG_PWM_IEP1_PWM_BASE_ADDR + IEP_PWM_RECFG_OFFSET )
173#define ICSSG_PWM_IEP1_PWM_MODE ( ICSSG_PWM_IEP1_PWM_BASE_ADDR + IEP_PWM_MODE_OFFSET )
174#define ICSSG_PWM_IEP1_PWM_EN ( ICSSG_PWM_IEP1_PWM_BASE_ADDR + IEP_PWM_EN_OFFSET )
175#define ICSSG_PWM_IEP1_PWM_PRD_COUNT ( ICSSG_PWM_IEP1_PWM_BASE_ADDR + IEP_PWM_PRD_COUNT_OFFSET )
176#define ICSSG_PWM_IEP1_PWM0_DC_COUNT ( ICSSG_PWM_IEP1_PWM_BASE_ADDR + IEP_PWM0_DC_COUNT_OFFSET )
177#define ICSSG_PWM_IEP1_PWM1_DC_COUNT ( ICSSG_PWM_IEP1_PWM_BASE_ADDR + IEP_PWM1_DC_COUNT_OFFSET )
178#define ICSSG_PWM_IEP1_PWM2_DC_COUNT ( ICSSG_PWM_IEP1_PWM_BASE_ADDR + IEP_PWM2_DC_COUNT_OFFSET )
179#define ICSSG_PWM_IEP1_PWM3_DC_COUNT ( ICSSG_PWM_IEP1_PWM_BASE_ADDR + IEP_PWM3_DC_COUNT_OFFSET )
180#define ICSSG_PWM_IEP1_PWM4_DC_COUNT ( ICSSG_PWM_IEP1_PWM_BASE_ADDR + IEP_PWM4_DC_COUNT_OFFSET )
181#define ICSSG_PWM_IEP1_PWM5_DC_COUNT ( ICSSG_PWM_IEP1_PWM_BASE_ADDR + IEP_PWM5_DC_COUNT_OFFSET )
182#define ICSSG_PWM_IEP1_PWM6_DC_COUNT ( ICSSG_PWM_IEP1_PWM_BASE_ADDR + IEP_PWM6_DC_COUNT_OFFSET )
183#define ICSSG_PWM_IEP1_PWM7_DC_COUNT ( ICSSG_PWM_IEP1_PWM_BASE_ADDR + IEP_PWM7_DC_COUNT_OFFSET )
184#define ICSSG_PWM_IEP1_PWM8_DC_COUNT ( ICSSG_PWM_IEP1_PWM_BASE_ADDR + IEP_PWM8_DC_COUNT_OFFSET )
185#define ICSSG_PWM_IEP1_PWM9_DC_COUNT ( ICSSG_PWM_IEP1_PWM_BASE_ADDR + IEP_PWM9_DC_COUNT_OFFSET )
186#define ICSSG_PWM_IEP1_PWM10_DC_COUNT ( ICSSG_PWM_IEP1_PWM_BASE_ADDR + IEP_PWM10_DC_COUNT_OFFSET )
187#define ICSSG_PWM_IEP1_PWM11_DC_COUNT ( ICSSG_PWM_IEP1_PWM_BASE_ADDR + IEP_PWM11_DC_COUNT_OFFSET )
188#define ICSSG_PWM_IEP1_PWM0_1_DB_COUNT ( ICSSG_PWM_IEP1_PWM_BASE_ADDR + IEP_PWM0_1_DB_COUNT_OFFSET )
189#define ICSSG_PWM_IEP1_PWM2_3_DB_COUNT ( ICSSG_PWM_IEP1_PWM_BASE_ADDR + IEP_PWM2_3_DB_COUNT_OFFSET )
190#define ICSSG_PWM_IEP1_PWM4_5_DB_COUNT ( ICSSG_PWM_IEP1_PWM_BASE_ADDR + IEP_PWM4_5_DB_COUNT_OFFSET )
191#define ICSSG_PWM_IEP1_PWM6_7_DB_COUNT ( ICSSG_PWM_IEP1_PWM_BASE_ADDR + IEP_PWM6_7_DB_COUNT_OFFSET )
192#define ICSSG_PWM_IEP1_PWM8_9_DB_COUNT ( ICSSG_PWM_IEP1_PWM_BASE_ADDR + IEP_PWM8_9_DB_COUNT_OFFSET )
193#define ICSSG_PWM_IEP1_PWM10_11_DB_COUNT ( ICSSG_PWM_IEP1_PWM_BASE_ADDR + IEP_PWM10_11_DB_COUNT_OFFSET )
194
195/*
196 * Firmware IEP PWM instance register bit fields
197 */
198
199/* IEPx_PWM_RECFG */
200#define RECFG_IEP_PWM_EN_MASK ( 0x1 )
201#define RECFG_IEP_PWM_PRD_COUNT_MASK ( 0x1 )
202#define RECFG_IEP_PWM_DC_COUNT_MASK ( 0xFFF )
203#define RECFG_IEP_PWM_DB_COUNT_MASK ( 0x3F )
204#define IEP_PWM_RECFG_RECFG_IEP_PWM_EN_SHIFT ( 0 )
205#define IEP_PWM_RECFG_RECFG_IEP_PWM_EN_MASK ( RECFG_IEP_PWM_EN_MASK << IEP_PWM_RECFG_RECFG_IEP_PWM_EN_SHIFT )
206#define IEP_PWM_RECFG_RECFG_IEP_PWM_PRD_COUNT_SHIFT ( 1 )
207#define IEP_PWM_RECFG_RECFG_IEP_PWM_PRD_COUNT_MASK ( RECFG_IEP_PWM_PRD_COUNT_MASK << IEP_PWM_RECFG_RECFG_IEP_PWM_PRD_COUNT_SHIFT )
208#define IEP_PWM_RECFG_RECFG_IEP_PWM_DC_COUNT_SHIFT ( 2 )
209#define IEP_PWM_RECFG_RECFG_IEP_PWM_DC_COUNT_MASK ( RECFG_IEP_PWM_DC_COUNT_MASK << IEP_PWM_RECFG_RECFG_IEP_PWM_DC_COUNT_SHIFT )
210#define IEP_PWM_RECFG_RECFG_IEP_PWM_DB_COUNT_SHIFT ( 14 )
211#define IEP_PWM_RECFG_RECFG_IEP_PWM_DB_COUNT_MASK ( RECFG_IEP_PWM_DB_COUNT_MASK << IEP_PWM_RECFG_RECFG_IEP_PWM_DB_COUNT_SHIFT )
212
213/* IEPx_PWM_MODE */
214#define PWM_MODE_MASK ( 0x1 )
215#define IEP_PWM_MODE_PWM0_1_MODE_SHIFT ( 0 )
216#define IEP_PWM_MODE_PWM0_1_MODE_MASK ( PWM_MODE_MASK << IEP_PWM_MODE_PWM0_1_MODE_SHIFT )
217#define IEP_PWM_MODE_PWM2_3_MODE_SHIFT ( 1 )
218#define IEP_PWM_MODE_PWM2_3_MODE_MASK ( PWM_MODE_MASK << IEP_PWM_MODE_PWM2_3_MODE_SHIFT )
219#define IEP_PWM_MODE_PWM4_5_MODE_SHIFT ( 2 )
220#define IEP_PWM_MODE_PWM4_5_MODE_MASK ( PWM_MODE_MASK << IEP_PWM_MODE_PWM4_5_MODE_SHIFT )
221#define IEP_PWM_MODE_PWM6_7_MODE_SHIFT ( 3 )
222#define IEP_PWM_MODE_PWM6_7_MODE_MASK ( PWM_MODE_MASK << IEP_PWM_MODE_PWM6_7_MODE_SHIFT )
223#define IEP_PWM_MODE_PWM8_9_MODE_SHIFT ( 4 )
224#define IEP_PWM_MODE_PWM8_9_MODE_MASK ( PWM_MODE_MASK << IEP_PWM_MODE_PWM8_9_MODE_SHIFT )
225#define IEP_PWM_MODE_PWM10_11_MODE_SHIFT ( 5 )
226#define IEP_PWM_MODE_PWM10_11_MODE_MASK ( PWM_MODE_MASK << IEP_PWM_MODE_PWM10_11_MODE_SHIFT )
227
228/* IEPx_PWM_EN */
229#define PWM_EN_MASK ( 0x1 )
230#define IEP_PWM_EN_PWM0_EN_MASK ( PWM_EN_MASK << IEP_PWM_EN_PWM0_EN_SHIFT )
231#define IEP_PWM_EN_PWM1_EN_SHIFT ( 0x1 )
232#define IEP_PWM_EN_PWM1_EN_MASK ( PWM_EN_MASK << IEP_PWM_EN_PWM1_EN_SHIFT )
233#define IEP_PWM_EN_PWM2_EN_SHIFT ( 0x1 )
234#define IEP_PWM_EN_PWM2_EN_MASK ( PWM_EN_MASK << IEP_PWM_EN_PWM2_EN_SHIFT )
235#define IEP_PWM_EN_PWM3_EN_SHIFT ( 0x1 )
236#define IEP_PWM_EN_PWM3_EN_MASK ( PWM_EN_MASK << IEP_PWM_EN_PWM3_EN_SHIFT )
237#define IEP_PWM_EN_PWM4_EN_SHIFT ( 0x1 )
238#define IEP_PWM_EN_PWM4_EN_MASK ( PWM_EN_MASK << IEP_PWM_EN_PWM4_EN_SHIFT )
239#define IEP_PWM_EN_PWM5_EN_SHIFT ( 0x1 )
240#define IEP_PWM_EN_PWM5_EN_MASK ( PWM_EN_MASK << IEP_PWM_EN_PWM5_EN_SHIFT )
241#define IEP_PWM_EN_PWM6_EN_SHIFT ( 0x1 )
242#define IEP_PWM_EN_PWM6_EN_MASK ( PWM_EN_MASK << IEP_PWM_EN_PWM6_EN_SHIFT )
243#define IEP_PWM_EN_PWM7_EN_SHIFT ( 0x1 )
244#define IEP_PWM_EN_PWM7_EN_MASK ( PWM_EN_MASK << IEP_PWM_EN_PWM7_EN_SHIFT )
245#define IEP_PWM_EN_PWM8_EN_SHIFT ( 0x1 )
246#define IEP_PWM_EN_PWM8_EN_MASK ( PWM_EN_MASK << IEP_PWM_EN_PWM8_EN_SHIFT )
247#define IEP_PWM_EN_PWM9_EN_SHIFT ( 0x1 )
248#define IEP_PWM_EN_PWM9_EN_MASK ( PWM_EN_MASK << IEP_PWM_EN_PWM9_EN_SHIFT )
249#define IEP_PWM_EN_PWM10_EN_SHIFT ( 0x1 )
250#define IEP_PWM_EN_PWM10_EN_MASK ( PWM_EN_MASK << IEP_PWM_EN_PWM10_EN_SHIFT )
251#define IEP_PWM_EN_PWM11_EN_SHIFT ( 0x1 )
252#define IEP_PWM_EN_PWM11_EN_MASK ( PWM_EN_MASK << IEP_PWM_EN_PWM11_EN_SHIFT )
253
254/* IEPx_PWM_PRD_COUNT */
255#define PRD_COUNT_MASK ( 0xFFFFFFFF )
256#define IEP_PWM_PRD_COUNT_SHIFT ( 0 )
257#define IEP_PWM_PRD_COUNT_MASK ( PRD_COUNT_MASK << IEP_PWM_PRD_COUNT_SHIFT )
258
259/* IEPx_PWMm_DC_COUNT */
260#define DC_COUNT_MASK ( 0xFFFFFFFF )
261#define IEP_PWM_DC_COUNT_SHIFT ( 0 )
262#define IEP_PWM_DC_COUNT_MASK ( DC_COUNT_MASK << IEP_PWM_DC_COUNT_SHIFT )
263
264/* IEPx_PWMn_n+1_DB_COUNT */
265#define DB_COUNT_MASK ( 0xFFFF )
266#define IEP_PWM_DB_COUNT_SHIFT ( 0 )
267#define IEP_PWM_DB_COUNT_MASK ( DB_COUNT_MASK << IEP_PWM_DB_COUNT_SHIFT )
268
269
270#endif /* _ICSSG_IEP_PWM_H_ */
diff --git a/example/apps/icssg_pwm/firmware/src/iepPwm.c b/example/apps/icssg_pwm/firmware/src/iepPwm.c
index 0584ff4..4ae397b 100644
--- a/example/apps/icssg_pwm/firmware/src/iepPwm.c
+++ b/example/apps/icssg_pwm/firmware/src/iepPwm.c
@@ -34,6 +34,7 @@
34#include <string.h> 34#include <string.h>
35#include <ti/csl/tistdtypes.h> 35#include <ti/csl/tistdtypes.h>
36#include <ti/csl/hw_types.h> 36#include <ti/csl/hw_types.h>
37#include "icssg_iep_pwm.h"
37#include "iepPwmFwRegs.h" 38#include "iepPwmFwRegs.h"
38#include "iepPwmHwRegs.h" 39#include "iepPwmHwRegs.h"
39#include "iepPwm.h" 40#include "iepPwm.h"
@@ -551,7 +552,7 @@ Int32 resetPwmCtrlFwRegs(
551 IcssgIepPwmCtrlObj *pIcssgIepPwmCtrlObj 552 IcssgIepPwmCtrlObj *pIcssgIepPwmCtrlObj
552) 553)
553{ 554{
554 pIcssgIepPwmCtrlObj->pIepPwmCtrlFwRegs = (IepPwmCtrlFwRegs *)FW_REG_PWM_CTRL; 555 pIcssgIepPwmCtrlObj->pIepPwmCtrlFwRegs = (IepPwmCtrlFwRegs *)ICSSG_IEPPWM_PWM_CTRL_ADDR;
555 return IEP_STS_NERR; 556 return IEP_STS_NERR;
556} 557}
557 558
@@ -570,13 +571,13 @@ Int32 resetIepPwmObj(
570 pIcssgIepPwmObj->iepId = iepId; 571 pIcssgIepPwmObj->iepId = iepId;
571 pIcssgIepPwmObj->iepPwmGblEn = FALSE; 572 pIcssgIepPwmObj->iepPwmGblEn = FALSE;
572 if (iepId == IEP_ID_0) { 573 if (iepId == IEP_ID_0) {
573 pIcssgIepPwmObj->pIepPwmFwRegs = (IepPwmFwRegs *)FW_REG_IEP0_PWM_RECFG; 574 pIcssgIepPwmObj->pIepPwmFwRegs = (IepPwmFwRegs *)ICSSG_PWM_IEP0_PWM_BASE_ADDR;
574 pIcssgIepPwmObj->pIepHwRegs = (CSL_icss_g_pr1_iep1_slvRegs *)ICSS_IEP0_CFG_BASE; 575 pIcssgIepPwmObj->pIepHwRegs = (CSL_icss_g_pr1_iep1_slvRegs *)ICSS_IEP0_CFG_BASE;
575 pIcssgIepPwmObj->pIepPwmTripHwRegs = (IepPwmTripHwRegs *)(&pruIcssgCfg->PWM0); 576 pIcssgIepPwmObj->pIepPwmTripHwRegs = (IepPwmTripHwRegs *)(&pruIcssgCfg->PWM0);
576 pIcssgIepPwmObj->pPwmStateCfgHwRegs = (IepPwmStateCfgHwRegs *)(&pruIcssgCfg->PWM0_0); 577 pIcssgIepPwmObj->pPwmStateCfgHwRegs = (IepPwmStateCfgHwRegs *)(&pruIcssgCfg->PWM0_0);
577 } 578 }
578 else if (iepId == IEP_ID_1) { 579 else if (iepId == IEP_ID_1) {
579 pIcssgIepPwmObj->pIepPwmFwRegs = (IepPwmFwRegs *)FW_REG_IEP1_PWM_RECFG; 580 pIcssgIepPwmObj->pIepPwmFwRegs = (IepPwmFwRegs *)ICSSG_PWM_IEP1_PWM_BASE_ADDR;
580 pIcssgIepPwmObj->pIepHwRegs = (CSL_icss_g_pr1_iep1_slvRegs *)ICSS_IEP1_CFG_BASE; 581 pIcssgIepPwmObj->pIepHwRegs = (CSL_icss_g_pr1_iep1_slvRegs *)ICSS_IEP1_CFG_BASE;
581 pIcssgIepPwmObj->pIepPwmTripHwRegs = (IepPwmTripHwRegs *)(&pruIcssgCfg->PWM2); 582 pIcssgIepPwmObj->pIepPwmTripHwRegs = (IepPwmTripHwRegs *)(&pruIcssgCfg->PWM2);
582 pIcssgIepPwmObj->pPwmStateCfgHwRegs = (IepPwmStateCfgHwRegs *)(&pruIcssgCfg->PWM2_0); 583 pIcssgIepPwmObj->pPwmStateCfgHwRegs = (IepPwmStateCfgHwRegs *)(&pruIcssgCfg->PWM2_0);
@@ -688,7 +689,7 @@ Int32 setPwmFwInitFlag(
688) 689)
689{ 690{
690 IepPwmCtrlFwRegs *pIepPwmCtrlFwRegs = pIcssgIepPwmCtrlObj->pIepPwmCtrlFwRegs; 691 IepPwmCtrlFwRegs *pIepPwmCtrlFwRegs = pIcssgIepPwmCtrlObj->pIepPwmCtrlFwRegs;
691 pIepPwmCtrlFwRegs->PWM_STAT |= 0x1 << IEP_PWM_FW_INIT_SHIFT; /* PWM_STAT:FW_INIT=1 */ 692 pIepPwmCtrlFwRegs->PWM_STAT |= 0x1 << PWM_STAT_FW_INIT_SHIFT; /* PWM_STAT:FW_INIT=1 */
692 693
693 return IEP_STS_NERR; 694 return IEP_STS_NERR;
694} 695}
@@ -1306,11 +1307,11 @@ static void latchIepPwmDcCounts(
1306 1307
1307 if (recfgFlag == TRUE) { 1308 if (recfgFlag == TRUE) {
1308 /* Get Duty Cycle reconfiguration */ 1309 /* Get Duty Cycle reconfiguration */
1309 recfgDcCount = (pIepPwmFwRegs->IEP_PWM_RECFG & RECFG_IEP_PWM_DC_COUNT_MASK) >> RECFG_IEP_PWM_DC_COUNT_SHIFT; 1310 recfgDcCount = (pIepPwmFwRegs->IEP_PWM_RECFG & IEP_PWM_RECFG_RECFG_IEP_PWM_DC_COUNT_MASK) >> IEP_PWM_RECFG_RECFG_IEP_PWM_DC_COUNT_SHIFT;
1310 } 1311 }
1311 else { 1312 else {
1312 /* Set Duty Cycle reconfiguration reconfiguration to full mask */ 1313 /* Set Duty Cycle reconfiguration reconfiguration to full mask */
1313 recfgDcCount = RECFG_IEP_PWM_DC_COUNT_MASK >> RECFG_IEP_PWM_DC_COUNT_SHIFT; 1314 recfgDcCount = IEP_PWM_RECFG_RECFG_IEP_PWM_DC_COUNT_MASK >> IEP_PWM_RECFG_RECFG_IEP_PWM_DC_COUNT_SHIFT;
1314 } 1315 }
1315 1316
1316 /* Compute LHS/RHS Duty Cycle counts */ 1317 /* Compute LHS/RHS Duty Cycle counts */
@@ -1360,11 +1361,11 @@ static void latchIepPwmDbCount(
1360 1361
1361 if (recfgFlag == TRUE) { 1362 if (recfgFlag == TRUE) {
1362 /* Get Deadband reconfiguration register */ 1363 /* Get Deadband reconfiguration register */
1363 dbCountRecfg = (pIepPwmFwRegs->IEP_PWM_RECFG & RECFG_IEP_PWM_DB_COUNT_MASK) >> RECFG_IEP_PWM_DB_COUNT_SHIFT; 1364 dbCountRecfg = (pIepPwmFwRegs->IEP_PWM_RECFG & IEP_PWM_RECFG_RECFG_IEP_PWM_DB_COUNT_MASK) >> IEP_PWM_RECFG_RECFG_IEP_PWM_DB_COUNT_SHIFT;
1364 } 1365 }
1365 else { 1366 else {
1366 /* Set Deadband reconfiguration register to full mask */ 1367 /* Set Deadband reconfiguration register to full mask */
1367 dbCountRecfg = RECFG_IEP_PWM_DB_COUNT_MASK >> RECFG_IEP_PWM_DB_COUNT_SHIFT; 1368 dbCountRecfg = IEP_PWM_RECFG_RECFG_IEP_PWM_DB_COUNT_MASK >> IEP_PWM_RECFG_RECFG_IEP_PWM_DB_COUNT_SHIFT;
1368 } 1369 }
1369 1370
1370 pIepPwmDbCount = &pIepPwmFwRegs->IEP_PWM0_1_DB_COUNT; /* init pointer to IEP PWM Deadband Count */ 1371 pIepPwmDbCount = &pIepPwmFwRegs->IEP_PWM0_1_DB_COUNT; /* init pointer to IEP PWM Deadband Count */
@@ -1447,11 +1448,11 @@ static Int32 calcAndLatchIepPwmDcLhsRhsCount(
1447 1448
1448 if (recfgFlag == TRUE) { 1449 if (recfgFlag == TRUE) {
1449 /* Get Duty Cycle reconfiguration */ 1450 /* Get Duty Cycle reconfiguration */
1450 recfgDcCount = (pIepPwmFwRegs->IEP_PWM_RECFG & RECFG_IEP_PWM_DC_COUNT_MASK) >> RECFG_IEP_PWM_DC_COUNT_SHIFT; 1451 recfgDcCount = (pIepPwmFwRegs->IEP_PWM_RECFG & IEP_PWM_RECFG_RECFG_IEP_PWM_DC_COUNT_MASK) >> IEP_PWM_RECFG_RECFG_IEP_PWM_DC_COUNT_SHIFT;
1451 } 1452 }
1452 else { 1453 else {
1453 /* Set Duty Cycle reconfiguration to full mask */ 1454 /* Set Duty Cycle reconfiguration to full mask */
1454 recfgDcCount = RECFG_IEP_PWM_DC_COUNT_MASK >> RECFG_IEP_PWM_DC_COUNT_SHIFT; 1455 recfgDcCount = IEP_PWM_RECFG_RECFG_IEP_PWM_DC_COUNT_MASK >> IEP_PWM_RECFG_RECFG_IEP_PWM_DC_COUNT_SHIFT;
1455 } 1456 }
1456 1457
1457 /* Calculate PWM period. 1458 /* Calculate PWM period.
@@ -1861,7 +1862,7 @@ static Int32 updateIepPwmCmpxShReg(
1861 Uint32 status = IEP_STS_NERR; 1862 Uint32 status = IEP_STS_NERR;
1862 1863
1863 /* Get Duty Cycle reconfiguration */ 1864 /* Get Duty Cycle reconfiguration */
1864 recfgDcCount = (pIepPwmFwRegs->IEP_PWM_RECFG & RECFG_IEP_PWM_DC_COUNT_MASK) >> RECFG_IEP_PWM_DC_COUNT_SHIFT; 1865 recfgDcCount = (pIepPwmFwRegs->IEP_PWM_RECFG & IEP_PWM_RECFG_RECFG_IEP_PWM_DC_COUNT_MASK) >> IEP_PWM_RECFG_RECFG_IEP_PWM_DC_COUNT_SHIFT;
1865 /* Get input (new) IEP PWM DC count array */ 1866 /* Get input (new) IEP PWM DC count array */
1866 pIepPwmDcCountNew = &pIepPwmFwRegs->IEP_PWM0_DC_COUNT; 1867 pIepPwmDcCountNew = &pIepPwmFwRegs->IEP_PWM0_DC_COUNT;
1867 /* Get latched (old) IEP PWM DC count array */ 1868 /* Get latched (old) IEP PWM DC count array */
diff --git a/example/apps/icssg_pwm/firmware/src/iepPwmFwRegs.h b/example/apps/icssg_pwm/firmware/src/iepPwmFwRegs.h
index 01b3d21..73b125e 100644
--- a/example/apps/icssg_pwm/firmware/src/iepPwmFwRegs.h
+++ b/example/apps/icssg_pwm/firmware/src/iepPwmFwRegs.h
@@ -36,26 +36,6 @@
36 36
37#include <ti/csl/cslr_icss.h> 37#include <ti/csl/cslr_icss.h>
38 38
39/* DMEM FW register addresses */
40#define FW_REG_PWM_CTRL ( 0x00000014 ) /* PWM_CTRL FW register */
41#define FW_REG_IEP0_PWM_RECFG ( 0x0000001C ) /* IEP0_PWM_RECFG FW register */
42#define FW_REG_IEP1_PWM_RECFG ( 0x00000068 ) /* IEP1_PWM_RECFG FW register */
43
44/* Bit field mask & shift macros for PWM_CTRL & PWM_STAT */
45#define IEP_PWM_GBL_EN_MASK ( 0x1 )
46#define IEP_PWM_FW_INIT_MASK ( 0x1 << IEP_PWM_FW_INIT_SHIFT ) /* PWM_CTRL:FW_INIT mask */
47#define IEP_PWM_FW_INIT_SHIFT ( 2 ) /* PWM_CTRL:FW_INIT shift */
48
49/* Bit field mask & shift macros for IEPx_PWM_RECFG */
50#define RECFG_IEP_PWM_EN_MASK ( 0x1 << RECFG_IEP_PWM_EN_SHIFT ) /* IEPx_PWM_RECFG:RECFG_IEPx_PWM_EN mask */
51#define RECFG_IEP_PWM_EN_SHIFT ( 0 ) /* IEPx_PWM_RECFG:RECFG_IEP_PWM_EN shift */
52#define RECFG_IEP_PWM_PRD_COUNT_MASK ( 0x1 << RECFG_IEP_PWM_PRD_COUNT_SHIFT ) /* IEPx_PWM_RECFG:RECFG_IEPx_PWM_PRD_COUNT mask */
53#define RECFG_IEP_PWM_PRD_COUNT_SHIFT ( 1 ) /* IEPx_PWM_RECFG:RECFG_IEPx_PWM_PRD_COUNT shift */
54#define RECFG_IEP_PWM_DC_COUNT_MASK ( 0xFFF << RECFG_IEP_PWM_DC_COUNT_SHIFT ) /* IEPx_PWM_RECFG:RECFG_IEPx_PWM_DC_COUNT mask */
55#define RECFG_IEP_PWM_DC_COUNT_SHIFT ( 2 ) /* IEPx_PWM_RECFG:RECFG_IEPx_PWM_DC_COUNT shift */
56#define RECFG_IEP_PWM_DB_COUNT_MASK ( 0x7F << RECFG_IEP_PWM_DB_COUNT_SHIFT ) /* IEPx_PWM_RECFG:RECFG_IEPx_PWM_DB_COUNT mask */
57#define RECFG_IEP_PWM_DB_COUNT_SHIFT ( 14 ) /* IEPx_PWM_RECFG:RECFG_IEPx_PWM_DB_COUNT shift */
58
59/* PWM Firmware information registers */ 39/* PWM Firmware information registers */
60typedef struct IepPwmInfoFwRegs_s 40typedef struct IepPwmInfoFwRegs_s
61{ 41{