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authorFrank Livingston2019-06-28 09:50:12 -0500
committerFrank Livingston2019-06-28 09:50:12 -0500
commit5cf59f59a89315924be579b78093902b74bab363 (patch)
tree0b86cdb01927a35b7bbdde8a18992611861df0e2
parent73ab1ed89a8e54dd18e589ce074c97b1645c85c8 (diff)
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PRSDK-5738:Add bit field settings and aggregate RECFG mask to API header file
Signed-off-by: Frank Livingston <frank-livingston@ti.com>
-rw-r--r--example/apps/icssg_pwm/firmware/src/icssg_iep_pwm.h17
1 files changed, 16 insertions, 1 deletions
diff --git a/example/apps/icssg_pwm/firmware/src/icssg_iep_pwm.h b/example/apps/icssg_pwm/firmware/src/icssg_iep_pwm.h
index 244b9b4..f94b9eb 100644
--- a/example/apps/icssg_pwm/firmware/src/icssg_iep_pwm.h
+++ b/example/apps/icssg_pwm/firmware/src/icssg_iep_pwm.h
@@ -97,6 +97,8 @@
97#define FW_FEATURE_FW_NUM_PWMS_MASK ( FW_NUM_PWMS_MASK << FW_FEATURE_FW_NUM_PWMS_SHIFT ) 97#define FW_FEATURE_FW_NUM_PWMS_MASK ( FW_NUM_PWMS_MASK << FW_FEATURE_FW_NUM_PWMS_SHIFT )
98 98
99/* PWM_CTRL */ 99/* PWM_CTRL */
100#define BF_PWM_GBL_EN_DISABLE ( 0 ) /* Global Enable bit field disabled setting */
101#define BF_PWM_GBL_EN_ENABLE ( 1 ) /* Global Enable bit field enabled setting */
100#define IEP_PWM_GBL_EN_MASK ( 0x1 ) 102#define IEP_PWM_GBL_EN_MASK ( 0x1 )
101#define PWM_CTRL_IEP0_PWM_GBL_EN_SHIFT ( 0 ) 103#define PWM_CTRL_IEP0_PWM_GBL_EN_SHIFT ( 0 )
102#define PWM_CTRL_IEP0_PWM_GBL_EN_MASK ( IEP_PWM_GBL_EN_MASK << PWM_CTRL_IEP0_PWM_GBL_EN_SHIFT ) 104#define PWM_CTRL_IEP0_PWM_GBL_EN_MASK ( IEP_PWM_GBL_EN_MASK << PWM_CTRL_IEP0_PWM_GBL_EN_SHIFT )
@@ -104,6 +106,10 @@
104#define PWM_CTRL_IEP1_PWM_GBL_EN_MASK ( IEP_PWM_GBL_EN_MASK << PWM_CTRL_IEP1_PWM_GBL_EN_SHIFT ) 106#define PWM_CTRL_IEP1_PWM_GBL_EN_MASK ( IEP_PWM_GBL_EN_MASK << PWM_CTRL_IEP1_PWM_GBL_EN_SHIFT )
105 107
106/* PWM_STAT */ 108/* PWM_STAT */
109#define BF_PWM_GBL_EN_ACK_DISABLE ( 0 ) /* Global Enable ACK bit field disabled setting */
110#define BF_PWM_GBL_EN_ACK_ENABLE ( 1 ) /* Global Enable ACK bit field enabled setting */
111#define BF_PWM_FW_INIT_UNINIT ( 0 ) /* FW initialized bit field uninitialized setting */
112#define BF_PWM_FW_INIT_INIT ( 1 ) /* FW initialized bit field initialized setting */
107#define IEP_PWM_GBL_EN_ACK_MASK ( 0x1 ) 113#define IEP_PWM_GBL_EN_ACK_MASK ( 0x1 )
108#define FW_INIT_MASK ( 0x1 ) 114#define FW_INIT_MASK ( 0x1 )
109#define PWM_STAT_IEP0_PWM_GBL_EN_ACK_SHIFT ( 0 ) 115#define PWM_STAT_IEP0_PWM_GBL_EN_ACK_SHIFT ( 0 )
@@ -113,7 +119,6 @@
113#define PWM_STAT_FW_INIT_SHIFT ( 2 ) 119#define PWM_STAT_FW_INIT_SHIFT ( 2 )
114#define PWM_STAT_FW_INIT_MASK ( FW_INIT_MASK << PWM_STAT_FW_INIT_SHIFT ) 120#define PWM_STAT_FW_INIT_MASK ( FW_INIT_MASK << PWM_STAT_FW_INIT_SHIFT )
115 121
116
117/* 122/*
118 * Firmware IEP PWM instance registers 123 * Firmware IEP PWM instance registers
119 */ 124 */
@@ -209,8 +214,16 @@
209#define IEP_PWM_RECFG_RECFG_IEP_PWM_DC_COUNT_MASK ( RECFG_IEP_PWM_DC_COUNT_MASK << IEP_PWM_RECFG_RECFG_IEP_PWM_DC_COUNT_SHIFT ) 214#define IEP_PWM_RECFG_RECFG_IEP_PWM_DC_COUNT_MASK ( RECFG_IEP_PWM_DC_COUNT_MASK << IEP_PWM_RECFG_RECFG_IEP_PWM_DC_COUNT_SHIFT )
210#define IEP_PWM_RECFG_RECFG_IEP_PWM_DB_COUNT_SHIFT ( 14 ) 215#define IEP_PWM_RECFG_RECFG_IEP_PWM_DB_COUNT_SHIFT ( 14 )
211#define IEP_PWM_RECFG_RECFG_IEP_PWM_DB_COUNT_MASK ( RECFG_IEP_PWM_DB_COUNT_MASK << IEP_PWM_RECFG_RECFG_IEP_PWM_DB_COUNT_SHIFT ) 216#define IEP_PWM_RECFG_RECFG_IEP_PWM_DB_COUNT_MASK ( RECFG_IEP_PWM_DB_COUNT_MASK << IEP_PWM_RECFG_RECFG_IEP_PWM_DB_COUNT_SHIFT )
217/* Aggregate Reconfiguration bit field mask */
218#define IEP_PWM_RECFG_MASK \
219 ( IEP_PWM_RECFG_RECFG_IEP_PWM_EN_MASK | \
220 IEP_PWM_RECFG_RECFG_IEP_PWM_PRD_COUNT_MASK | \
221 IEP_PWM_RECFG_RECFG_IEP_PWM_DC_COUNT_MASK | \
222 IEP_PWM_RECFG_RECFG_IEP_PWM_DB_COUNT_MASK )
212 223
213/* IEPx_PWM_MODE */ 224/* IEPx_PWM_MODE */
225#define BF_PWM_MODE_SNGL ( 0 ) /* PWM mode bit field Single-Ended PWM setting */
226#define BF_PWM_MODE_COMP ( 1 ) /* PWM mode bit field Complementary PWM setting */
214#define PWM_MODE_MASK ( 0x1 ) 227#define PWM_MODE_MASK ( 0x1 )
215#define IEP_PWM_MODE_PWM0_1_MODE_SHIFT ( 0 ) 228#define IEP_PWM_MODE_PWM0_1_MODE_SHIFT ( 0 )
216#define IEP_PWM_MODE_PWM0_1_MODE_MASK ( PWM_MODE_MASK << IEP_PWM_MODE_PWM0_1_MODE_SHIFT ) 229#define IEP_PWM_MODE_PWM0_1_MODE_MASK ( PWM_MODE_MASK << IEP_PWM_MODE_PWM0_1_MODE_SHIFT )
@@ -226,6 +239,8 @@
226#define IEP_PWM_MODE_PWM10_11_MODE_MASK ( PWM_MODE_MASK << IEP_PWM_MODE_PWM10_11_MODE_SHIFT ) 239#define IEP_PWM_MODE_PWM10_11_MODE_MASK ( PWM_MODE_MASK << IEP_PWM_MODE_PWM10_11_MODE_SHIFT )
227 240
228/* IEPx_PWM_EN */ 241/* IEPx_PWM_EN */
242#define BF_PWM_EN_DISABLE ( 0 ) /* PWM enable bit field disabled setting */
243#define BF_PWM_EN_ENABLE ( 1 ) /* PWM enable bit field enabled setting */
229#define PWM_EN_MASK ( 0x1 ) 244#define PWM_EN_MASK ( 0x1 )
230#define IEP_PWM_EN_PWM0_EN_SHIFT ( 0 ) 245#define IEP_PWM_EN_PWM0_EN_SHIFT ( 0 )
231#define IEP_PWM_EN_PWM0_EN_MASK ( PWM_EN_MASK << IEP_PWM_EN_PWM0_EN_SHIFT ) 246#define IEP_PWM_EN_PWM0_EN_MASK ( PWM_EN_MASK << IEP_PWM_EN_PWM0_EN_SHIFT )