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authorTinku Mannan2019-04-18 13:11:17 -0500
committerTinku Mannan2019-04-18 14:54:06 -0500
commit658adde37786eef300ed3dec0a89810c250dfa91 (patch)
tree99b23a7db699af61abd451c8ba0188136f26c49f
parent9e65866250527b5281d3d7f2e7e914fee9b31392 (diff)
downloadpruss-lld-658adde37786eef300ed3dec0a89810c250dfa91.tar.gz
pruss-lld-658adde37786eef300ed3dec0a89810c250dfa91.tar.xz
pruss-lld-658adde37786eef300ed3dec0a89810c250dfa91.zip
j721e: pruss driver support
Signed-off-by: Tinku Mannan <tmannan@ti.com>
-rw-r--r--build/makefile.mk2
-rw-r--r--pruss_component.mk5
-rw-r--r--soc/j721e/pruicss_soc.c133
-rw-r--r--src/pruicss_drv.c31
4 files changed, 157 insertions, 14 deletions
diff --git a/build/makefile.mk b/build/makefile.mk
index e45769f..ea03662 100644
--- a/build/makefile.mk
+++ b/build/makefile.mk
@@ -35,7 +35,7 @@ include $(PDK_PRUSS_COMP_PATH)/src/src_files_common.mk
35 35
36MODULE_NAME = pruss 36MODULE_NAME = pruss
37 37
38ifeq ($(SOC),$(filter $(SOC), am571x am572x am437x am335x k2g am574x am65xx)) 38ifeq ($(SOC),$(filter $(SOC), am571x am572x am437x am335x k2g am574x am65xx j721e))
39SRCDIR += soc/$(SOC) 39SRCDIR += soc/$(SOC)
40INCDIR += soc 40INCDIR += soc
41# Common source files across all platforms and cores 41# Common source files across all platforms and cores
diff --git a/pruss_component.mk b/pruss_component.mk
index e854a11..02a8bf3 100644
--- a/pruss_component.mk
+++ b/pruss_component.mk
@@ -1,5 +1,5 @@
1# 1#
2# Copyright (c) 2016-2017, Texas Instruments Incorporated 2# Copyright (c) 2016-2019, Texas Instruments Incorporated
3# All rights reserved. 3# All rights reserved.
4# 4#
5# Redistribution and use in source and binary forms, with or without 5# Redistribution and use in source and binary forms, with or without
@@ -68,7 +68,7 @@ ifeq ($(pruss_component_make_include), )
68 68
69# under other list 69# under other list
70drvpruss_BOARDLIST = icev2AM335x idkAM437x idkAM571x idkAM572x iceK2G idkAM574x 70drvpruss_BOARDLIST = icev2AM335x idkAM437x idkAM571x idkAM572x iceK2G idkAM574x
71drvpruss_SOCLIST = am574x am572x am571x am437x am335x k2g am65xx 71drvpruss_SOCLIST = am574x am572x am571x am437x am335x k2g am65xx j721e
72drvpruss_am574x_CORELIST = c66x a15_0 ipu1_0 pru_0 pru_1 72drvpruss_am574x_CORELIST = c66x a15_0 ipu1_0 pru_0 pru_1
73drvpruss_am572x_CORELIST = c66x a15_0 ipu1_0 pru_0 pru_1 73drvpruss_am572x_CORELIST = c66x a15_0 ipu1_0 pru_0 pru_1
74drvpruss_k2g_CORELIST = c66x a15_0 pru_0 pru_1 74drvpruss_k2g_CORELIST = c66x a15_0 pru_0 pru_1
@@ -76,6 +76,7 @@ drvpruss_am571x_CORELIST = c66x a15_0 ipu1_0 pru_0 pru_1
76drvpruss_am437x_CORELIST = a9host pru_0 pru_1 76drvpruss_am437x_CORELIST = a9host pru_0 pru_1
77drvpruss_am335x_CORELIST = a8host pru_0 pru_1 77drvpruss_am335x_CORELIST = a8host pru_0 pru_1
78drvpruss_am65xx_CORELIST = mpu1_0 mcu1_0 78drvpruss_am65xx_CORELIST = mpu1_0 mcu1_0
79drvpruss_j721e_CORELIST = mcu1_0 mpu1_0
79 80
80############################ 81############################
81# uart package 82# uart package
diff --git a/soc/j721e/pruicss_soc.c b/soc/j721e/pruicss_soc.c
new file mode 100644
index 0000000..5ab799e
--- /dev/null
+++ b/soc/j721e/pruicss_soc.c
@@ -0,0 +1,133 @@
1/**
2 * @file pruicss_soc.c
3 *
4 * @brief This is device specific configuration file .
5 */
6/*
7 * Copyright (c) 2017-2018, Texas Instruments Incorporated
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 *
14 * * Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 *
17 * * Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 *
21 * * Neither the name of Texas Instruments Incorporated nor the names of
22 * its contributors may be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
27 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
29 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
30 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
31 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
32 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
33 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
34 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
35 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37/** ============================================================================*/
38
39
40#include <stdint.h>
41#include <ti/drv/pruss/pruicss.h>
42#include <ti/drv/pruss/soc/pruicss_v1.h>
43
44
45
46//#include <ti/csl/soc/j721e/src/cslr_soc.h>
47#include <ti/csl/soc.h>
48
49
50/* PRUICSS configuration structure */
51PRUICSS_HwAttrs prussInitCfg[PRUICCSS_INSTANCE_TWO] =
52{
53 {
54 CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE, /* baseAddr */
55 0, /* version */
56 CSL_PRU_ICSSG0_PR1_PDSP0_IRAM_BASE, /* prussPru0CtrlRegBase */
57 CSL_PRU_ICSSG0_PR1_PDSP1_IRAM_BASE, /* prussPru1CtrlRegBase */
58 CSL_PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV_BASE, /* prussIntcRegBase */
59 CSL_PRU_ICSSG0_PR1_CFG_SLV_BASE, /* prussCfgRegBase */
60 CSL_PRU_ICSSG0_PR1_ICSS_UART_UART_SLV_BASE, /* prussUartRegBase */
61 CSL_PRU_ICSSG0_IEP0_BASE, /* prussIepRegBase */
62 CSL_PRU_ICSSG0_PR1_ICSS_ECAP0_ECAP_SLV_BASE, /* prussEcapRegBase */
63 CSL_PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_CFG_BASE, /* prussMiiRtCfgRegBase */
64 CSL_PRU_ICSSG0_PR1_MDIO_V1P7_MDIO_BASE, /* prussMiiMdioRegBase */
65 CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE, /* prussPru0DramBase */
66 CSL_PRU_ICSSG0_DRAM1_SLV_RAM_BASE, /* prussPru1DramBase */
67 CSL_PRU_ICSSG0_PR1_PDSP0_IRAM_RAM_BASE, /* prussPru0IramBase */
68 CSL_PRU_ICSSG0_PR1_PDSP1_IRAM_RAM_BASE, /* prussPru1IramBase */
69 CSL_PRU_ICSSG0_RAM_SLV_RAM_BASE, /* prussSharedDramBase */
70 CSL_PRU_ICSSG0_PR1_RTU0_PR1_RTU0_IRAM_RAM_BASE, /* prussRtu0IramBase */
71 CSL_PRU_ICSSG0_PR1_RTU1_PR1_RTU1_IRAM_RAM_BASE, /* prussRtu1IramBase */
72 CSL_PRU_ICSSG0_PR1_RTU0_PR1_RTU0_IRAM_BASE, /* prussRtu0CtrlRegBase */
73 CSL_PRU_ICSSG0_PR1_RTU1_PR1_RTU1_IRAM_BASE, /* prussRtu1CtrlRegBase */
74 CSL_PRU_ICSSG0_DRAM0_SLV_RAM_SIZE, /* prussPru0DramSize */
75 CSL_PRU_ICSSG0_DRAM1_SLV_RAM_SIZE, /* prussPru1DramSize */
76 CSL_PRU_ICSSG0_PR1_PDSP0_IRAM_SIZE, /* prussPru0IramSize */
77 CSL_PRU_ICSSG0_PR1_PDSP1_IRAM_SIZE, /* prussPru1IramSize */
78 CSL_PRU_ICSSG0_RAM_SLV_RAM_SIZE, /* prussSharedDramSize */
79 CSL_PRU_ICSSG0_PR1_RTU0_PR1_RTU0_IRAM_RAM_SIZE, /* prussRtu0IramSize */
80 CSL_PRU_ICSSG0_PR1_RTU1_PR1_RTU1_IRAM_RAM_SIZE /* prussRtu1IramSize */
81 },
82 {
83 CSL_PRU_ICSSG1_DRAM0_SLV_RAM_BASE, /* baseAddr */
84 0, /* version */
85 CSL_PRU_ICSSG1_PR1_PDSP0_IRAM_BASE, /* prussPru0CtrlRegBase */
86 CSL_PRU_ICSSG1_PR1_PDSP1_IRAM_BASE, /* prussPru1CtrlRegBase */
87 CSL_PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV_BASE, /* prussIntcRegBase */
88 CSL_PRU_ICSSG1_PR1_CFG_SLV_BASE, /* prussCfgRegBase */
89 CSL_PRU_ICSSG1_PR1_ICSS_UART_UART_SLV_BASE, /* prussUartRegBase */
90 CSL_PRU_ICSSG1_IEP0_BASE, /* prussIepRegBase */
91 CSL_PRU_ICSSG1_PR1_ICSS_ECAP0_ECAP_SLV_BASE, /* prussEcapRegBase */
92 CSL_PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_CFG_BASE, /* prussMiiRtCfgRegBase */
93 CSL_PRU_ICSSG1_PR1_MDIO_V1P7_MDIO_BASE, /* prussMiiMdioRegBase */
94 CSL_PRU_ICSSG1_DRAM0_SLV_RAM_BASE, /* prussPru0DramBase */
95 CSL_PRU_ICSSG1_DRAM1_SLV_RAM_BASE, /* prussPru1DramBase */
96 CSL_PRU_ICSSG1_PR1_PDSP0_IRAM_RAM_BASE, /* prussPru0IramBase */
97 CSL_PRU_ICSSG1_PR1_PDSP1_IRAM_RAM_BASE, /* prussPru1IramBase */
98 CSL_PRU_ICSSG1_RAM_SLV_RAM_BASE, /* prussSharedDramBase */
99 CSL_PRU_ICSSG1_PR1_RTU0_PR1_RTU0_IRAM_RAM_BASE, /* prussRtu0IramBase */
100 CSL_PRU_ICSSG1_PR1_RTU1_PR1_RTU1_IRAM_RAM_BASE, /* prussRtu1IramBase */
101 CSL_PRU_ICSSG1_PR1_RTU0_PR1_RTU0_IRAM_BASE, /* prussRtu0CtrlRegBase */
102 CSL_PRU_ICSSG1_PR1_RTU1_PR1_RTU1_IRAM_BASE, /* prussRtu1CtrlRegBase */
103 CSL_PRU_ICSSG1_DRAM0_SLV_RAM_SIZE, /* prussPru0DramSize */
104 CSL_PRU_ICSSG1_DRAM1_SLV_RAM_SIZE, /* prussPru1DramSize */
105 CSL_PRU_ICSSG1_PR1_PDSP0_IRAM_SIZE, /* prussPru0IramSize */
106 CSL_PRU_ICSSG1_PR1_PDSP1_IRAM_SIZE, /* prussPru1IramSize */
107 CSL_PRU_ICSSG1_RAM_SLV_RAM_SIZE, /* prussSharedDramSize */
108 CSL_PRU_ICSSG1_PR1_RTU0_PR1_RTU0_IRAM_RAM_SIZE, /* prussRtu0IramSize */
109 CSL_PRU_ICSSG1_PR1_RTU1_PR1_RTU1_IRAM_RAM_SIZE /* prussRtu1IramSize */
110 }
111};
112
113/* PRUICSS objects */
114PRUICSS_V1_Object prussObjects[PRUICCSS_INSTANCE_MAX];
115
116/* PRUICSS configuration structure */
117PRUICSS_Config pruss_config[PRUICCSS_INSTANCE_MAX] = {
118 {
119 &prussObjects[0],
120 &prussInitCfg[0]
121 },
122 {
123 &prussObjects[1],
124 &prussInitCfg[1]
125 },
126 {
127 &prussObjects[2],
128 &prussInitCfg[2]
129 }
130};
131
132
133
diff --git a/src/pruicss_drv.c b/src/pruicss_drv.c
index b086672..ceeba87 100644
--- a/src/pruicss_drv.c
+++ b/src/pruicss_drv.c
@@ -359,7 +359,7 @@ int32_t PRUICSS_pruInitMemory(
359{ 359{
360 uint32_t addr = 0U; 360 uint32_t addr = 0U;
361 PRUICSS_HwAttrs const *hwAttrs; 361 PRUICSS_HwAttrs const *hwAttrs;
362 uint32_t temp_addr = 0U; 362 uintptr_t temp_addr = 0U;
363 int32_t size = 0; 363 int32_t size = 0;
364 int32_t i = 0; 364 int32_t i = 0;
365 365
@@ -388,7 +388,8 @@ int32_t PRUICSS_pruInitMemory(
388 { 388 {
389 for (i = 0; i < size; i = i+4) { 389 for (i = 0; i < size; i = i+4) {
390 temp_addr = (addr + (uint32_t)i); 390 temp_addr = (addr + (uint32_t)i);
391 HWREG(temp_addr) = (uint32_t)0x00000000U; 391 HW_WR_REG32(temp_addr,(uint32_t)0x00000000U);
392 //HWREG(temp_addr) = (uint32_t)0x00000000U;
392 } 393 }
393 } 394 }
394 395
@@ -884,7 +885,7 @@ int32_t PRUICSS_setConstantTblEntry(PRUICSS_Handle handle, uint8_t pruNum, int32
884{ 885{
885 PRUICSS_HwAttrs const *hwAttrs = NULL; 886 PRUICSS_HwAttrs const *hwAttrs = NULL;
886 uint32_t baseaddr = 0U; 887 uint32_t baseaddr = 0U;
887 uint32_t tempaddr = 0U; 888 uintptr_t tempaddr = 0U;
888 uint32_t tempval = 0U; 889 uint32_t tempval = 0U;
889 uint32_t currentval = 0U; 890 uint32_t currentval = 0U;
890 int32_t ret_val = PRUICSS_RETURN_SUCCESS; 891 int32_t ret_val = PRUICSS_RETURN_SUCCESS;
@@ -933,7 +934,8 @@ int32_t PRUICSS_setConstantTblEntry(PRUICSS_Handle handle, uint8_t pruNum, int32
933 currentval = HW_RD_REG32(tempaddr); 934 currentval = HW_RD_REG32(tempaddr);
934 currentval &= (~((uint32_t)CSL_ICSSPRUCTRL_CTBIR0_C24_BLK_INDEX_MASK)); 935 currentval &= (~((uint32_t)CSL_ICSSPRUCTRL_CTBIR0_C24_BLK_INDEX_MASK));
935 tempval = CSL_ICSSPRUCTRL_CTBIR0_C24_BLK_INDEX_MASK & constantTblVal; 936 tempval = CSL_ICSSPRUCTRL_CTBIR0_C24_BLK_INDEX_MASK & constantTblVal;
936 HWREG(tempaddr) =currentval |tempval; 937 //HWREG(tempaddr) =currentval |tempval;
938 HW_WR_REG32(tempaddr,(uint32_t)(currentval |tempval));
937 break; 939 break;
938 } 940 }
939 case PRUICCSS_ConstTblEntryC25: 941 case PRUICCSS_ConstTblEntryC25:
@@ -942,7 +944,8 @@ int32_t PRUICSS_setConstantTblEntry(PRUICSS_Handle handle, uint8_t pruNum, int32
942 currentval &= (~((uint32_t)CSL_ICSSPRUCTRL_CTBIR0_C25_BLK_INDEX_MASK)); 944 currentval &= (~((uint32_t)CSL_ICSSPRUCTRL_CTBIR0_C25_BLK_INDEX_MASK));
943 tempval = constantTblVal << CSL_ICSSPRUCTRL_CTBIR0_C25_BLK_INDEX_SHIFT; 945 tempval = constantTblVal << CSL_ICSSPRUCTRL_CTBIR0_C25_BLK_INDEX_SHIFT;
944 tempval = CSL_ICSSPRUCTRL_CTBIR0_C25_BLK_INDEX_MASK & tempval; 946 tempval = CSL_ICSSPRUCTRL_CTBIR0_C25_BLK_INDEX_MASK & tempval;
945 HWREG(tempaddr) =currentval |tempval; 947 //HWREG(tempaddr) =currentval |tempval;
948 HW_WR_REG32(tempaddr,(uint32_t)(currentval |tempval));
946 break; 949 break;
947 } 950 }
948 case PRUICCSS_ConstTblEntryC26: 951 case PRUICCSS_ConstTblEntryC26:
@@ -951,7 +954,8 @@ int32_t PRUICSS_setConstantTblEntry(PRUICSS_Handle handle, uint8_t pruNum, int32
951 currentval &= (~((uint32_t)CSL_ICSSPRUCTRL_CTBIR1_C26_BLK_INDEX_MASK)); 954 currentval &= (~((uint32_t)CSL_ICSSPRUCTRL_CTBIR1_C26_BLK_INDEX_MASK));
952 tempval = constantTblVal << CSL_ICSSPRUCTRL_CTBIR1_C26_BLK_INDEX_SHIFT; 955 tempval = constantTblVal << CSL_ICSSPRUCTRL_CTBIR1_C26_BLK_INDEX_SHIFT;
953 tempval = CSL_ICSSPRUCTRL_CTBIR1_C26_BLK_INDEX_MASK & tempval; 956 tempval = CSL_ICSSPRUCTRL_CTBIR1_C26_BLK_INDEX_MASK & tempval;
954 HWREG(tempaddr) =currentval |tempval; 957 //HWREG(tempaddr) =currentval |tempval;
958 HW_WR_REG32(tempaddr,(uint32_t)(currentval |tempval));
955 break; 959 break;
956 } 960 }
957 case PRUICCSS_ConstTblEntryC27: 961 case PRUICCSS_ConstTblEntryC27:
@@ -960,7 +964,8 @@ int32_t PRUICSS_setConstantTblEntry(PRUICSS_Handle handle, uint8_t pruNum, int32
960 currentval &= (~((uint32_t)CSL_ICSSPRUCTRL_CTBIR1_C27_BLK_INDEX_MASK)); 964 currentval &= (~((uint32_t)CSL_ICSSPRUCTRL_CTBIR1_C27_BLK_INDEX_MASK));
961 tempval = constantTblVal << CSL_ICSSPRUCTRL_CTBIR1_C27_BLK_INDEX_SHIFT; 965 tempval = constantTblVal << CSL_ICSSPRUCTRL_CTBIR1_C27_BLK_INDEX_SHIFT;
962 tempval = CSL_ICSSPRUCTRL_CTBIR1_C27_BLK_INDEX_MASK & tempval; 966 tempval = CSL_ICSSPRUCTRL_CTBIR1_C27_BLK_INDEX_MASK & tempval;
963 HWREG(tempaddr) =currentval |tempval; 967 //HWREG(tempaddr) =currentval |tempval;
968 HW_WR_REG32(tempaddr,(uint32_t)(currentval |tempval));
964 break; 969 break;
965 } 970 }
966 case PRUICCSS_ConstTblEntryC28: 971 case PRUICCSS_ConstTblEntryC28:
@@ -969,7 +974,8 @@ int32_t PRUICSS_setConstantTblEntry(PRUICSS_Handle handle, uint8_t pruNum, int32
969 currentval &= (~((uint32_t)CSL_ICSSPRUCTRL_CTPPR0_C28_POINTER_MASK)); 974 currentval &= (~((uint32_t)CSL_ICSSPRUCTRL_CTPPR0_C28_POINTER_MASK));
970 tempval = constantTblVal << CSL_ICSSPRUCTRL_CTPPR0_C28_POINTER_SHIFT; 975 tempval = constantTblVal << CSL_ICSSPRUCTRL_CTPPR0_C28_POINTER_SHIFT;
971 tempval &= CSL_ICSSPRUCTRL_CTPPR0_C28_POINTER_MASK; 976 tempval &= CSL_ICSSPRUCTRL_CTPPR0_C28_POINTER_MASK;
972 HWREG(tempaddr) =currentval |tempval; 977 //HWREG(tempaddr) =currentval |tempval;
978 HW_WR_REG32(tempaddr,(uint32_t)(currentval |tempval));
973 break; 979 break;
974 } 980 }
975 case PRUICCSS_ConstTblEntryC29: 981 case PRUICCSS_ConstTblEntryC29:
@@ -978,7 +984,8 @@ int32_t PRUICSS_setConstantTblEntry(PRUICSS_Handle handle, uint8_t pruNum, int32
978 currentval &= (~((uint32_t)CSL_ICSSPRUCTRL_CTPPR0_C29_POINTER_MASK)); 984 currentval &= (~((uint32_t)CSL_ICSSPRUCTRL_CTPPR0_C29_POINTER_MASK));
979 tempval = constantTblVal << CSL_ICSSPRUCTRL_CTPPR0_C29_POINTER_SHIFT; 985 tempval = constantTblVal << CSL_ICSSPRUCTRL_CTPPR0_C29_POINTER_SHIFT;
980 tempval &= CSL_ICSSPRUCTRL_CTPPR0_C29_POINTER_MASK; 986 tempval &= CSL_ICSSPRUCTRL_CTPPR0_C29_POINTER_MASK;
981 HWREG(tempaddr) =currentval |tempval; 987 //HWREG(tempaddr) =currentval |tempval;
988 HW_WR_REG32(tempaddr,(uint32_t)(currentval |tempval));
982 break; 989 break;
983 } 990 }
984 case PRUICCSS_ConstTblEntryC30: 991 case PRUICCSS_ConstTblEntryC30:
@@ -987,7 +994,8 @@ int32_t PRUICSS_setConstantTblEntry(PRUICSS_Handle handle, uint8_t pruNum, int32
987 currentval &= (~((uint32_t)CSL_ICSSPRUCTRL_CTPPR1_C30_POINTER_MASK)); 994 currentval &= (~((uint32_t)CSL_ICSSPRUCTRL_CTPPR1_C30_POINTER_MASK));
988 tempval = constantTblVal << CSL_ICSSPRUCTRL_CTPPR1_C30_POINTER_SHIFT; 995 tempval = constantTblVal << CSL_ICSSPRUCTRL_CTPPR1_C30_POINTER_SHIFT;
989 tempval &= CSL_ICSSPRUCTRL_CTPPR1_C30_POINTER_MASK; 996 tempval &= CSL_ICSSPRUCTRL_CTPPR1_C30_POINTER_MASK;
990 HWREG(tempaddr) =currentval |tempval; 997 //HWREG(tempaddr) =currentval |tempval;
998 HW_WR_REG32(tempaddr,(uint32_t)(currentval |tempval));
991 break; 999 break;
992 } 1000 }
993 case PRUICCSS_ConstTblEntryC31: 1001 case PRUICCSS_ConstTblEntryC31:
@@ -996,7 +1004,8 @@ int32_t PRUICSS_setConstantTblEntry(PRUICSS_Handle handle, uint8_t pruNum, int32
996 currentval &= (~((uint32_t)CSL_ICSSPRUCTRL_CTPPR1_C31_POINTER_MASK)); 1004 currentval &= (~((uint32_t)CSL_ICSSPRUCTRL_CTPPR1_C31_POINTER_MASK));
997 tempval = constantTblVal << CSL_ICSSPRUCTRL_CTPPR1_C31_POINTER_SHIFT; 1005 tempval = constantTblVal << CSL_ICSSPRUCTRL_CTPPR1_C31_POINTER_SHIFT;
998 tempval &= CSL_ICSSPRUCTRL_CTPPR1_C31_POINTER_MASK; 1006 tempval &= CSL_ICSSPRUCTRL_CTPPR1_C31_POINTER_MASK;
999 HWREG(tempaddr) =currentval |tempval; 1007 //HWREG(tempaddr) =currentval |tempval;
1008 HW_WR_REG32(tempaddr,(uint32_t)(currentval |tempval));
1000 break; 1009 break;
1001 } 1010 }
1002 default: 1011 default: