summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorFrank Livingston2019-06-30 12:57:19 -0500
committerFrank Livingston2019-06-30 12:57:19 -0500
commit659e800c657e4c33d6b3cada37b2bc784079f1e0 (patch)
treefa365cd873bb2bb6a79262e4753e20f4ffc9ccac
parentff7ab50797fab246d5895f508d6171ac3893b3df (diff)
downloadpruss-lld-659e800c657e4c33d6b3cada37b2bc784079f1e0.tar.gz
pruss-lld-659e800c657e4c33d6b3cada37b2bc784079f1e0.tar.xz
pruss-lld-659e800c657e4c33d6b3cada37b2bc784079f1e0.zip
PRSDK-5738:Change default build settings
- Remove IEP0 & 1 clock synchronization by default because: (1) this isn't a requirement for "Arduino" PWMs (2) driver doesn't properly support PWM period reconfiguration in case clocks are sync'd. - Remove Tx Host interrupt on IEPx CMP0 event option since this isn't an explicity requirement for "Arduino" PWMs Signed-off-by: Frank Livingston <frank-livingston@ti.com>
-rw-r--r--example/apps/icssg_pwm/firmware/src/iepPwm.c31
1 files changed, 24 insertions, 7 deletions
diff --git a/example/apps/icssg_pwm/firmware/src/iepPwm.c b/example/apps/icssg_pwm/firmware/src/iepPwm.c
index 3ec8c75..91e091b 100644
--- a/example/apps/icssg_pwm/firmware/src/iepPwm.c
+++ b/example/apps/icssg_pwm/firmware/src/iepPwm.c
@@ -39,6 +39,12 @@
39#include "iepPwmHwRegs.h" 39#include "iepPwmHwRegs.h"
40#include "iepPwm.h" 40#include "iepPwm.h"
41 41
42/* Define to synchronize IEP0 & 1 clocks. */
43//#define IEP_SYNC_CLK_EN
44/* Define to enable Tx Host interrupt on IEP0 CMP0 */
45//#define TX_HOST_INT
46
47
42#define CLK_TO_COUNT(x) ( DEF_COUNT_INC_PER_CLK * x ) /* For default increment per clock, compute count corresponding to number of IEP clocks */ 48#define CLK_TO_COUNT(x) ( DEF_COUNT_INC_PER_CLK * x ) /* For default increment per clock, compute count corresponding to number of IEP clocks */
43#define COUNT_TO_CLK(x) ( x / DEF_COUNT_INC_PER_CLK ) /* For default increment per clock, compute IEP clocks corresponding to count */ 49#define COUNT_TO_CLK(x) ( x / DEF_COUNT_INC_PER_CLK ) /* For default increment per clock, compute IEP clocks corresponding to count */
44 50
@@ -626,11 +632,12 @@ Int32 initPwmCtrl(
626) 632)
627{ 633{
628 IepPwmCtrlFwRegs *pIepPwmCtrlFwRegs = pIcssgIepPwmCtrlObj->pIepPwmCtrlFwRegs; 634 IepPwmCtrlFwRegs *pIepPwmCtrlFwRegs = pIcssgIepPwmCtrlObj->pIepPwmCtrlFwRegs;
629 Bool iepSync;
630 volatile Uint32 iepClkReg; 635 volatile Uint32 iepClkReg;
631 Uint8 i; 636 Uint8 i;
632 637#ifdef IEP_SYNC_CLK_EN
633 iepSync = TRUE; 638 Bool iepSync;
639#endif
640
634 for (i = 0; i < ICSSG_NUM_IEP; i++) 641 for (i = 0; i < ICSSG_NUM_IEP; i++)
635 { 642 {
636 /* Latch IEP PWM global enable. 643 /* Latch IEP PWM global enable.
@@ -639,12 +646,16 @@ Int32 initPwmCtrl(
639 (Bool)((pIepPwmCtrlFwRegs->PWM_CTRL >> i ) & IEP_PWM_GBL_EN_MASK); 646 (Bool)((pIepPwmCtrlFwRegs->PWM_CTRL >> i ) & IEP_PWM_GBL_EN_MASK);
640 /* Acknowledge IEP PWM global enable */ 647 /* Acknowledge IEP PWM global enable */
641 pIepPwmCtrlFwRegs->PWM_STAT |= (Uint32)pIcssgIepPwmCtrlObj->iepPwmGblEn[i] << i; 648 pIepPwmCtrlFwRegs->PWM_STAT |= (Uint32)pIcssgIepPwmCtrlObj->iepPwmGblEn[i] << i;
642 649 }
650
651#ifdef IEP_SYNC_CLK_EN
652 iepSync = TRUE;
653 for (i = 0; i < ICSSG_NUM_IEP; i++)
654 {
643 /* Update IEP clock synchronization flag. 655 /* Update IEP clock synchronization flag.
644 All IEPs must be enabled for IEP clock synchronization to be enabled. */ 656 All IEPs must be enabled for IEP clock synchronization to be enabled. */
645 iepSync = iepSync && pIcssgIepPwmCtrlObj->iepPwmGblEn[i]; 657 iepSync = iepSync && pIcssgIepPwmCtrlObj->iepPwmGblEn[i];
646 } 658 }
647
648 if (iepSync == TRUE) { 659 if (iepSync == TRUE) {
649 /* Set IEP0 & 1 synchronization */ 660 /* Set IEP0 & 1 synchronization */
650 661
@@ -658,7 +669,8 @@ Int32 initPwmCtrl(
658 /* Write ICSSG_IEPCLK_REG HW register */ 669 /* Write ICSSG_IEPCLK_REG HW register */
659 pIcssgIepPwmCtrlObj->pIcssgCfgHwRegs->IEPCLK_REG = iepClkReg; 670 pIcssgIepPwmCtrlObj->pIcssgCfgHwRegs->IEPCLK_REG = iepClkReg;
660 } 671 }
661 672#endif
673
662 return IEP_STS_NERR; 674 return IEP_STS_NERR;
663} 675}
664 676
@@ -793,9 +805,11 @@ Int32 execIepPwmSm(
793 if (pIcssgIepPwmObj->iepPwmState == IEP_SM_STATE_INIT) { 805 if (pIcssgIepPwmObj->iepPwmState == IEP_SM_STATE_INIT) {
794 if ((cmpStatus & IEP_CMP_STATUS_CMP0_MASK) == IEP_CMP_STATUS_CMP0_MASK) { /* CMP0 event has occurred */ 806 if ((cmpStatus & IEP_CMP_STATUS_CMP0_MASK) == IEP_CMP_STATUS_CMP0_MASK) { /* CMP0 event has occurred */
795 pIepHwRegs->CMP_STATUS_REG = IEP_CMP_STATUS_CMP0_12_MASK; /* clear CMP0-12 events */ 807 pIepHwRegs->CMP_STATUS_REG = IEP_CMP_STATUS_CMP0_12_MASK; /* clear CMP0-12 events */
808#ifdef TX_HOST_INT
796 if (txHostEvt == TRUE) { 809 if (txHostEvt == TRUE) {
797 __R31 = 16 + TRIGGER_HOST_EVT; /* trigger Host interrupt on IEP CMP0 event */ 810 __R31 = 16 + TRIGGER_HOST_EVT; /* trigger Host interrupt on IEP CMP0 event */
798 } 811 }
812#endif
799 813
800 /* Initialize IEP PWM CMPx Shadow Registers */ 814 /* Initialize IEP PWM CMPx Shadow Registers */
801 status = initIepPwmCmpxShReg(pIcssgIepPwmObj); 815 status = initIepPwmCmpxShReg(pIcssgIepPwmObj);
@@ -813,10 +827,11 @@ Int32 execIepPwmSm(
813 if (pIcssgIepPwmObj->iepPwmState == IEP_SM_STATE_LHS) { 827 if (pIcssgIepPwmObj->iepPwmState == IEP_SM_STATE_LHS) {
814 if ((cmpStatus & IEP_CMP_STATUS_CMP0_MASK) == IEP_CMP_STATUS_CMP0_MASK) { /* CMP0 event has occurred */ 828 if ((cmpStatus & IEP_CMP_STATUS_CMP0_MASK) == IEP_CMP_STATUS_CMP0_MASK) { /* CMP0 event has occurred */
815 pIepHwRegs->CMP_STATUS_REG = IEP_CMP_STATUS_CMP0_12_MASK; /* clear CMP0-12 events */ 829 pIepHwRegs->CMP_STATUS_REG = IEP_CMP_STATUS_CMP0_12_MASK; /* clear CMP0-12 events */
830#ifdef TX_HOST_INT
816 if (txHostEvt == TRUE) { 831 if (txHostEvt == TRUE) {
817 __R31 = 16 + TRIGGER_HOST_EVT; /* trigger Host interrupt on IEP CMP0 event */ 832 __R31 = 16 + TRIGGER_HOST_EVT; /* trigger Host interrupt on IEP CMP0 event */
818 } 833 }
819 834#endif
820 /* Perform LHS processing */ 835 /* Perform LHS processing */
821 iepPwmLhs(pIcssgIepPwmObj); 836 iepPwmLhs(pIcssgIepPwmObj);
822 837
@@ -827,9 +842,11 @@ Int32 execIepPwmSm(
827 else if (pIcssgIepPwmObj->iepPwmState == IEP_SM_STATE_RHS) { 842 else if (pIcssgIepPwmObj->iepPwmState == IEP_SM_STATE_RHS) {
828 if ((cmpStatus & IEP_CMP_STATUS_CMP0_MASK) == IEP_CMP_STATUS_CMP0_MASK) { /* CMP0 event has occurred */ 843 if ((cmpStatus & IEP_CMP_STATUS_CMP0_MASK) == IEP_CMP_STATUS_CMP0_MASK) { /* CMP0 event has occurred */
829 pIepHwRegs->CMP_STATUS_REG = IEP_CMP_STATUS_CMP0_12_MASK; /* clear CMP0-12 events */ 844 pIepHwRegs->CMP_STATUS_REG = IEP_CMP_STATUS_CMP0_12_MASK; /* clear CMP0-12 events */
845#ifdef TX_HOST_INT
830 if (txHostEvt == TRUE) { 846 if (txHostEvt == TRUE) {
831 __R31 = 16 + TRIGGER_HOST_EVT; /* trigger Host interrupt on IEP CMP0 event */ 847 __R31 = 16 + TRIGGER_HOST_EVT; /* trigger Host interrupt on IEP CMP0 event */
832 } 848 }
849#endif
833 850
834 /* Perform RHS processing */ 851 /* Perform RHS processing */
835 iepPwmRhs(pIcssgIepPwmObj); 852 iepPwmRhs(pIcssgIepPwmObj);