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authorMahesh Radhakrishnan2018-11-07 14:38:15 -0600
committerMahesh Radhakrishnan2018-11-07 14:38:15 -0600
commitaa58dc96ad2d6bb2b3f4cbc105ff88e78420a767 (patch)
tree05663c6fd4a832fc2f5d833fdec860fd5156d45c
parent4319eb250685f672979d4d6cc80c40a56e1afa0d (diff)
parent25d3914e9b7eee24dd903bc03d44a778381cee19 (diff)
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Merge pull request #56 in PROCESSOR-SDK/pruss-lld from prsdk-4794 to masterDEV.PRUSS_LLD.01.00.00.12DEV.PROCESSOR-SDK.05.02.00.07
* commit '25d3914e9b7eee24dd903bc03d44a778381cee19': set PRU PC to zero when reset the PRU
-rw-r--r--src/pruicss_drv.c92
1 files changed, 24 insertions, 68 deletions
diff --git a/src/pruicss_drv.c b/src/pruicss_drv.c
index 5794d1a..b086672 100644
--- a/src/pruicss_drv.c
+++ b/src/pruicss_drv.c
@@ -68,36 +68,21 @@ static uintptr_t pruicss_get_ctrl_addr (PRUICSS_HwAttrs const *hwAttrs,
68 int32_t instance, 68 int32_t instance,
69 uint8_t pruNum) 69 uint8_t pruNum)
70{ 70{
71 uintptr_t baseaddr; 71 uintptr_t baseaddr = 0;
72 72
73 if ((instance >= PRUICCSS_INSTANCE_ONE) && (instance <= PRUICCSS_INSTANCE_MAX)) 73 if ((instance >= PRUICCSS_INSTANCE_ONE) && (instance <= PRUICCSS_INSTANCE_MAX))
74 { 74 {
75 if(PRUICCSS_PRU0 == pruNum) 75 switch (pruNum) {
76 { 76 case PRUICCSS_PRU0: baseaddr = hwAttrs->prussPru0CtrlRegBase;
77 baseaddr = hwAttrs->prussPru0CtrlRegBase; 77 break;
78 } 78 case PRUICCSS_PRU1: baseaddr = hwAttrs->prussPru1CtrlRegBase;
79 else if(PRUICCSS_PRU1 == pruNum) 79 break;
80 { 80 case PRUICCSS_RTU0: baseaddr = hwAttrs->prussRtu0CtrlRegBase;
81 baseaddr = hwAttrs->prussPru1CtrlRegBase; 81 break;
82 } 82 case PRUICCSS_RTU1: baseaddr = hwAttrs->prussRtu1CtrlRegBase;
83 else if(PRUICCSS_RTU0 == pruNum) 83 break;
84 {
85 baseaddr = hwAttrs->prussRtu0CtrlRegBase;
86 }
87 else if(PRUICCSS_RTU1 == pruNum)
88 {
89 baseaddr = hwAttrs->prussRtu1CtrlRegBase;
90 }
91 else
92 {
93 baseaddr = 0;
94 } 84 }
95 } 85 }
96 else
97 {
98 baseaddr = 0;
99 }
100
101 return baseaddr; 86 return baseaddr;
102} 87}
103 88
@@ -180,26 +165,16 @@ int32_t PRUICSS_pruReset(PRUICSS_Handle handle, uint8_t pruNum)
180 uintptr_t baseaddr; 165 uintptr_t baseaddr;
181 PRUICSS_V1_Object *object; 166 PRUICSS_V1_Object *object;
182 PRUICSS_HwAttrs const *hwAttrs; 167 PRUICSS_HwAttrs const *hwAttrs;
183 int32_t ret_val = PRUICSS_RETURN_SUCCESS; 168 int32_t ret_val = PRUICSS_RETURN_FAILURE;
184 169
185 object = (PRUICSS_V1_Object *)handle->object; 170 object = (PRUICSS_V1_Object *)handle->object;
186 hwAttrs = (PRUICSS_HwAttrs const *)handle->hwAttrs; 171 hwAttrs = (PRUICSS_HwAttrs const *)handle->hwAttrs;
187 172
188 if(pruNum >= PRUICSS_MAX_PRU) 173 if(pruNum < PRUICSS_MAX_PRU) {
189 {
190 ret_val = PRUICSS_RETURN_FAILURE;
191 }
192 else
193 {
194 baseaddr = pruicss_get_ctrl_addr (hwAttrs, object->instance, pruNum); 174 baseaddr = pruicss_get_ctrl_addr (hwAttrs, object->instance, pruNum);
195 if(baseaddr != 0) 175 if(baseaddr != 0) {
196 { 176 HW_WR_REG32((baseaddr) + CSL_ICSSPRUCTRL_CONTROL, 0);
197 HW_WR_FIELD32((baseaddr), CSL_ICSSPRUCTRL_CONTROL_ENABLE, CSL_ICSSPRUCTRL_CONTROL_ENABLE_RESETVAL); 177 ret_val = PRUICSS_RETURN_SUCCESS;
198 HW_WR_FIELD32((baseaddr), CSL_ICSSPRUCTRL_CONTROL_SOFT_RST_N, PRUICSS_PRU_SOFT_RESET_VAL);
199 }
200 else
201 {
202 ret_val = PRUICSS_RETURN_FAILURE;
203 } 178 }
204 } 179 }
205 return ret_val; 180 return ret_val;
@@ -212,31 +187,21 @@ int32_t PRUICSS_pruReset(PRUICSS_Handle handle, uint8_t pruNum)
212 * 187 *
213 * @return 0 in case of successful disable, -1 otherwise. 188 * @return 0 in case of successful disable, -1 otherwise.
214 **/ 189 **/
215 int32_t PRUICSS_pruDisable(PRUICSS_Handle handle, uint8_t pruNum) 190int32_t PRUICSS_pruDisable(PRUICSS_Handle handle, uint8_t pruNum)
216{ 191{
217 uintptr_t baseaddr = 0; 192 uintptr_t baseaddr = 0;
218 PRUICSS_V1_Object *object; 193 PRUICSS_V1_Object *object;
219 PRUICSS_HwAttrs const *hwAttrs; 194 PRUICSS_HwAttrs const *hwAttrs;
220 int32_t ret_val = PRUICSS_RETURN_SUCCESS; 195 int32_t ret_val = PRUICSS_RETURN_FAILURE;
221 196
222 object = (PRUICSS_V1_Object *)handle->object; 197 object = (PRUICSS_V1_Object *)handle->object;
223 hwAttrs = (PRUICSS_HwAttrs const *)handle->hwAttrs; 198 hwAttrs = (PRUICSS_HwAttrs const *)handle->hwAttrs;
224 199
225 if(pruNum >= PRUICSS_MAX_PRU) 200 if(pruNum < PRUICSS_MAX_PRU) {
226 {
227 ret_val = PRUICSS_RETURN_FAILURE;
228 }
229 else
230 {
231 baseaddr = pruicss_get_ctrl_addr (hwAttrs, object->instance, pruNum); 201 baseaddr = pruicss_get_ctrl_addr (hwAttrs, object->instance, pruNum);
232 202 if(baseaddr != 0) {
233 if(baseaddr != 0)
234 {
235 HW_WR_FIELD32((baseaddr), CSL_ICSSPRUCTRL_CONTROL_ENABLE, CSL_ICSSPRUCTRL_CONTROL_ENABLE_RESETVAL); 203 HW_WR_FIELD32((baseaddr), CSL_ICSSPRUCTRL_CONTROL_ENABLE, CSL_ICSSPRUCTRL_CONTROL_ENABLE_RESETVAL);
236 } 204 ret_val = PRUICSS_RETURN_SUCCESS;
237 else
238 {
239 ret_val = PRUICSS_RETURN_FAILURE;
240 } 205 }
241 } 206 }
242 return ret_val; 207 return ret_val;
@@ -254,25 +219,16 @@ int32_t PRUICSS_pruEnable(PRUICSS_Handle handle,uint8_t pruNum)
254 uintptr_t baseaddr; 219 uintptr_t baseaddr;
255 PRUICSS_V1_Object *object; 220 PRUICSS_V1_Object *object;
256 PRUICSS_HwAttrs const *hwAttrs; 221 PRUICSS_HwAttrs const *hwAttrs;
257 int32_t ret_val = PRUICSS_RETURN_SUCCESS; 222 int32_t ret_val = PRUICSS_RETURN_FAILURE;
258 223
259 object = (PRUICSS_V1_Object *)handle->object; 224 object = (PRUICSS_V1_Object *)handle->object;
260 hwAttrs = (PRUICSS_HwAttrs const *)handle->hwAttrs; 225 hwAttrs = (PRUICSS_HwAttrs const *)handle->hwAttrs;
261 226
262 if(pruNum >= PRUICSS_MAX_PRU) 227 if(pruNum < PRUICSS_MAX_PRU) {
263 {
264 ret_val = PRUICSS_RETURN_FAILURE;
265 }
266 else
267 {
268 baseaddr = pruicss_get_ctrl_addr (hwAttrs, object->instance, pruNum); 228 baseaddr = pruicss_get_ctrl_addr (hwAttrs, object->instance, pruNum);
269 if(baseaddr != 0) 229 if(baseaddr != 0) {
270 {
271 HW_WR_FIELD32((baseaddr), CSL_ICSSPRUCTRL_CONTROL_ENABLE, CSL_ICSSPRUCTRL_CONTROL_ENABLE_MAX); 230 HW_WR_FIELD32((baseaddr), CSL_ICSSPRUCTRL_CONTROL_ENABLE, CSL_ICSSPRUCTRL_CONTROL_ENABLE_MAX);
272 } 231 ret_val = PRUICSS_RETURN_SUCCESS;
273 else
274 {
275 ret_val = PRUICSS_RETURN_FAILURE;
276 } 232 }
277 } 233 }
278 return ret_val; 234 return ret_val;