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authorFrank Livingston2019-05-20 10:23:26 -0500
committerFrank Livingston2019-05-20 10:23:26 -0500
commitafcbb2869a71c959e81877917e1ce4f7b59ca6f0 (patch)
treee3e6186cf31ed02c39c23ad20a5170ecb4f6f8be
parent0e616766afcafc3085f73fefce2498bfaaa10528 (diff)
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PRSDK-5738:Update execRhsActionStash() to take correct action
Signed-off-by: Frank Livingston <frank-livingston@ti.com>
-rw-r--r--example/apps/icssg_pwm/firmware/src/iepPwm.c36
-rw-r--r--example/apps/icssg_pwm/firmware/src/iepPwm.h2
2 files changed, 20 insertions, 18 deletions
diff --git a/example/apps/icssg_pwm/firmware/src/iepPwm.c b/example/apps/icssg_pwm/firmware/src/iepPwm.c
index 233ef65..0584ff4 100644
--- a/example/apps/icssg_pwm/firmware/src/iepPwm.c
+++ b/example/apps/icssg_pwm/firmware/src/iepPwm.c
@@ -50,7 +50,6 @@
50/* Active state Toggle:0000, Trip state HiZ:0000, Initial state L/L:0101 */ 50/* Active state Toggle:0000, Trip state HiZ:0000, Initial state L/L:0101 */
51#define SNGL_PWM_STATE_INIT \ 51#define SNGL_PWM_STATE_INIT \
52 ((PWM_ACT_TOGGLE<<10) | (PWM_ACT_TOGGLE<<8) | (PWM_TRIP_HIZ<<6) | (PWM_TRIP_HIZ<<4) | (PWM_INIT_LO<<2) | (PWM_INIT_LO<<0)) 52 ((PWM_ACT_TOGGLE<<10) | (PWM_ACT_TOGGLE<<8) | (PWM_TRIP_HIZ<<6) | (PWM_TRIP_HIZ<<4) | (PWM_INIT_LO<<2) | (PWM_INIT_LO<<0))
53/* Differential PWM Initial State Configuration register for "sacrificial" PWM */
54/* Differential PWM Initial State Configuration register */ 53/* Differential PWM Initial State Configuration register */
55/* Active state Toggle:0000, Trip state HiZ:0000, Initial state H/L:1001 */ 54/* Active state Toggle:0000, Trip state HiZ:0000, Initial state H/L:1001 */
56#define DIFF_PWM_STATE_INIT \ 55#define DIFF_PWM_STATE_INIT \
@@ -166,7 +165,7 @@ static const IepPwmActionTableEntry gActT2_EnRecfgNo_EnOldEnable[AT_NROW] =
166 /* DC_old = 100, DC_new = y */ 165 /* DC_old = 100, DC_new = y */
167 {LATCH_ACTION_Latch_New, 166 {LATCH_ACTION_Latch_New,
168 LHS_ACTION_None, 167 LHS_ACTION_None,
169 RHS_ACTION_Set_CmpSr_DcLhsY_And_EnableSrUpdate}, 168 RHS_ACTION_Set_CmpSr_DcRhsY_And_EnableSrUpdate},
170 /* DC_old = 100, DC_new = 0 */ 169 /* DC_old = 100, DC_new = 0 */
171 {LATCH_ACTION_Latch_0, 170 {LATCH_ACTION_Latch_0,
172 LHS_ACTION_Set_CmpSr_EarlyInPrd_And_EnableSrUpdate, 171 LHS_ACTION_Set_CmpSr_EarlyInPrd_And_EnableSrUpdate,
@@ -747,7 +746,7 @@ Int32 execIepPwmSm(
747 status = initIepPwmCmpxShReg(pIcssgIepPwmObj); 746 status = initIepPwmCmpxShReg(pIcssgIepPwmObj);
748 747
749 if (status == IEP_STS_NERR) { 748 if (status == IEP_STS_NERR) {
750 /* Update State to Right-Hand Side */ 749 /* Update State to Left-Hand Side */
751 pIcssgIepPwmObj->iepPwmState = IEP_SM_STATE_LHS; 750 pIcssgIepPwmObj->iepPwmState = IEP_SM_STATE_LHS;
752 } 751 }
753 else { 752 else {
@@ -2534,17 +2533,20 @@ static void execRhsActionStash(
2534) 2533)
2535{ 2534{
2536 Uint32 *pIepPwmDcCountRhs; 2535 Uint32 *pIepPwmDcCountRhs;
2536 Uint16 *pIepPwmDbCount;
2537 Uint16 *pIepPwmSnglUpdEn; 2537 Uint16 *pIepPwmSnglUpdEn;
2538 Uint8 *pIepPwmDiffUpdEn; 2538 Uint8 *pIepPwmDiffUpdEn;
2539 volatile uint32_t **pIepCmpSrAddr; 2539 volatile uint32_t **pIepCmpSrAddr;
2540 Uint32 iepPwmPeriodCount; 2540 Uint32 iepPwmPeriodCount;
2541 IepPwmRhsAction *pIepPwmRhsAction; 2541 IepPwmRhsAction *pIepPwmRhsAction;
2542 Uint32 dcLhsY; 2542 Uint32 dcRhsY;
2543 volatile uint32_t *pCmpSr; 2543 volatile uint32_t *pCmpSr;
2544 Uint8 pwmIdx, dPwmIdx; 2544 Uint8 pwmIdx, dPwmIdx;
2545 2545
2546 /* Get latched IEP PWM DC RHS count array */ 2546 /* Get latched IEP PWM DC RHS count array */
2547 pIepPwmDcCountRhs = &pIcssgIepPwmObj->iepPwmDcCountRhs[0]; 2547 pIepPwmDcCountRhs = &pIcssgIepPwmObj->iepPwmDcCountRhs[0];
2548 /* Get Deadband count array */
2549 pIepPwmDbCount = &pIcssgIepPwmObj->iepPwmDbCount[0];
2548 /* Get Single-Ended & Differential PWM Update Enable */ 2550 /* Get Single-Ended & Differential PWM Update Enable */
2549 pIepPwmSnglUpdEn = &pIcssgIepPwmObj->iepPwmSnglUpdEn; 2551 pIepPwmSnglUpdEn = &pIcssgIepPwmObj->iepPwmSnglUpdEn;
2550 pIepPwmDiffUpdEn = &pIcssgIepPwmObj->iepPwmDiffUpdEn; 2552 pIepPwmDiffUpdEn = &pIcssgIepPwmObj->iepPwmDiffUpdEn;
@@ -2564,30 +2566,30 @@ static void execRhsActionStash(
2564 pwmIdx = dPwmIdx << 1; 2566 pwmIdx = dPwmIdx << 1;
2565 switch(pIepPwmRhsAction[pwmIdx]) 2567 switch(pIepPwmRhsAction[pwmIdx])
2566 { 2568 {
2567 case RHS_ACTION_Set_CmpSr_DcLhsY_And_EnableSrUpdate: 2569 case RHS_ACTION_Set_CmpSr_DcRhsY_And_EnableSrUpdate:
2568 dcLhsY = pIepPwmDcCountRhs[pwmIdx]; 2570 dcRhsY = pIepPwmDcCountRhs[pwmIdx];
2569 2571
2570 pCmpSr = pIepCmpSrAddr[pwmIdx]; 2572 pCmpSr = pIepCmpSrAddr[pwmIdx];
2571 *pCmpSr = dcLhsY; /* Write LHS value to CMP Shadow Register */ 2573 *pCmpSr = dcRhsY; /* Write RHS value to CMP Shadow Register */
2572 pwmIdx++; 2574 pwmIdx++;
2573 pCmpSr = pIepCmpSrAddr[pwmIdx]; 2575 pCmpSr = pIepCmpSrAddr[pwmIdx];
2574 *pCmpSr = dcLhsY; /* Write LHS value to CMP Shadow Register */ 2576 *pCmpSr = dcRhsY + pIepPwmDbCount[dPwmIdx]; /* Write RHS value to CMP Shadow Register */
2575 2577
2576 *pIepPwmDiffUpdEn |= 1<<dPwmIdx; /* Enable CMP SR update */ 2578 *pIepPwmDiffUpdEn |= 1<<dPwmIdx; /* Enable CMP SR update */
2577 break; 2579 break;
2578 2580
2579 case RHS_ACTION_Set_CmpSr_GtPrd_And_DisableSrUpdate: 2581 case RHS_ACTION_Set_CmpSr_GtPrd_And_DisableSrUpdate:
2580 dcLhsY = pIepPwmDcCountRhs[pwmIdx]; 2582 dcRhsY = pIepPwmDcCountRhs[pwmIdx];
2581 2583
2582 /* Write same LHS value to both CMP Shadow Registers in differential pair */ 2584 /* Write same LHS value to both CMP Shadow Registers in differential pair */
2583 pCmpSr = pIepCmpSrAddr[pwmIdx]; 2585 pCmpSr = pIepCmpSrAddr[pwmIdx];
2584 *pCmpSr = iepPwmPeriodCount; 2586 *pCmpSr = iepPwmPeriodCount; /* Write value greater than Period to Shadow Register */
2585 pwmIdx++; 2587 pwmIdx++;
2586 pCmpSr = pIepCmpSrAddr[pwmIdx]; 2588 pCmpSr = pIepCmpSrAddr[pwmIdx];
2587 *pCmpSr = iepPwmPeriodCount; 2589 *pCmpSr = iepPwmPeriodCount; /* Write value greater than Period to Shadow Register */
2588 2590
2589 /* Enable CMP SR update */ 2591 /* Enable CMP SR update */
2590 *pIepPwmDiffUpdEn &= ~(1<<dPwmIdx); /* Disable CMP SR update */ 2592 *pIepPwmDiffUpdEn &= ~(1<<dPwmIdx); /* Disable CMP SR update */
2591 break; 2593 break;
2592 2594
2593 case RHS_ACTION_None: 2595 case RHS_ACTION_None:
@@ -2603,15 +2605,15 @@ static void execRhsActionStash(
2603 { 2605 {
2604 switch (pIepPwmRhsAction[pwmIdx]) 2606 switch (pIepPwmRhsAction[pwmIdx])
2605 { 2607 {
2606 case RHS_ACTION_Set_CmpSr_DcLhsY_And_EnableSrUpdate: 2608 case RHS_ACTION_Set_CmpSr_DcRhsY_And_EnableSrUpdate:
2607 dcLhsY = pIepPwmDcCountRhs[pwmIdx]; 2609 dcRhsY = pIepPwmDcCountRhs[pwmIdx];
2608 pCmpSr = pIepCmpSrAddr[pwmIdx]; 2610 pCmpSr = pIepCmpSrAddr[pwmIdx];
2609 *pCmpSr = dcLhsY; /* Write LHS value to CMP Shadow Register */ 2611 *pCmpSr = dcRhsY; /* Write RHS value to CMP Shadow Register */
2610 *pIepPwmSnglUpdEn |= 1<<pwmIdx; /* Enable CMP SR update */ 2612 *pIepPwmSnglUpdEn |= 1<<pwmIdx; /* Enable CMP SR update */
2611 break; 2613 break;
2612 case RHS_ACTION_Set_CmpSr_GtPrd_And_DisableSrUpdate: 2614 case RHS_ACTION_Set_CmpSr_GtPrd_And_DisableSrUpdate:
2613 pCmpSr = pIepCmpSrAddr[pwmIdx]; 2615 pCmpSr = pIepCmpSrAddr[pwmIdx];
2614 *pCmpSr = iepPwmPeriodCount; /* Write LHS value to CMP Shadow Register */ 2616 *pCmpSr = iepPwmPeriodCount; /* Write value greater than Period to CMP Shadow Register */
2615 *pIepPwmSnglUpdEn &= ~(1<<pwmIdx); /* Disable CMP SR update */ 2617 *pIepPwmSnglUpdEn &= ~(1<<pwmIdx); /* Disable CMP SR update */
2616 break; 2618 break;
2617 case RHS_ACTION_None: 2619 case RHS_ACTION_None:
diff --git a/example/apps/icssg_pwm/firmware/src/iepPwm.h b/example/apps/icssg_pwm/firmware/src/iepPwm.h
index c10d0b1..c52631b 100644
--- a/example/apps/icssg_pwm/firmware/src/iepPwm.h
+++ b/example/apps/icssg_pwm/firmware/src/iepPwm.h
@@ -114,7 +114,7 @@ typedef enum IepPwmRhsAction_e
114 RHS_ACTION_None = 0, 114 RHS_ACTION_None = 0,
115 /* RHS Action: Set IEP CMP Shadow Register to new value Y & 115 /* RHS Action: Set IEP CMP Shadow Register to new value Y &
116 enable Shadow Register update */ 116 enable Shadow Register update */
117 RHS_ACTION_Set_CmpSr_DcLhsY_And_EnableSrUpdate = 1, 117 RHS_ACTION_Set_CmpSr_DcRhsY_And_EnableSrUpdate = 1,
118 /* RHS Action: Set IEP CMP Shadow Register > CMP0 Period & 118 /* RHS Action: Set IEP CMP Shadow Register > CMP0 Period &
119 enable Shadow Register update */ 119 enable Shadow Register update */
120 RHS_ACTION_Set_CmpSr_GtPrd_And_DisableSrUpdate = 2 120 RHS_ACTION_Set_CmpSr_GtPrd_And_DisableSrUpdate = 2