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authorTinku Mannan2016-08-19 12:37:55 -0500
committerTinku Mannan2016-08-31 08:19:27 -0500
commit32bd47f2f5041028ea5cf52c8e9cd3b6b11de903 (patch)
tree4b494bdf7c08960cc7a40c91a51321838ec18f9c /src/pruicss_intc.c
parentca56d0e545124dced7f0129b001f66f2be43139f (diff)
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FIX PRSDK-1020
Diffstat (limited to 'src/pruicss_intc.c')
-rw-r--r--src/pruicss_intc.c58
1 files changed, 58 insertions, 0 deletions
diff --git a/src/pruicss_intc.c b/src/pruicss_intc.c
index e0933ff..52feae8 100644
--- a/src/pruicss_intc.c
+++ b/src/pruicss_intc.c
@@ -375,6 +375,64 @@ static void PRUICSS_intcSetHmr( uint8_t channel,
375 HWREG(temp_addr1) = HWREG(temp_addr2) | ((((uint32_t)host) & ((uint32_t)0xFU)) << ((((uint32_t)channel) & ((uint32_t)0x3U)) << 3U)); 375 HWREG(temp_addr1) = HWREG(temp_addr2) | ((((uint32_t)host) & ((uint32_t)0xFU)) << ((((uint32_t)channel) & ((uint32_t)0x3U)) << 3U));
376} 376}
377 377
378/**
379 * @brief This function clears all Interrupt-Channel-host mapping.
380 *
381 * @param handle Pruss's driver handle
382 *
383 * @return 0 in case of successful transition, -1 otherwise. \n
384 */
385int32_t PRUICSS_pruIntcClear(PRUICSS_Handle handle)
386{
387 uint32_t baseaddr;
388 PRUICSS_HwAttrs const *hwAttrs;
389 PRUICSS_V1_Object *object;
390
391 uint32_t i = 0;
392
393 uint32_t temp_addr = 0U;
394
395 int32_t ret_val = PRUICSS_RETURN_SUCCESS;
396
397 hwAttrs = handle->hwAttrs;
398 baseaddr = hwAttrs->baseAddr;
399 object = handle->object;
400
401 if(object->instance == PRUICCSS_INSTANCE_ONE)
402 {
403 baseaddr = hwAttrs->prussIntcRegBase;
404 }
405 else if(object->instance == PRUICCSS_INSTANCE_TWO )
406 {
407 baseaddr = hwAttrs->prussIntcRegBase;
408 }
409 else
410 {
411 ret_val = PRUICSS_RETURN_FAILURE;
412 }
413 for (i = 0; i < (PRUICSS_NUM_PRU_SYS_EVTS + 3U) >> 2; i++)
414 {
415 temp_addr = ((baseaddr + CSL_ICSSINTC_CMR0 ) + (i << 2));
416 HWREG(temp_addr) = 0;
417 }
418
419 for (i = 0; i < (PRUICSS_NUM_PRU_HOSTS + 3U) >> 2; i++)
420 {
421 temp_addr = (baseaddr + CSL_ICSSINTC_HMR0 + (i << 2));
422 HWREG(temp_addr) = 0;
423 }
424
425 HWREG(baseaddr + CSL_ICSSINTC_ESR0) = 0;
378 426
427 HWREG(baseaddr + CSL_ICSSINTC_SECR0) = 0;
379 428
429 HWREG(baseaddr + CSL_ICSSINTC_ERS1) = 0;
380 430
431 HWREG(baseaddr + CSL_ICSSINTC_SECR1) = 0;
432
433 HWREG(baseaddr + CSL_ICSSINTC_HIER) = 0;
434
435 HWREG(baseaddr + CSL_ICSSINTC_GER) = 0;
436
437 return ret_val;
438}