summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorTinku Mannan2018-06-05 13:41:25 -0500
committerTinku Mannan2018-06-05 13:54:44 -0500
commitbcddfcab144e5c6a9c3d1445af3fb76032e8e4a6 (patch)
treeb0200f0788db425a4a7e1acb7df9a7432922d79a /src/pruicss_intc.c
parenta0e5e8d726282fb477ed0bff0b27a3dca1a7eef5 (diff)
downloadpruss-lld-bcddfcab144e5c6a9c3d1445af3fb76032e8e4a6.tar.gz
pruss-lld-bcddfcab144e5c6a9c3d1445af3fb76032e8e4a6.tar.xz
pruss-lld-bcddfcab144e5c6a9c3d1445af3fb76032e8e4a6.zip
Adding support for SOC_AM65XX
Diffstat (limited to 'src/pruicss_intc.c')
-rw-r--r--src/pruicss_intc.c71
1 files changed, 33 insertions, 38 deletions
diff --git a/src/pruicss_intc.c b/src/pruicss_intc.c
index 95a4ac6..7f5b804 100644
--- a/src/pruicss_intc.c
+++ b/src/pruicss_intc.c
@@ -7,7 +7,7 @@
7 */ 7 */
8 8
9/* 9/*
10* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ 10* Copyright (C) 2015-2018 Texas Instruments Incorporated - http://www.ti.com/
11* 11*
12* 12*
13* Redistribution and use in source and binary forms, with or without 13* Redistribution and use in source and binary forms, with or without
@@ -79,7 +79,7 @@ static void PRUICSS_intcSetCmr(uint8_t sysevt,
79 uint8_t channel, 79 uint8_t channel,
80 uint8_t polarity, 80 uint8_t polarity,
81 uint8_t type, 81 uint8_t type,
82 uint32_t baseaddr); 82 uintptr_t baseaddr);
83/** 83/**
84 * \brief Sets Channel-Host Map registers: \n 84 * \brief Sets Channel-Host Map registers: \n
85 * 85 *
@@ -91,7 +91,7 @@ static void PRUICSS_intcSetCmr(uint8_t sysevt,
91 */ 91 */
92static void PRUICSS_intcSetHmr(uint8_t channel, 92static void PRUICSS_intcSetHmr(uint8_t channel,
93 uint8_t host, 93 uint8_t host,
94 uint32_t baseaddr); 94 uintptr_t baseaddr);
95 95
96/** 96/**
97 * \brief PRUICSS interrupt handler 97 * \brief PRUICSS interrupt handler
@@ -123,17 +123,17 @@ static void PRUICSS_hwiIntHandler(uintptr_t ptrPpruEvtoutNum);
123 */ 123 */
124int32_t PRUICSS_pruIntcInit(PRUICSS_Handle handle, const PRUICSS_IntcInitData * prussintc_init_data) 124int32_t PRUICSS_pruIntcInit(PRUICSS_Handle handle, const PRUICSS_IntcInitData * prussintc_init_data)
125{ 125{
126 uint32_t baseaddr; 126 uintptr_t baseaddr;
127 PRUICSS_HwAttrs const *hwAttrs; 127 PRUICSS_HwAttrs const *hwAttrs;
128 PRUICSS_V1_Object *object; 128 PRUICSS_V1_Object *object;
129 129
130 uint32_t i = 0, mask1 = 0, mask2 = 0; 130 uint32_t i = 0, mask1 = 0, mask2 = 0;
131 131
132 uint32_t temp_addr = 0U; 132 uintptr_t temp_addr = 0U;
133 133
134 int32_t ret_val = PRUICSS_RETURN_SUCCESS; 134 int32_t ret_val = PRUICSS_RETURN_SUCCESS;
135 135
136 object = (PRUICSS_V1_Object*)handle->object; 136 object = (PRUICSS_V1_Object *)handle->object;
137 hwAttrs = (PRUICSS_HwAttrs const *)handle->hwAttrs; 137 hwAttrs = (PRUICSS_HwAttrs const *)handle->hwAttrs;
138 baseaddr = hwAttrs->baseAddr; 138 baseaddr = hwAttrs->baseAddr;
139 139
@@ -163,7 +163,7 @@ int32_t PRUICSS_pruIntcInit(PRUICSS_Handle handle, const PRUICSS_IntcInitData *
163 for (i = 0; i < (PRUICSS_NUM_PRU_SYS_EVTS + 3U) >> 2; i++) 163 for (i = 0; i < (PRUICSS_NUM_PRU_SYS_EVTS + 3U) >> 2; i++)
164 { 164 {
165 temp_addr = ((baseaddr + CSL_ICSSINTC_CMR0 ) + (i << 2)); 165 temp_addr = ((baseaddr + CSL_ICSSINTC_CMR0 ) + (i << 2));
166 HWREG(temp_addr) = 0; 166 CSL_REG32_WR(temp_addr, 0);
167 } 167 }
168 for (i = 0; 168 for (i = 0;
169 ((prussintc_init_data->sysevt_to_channel_map[i].sysevt != 0xFF) 169 ((prussintc_init_data->sysevt_to_channel_map[i].sysevt != 0xFF)
@@ -180,7 +180,7 @@ int32_t PRUICSS_pruIntcInit(PRUICSS_Handle handle, const PRUICSS_IntcInitData *
180 for (i = 0; i < (PRUICSS_NUM_PRU_HOSTS + 3U) >> 2; i++) 180 for (i = 0; i < (PRUICSS_NUM_PRU_HOSTS + 3U) >> 2; i++)
181 { 181 {
182 temp_addr = (baseaddr + CSL_ICSSINTC_HMR0 + (i << 2)); 182 temp_addr = (baseaddr + CSL_ICSSINTC_HMR0 + (i << 2));
183 HWREG(temp_addr) = 0; 183 CSL_REG32_WR(temp_addr, 0);
184 } 184 }
185 for (i = 0; 185 for (i = 0;
186 ((i<PRUICSS_NUM_PRU_HOSTS) && 186 ((i<PRUICSS_NUM_PRU_HOSTS) &&
@@ -334,7 +334,7 @@ int32_t PRUICSS_registerIrqHandler2(PRUICSS_Handle handle,
334 SemaphoreP_Params semParams; 334 SemaphoreP_Params semParams;
335 HwiP_Handle hwiHandle = NULL; 335 HwiP_Handle hwiHandle = NULL;
336 void* semHandle = NULL; 336 void* semHandle = NULL;
337 object = (PRUICSS_V1_Object*)handle->object; 337 object = (PRUICSS_V1_Object *)handle->object;
338 HwiP_Params hwiInputParams; 338 HwiP_Params hwiInputParams;
339 MuxIntcP_inParams muxInParams; 339 MuxIntcP_inParams muxInParams;
340 MuxIntcP_outParams muxOutParams; 340 MuxIntcP_outParams muxOutParams;
@@ -439,41 +439,41 @@ static void PRUICSS_intcSetCmr( uint8_t sysevt,
439 uint8_t channel, 439 uint8_t channel,
440 uint8_t polarity, 440 uint8_t polarity,
441 uint8_t type, 441 uint8_t type,
442 uint32_t baseaddr) 442 uintptr_t baseaddr)
443{ 443{
444 uint32_t temp_addr1 = 0U; 444 uintptr_t temp_addr1 = 0U;
445 uint32_t temp_addr2 = 0U; 445 uintptr_t temp_addr2 = 0U;
446 446
447 temp_addr1 = ((baseaddr)+(CSL_ICSSINTC_CMR0 + (((uint32_t)sysevt) & ~((uint32_t)0x3U)))); 447 temp_addr1 = ((baseaddr)+(CSL_ICSSINTC_CMR0 + (((uint32_t)sysevt) & ~((uint32_t)0x3U))));
448 HWREG(temp_addr1) |= ((((uint32_t)channel) & ((uint32_t)0xFU)) << ((((uint32_t)sysevt) & ((uint32_t)0x3U)) << 3U)); 448 CSL_REG32_WR(temp_addr1, CSL_REG32_RD(temp_addr1) | ((((uint32_t)channel) & ((uint32_t)0xFU)) << ((((uint32_t)sysevt) & ((uint32_t)0x3U)) << 3U)));
449 449
450 if(sysevt < 32U) 450 if(sysevt < 32U)
451 { 451 {
452 temp_addr1 = (baseaddr + CSL_ICSSINTC_SIPR0); 452 temp_addr1 = (baseaddr + CSL_ICSSINTC_SIPR0);
453 temp_addr2 = (baseaddr + CSL_ICSSINTC_SITR0); 453 temp_addr2 = (baseaddr + CSL_ICSSINTC_SITR0);
454 HWREG(temp_addr1) &= ~(((uint32_t)polarity) << sysevt); 454 CSL_REG32_WR(temp_addr1, CSL_REG32_RD (temp_addr1) & ~(((uint32_t)polarity) << sysevt));
455 HWREG(temp_addr2) &= ~(((uint32_t)type) << sysevt); 455 CSL_REG32_WR(temp_addr2, CSL_REG32_RD (temp_addr2) & ~(((uint32_t)type) << sysevt));
456 } 456 }
457 else 457 else
458 { 458 {
459 temp_addr1 = (baseaddr + CSL_ICSSINTC_SIPR1); 459 temp_addr1 = (baseaddr + CSL_ICSSINTC_SIPR1);
460 temp_addr2 = (baseaddr + CSL_ICSSINTC_SITR1); 460 temp_addr2 = (baseaddr + CSL_ICSSINTC_SITR1);
461 HWREG(temp_addr1) &= ~(((uint32_t)polarity) << (sysevt - 32U)); 461 CSL_REG32_WR(temp_addr1, CSL_REG32_RD(temp_addr1) & ~(((uint32_t)polarity) << (sysevt - 32U)));
462 HWREG(temp_addr2) &= ~(((uint32_t)type) << (sysevt - 32U)); 462 CSL_REG32_WR(temp_addr2, CSL_REG32_RD(temp_addr2) & ~(((uint32_t)type) << (sysevt - 32U)));
463 } 463 }
464} 464}
465 465
466 466
467static void PRUICSS_intcSetHmr( uint8_t channel, 467static void PRUICSS_intcSetHmr( uint8_t channel,
468 uint8_t host, 468 uint8_t host,
469 uint32_t baseaddr) 469 uintptr_t baseaddr)
470{ 470{
471 uint32_t temp_addr1 = 0U; 471 uintptr_t temp_addr1 = 0U;
472 uint32_t temp_addr2 = 0U; 472 uintptr_t temp_addr2 = 0U;
473 473
474 temp_addr1 = ((baseaddr) + (CSL_ICSSINTC_HMR0 + (((uint32_t)channel) & ~((uint32_t)0x3U)))); 474 temp_addr1 = ((baseaddr) + (CSL_ICSSINTC_HMR0 + (((uint32_t)channel) & ~((uint32_t)0x3U))));
475 temp_addr2 = ((baseaddr) + (CSL_ICSSINTC_HMR0 + (((uint32_t)channel) & ~((uint32_t)0x3U)))); 475 temp_addr2 = ((baseaddr) + (CSL_ICSSINTC_HMR0 + (((uint32_t)channel) & ~((uint32_t)0x3U))));
476 HWREG(temp_addr1) = HWREG(temp_addr2) | ((((uint32_t)host) & ((uint32_t)0xFU)) << ((((uint32_t)channel) & ((uint32_t)0x3U)) << 3U)); 476 CSL_REG32_WR(temp_addr1, CSL_REG32_RD(temp_addr2) | ((((uint32_t)host) & ((uint32_t)0xFU)) << ((((uint32_t)channel) & ((uint32_t)0x3U)) << 3U)));
477} 477}
478 478
479/** 479/**
@@ -485,21 +485,22 @@ static void PRUICSS_intcSetHmr( uint8_t channel,
485 */ 485 */
486int32_t PRUICSS_pruIntcClear(PRUICSS_Handle handle) 486int32_t PRUICSS_pruIntcClear(PRUICSS_Handle handle)
487{ 487{
488 uint32_t baseaddr; 488 uintptr_t baseaddr;
489 PRUICSS_HwAttrs const *hwAttrs; 489 PRUICSS_HwAttrs const *hwAttrs;
490 PRUICSS_V1_Object *object; 490 PRUICSS_V1_Object *object;
491 491
492 uint32_t i = 0; 492 uint32_t i = 0;
493 493
494 uint32_t temp_addr = 0U; 494 uintptr_t temp_addr = 0U;
495 495
496 int32_t ret_val = PRUICSS_RETURN_SUCCESS; 496 int32_t ret_val = PRUICSS_RETURN_SUCCESS;
497 497
498 /* verify the handle */ 498 /* verify the handle */
499 if (handle != NULL) 499 if (handle != NULL)
500 { 500 {
501 object = (PRUICSS_V1_Object*)handle->object; 501 object = (PRUICSS_V1_Object *)handle->object;
502 hwAttrs = (PRUICSS_HwAttrs const *)handle->hwAttrs; 502 hwAttrs = (PRUICSS_HwAttrs const *)handle->hwAttrs;
503
503 /* verify the instance */ 504 /* verify the instance */
504 if ((object->instance == PRUICCSS_INSTANCE_ONE) || (object->instance == PRUICCSS_INSTANCE_TWO)) 505 if ((object->instance == PRUICCSS_INSTANCE_ONE) || (object->instance == PRUICCSS_INSTANCE_TWO))
505 { 506 {
@@ -515,32 +516,26 @@ int32_t PRUICSS_pruIntcClear(PRUICSS_Handle handle)
515 for (i = 0; i < PRUICSS_NUM_PRU_SYS_EVTS >> 2; i++) 516 for (i = 0; i < PRUICSS_NUM_PRU_SYS_EVTS >> 2; i++)
516 { 517 {
517 temp_addr = ((baseaddr + CSL_ICSSINTC_CMR0 ) + (i << 2)); 518 temp_addr = ((baseaddr + CSL_ICSSINTC_CMR0 ) + (i << 2));
518 HWREG(temp_addr) = 0; 519 CSL_REG32_WR(temp_addr, 0);
519 } 520 }
520 521
521 for (i = 0; i < (PRUICSS_NUM_PRU_HOSTS + 3U) >> 2; i++) 522 for (i = 0; i < (PRUICSS_NUM_PRU_HOSTS + 3U) >> 2; i++)
522 { 523 {
523 temp_addr = (baseaddr + CSL_ICSSINTC_HMR0 + (i << 2)); 524 temp_addr = (baseaddr + CSL_ICSSINTC_HMR0 + (i << 2));
524 HWREG(temp_addr) = 0; 525 CSL_REG32_WR(temp_addr, 0);
525 } 526 }
526 527
527 temp_addr = baseaddr + CSL_ICSSINTC_ESR0; 528 CSL_REG32_WR(baseaddr + CSL_ICSSINTC_ESR0, 0);
528 HWREG(temp_addr) = 0;
529 529
530 temp_addr = baseaddr + CSL_ICSSINTC_SECR0; 530 CSL_REG32_WR(baseaddr + CSL_ICSSINTC_SECR0, 0);
531 HWREG(temp_addr) = 0;
532 531
533 temp_addr = baseaddr + CSL_ICSSINTC_ERS1; 532 CSL_REG32_WR(baseaddr + CSL_ICSSINTC_ERS1, 0);
534 HWREG(temp_addr) = 0;
535 533
536 temp_addr = baseaddr + CSL_ICSSINTC_SECR1; 534 CSL_REG32_WR(baseaddr + CSL_ICSSINTC_SECR1, 0);
537 HWREG(temp_addr) = 0;
538 535
539 temp_addr = baseaddr + CSL_ICSSINTC_HIER; 536 CSL_REG32_WR(baseaddr + CSL_ICSSINTC_HIER, 0);
540 HWREG(temp_addr) = 0;
541 537
542 temp_addr = baseaddr + CSL_ICSSINTC_GER; 538 CSL_REG32_WR(baseaddr + CSL_ICSSINTC_GER, 0);
543 HWREG(temp_addr) = 0;
544 } 539 }
545 else 540 else
546 { 541 {