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authorTinku Mannan2016-08-30 12:09:43 -0500
committerTinku Mannan2016-08-31 08:19:27 -0500
commitf4a0e2d2f12682b7d6c29e1815dcaf813d8fc23f (patch)
tree58b853edc0e8ee16efbb69b5053dfce56a2cd2cc /src
parent32bd47f2f5041028ea5cf52c8e9cd3b6b11de903 (diff)
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FIX PRSDK-1020: Incorporate review comments
Diffstat (limited to 'src')
-rw-r--r--src/pruicss_intc.c76
1 files changed, 44 insertions, 32 deletions
diff --git a/src/pruicss_intc.c b/src/pruicss_intc.c
index 52feae8..dc4af58 100644
--- a/src/pruicss_intc.c
+++ b/src/pruicss_intc.c
@@ -394,45 +394,57 @@ int32_t PRUICSS_pruIntcClear(PRUICSS_Handle handle)
394 394
395 int32_t ret_val = PRUICSS_RETURN_SUCCESS; 395 int32_t ret_val = PRUICSS_RETURN_SUCCESS;
396 396
397 hwAttrs = handle->hwAttrs; 397 /* verify the handle */
398 baseaddr = hwAttrs->baseAddr; 398 if (handle != NULL)
399 object = handle->object;
400
401 if(object->instance == PRUICCSS_INSTANCE_ONE)
402 {
403 baseaddr = hwAttrs->prussIntcRegBase;
404 }
405 else if(object->instance == PRUICCSS_INSTANCE_TWO )
406 {
407 baseaddr = hwAttrs->prussIntcRegBase;
408 }
409 else
410 {
411 ret_val = PRUICSS_RETURN_FAILURE;
412 }
413 for (i = 0; i < (PRUICSS_NUM_PRU_SYS_EVTS + 3U) >> 2; i++)
414 {
415 temp_addr = ((baseaddr + CSL_ICSSINTC_CMR0 ) + (i << 2));
416 HWREG(temp_addr) = 0;
417 }
418
419 for (i = 0; i < (PRUICSS_NUM_PRU_HOSTS + 3U) >> 2; i++)
420 { 399 {
421 temp_addr = (baseaddr + CSL_ICSSINTC_HMR0 + (i << 2)); 400 hwAttrs = handle->hwAttrs;
422 HWREG(temp_addr) = 0; 401 object = handle->object;
423 } 402 /* verify the instance */
403 if ((object->instance == PRUICCSS_INSTANCE_ONE) || (object->instance == PRUICCSS_INSTANCE_TWO))
404 {
405 baseaddr = hwAttrs->prussIntcRegBase;
406 }
407 else
408 {
409 ret_val = PRUICSS_RETURN_FAILURE;
410 }
411
412 if(ret_val == PRUICSS_RETURN_SUCCESS)
413 {
414 for (i = 0; i < (PRUICSS_NUM_PRU_SYS_EVTS + 3U) >> 2; i++)
415 {
416 temp_addr = ((baseaddr + CSL_ICSSINTC_CMR0 ) + (i << 2));
417 HWREG(temp_addr) = 0;
418 }
419
420 for (i = 0; i < (PRUICSS_NUM_PRU_HOSTS + 3U) >> 2; i++)
421 {
422 temp_addr = (baseaddr + CSL_ICSSINTC_HMR0 + (i << 2));
423 HWREG(temp_addr) = 0;
424 }
424 425
425 HWREG(baseaddr + CSL_ICSSINTC_ESR0) = 0; 426 HWREG(baseaddr + CSL_ICSSINTC_ESR0) = 0;
426 427
427 HWREG(baseaddr + CSL_ICSSINTC_SECR0) = 0; 428 HWREG(baseaddr + CSL_ICSSINTC_SECR0) = 0;
428 429
429 HWREG(baseaddr + CSL_ICSSINTC_ERS1) = 0; 430 HWREG(baseaddr + CSL_ICSSINTC_ERS1) = 0;
430 431
431 HWREG(baseaddr + CSL_ICSSINTC_SECR1) = 0; 432 HWREG(baseaddr + CSL_ICSSINTC_SECR1) = 0;
432 433
433 HWREG(baseaddr + CSL_ICSSINTC_HIER) = 0; 434 HWREG(baseaddr + CSL_ICSSINTC_HIER) = 0;
434 435
435 HWREG(baseaddr + CSL_ICSSINTC_GER) = 0; 436 HWREG(baseaddr + CSL_ICSSINTC_GER) = 0;
437 }
438 else
439 {
440 ret_val = PRUICSS_RETURN_FAILURE;
441 }
442 }
443 else
444 {
445 ret_val = PRUICSS_RETURN_FAILURE;
446 }
436 447
437 return ret_val; 448 return ret_val;
438} 449}
450