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1/*
2 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the
15 * distribution.
16 *
17 * * Neither the name of Texas Instruments Incorporated nor the names of
18 * its contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34#ifndef _IEP_PWM_FW_REGS_H_
35#define _IEP_PWM_FW_REGS_H_
36
37#include <ti/csl/cslr_icss.h>
38
39/* DMEM FW register addresses */
40#define FW_REG_PWM_CTRL ( 0x00000014 ) /* PWM_CTRL FW register */
41#define FW_REG_IEP0_PWM_RECFG ( 0x0000001C ) /* IEP0_PWM_RECFG FW register */
42#define FW_REG_IEP1_PWM_RECFG ( 0x00000068 ) /* IEP1_PWM_RECFG FW register */
43
44/* Bit field mask & shift macros for PWM_CTRL & PWM_STAT */
45#define IEP_PWM_GBL_EN_MASK ( 0x1 )
46#define IEP_PWM_FW_INIT_MASK ( 0x1 << IEP_PWM_FW_INIT_SHIFT ) /* PWM_CTRL:FW_INIT mask */
47#define IEP_PWM_FW_INIT_SHIFT ( 2 ) /* PWM_CTRL:FW_INIT shift */
48
49/* Bit field mask & shift macros for IEPx_PWM_RECFG */
50#define RECFG_IEP_PWM_EN_MASK ( 0x1 << RECFG_IEP_PWM_EN_SHIFT ) /* IEPx_PWM_RECFG:RECFG_IEPx_PWM_EN mask */
51#define RECFG_IEP_PWM_EN_SHIFT ( 0 ) /* IEPx_PWM_RECFG:RECFG_IEP_PWM_EN shift */
52#define RECFG_IEP_PWM_PRD_COUNT_MASK ( 0x1 << RECFG_IEP_PWM_PRD_COUNT_SHIFT ) /* IEPx_PWM_RECFG:RECFG_IEPx_PWM_PRD_COUNT mask */
53#define RECFG_IEP_PWM_PRD_COUNT_SHIFT ( 1 ) /* IEPx_PWM_RECFG:RECFG_IEPx_PWM_PRD_COUNT shift */
54#define RECFG_IEP_PWM_DC_COUNT_MASK ( 0xFFF << RECFG_IEP_PWM_DC_COUNT_SHIFT ) /* IEPx_PWM_RECFG:RECFG_IEPx_PWM_DC_COUNT mask */
55#define RECFG_IEP_PWM_DC_COUNT_SHIFT ( 2 ) /* IEPx_PWM_RECFG:RECFG_IEPx_PWM_DC_COUNT shift */
56#define RECFG_IEP_PWM_DB_COUNT_MASK ( 0x7F << RECFG_IEP_PWM_DB_COUNT_SHIFT ) /* IEPx_PWM_RECFG:RECFG_IEPx_PWM_DB_COUNT mask */
57#define RECFG_IEP_PWM_DB_COUNT_SHIFT ( 14 ) /* IEPx_PWM_RECFG:RECFG_IEPx_PWM_DB_COUNT shift */
58
59/* PWM Firmware information registers */
60typedef struct IepPwmInfoFwRegs_s
61{
62 volatile Uint32 FwMagicNumber; /* Firmware Magic Number Fw Reg */
63 volatile Uint32 FwType; /* Firmware Type Information Fw Reg */
64 volatile Uint32 FwVersion; /* Firmware Version Information Fw Reg */
65 volatile Uint32 FwFeature; /* Firmware Feature Information Fw Reg */
66 volatile Uint32 FwExtendedFeature; /* Firmware Extended Feature Information Fw Reg */
67} IepPwmInfoFwRegs;
68
69/* PWM Firmware Control/Status registers */
70typedef struct IepPwmCtrlFwRegs_s
71{
72 volatile Uint32 PWM_CTRL; /* PWM Control Fw Reg */
73 volatile Uint32 PWM_STAT; /* PWM Status Fw Reg */
74} IepPwmCtrlFwRegs;
75
76/* IEP PWM Firmware registers */
77typedef struct IepPwmFwRegs_s
78{
79 volatile Uint32 IEP_PWM_RECFG; /* IEP PWM Reconfiguration Fw Reg */
80 volatile Uint32 IEP_PWM_MODE; /* IEP PWM Mode Fw Reg */
81 volatile Uint32 IEP_PWM_EN; /* IEP PWM Enable Fw Reg */
82 volatile Uint32 IEP_PWM_PRD_COUNT; /* IEP PWM Period Count Fw Reg */
83 volatile Uint32 IEP_PWM0_DC_COUNT; /* IEP PWM0 Duty Cycle Count Fw Reg */
84 volatile Uint32 IEP_PWM1_DC_COUNT; /* IEP PWM1 Duty Cycle Count Fw Reg */
85 volatile Uint32 IEP_PWM2_DC_COUNT; /* IEP PWM2 Duty Cycle Count Fw Reg */
86 volatile Uint32 IEP_PWM3_DC_COUNT; /* IEP PWM3 Duty Cycle Count Fw Reg */
87 volatile Uint32 IEP_PWM4_DC_COUNT; /* IEP PWM4 Duty Cycle Count Fw Reg */
88 volatile Uint32 IEP_PWM5_DC_COUNT; /* IEP PWM5 Duty Cycle Count Fw Reg */
89 volatile Uint32 IEP_PWM6_DC_COUNT; /* IEP PWM6 Duty Cycle Count Fw Reg */
90 volatile Uint32 IEP_PWM7_DC_COUNT; /* IEP PWM7 Duty Cycle Count Fw Reg */
91 volatile Uint32 IEP_PWM8_DC_COUNT; /* IEP PWM8 Duty Cycle Count Fw Reg */
92 volatile Uint32 IEP_PWM9_DC_COUNT; /* IEP PWM9 Duty Cycle Count Fw Reg */
93 volatile Uint32 IEP_PWM10_DC_COUNT; /* IEP PWM10 Duty Cycle Count Fw Reg */
94 volatile Uint32 IEP_PWM11_DC_COUNT; /* IEP PWM11 Duty Cycle Count Fw Reg */
95 volatile Uint16 IEP_PWM0_1_DB_COUNT; /* IEP PWM0/1 Dead Band Cycle Count Fw Reg */
96 volatile Uint16 IEP_PWM2_3_DB_COUNT; /* IEP PWM2/3 Dead Band Cycle Count Fw Reg */
97 volatile Uint16 IEP_PWM4_5_DB_COUNT; /* IEP PWM4/5 Dead Band Cycle Count Fw Reg */
98 volatile Uint16 IEP_PWM6_7_DB_COUNT; /* IEP PWM6/7 Dead Band Cycle Count Fw Reg */
99 volatile Uint16 IEP_PWM8_9_DB_COUNT; /* IEP PWM8/9 Dead Band Cycle Count Fw Reg */
100 volatile Uint16 IEP_PWM10_11_DB_COUNT; /* IEP PWM10/11 Dead Band Cycle Count Fw Reg */
101} IepPwmFwRegs;
102
103#endif /* _IEP_PWM_FW_REGS_H_ */
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