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Diffstat (limited to 'example/apps/sorte/firmware/src/master/firm_main.asm')
-rw-r--r--example/apps/sorte/firmware/src/master/firm_main.asm14
1 files changed, 9 insertions, 5 deletions
diff --git a/example/apps/sorte/firmware/src/master/firm_main.asm b/example/apps/sorte/firmware/src/master/firm_main.asm
index 7793ef0..353f38f 100644
--- a/example/apps/sorte/firmware/src/master/firm_main.asm
+++ b/example/apps/sorte/firmware/src/master/firm_main.asm
@@ -135,12 +135,10 @@ firm_main:
135 135
136; starting with idle state 136; starting with idle state
137; test if there is an active link on the port using mdio interface 137; test if there is an active link on the port using mdio interface
138
139; test if there is an active link on the port using mdio interface
140 lbco &TEMP_REG_2.b0, ICSS_SHARED_RAM_CONST, MDIO_PHY_CONFIG_OFFSET, 1
141IDLE_WAIT_FOR_LINK_ACTIVE: 138IDLE_WAIT_FOR_LINK_ACTIVE:
139 lbco &TEMP_REG_2.b0, ICSS_SHARED_RAM_CONST, MDIO_PHY_CONFIG_OFFSET, 1
142 lbco &TEMP_REG_1, ICSS_MDIO_CONST, ICSS_MDIO_LINK, 4 140 lbco &TEMP_REG_1, ICSS_MDIO_CONST, ICSS_MDIO_LINK, 4
143 qbbc IDLE_WAIT_FOR_LINK_ACTIVE, TEMP_REG_1.b0, TEMP_REG_2.b0 141 qbbc IDLE_WAIT_FOR_LINK_ACTIVE, TEMP_REG_1, TEMP_REG_2.b0
144 142
145; check if enabled, enabling done at startup of pru firmware. 143; check if enabled, enabling done at startup of pru firmware.
146 lbco &TEMP_REG_1.b0, PRU0_DMEM_CONST, CTRL_REG_OFFSET , 1 144 lbco &TEMP_REG_1.b0, PRU0_DMEM_CONST, CTRL_REG_OFFSET , 1
@@ -461,11 +459,17 @@ STATE_PARAM_SEND:
461; end packet with crc generated by PRU 459; end packet with crc generated by PRU
462 M_CMD16 D_PUSH_CRC_MSWORD_CMD | D_PUSH_CRC_LSWORD_CMD | D_TX_EOF 460 M_CMD16 D_PUSH_CRC_MSWORD_CMD | D_PUSH_CRC_LSWORD_CMD | D_TX_EOF
463 461
462 ldi R2.w0, 0
463 ldi R2.w2, 1000
464; receive packet and check if all accepted 464; receive packet and check if all accepted
465STATE_PARAM_WAIT_BANK0: 465STATE_PARAM_WAIT_BANK0:
466 add R2.w0, R2.w0, 1
466 xin RXL2_BANK0, &R18, 1 467 xin RXL2_BANK0, &R18, 1
468 qbeq STATE_PARAM_WAIT, R2.w0, R2.w2
467 qbgt STATE_PARAM_WAIT_BANK0, r18.b0, 32 469 qbgt STATE_PARAM_WAIT_BANK0, r18.b0, 32
468 470
471
472
469 xin RXL2_BANK0, &r2, 32+16 473 xin RXL2_BANK0, &r2, 32+16
470 474
471; received packet has PA? 475; received packet has PA?
@@ -488,6 +492,7 @@ STATE_PARAM_PA_CONT:
488; qba STATE_DISCOVERY 492; qba STATE_DISCOVERY
489STATE_PARAM_RCV_OK: 493STATE_PARAM_RCV_OK:
490 494
495 sub TEMP_REG_4.b0,TEMP_REG_4.b0,1
491; todo: read and verify rest of packet 496; todo: read and verify rest of packet
492; wait for end of 1 ms period 497; wait for end of 1 ms period
493STATE_PARAM_WAIT: 498STATE_PARAM_WAIT:
@@ -495,7 +500,6 @@ STATE_PARAM_WAIT:
495 lbbo &PRU_CC_REG, r27, 0x0c , 4 500 lbbo &PRU_CC_REG, r27, 0x0c , 4
496 qblt STATE_PARAM_WAIT, TEMP_REG_1, PRU_CC_REG 501 qblt STATE_PARAM_WAIT, TEMP_REG_1, PRU_CC_REG
497 502
498 sub TEMP_REG_4.b0,TEMP_REG_4.b0,1
499 qbne STATE_PARAM_ITERATION,TEMP_REG_4.b0, 0 503 qbne STATE_PARAM_ITERATION,TEMP_REG_4.b0, 0
500 504
501 505