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Diffstat (limited to 'src/pruicss_intc.c')
-rw-r--r--src/pruicss_intc.c71
1 files changed, 33 insertions, 38 deletions
diff --git a/src/pruicss_intc.c b/src/pruicss_intc.c
index f2ccc1b..d681dd4 100644
--- a/src/pruicss_intc.c
+++ b/src/pruicss_intc.c
@@ -7,7 +7,7 @@
7 */ 7 */
8 8
9/* 9/*
10* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ 10* Copyright (C) 2015-2018 Texas Instruments Incorporated - http://www.ti.com/
11* 11*
12* 12*
13* Redistribution and use in source and binary forms, with or without 13* Redistribution and use in source and binary forms, with or without
@@ -79,7 +79,7 @@ static void PRUICSS_intcSetCmr(uint8_t sysevt,
79 uint8_t channel, 79 uint8_t channel,
80 uint8_t polarity, 80 uint8_t polarity,
81 uint8_t type, 81 uint8_t type,
82 uint32_t baseaddr); 82 uintptr_t baseaddr);
83/** 83/**
84 * \brief Sets Channel-Host Map registers: \n 84 * \brief Sets Channel-Host Map registers: \n
85 * 85 *
@@ -91,7 +91,7 @@ static void PRUICSS_intcSetCmr(uint8_t sysevt,
91 */ 91 */
92static void PRUICSS_intcSetHmr(uint8_t channel, 92static void PRUICSS_intcSetHmr(uint8_t channel,
93 uint8_t host, 93 uint8_t host,
94 uint32_t baseaddr); 94 uintptr_t baseaddr);
95 95
96/** 96/**
97 * \brief PRUICSS interrupt handler 97 * \brief PRUICSS interrupt handler
@@ -123,17 +123,17 @@ static void PRUICSS_hwiIntHandler(uintptr_t ptrPpruEvtoutNum);
123 */ 123 */
124int32_t PRUICSS_pruIntcInit(PRUICSS_Handle handle, const PRUICSS_IntcInitData * prussintc_init_data) 124int32_t PRUICSS_pruIntcInit(PRUICSS_Handle handle, const PRUICSS_IntcInitData * prussintc_init_data)
125{ 125{
126 uint32_t baseaddr; 126 uintptr_t baseaddr;
127 PRUICSS_HwAttrs const *hwAttrs; 127 PRUICSS_HwAttrs const *hwAttrs;
128 PRUICSS_V1_Object *object; 128 PRUICSS_V1_Object *object;
129 129
130 uint32_t i = 0, mask1 = 0, mask2 = 0; 130 uint32_t i = 0, mask1 = 0, mask2 = 0;
131 131
132 uint32_t temp_addr = 0U; 132 uintptr_t temp_addr = 0U;
133 133
134 int32_t ret_val = PRUICSS_RETURN_SUCCESS; 134 int32_t ret_val = PRUICSS_RETURN_SUCCESS;
135 135
136 object = (PRUICSS_V1_Object*)handle->object; 136 object = (PRUICSS_V1_Object *)handle->object;
137 hwAttrs = (PRUICSS_HwAttrs const *)handle->hwAttrs; 137 hwAttrs = (PRUICSS_HwAttrs const *)handle->hwAttrs;
138 baseaddr = hwAttrs->baseAddr; 138 baseaddr = hwAttrs->baseAddr;
139 139
@@ -163,7 +163,7 @@ int32_t PRUICSS_pruIntcInit(PRUICSS_Handle handle, const PRUICSS_IntcInitData *
163 for (i = 0; i < (PRUICSS_NUM_PRU_SYS_EVTS + 3U) >> 2; i++) 163 for (i = 0; i < (PRUICSS_NUM_PRU_SYS_EVTS + 3U) >> 2; i++)
164 { 164 {
165 temp_addr = ((baseaddr + CSL_ICSSINTC_CMR0 ) + (i << 2)); 165 temp_addr = ((baseaddr + CSL_ICSSINTC_CMR0 ) + (i << 2));
166 HWREG(temp_addr) = 0; 166 CSL_REG32_WR(temp_addr, 0);
167 } 167 }
168 for (i = 0; 168 for (i = 0;
169 ((prussintc_init_data->sysevt_to_channel_map[i].sysevt != 0xFF) 169 ((prussintc_init_data->sysevt_to_channel_map[i].sysevt != 0xFF)
@@ -180,7 +180,7 @@ int32_t PRUICSS_pruIntcInit(PRUICSS_Handle handle, const PRUICSS_IntcInitData *
180 for (i = 0; i < (PRUICSS_NUM_PRU_HOSTS + 3U) >> 2; i++) 180 for (i = 0; i < (PRUICSS_NUM_PRU_HOSTS + 3U) >> 2; i++)
181 { 181 {
182 temp_addr = (baseaddr + CSL_ICSSINTC_HMR0 + (i << 2)); 182 temp_addr = (baseaddr + CSL_ICSSINTC_HMR0 + (i << 2));
183 HWREG(temp_addr) = 0; 183 CSL_REG32_WR(temp_addr, 0);
184 } 184 }
185 for (i = 0; 185 for (i = 0;
186 ((i<PRUICSS_NUM_PRU_HOSTS) && 186 ((i<PRUICSS_NUM_PRU_HOSTS) &&
@@ -337,7 +337,7 @@ int32_t PRUICSS_registerIrqHandler2(PRUICSS_Handle handle,
337 SemaphoreP_Params semParams; 337 SemaphoreP_Params semParams;
338 HwiP_Handle hwiHandle = NULL; 338 HwiP_Handle hwiHandle = NULL;
339 void* semHandle = NULL; 339 void* semHandle = NULL;
340 object = (PRUICSS_V1_Object*)handle->object; 340 object = (PRUICSS_V1_Object *)handle->object;
341 HwiP_Params hwiInputParams; 341 HwiP_Params hwiInputParams;
342 MuxIntcP_inParams muxInParams; 342 MuxIntcP_inParams muxInParams;
343 MuxIntcP_outParams muxOutParams; 343 MuxIntcP_outParams muxOutParams;
@@ -445,41 +445,41 @@ static void PRUICSS_intcSetCmr( uint8_t sysevt,
445 uint8_t channel, 445 uint8_t channel,
446 uint8_t polarity, 446 uint8_t polarity,
447 uint8_t type, 447 uint8_t type,
448 uint32_t baseaddr) 448 uintptr_t baseaddr)
449{ 449{
450 uint32_t temp_addr1 = 0U; 450 uintptr_t temp_addr1 = 0U;
451 uint32_t temp_addr2 = 0U; 451 uintptr_t temp_addr2 = 0U;
452 452
453 temp_addr1 = ((baseaddr)+(CSL_ICSSINTC_CMR0 + (((uint32_t)sysevt) & ~((uint32_t)0x3U)))); 453 temp_addr1 = ((baseaddr)+(CSL_ICSSINTC_CMR0 + (((uint32_t)sysevt) & ~((uint32_t)0x3U))));
454 HWREG(temp_addr1) |= ((((uint32_t)channel) & ((uint32_t)0xFU)) << ((((uint32_t)sysevt) & ((uint32_t)0x3U)) << 3U)); 454 CSL_REG32_WR(temp_addr1, CSL_REG32_RD(temp_addr1) | ((((uint32_t)channel) & ((uint32_t)0xFU)) << ((((uint32_t)sysevt) & ((uint32_t)0x3U)) << 3U)));
455 455
456 if(sysevt < 32U) 456 if(sysevt < 32U)
457 { 457 {
458 temp_addr1 = (baseaddr + CSL_ICSSINTC_SIPR0); 458 temp_addr1 = (baseaddr + CSL_ICSSINTC_SIPR0);
459 temp_addr2 = (baseaddr + CSL_ICSSINTC_SITR0); 459 temp_addr2 = (baseaddr + CSL_ICSSINTC_SITR0);
460 HWREG(temp_addr1) &= ~(((uint32_t)polarity) << sysevt); 460 CSL_REG32_WR(temp_addr1, CSL_REG32_RD (temp_addr1) & ~(((uint32_t)polarity) << sysevt));
461 HWREG(temp_addr2) &= ~(((uint32_t)type) << sysevt); 461 CSL_REG32_WR(temp_addr2, CSL_REG32_RD (temp_addr2) & ~(((uint32_t)type) << sysevt));
462 } 462 }
463 else 463 else
464 { 464 {
465 temp_addr1 = (baseaddr + CSL_ICSSINTC_SIPR1); 465 temp_addr1 = (baseaddr + CSL_ICSSINTC_SIPR1);
466 temp_addr2 = (baseaddr + CSL_ICSSINTC_SITR1); 466 temp_addr2 = (baseaddr + CSL_ICSSINTC_SITR1);
467 HWREG(temp_addr1) &= ~(((uint32_t)polarity) << (sysevt - 32U)); 467 CSL_REG32_WR(temp_addr1, CSL_REG32_RD(temp_addr1) & ~(((uint32_t)polarity) << (sysevt - 32U)));
468 HWREG(temp_addr2) &= ~(((uint32_t)type) << (sysevt - 32U)); 468 CSL_REG32_WR(temp_addr2, CSL_REG32_RD(temp_addr2) & ~(((uint32_t)type) << (sysevt - 32U)));
469 } 469 }
470} 470}
471 471
472 472
473static void PRUICSS_intcSetHmr( uint8_t channel, 473static void PRUICSS_intcSetHmr( uint8_t channel,
474 uint8_t host, 474 uint8_t host,
475 uint32_t baseaddr) 475 uintptr_t baseaddr)
476{ 476{
477 uint32_t temp_addr1 = 0U; 477 uintptr_t temp_addr1 = 0U;
478 uint32_t temp_addr2 = 0U; 478 uintptr_t temp_addr2 = 0U;
479 479
480 temp_addr1 = ((baseaddr) + (CSL_ICSSINTC_HMR0 + (((uint32_t)channel) & ~((uint32_t)0x3U)))); 480 temp_addr1 = ((baseaddr) + (CSL_ICSSINTC_HMR0 + (((uint32_t)channel) & ~((uint32_t)0x3U))));
481 temp_addr2 = ((baseaddr) + (CSL_ICSSINTC_HMR0 + (((uint32_t)channel) & ~((uint32_t)0x3U)))); 481 temp_addr2 = ((baseaddr) + (CSL_ICSSINTC_HMR0 + (((uint32_t)channel) & ~((uint32_t)0x3U))));
482 HWREG(temp_addr1) = HWREG(temp_addr2) | ((((uint32_t)host) & ((uint32_t)0xFU)) << ((((uint32_t)channel) & ((uint32_t)0x3U)) << 3U)); 482 CSL_REG32_WR(temp_addr1, CSL_REG32_RD(temp_addr2) | ((((uint32_t)host) & ((uint32_t)0xFU)) << ((((uint32_t)channel) & ((uint32_t)0x3U)) << 3U)));
483} 483}
484 484
485/** 485/**
@@ -491,21 +491,22 @@ static void PRUICSS_intcSetHmr( uint8_t channel,
491 */ 491 */
492int32_t PRUICSS_pruIntcClear(PRUICSS_Handle handle) 492int32_t PRUICSS_pruIntcClear(PRUICSS_Handle handle)
493{ 493{
494 uint32_t baseaddr; 494 uintptr_t baseaddr;
495 PRUICSS_HwAttrs const *hwAttrs; 495 PRUICSS_HwAttrs const *hwAttrs;
496 PRUICSS_V1_Object *object; 496 PRUICSS_V1_Object *object;
497 497
498 uint32_t i = 0; 498 uint32_t i = 0;
499 499
500 uint32_t temp_addr = 0U; 500 uintptr_t temp_addr = 0U;
501 501
502 int32_t ret_val = PRUICSS_RETURN_SUCCESS; 502 int32_t ret_val = PRUICSS_RETURN_SUCCESS;
503 503
504 /* verify the handle */ 504 /* verify the handle */
505 if (handle != NULL) 505 if (handle != NULL)
506 { 506 {
507 object = (PRUICSS_V1_Object*)handle->object; 507 object = (PRUICSS_V1_Object *)handle->object;
508 hwAttrs = (PRUICSS_HwAttrs const *)handle->hwAttrs; 508 hwAttrs = (PRUICSS_HwAttrs const *)handle->hwAttrs;
509
509 /* verify the instance */ 510 /* verify the instance */
510 if ((object->instance == PRUICCSS_INSTANCE_ONE) || (object->instance == PRUICCSS_INSTANCE_TWO)) 511 if ((object->instance == PRUICCSS_INSTANCE_ONE) || (object->instance == PRUICCSS_INSTANCE_TWO))
511 { 512 {
@@ -521,32 +522,26 @@ int32_t PRUICSS_pruIntcClear(PRUICSS_Handle handle)
521 for (i = 0; i < PRUICSS_NUM_PRU_SYS_EVTS >> 2; i++) 522 for (i = 0; i < PRUICSS_NUM_PRU_SYS_EVTS >> 2; i++)
522 { 523 {
523 temp_addr = ((baseaddr + CSL_ICSSINTC_CMR0 ) + (i << 2)); 524 temp_addr = ((baseaddr + CSL_ICSSINTC_CMR0 ) + (i << 2));
524 HWREG(temp_addr) = 0; 525 CSL_REG32_WR(temp_addr, 0);
525 } 526 }
526 527
527 for (i = 0; i < (PRUICSS_NUM_PRU_HOSTS + 3U) >> 2; i++) 528 for (i = 0; i < (PRUICSS_NUM_PRU_HOSTS + 3U) >> 2; i++)
528 { 529 {
529 temp_addr = (baseaddr + CSL_ICSSINTC_HMR0 + (i << 2)); 530 temp_addr = (baseaddr + CSL_ICSSINTC_HMR0 + (i << 2));
530 HWREG(temp_addr) = 0; 531 CSL_REG32_WR(temp_addr, 0);
531 } 532 }
532 533
533 temp_addr = baseaddr + CSL_ICSSINTC_ESR0; 534 CSL_REG32_WR(baseaddr + CSL_ICSSINTC_ESR0, 0);
534 HWREG(temp_addr) = 0;
535 535
536 temp_addr = baseaddr + CSL_ICSSINTC_SECR0; 536 CSL_REG32_WR(baseaddr + CSL_ICSSINTC_SECR0, 0);
537 HWREG(temp_addr) = 0;
538 537
539 temp_addr = baseaddr + CSL_ICSSINTC_ERS1; 538 CSL_REG32_WR(baseaddr + CSL_ICSSINTC_ERS1, 0);
540 HWREG(temp_addr) = 0;
541 539
542 temp_addr = baseaddr + CSL_ICSSINTC_SECR1; 540 CSL_REG32_WR(baseaddr + CSL_ICSSINTC_SECR1, 0);
543 HWREG(temp_addr) = 0;
544 541
545 temp_addr = baseaddr + CSL_ICSSINTC_HIER; 542 CSL_REG32_WR(baseaddr + CSL_ICSSINTC_HIER, 0);
546 HWREG(temp_addr) = 0;
547 543
548 temp_addr = baseaddr + CSL_ICSSINTC_GER; 544 CSL_REG32_WR(baseaddr + CSL_ICSSINTC_GER, 0);
549 HWREG(temp_addr) = 0;
550 } 545 }
551 else 546 else
552 { 547 {